Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2551

1

T5

11

T50

8

T52

14

auto[1]

2601

1

T5

8

T50

13

T52

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2751

1

T5

19

T52

17

T6

9

auto[1]

2401

1

T50

21

T52

5

T121

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4090

1

T5

12

T50

21

T52

16

auto[1]

1062

1

T5

7

T52

6

T6

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1040	1			T5	3		T50	6		T52	6
valid[1]	1025	1			T5	4		T50	3		T52	2
valid[2]	1022	1			T5	7		T50	5		T52	5
valid[3]	1026	1			T5	1		T50	2		T52	5
valid[4]	1039	1			T5	4		T50	5		T52	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	167	1			T5	1		T52	1		T120	3
auto[0]	auto[0]	valid[0]	auto[1]	243	1			T52	1		T123	1		T163	3
auto[0]	auto[0]	valid[1]	auto[0]	144	1			T5	2		T52	1		T6	2
auto[0]	auto[0]	valid[1]	auto[1]	237	1			T50	3		T121	2		T123	5
auto[0]	auto[0]	valid[2]	auto[0]	185	1			T5	3		T52	3		T6	1
auto[0]	auto[0]	valid[2]	auto[1]	228	1			T50	2		T52	1		T123	3
auto[0]	auto[0]	valid[3]	auto[0]	165	1			T52	1		T6	1		T121	2
auto[0]	auto[0]	valid[3]	auto[1]	228	1			T121	2		T123	5		T28	1
auto[0]	auto[0]	valid[4]	auto[0]	186	1			T5	1		T52	1		T6	1
auto[0]	auto[0]	valid[4]	auto[1]	253	1			T50	3		T52	1		T121	1
auto[0]	auto[1]	valid[0]	auto[0]	152	1			T5	1		T52	1		T121	1
auto[0]	auto[1]	valid[0]	auto[1]	253	1			T50	6		T121	2		T123	4
auto[0]	auto[1]	valid[1]	auto[0]	191	1			T5	1		T52	1		T121	2
auto[0]	auto[1]	valid[1]	auto[1]	249	1			T121	1		T123	6		T127	2
auto[0]	auto[1]	valid[2]	auto[0]	179	1			T5	1		T52	1		T120	1
auto[0]	auto[1]	valid[2]	auto[1]	237	1			T50	3		T121	1		T123	3
auto[0]	auto[1]	valid[3]	auto[0]	152	1			T52	1		T120	3		T39	1
auto[0]	auto[1]	valid[3]	auto[1]	261	1			T50	2		T52	1		T123	1
auto[0]	auto[1]	valid[4]	auto[0]	168	1			T5	2		T6	2		T120	2
auto[0]	auto[1]	valid[4]	auto[1]	212	1			T50	2		T52	1		T123	3
auto[1]	auto[0]	valid[0]	auto[0]	105	1			T5	1		T52	2		T121	1
auto[1]	auto[0]	valid[1]	auto[0]	110	1			T5	1		T121	2		T22	1
auto[1]	auto[0]	valid[2]	auto[0]	90	1			T5	2		T120	1		T124	1
auto[1]	auto[0]	valid[3]	auto[0]	100	1			T52	2		T121	2		T22	1
auto[1]	auto[0]	valid[4]	auto[0]	110	1			T44	1		T22	3		T45	2
auto[1]	auto[1]	valid[0]	auto[0]	120	1			T52	1		T6	1		T121	1
auto[1]	auto[1]	valid[1]	auto[0]	94	1			T120	2		T44	1		T22	1
auto[1]	auto[1]	valid[2]	auto[0]	103	1			T5	1		T120	1		T121	1
auto[1]	auto[1]	valid[3]	auto[0]	120	1			T5	1		T6	1		T121	1
auto[1]	auto[1]	valid[4]	auto[0]	110	1			T5	1		T52	1		T121	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal