Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	412	1			T79	4		T80	7		T86	7
all_values[1]	412	1			T79	4		T80	7		T86	7
all_values[2]	412	1			T79	4		T80	7		T86	7
all_values[3]	412	1			T79	4		T80	7		T86	7
all_values[4]	412	1			T79	4		T80	7		T86	7
all_values[5]	412	1			T79	4		T80	7		T86	7
all_values[6]	412	1			T79	4		T80	7		T86	7
all_values[7]	412	1			T79	4		T80	7		T86	7
all_values[8]	412	1			T79	4		T80	7		T86	7
all_values[9]	412	1			T79	4		T80	7		T86	7
all_values[10]	412	1			T79	4		T80	7		T86	7
all_values[11]	412	1			T79	4		T80	7		T86	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2682

1

T79

32

T80

38

T86

41

auto[1]

2262

1

T79

16

T80

46

T86

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1901

1

T79

19

T80

29

T86

27

auto[1]

3043

1

T79

29

T80

55

T86

57

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2835

1

T79

33

T80

45

T86

43

auto[1]

2109

1

T79

15

T80

39

T86

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	80	1			T79	1		T87	1		T228	1
all_values[0]	auto[0]	auto[0]	auto[1]	36	1			T86	1		T229	1		T184	2
all_values[0]	auto[0]	auto[1]	auto[0]	67	1			T79	1		T80	1		T86	1
all_values[0]	auto[0]	auto[1]	auto[1]	40	1			T79	1		T80	1		T86	1
all_values[0]	auto[1]	auto[0]	auto[1]	92	1			T80	1		T86	1		T87	1
all_values[0]	auto[1]	auto[1]	auto[1]	97	1			T79	1		T80	4		T86	3
all_values[1]	auto[0]	auto[0]	auto[0]	84	1			T79	1		T80	2		T86	1
all_values[1]	auto[0]	auto[0]	auto[1]	39	1			T79	1		T184	1		T185	1
all_values[1]	auto[0]	auto[1]	auto[0]	77	1			T80	2		T86	1		T87	3
all_values[1]	auto[0]	auto[1]	auto[1]	44	1			T86	2		T87	1		T229	1
all_values[1]	auto[1]	auto[0]	auto[1]	85	1			T79	1		T86	2		T87	2
all_values[1]	auto[1]	auto[1]	auto[1]	83	1			T79	1		T80	3		T86	1
all_values[2]	auto[0]	auto[0]	auto[0]	86	1			T79	1		T80	1		T87	1
all_values[2]	auto[0]	auto[0]	auto[1]	37	1			T87	4		T228	1		T229	2
all_values[2]	auto[0]	auto[1]	auto[0]	73	1			T80	4		T86	4		T230	2
all_values[2]	auto[0]	auto[1]	auto[1]	43	1			T79	2		T229	2		T184	1
all_values[2]	auto[1]	auto[0]	auto[1]	102	1			T79	1		T80	2		T87	2
all_values[2]	auto[1]	auto[1]	auto[1]	71	1			T86	3		T229	2		T184	3
all_values[3]	auto[0]	auto[0]	auto[0]	64	1			T80	1		T228	1		T229	3
all_values[3]	auto[0]	auto[0]	auto[1]	45	1			T80	2		T86	1		T229	1
all_values[3]	auto[0]	auto[1]	auto[0]	61	1			T86	1		T228	1		T229	2
all_values[3]	auto[0]	auto[1]	auto[1]	55	1			T79	3		T80	1		T86	1
all_values[3]	auto[1]	auto[0]	auto[1]	94	1			T79	1		T80	2		T86	2
all_values[3]	auto[1]	auto[1]	auto[1]	93	1			T80	1		T86	2		T87	6
all_values[4]	auto[0]	auto[0]	auto[0]	83	1			T80	1		T86	1		T87	1
all_values[4]	auto[0]	auto[0]	auto[1]	37	1			T228	1		T229	1		T208	1
all_values[4]	auto[0]	auto[1]	auto[0]	63	1			T79	2		T80	3		T86	1
all_values[4]	auto[0]	auto[1]	auto[1]	50	1			T86	1		T87	1		T229	1
all_values[4]	auto[1]	auto[0]	auto[1]	95	1			T79	1		T80	2		T87	1
all_values[4]	auto[1]	auto[1]	auto[1]	84	1			T79	1		T80	1		T86	4
all_values[5]	auto[0]	auto[0]	auto[0]	95	1			T79	1		T80	2		T86	3
all_values[5]	auto[0]	auto[0]	auto[1]	50	1			T79	2		T80	1		T87	1
all_values[5]	auto[0]	auto[1]	auto[0]	66	1			T80	1		T86	1		T229	2
all_values[5]	auto[0]	auto[1]	auto[1]	34	1			T80	2		T86	1		T184	2
all_values[5]	auto[1]	auto[0]	auto[1]	90	1			T86	1		T87	2		T228	1
all_values[5]	auto[1]	auto[1]	auto[1]	77	1			T79	1		T80	1		T86	1
all_values[6]	auto[0]	auto[0]	auto[0]	69	1			T86	1		T229	2		T230	1
all_values[6]	auto[0]	auto[0]	auto[1]	53	1			T79	2		T80	2		T86	1
all_values[6]	auto[0]	auto[1]	auto[0]	68	1			T87	1		T228	2		T229	1
all_values[6]	auto[0]	auto[1]	auto[1]	43	1			T80	1		T86	1		T87	1
all_values[6]	auto[1]	auto[0]	auto[1]	102	1			T79	1		T80	3		T86	3
all_values[6]	auto[1]	auto[1]	auto[1]	77	1			T79	1		T80	1		T86	1
all_values[7]	auto[0]	auto[0]	auto[0]	111	1			T79	4		T86	1		T229	2
all_values[7]	auto[0]	auto[0]	auto[1]	55	1			T80	2		T86	1		T87	2
all_values[7]	auto[0]	auto[1]	auto[0]	62	1			T80	2		T229	5		T184	3
all_values[7]	auto[0]	auto[1]	auto[1]	32	1			T80	1		T87	2		T230	2
all_values[7]	auto[1]	auto[0]	auto[1]	93	1			T86	2		T87	1		T228	2
all_values[7]	auto[1]	auto[1]	auto[1]	59	1			T80	2		T86	3		T87	2
all_values[8]	auto[0]	auto[0]	auto[0]	77	1			T79	4		T80	1		T87	3
all_values[8]	auto[0]	auto[0]	auto[1]	40	1			T86	3		T184	2		T185	1
all_values[8]	auto[0]	auto[1]	auto[0]	66	1			T86	1		T87	1		T228	1
all_values[8]	auto[0]	auto[1]	auto[1]	42	1			T80	2		T87	1		T228	1
all_values[8]	auto[1]	auto[0]	auto[1]	104	1			T80	3		T86	2		T87	1
all_values[8]	auto[1]	auto[1]	auto[1]	83	1			T80	1		T86	1		T87	1
all_values[9]	auto[0]	auto[0]	auto[0]	91	1			T80	1		T86	2		T87	2
all_values[9]	auto[0]	auto[0]	auto[1]	37	1			T79	2		T189	1		T208	2
all_values[9]	auto[0]	auto[1]	auto[0]	63	1			T80	3		T86	2		T213	2
all_values[9]	auto[0]	auto[1]	auto[1]	45	1			T87	2		T230	1		T184	1
all_values[9]	auto[1]	auto[0]	auto[1]	92	1			T79	1		T80	1		T86	1
all_values[9]	auto[1]	auto[1]	auto[1]	84	1			T79	1		T80	2		T86	2
all_values[10]	auto[0]	auto[0]	auto[0]	92	1			T79	1		T80	1		T86	1
all_values[10]	auto[0]	auto[0]	auto[1]	44	1			T79	1		T80	1		T86	2
all_values[10]	auto[0]	auto[1]	auto[0]	66	1			T87	3		T228	1		T229	1
all_values[10]	auto[0]	auto[1]	auto[1]	33	1			T87	2		T228	1		T208	3
all_values[10]	auto[1]	auto[0]	auto[1]	105	1			T79	2		T80	4		T86	4
all_values[10]	auto[1]	auto[1]	auto[1]	72	1			T80	1		T87	2		T228	1
all_values[11]	auto[0]	auto[0]	auto[0]	127	1			T79	3		T86	2		T87	3
all_values[11]	auto[0]	auto[1]	auto[0]	110	1			T80	3		T86	3		T87	2
all_values[11]	auto[1]	auto[0]	auto[1]	96	1			T80	2		T86	2		T87	2
all_values[11]	auto[1]	auto[1]	auto[1]	79	1			T79	1		T80	2		T229	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal