Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72892

1

T5

399

T52

410

T6

405

auto[1]

25207

1

T50

278

T52

66

T121

113

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71566

1

T5

261

T50

278

T52

326

auto[1]

26533

1

T5

138

T52

150

T6

142

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	50570	1			T5	203		T50	141		T52	249
others[1]	8256	1			T5	36		T50	27		T52	38
others[2]	8368	1			T5	45		T50	22		T52	48
others[3]	9315	1			T5	36		T50	26		T52	44
interest[1]	5406	1			T5	19		T50	18		T52	26
interest[4]	33228	1			T5	130		T50	93		T52	159
interest[64]	16184	1			T5	60		T50	44		T52	71

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	23795	1			T5	134		T52	133		T6	143
auto[0]	auto[0]	others[1]	3897	1			T5	23		T52	24		T6	22
auto[0]	auto[0]	others[2]	3970	1			T5	22		T52	32		T6	31
auto[0]	auto[0]	others[3]	4371	1			T5	27		T52	24		T6	21
auto[0]	auto[0]	interest[1]	2570	1			T5	14		T52	11		T6	10
auto[0]	auto[0]	interest[4]	15567	1			T5	85		T52	88		T6	91
auto[0]	auto[0]	interest[64]	7756	1			T5	41		T52	36		T6	36
auto[0]	auto[1]	others[0]	13228	1			T50	141		T52	36		T121	57
auto[0]	auto[1]	others[1]	2110	1			T50	27		T52	5		T121	7
auto[0]	auto[1]	others[2]	2116	1			T50	22		T52	6		T121	8
auto[0]	auto[1]	others[3]	2339	1			T50	26		T52	9		T121	7
auto[0]	auto[1]	interest[1]	1388	1			T50	18		T52	2		T121	8
auto[0]	auto[1]	interest[4]	8854	1			T50	93		T52	23		T121	33
auto[0]	auto[1]	interest[64]	4026	1			T50	44		T52	8		T121	26
auto[1]	auto[0]	others[0]	13547	1			T5	69		T52	80		T6	88
auto[1]	auto[0]	others[1]	2249	1			T5	13		T52	9		T6	10
auto[1]	auto[0]	others[2]	2282	1			T5	23		T52	10		T6	7
auto[1]	auto[0]	others[3]	2605	1			T5	9		T52	11		T6	14
auto[1]	auto[0]	interest[1]	1448	1			T5	5		T52	13		T6	5
auto[1]	auto[0]	interest[4]	8807	1			T5	45		T52	48		T6	44
auto[1]	auto[0]	interest[64]	4402	1			T5	19		T52	27		T6	18

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal