Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.33 98.63 92.06 98.05 95.86 99.76


Total test records in report: 1782
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T1751 /workspace/coverage/default/3.spi_device_bit_transfer.3452277930 Jan 21 07:53:43 PM PST 24 Jan 21 07:53:49 PM PST 24 241814355 ps
T1752 /workspace/coverage/default/48.spi_device_flash_all.930233815 Jan 21 08:16:32 PM PST 24 Jan 21 08:19:30 PM PST 24 32981697327 ps
T1753 /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1538680064 Jan 21 08:10:13 PM PST 24 Jan 21 08:10:23 PM PST 24 319993581 ps
T1754 /workspace/coverage/default/20.spi_device_upload.468670862 Jan 21 07:59:51 PM PST 24 Jan 21 08:00:18 PM PST 24 5896289284 ps
T1755 /workspace/coverage/default/26.spi_device_alert_test.1347667321 Jan 21 08:02:54 PM PST 24 Jan 21 08:03:26 PM PST 24 17128374 ps
T1756 /workspace/coverage/default/22.spi_device_dummy_item_extra_dly.4098047492 Jan 21 08:00:23 PM PST 24 Jan 21 08:06:52 PM PST 24 44037336610 ps
T1757 /workspace/coverage/default/21.spi_device_upload.4194795029 Jan 21 08:00:21 PM PST 24 Jan 21 08:00:33 PM PST 24 2486199750 ps
T1758 /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1636592759 Jan 21 08:03:23 PM PST 24 Jan 21 08:04:00 PM PST 24 55424282038 ps
T1759 /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1247611921 Jan 21 07:53:36 PM PST 24 Jan 21 07:53:49 PM PST 24 6132898972 ps
T1760 /workspace/coverage/default/9.spi_device_tpm_sts_read.1694492895 Jan 21 07:55:26 PM PST 24 Jan 21 07:55:28 PM PST 24 93014653 ps
T1761 /workspace/coverage/default/48.spi_device_csb_read.1407646174 Jan 21 08:16:12 PM PST 24 Jan 21 08:16:14 PM PST 24 20210143 ps
T1762 /workspace/coverage/default/24.spi_device_tpm_rw.3376435993 Jan 21 08:01:49 PM PST 24 Jan 21 08:02:00 PM PST 24 1011639405 ps
T1763 /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.568880068 Jan 21 08:15:35 PM PST 24 Jan 21 08:18:18 PM PST 24 10233047952 ps
T1764 /workspace/coverage/default/25.spi_device_txrx.1270201838 Jan 21 08:02:07 PM PST 24 Jan 21 08:13:22 PM PST 24 47257660469 ps
T1765 /workspace/coverage/default/18.spi_device_intercept.175142640 Jan 21 07:58:58 PM PST 24 Jan 21 07:59:02 PM PST 24 1161209010 ps
T1766 /workspace/coverage/default/25.spi_device_smoke.3008535156 Jan 21 08:01:55 PM PST 24 Jan 21 08:01:58 PM PST 24 88280617 ps
T1767 /workspace/coverage/default/20.spi_device_byte_transfer.2604873000 Jan 21 07:59:44 PM PST 24 Jan 21 07:59:49 PM PST 24 629380834 ps
T1768 /workspace/coverage/default/49.spi_device_flash_all.3894726381 Jan 21 08:16:49 PM PST 24 Jan 21 08:17:24 PM PST 24 11938257534 ps
T1769 /workspace/coverage/default/12.spi_device_flash_mode.372256100 Jan 21 07:56:44 PM PST 24 Jan 21 07:57:10 PM PST 24 4840275337 ps
T1770 /workspace/coverage/default/43.spi_device_flash_mode.2780622077 Jan 21 08:18:54 PM PST 24 Jan 21 08:19:23 PM PST 24 1653533987 ps
T1771 /workspace/coverage/default/33.spi_device_byte_transfer.1088838730 Jan 21 08:10:26 PM PST 24 Jan 21 08:10:32 PM PST 24 151670873 ps
T1772 /workspace/coverage/default/42.spi_device_fifo_full.2699860374 Jan 21 08:13:29 PM PST 24 Jan 21 08:34:26 PM PST 24 76407142625 ps
T1773 /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.922628704 Jan 21 08:08:48 PM PST 24 Jan 21 08:19:52 PM PST 24 604546364279 ps
T1774 /workspace/coverage/default/49.spi_device_tx_async_fifo_reset.1890051781 Jan 21 08:16:45 PM PST 24 Jan 21 08:16:48 PM PST 24 56373882 ps
T1775 /workspace/coverage/default/16.spi_device_mailbox.2689896481 Jan 21 07:58:17 PM PST 24 Jan 21 07:58:29 PM PST 24 3121861540 ps
T1776 /workspace/coverage/default/32.spi_device_flash_and_tpm.2567551568 Jan 21 08:10:14 PM PST 24 Jan 21 08:11:16 PM PST 24 7294782710 ps
T1777 /workspace/coverage/default/47.spi_device_tpm_sts_read.3396442256 Jan 21 08:15:53 PM PST 24 Jan 21 08:15:58 PM PST 24 63347922 ps
T1778 /workspace/coverage/default/0.spi_device_ram_cfg.3673193632 Jan 21 07:52:58 PM PST 24 Jan 21 07:53:04 PM PST 24 30867322 ps
T1779 /workspace/coverage/default/32.spi_device_smoke.1709490474 Jan 21 08:09:49 PM PST 24 Jan 21 08:09:52 PM PST 24 50262890 ps
T1780 /workspace/coverage/default/11.spi_device_mem_parity.3393195953 Jan 21 07:56:10 PM PST 24 Jan 21 07:56:12 PM PST 24 18695494 ps
T1781 /workspace/coverage/default/19.spi_device_tpm_sts_read.2539058752 Jan 21 07:59:30 PM PST 24 Jan 21 07:59:32 PM PST 24 88614319 ps
T1782 /workspace/coverage/default/11.spi_device_tpm_rw.108678107 Jan 21 07:56:14 PM PST 24 Jan 21 07:56:16 PM PST 24 141932172 ps

Test location /workspace/coverage/default/25.spi_device_mailbox.3750962473
Short name T9
Test name
Test status
Simulation time 66779249725 ps
CPU time 34.24 seconds
Started Jan 21 08:02:20 PM PST 24
Finished Jan 21 08:02:58 PM PST 24
Peak memory 245004 kb
Host smart-5820ea62-480e-4e6a-8584-dc86e9239258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750962473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3750962473
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.798798902
Short name T6
Test name
Test status
Simulation time 26476387822 ps
CPU time 222.2 seconds
Started Jan 21 08:01:59 PM PST 24
Finished Jan 21 08:05:45 PM PST 24
Peak memory 260724 kb
Host smart-6408214d-368e-440b-8022-977c4a683bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798798902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.798798902
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_extreme_fifo_size.2908971247
Short name T12
Test name
Test status
Simulation time 92280726426 ps
CPU time 888.83 seconds
Started Jan 21 07:59:09 PM PST 24
Finished Jan 21 08:13:59 PM PST 24
Peak memory 219508 kb
Host smart-7a5441a7-de62-4aa1-8219-7fba98e8641d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908971247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_extreme_fifo_size.2908971247
Directory /workspace/19.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.687705078
Short name T28
Test name
Test status
Simulation time 45574498896 ps
CPU time 217.19 seconds
Started Jan 21 08:08:50 PM PST 24
Finished Jan 21 08:12:30 PM PST 24
Peak memory 265852 kb
Host smart-3b6d21fd-175b-4e64-97df-9ceba013cacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687705078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.687705078
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2132123707
Short name T104
Test name
Test status
Simulation time 143250363 ps
CPU time 3.15 seconds
Started Jan 21 09:55:43 PM PST 24
Finished Jan 21 09:55:53 PM PST 24
Peak memory 215928 kb
Host smart-01acec29-3ad8-4489-a8c1-459a62b13131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132123707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2132123707
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.97685210
Short name T86
Test name
Test status
Simulation time 44648795 ps
CPU time 0.76 seconds
Started Jan 21 10:34:58 PM PST 24
Finished Jan 21 10:34:59 PM PST 24
Peak memory 204832 kb
Host smart-bebe509d-1130-48a1-b109-54b6be13d78d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97685210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.97685210
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1229195056
Short name T32
Test name
Test status
Simulation time 37117050580 ps
CPU time 243.1 seconds
Started Jan 21 07:58:01 PM PST 24
Finished Jan 21 08:02:06 PM PST 24
Peak memory 283208 kb
Host smart-03fa692b-d6fc-4719-8d1d-d236372abb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229195056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1229195056
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1969930335
Short name T140
Test name
Test status
Simulation time 323608957 ps
CPU time 4.79 seconds
Started Jan 21 09:54:48 PM PST 24
Finished Jan 21 09:54:59 PM PST 24
Peak memory 216408 kb
Host smart-15a01d94-ee26-4822-8548-d1e6fde7c9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969930335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
969930335
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1626642302
Short name T560
Test name
Test status
Simulation time 17202977 ps
CPU time 0.75 seconds
Started Jan 21 07:55:44 PM PST 24
Finished Jan 21 07:55:45 PM PST 24
Peak memory 217072 kb
Host smart-1448ba16-3d88-4e33-a10f-a12ce75004c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626642302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1626642302
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2305819606
Short name T233
Test name
Test status
Simulation time 7190790456 ps
CPU time 121.9 seconds
Started Jan 21 08:00:22 PM PST 24
Finished Jan 21 08:02:26 PM PST 24
Peak memory 269768 kb
Host smart-4fa16565-a2f2-40ec-897d-629f0d3c80af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305819606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2305819606
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3945140488
Short name T197
Test name
Test status
Simulation time 39685590165 ps
CPU time 330.66 seconds
Started Jan 21 07:56:26 PM PST 24
Finished Jan 21 08:01:58 PM PST 24
Peak memory 318752 kb
Host smart-be2d1d62-94f0-4378-8039-a4f08ddcb41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945140488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3945140488
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3402262173
Short name T232
Test name
Test status
Simulation time 267956398837 ps
CPU time 1017 seconds
Started Jan 21 07:54:19 PM PST 24
Finished Jan 21 08:11:17 PM PST 24
Peak memory 283224 kb
Host smart-c3c11d1c-32fe-432f-8de3-6a23a8ee1d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402262173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3402262173
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_rx_timeout.1547553959
Short name T40
Test name
Test status
Simulation time 8733167838 ps
CPU time 5.69 seconds
Started Jan 21 08:14:03 PM PST 24
Finished Jan 21 08:14:10 PM PST 24
Peak memory 217248 kb
Host smart-9343b5e1-8fcc-40d5-a079-b75338ecd4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547553959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_timeout.1547553959
Directory /workspace/43.spi_device_rx_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.476785099
Short name T136
Test name
Test status
Simulation time 2257818422 ps
CPU time 15.42 seconds
Started Jan 21 09:55:46 PM PST 24
Finished Jan 21 09:56:07 PM PST 24
Peak memory 216688 kb
Host smart-1a52c127-66a1-443e-9af6-2761cedd03cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476785099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.476785099
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.531259961
Short name T88
Test name
Test status
Simulation time 348516867579 ps
CPU time 1413.79 seconds
Started Jan 21 08:01:59 PM PST 24
Finished Jan 21 08:25:36 PM PST 24
Peak memory 365644 kb
Host smart-9439be30-2791-472d-aef9-0eab623c0a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531259961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.531259961
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1874849766
Short name T200
Test name
Test status
Simulation time 3638719073 ps
CPU time 25.49 seconds
Started Jan 21 08:14:49 PM PST 24
Finished Jan 21 08:15:17 PM PST 24
Peak memory 240356 kb
Host smart-bdae9434-bfef-41bd-ad29-a5d10d9fa420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874849766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1874849766
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3985374575
Short name T20
Test name
Test status
Simulation time 47803475574 ps
CPU time 302.24 seconds
Started Jan 21 08:12:19 PM PST 24
Finished Jan 21 08:17:26 PM PST 24
Peak memory 274824 kb
Host smart-48584f0d-b8a7-46b6-a890-ab82e51be008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985374575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3985374575
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.143383959
Short name T184
Test name
Test status
Simulation time 13378877 ps
CPU time 0.76 seconds
Started Jan 21 09:55:45 PM PST 24
Finished Jan 21 09:55:52 PM PST 24
Peak memory 204812 kb
Host smart-a86d855c-0072-432b-b2ab-7285109b77fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143383959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.143383959
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3403511592
Short name T357
Test name
Test status
Simulation time 268319399862 ps
CPU time 753.56 seconds
Started Jan 21 08:10:20 PM PST 24
Finished Jan 21 08:22:58 PM PST 24
Peak memory 323824 kb
Host smart-a77236a8-a338-4ce2-9d9e-36c8f05ecbc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403511592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3403511592
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1074225889
Short name T85
Test name
Test status
Simulation time 928359247 ps
CPU time 2.1 seconds
Started Jan 21 09:55:39 PM PST 24
Finished Jan 21 09:55:49 PM PST 24
Peak memory 207744 kb
Host smart-6e1988de-e384-498a-9c1b-a52199a88e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074225889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1074225889
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/default/19.spi_device_intr.3288735231
Short name T33
Test name
Test status
Simulation time 15000548449 ps
CPU time 10.15 seconds
Started Jan 21 07:59:10 PM PST 24
Finished Jan 21 07:59:22 PM PST 24
Peak memory 223116 kb
Host smart-21a18cca-5bc7-4325-90e2-4d4b62297a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288735231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intr.3288735231
Directory /workspace/19.spi_device_intr/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2267648794
Short name T231
Test name
Test status
Simulation time 26713249910 ps
CPU time 140.91 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:12:12 PM PST 24
Peak memory 271340 kb
Host smart-a654793c-a76c-479d-9733-470bedfda47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267648794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2267648794
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2568980947
Short name T150
Test name
Test status
Simulation time 720400142199 ps
CPU time 2592.55 seconds
Started Jan 21 08:03:58 PM PST 24
Finished Jan 21 08:47:12 PM PST 24
Peak memory 400068 kb
Host smart-757371f8-5c73-45de-b2dc-749b8bc8c4cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568980947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2568980947
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2589762183
Short name T121
Test name
Test status
Simulation time 28164059360 ps
CPU time 100.37 seconds
Started Jan 21 08:16:43 PM PST 24
Finished Jan 21 08:18:24 PM PST 24
Peak memory 217380 kb
Host smart-12f08ec5-55a3-44d9-8b85-735c003cc354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589762183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2589762183
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.977652455
Short name T352
Test name
Test status
Simulation time 130506697873 ps
CPU time 1295.13 seconds
Started Jan 21 08:11:56 PM PST 24
Finished Jan 21 08:33:34 PM PST 24
Peak memory 332516 kb
Host smart-5ebd3b39-2958-45df-af86-4dacfcdcce7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977652455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.977652455
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_bit_transfer.17861041
Short name T3
Test name
Test status
Simulation time 325769728 ps
CPU time 2.62 seconds
Started Jan 21 08:02:58 PM PST 24
Finished Jan 21 08:03:28 PM PST 24
Peak memory 217204 kb
Host smart-522dee7c-3857-447a-975d-23de7153f416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17861041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_bit_transfer.17861041
Directory /workspace/27.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3738359098
Short name T112
Test name
Test status
Simulation time 83417896 ps
CPU time 1.19 seconds
Started Jan 21 07:53:11 PM PST 24
Finished Jan 21 07:53:14 PM PST 24
Peak memory 238728 kb
Host smart-73faa49b-7958-40c7-a689-d4ed6a71be98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738359098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3738359098
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1170533758
Short name T63
Test name
Test status
Simulation time 531521539505 ps
CPU time 1006.83 seconds
Started Jan 21 08:15:37 PM PST 24
Finished Jan 21 08:32:27 PM PST 24
Peak memory 434360 kb
Host smart-d7a39f4e-eee5-4de6-ac97-8c18991808eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170533758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1170533758
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.381179849
Short name T18
Test name
Test status
Simulation time 12922903532 ps
CPU time 51.15 seconds
Started Jan 21 07:53:03 PM PST 24
Finished Jan 21 07:53:58 PM PST 24
Peak memory 250216 kb
Host smart-6004be0f-024d-486b-b35d-3c7b0531507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381179849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.381179849
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3598079592
Short name T208
Test name
Test status
Simulation time 15867052 ps
CPU time 0.78 seconds
Started Jan 21 09:55:50 PM PST 24
Finished Jan 21 09:55:55 PM PST 24
Peak memory 205028 kb
Host smart-36c4bb7e-ca7c-44d2-889c-391b6edb28c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598079592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3598079592
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2083011650
Short name T288
Test name
Test status
Simulation time 330729134690 ps
CPU time 905.36 seconds
Started Jan 21 07:57:07 PM PST 24
Finished Jan 21 08:12:15 PM PST 24
Peak memory 350524 kb
Host smart-7ba0f47e-cdcd-4173-8267-9488bff98e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083011650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2083011650
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1336975203
Short name T248
Test name
Test status
Simulation time 14606380410 ps
CPU time 176.7 seconds
Started Jan 21 08:00:49 PM PST 24
Finished Jan 21 08:03:48 PM PST 24
Peak memory 282800 kb
Host smart-33c0afe1-c764-442b-8285-11ff96989c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336975203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1336975203
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2199966434
Short name T48
Test name
Test status
Simulation time 35820976 ps
CPU time 1.15 seconds
Started Jan 21 07:53:01 PM PST 24
Finished Jan 21 07:53:04 PM PST 24
Peak memory 219328 kb
Host smart-48c540fd-e5f8-4ee5-9115-180197db3160
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199966434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2199966434
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.354762972
Short name T517
Test name
Test status
Simulation time 12298794 ps
CPU time 0.74 seconds
Started Jan 21 08:00:02 PM PST 24
Finished Jan 21 08:00:08 PM PST 24
Peak memory 206736 kb
Host smart-91381869-a894-4499-94f1-71318a384502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354762972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.354762972
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.973160092
Short name T243
Test name
Test status
Simulation time 413916746 ps
CPU time 12.77 seconds
Started Jan 21 09:55:33 PM PST 24
Finished Jan 21 09:55:56 PM PST 24
Peak memory 215972 kb
Host smart-7d00b3c1-fd42-493c-989a-7b49fec53954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973160092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.973160092
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3699245216
Short name T353
Test name
Test status
Simulation time 87540222101 ps
CPU time 581.03 seconds
Started Jan 21 07:57:29 PM PST 24
Finished Jan 21 08:07:12 PM PST 24
Peak memory 317456 kb
Host smart-f2c279f1-ec55-42de-a3d4-19955c8aeefc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699245216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3699245216
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3801479421
Short name T170
Test name
Test status
Simulation time 3446026131 ps
CPU time 25.3 seconds
Started Jan 21 09:55:01 PM PST 24
Finished Jan 21 09:55:31 PM PST 24
Peak memory 216768 kb
Host smart-82ebd686-a528-4c43-be9a-5a3c5f59166e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801479421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3801479421
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_intr.1972163412
Short name T38
Test name
Test status
Simulation time 37531313548 ps
CPU time 135.72 seconds
Started Jan 21 08:01:25 PM PST 24
Finished Jan 21 08:03:42 PM PST 24
Peak memory 254508 kb
Host smart-6a20f479-2d95-4937-b037-777940a17b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972163412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intr.1972163412
Directory /workspace/24.spi_device_intr/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.149842239
Short name T282
Test name
Test status
Simulation time 3191706521 ps
CPU time 20.52 seconds
Started Jan 21 07:54:32 PM PST 24
Finished Jan 21 07:54:55 PM PST 24
Peak memory 237720 kb
Host smart-745d96dc-61e1-4add-ac5d-e0db2ea03ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149842239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.149842239
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1297345731
Short name T425
Test name
Test status
Simulation time 66543352 ps
CPU time 4.41 seconds
Started Jan 21 09:54:16 PM PST 24
Finished Jan 21 09:54:37 PM PST 24
Peak memory 217144 kb
Host smart-75918266-8010-4c0e-a5e8-2d3e4bb6b111
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297345731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
297345731
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2676858865
Short name T87
Test name
Test status
Simulation time 29883745 ps
CPU time 0.76 seconds
Started Jan 21 09:56:05 PM PST 24
Finished Jan 21 09:56:08 PM PST 24
Peak memory 204832 kb
Host smart-b12a7159-ca9b-4ab7-ac69-ca83e48f92ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676858865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2676858865
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.939145228
Short name T56
Test name
Test status
Simulation time 210359476197 ps
CPU time 278.52 seconds
Started Jan 21 07:55:39 PM PST 24
Finished Jan 21 08:00:19 PM PST 24
Peak memory 333196 kb
Host smart-bf1fe140-a45b-44cf-89ce-a589a388ccaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939145228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_underflow_overfl
ow.939145228
Directory /workspace/10.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3224817013
Short name T329
Test name
Test status
Simulation time 46866355826 ps
CPU time 148.95 seconds
Started Jan 21 07:58:47 PM PST 24
Finished Jan 21 08:01:17 PM PST 24
Peak memory 258392 kb
Host smart-c26e4166-6fa2-461f-874c-23ba2df668bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224817013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3224817013
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1031693583
Short name T348
Test name
Test status
Simulation time 75749754168 ps
CPU time 201.04 seconds
Started Jan 21 08:02:54 PM PST 24
Finished Jan 21 08:06:46 PM PST 24
Peak memory 283112 kb
Host smart-feb7f0ef-7ec0-4a2e-ac5c-2c7355fb7723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031693583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1031693583
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_intr.4030582641
Short name T503
Test name
Test status
Simulation time 11883094154 ps
CPU time 24.74 seconds
Started Jan 21 08:13:55 PM PST 24
Finished Jan 21 08:14:21 PM PST 24
Peak memory 240376 kb
Host smart-e95cd48a-a825-4bbc-a176-ac03705ebdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030582641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intr.4030582641
Directory /workspace/43.spi_device_intr/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3446631464
Short name T361
Test name
Test status
Simulation time 6204333718 ps
CPU time 70.91 seconds
Started Jan 21 07:55:10 PM PST 24
Finished Jan 21 07:56:23 PM PST 24
Peak memory 267420 kb
Host smart-c2c2c8e6-12e9-48ad-83b2-3e311e18a5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446631464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3446631464
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3643613240
Short name T157
Test name
Test status
Simulation time 883276024 ps
CPU time 8.57 seconds
Started Jan 21 08:00:53 PM PST 24
Finished Jan 21 08:01:06 PM PST 24
Peak memory 240028 kb
Host smart-92daf595-64f0-419e-abb6-b9b43a37e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643613240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3643613240
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4130428583
Short name T81
Test name
Test status
Simulation time 63412476 ps
CPU time 1.88 seconds
Started Jan 21 09:54:20 PM PST 24
Finished Jan 21 09:54:37 PM PST 24
Peak memory 217348 kb
Host smart-f288a0c4-d43b-42ed-a423-e6f0f67011eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130428583 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4130428583
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.268299621
Short name T456
Test name
Test status
Simulation time 837365171 ps
CPU time 24.85 seconds
Started Jan 21 09:54:14 PM PST 24
Finished Jan 21 09:54:57 PM PST 24
Peak memory 215956 kb
Host smart-7188833d-456f-4601-ac17-42f2f4d81a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268299621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.268299621
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2505212431
Short name T239
Test name
Test status
Simulation time 23744513539 ps
CPU time 220.58 seconds
Started Jan 21 07:53:11 PM PST 24
Finished Jan 21 07:56:54 PM PST 24
Peak memory 258452 kb
Host smart-fcbb7e62-fb82-47c3-babb-31fa98a5e979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505212431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2505212431
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_extreme_fifo_size.4237383482
Short name T294
Test name
Test status
Simulation time 83480060612 ps
CPU time 1379.97 seconds
Started Jan 21 08:58:44 PM PST 24
Finished Jan 21 09:22:12 PM PST 24
Peak memory 221820 kb
Host smart-d7dbe5a4-415d-4048-88f1-0e42521552ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237383482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_extreme_fifo_size.4237383482
Directory /workspace/10.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2372216141
Short name T358
Test name
Test status
Simulation time 178645573144 ps
CPU time 2319.75 seconds
Started Jan 21 07:56:00 PM PST 24
Finished Jan 21 08:34:41 PM PST 24
Peak memory 332524 kb
Host smart-997bb966-456a-4712-bca4-ca04585fc717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372216141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2372216141
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.4060893999
Short name T1093
Test name
Test status
Simulation time 334537196 ps
CPU time 8.85 seconds
Started Jan 21 07:58:01 PM PST 24
Finished Jan 21 07:58:12 PM PST 24
Peak memory 241152 kb
Host smart-14224d4d-f307-481d-9cf0-cfc2bcd1b49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060893999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4060893999
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2988261983
Short name T1540
Test name
Test status
Simulation time 294287024768 ps
CPU time 618.32 seconds
Started Jan 21 07:58:22 PM PST 24
Finished Jan 21 08:08:42 PM PST 24
Peak memory 288692 kb
Host smart-64ebf82d-acf0-48d5-8f0a-5d66d3456e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988261983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2988261983
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2964425523
Short name T1607
Test name
Test status
Simulation time 735826657899 ps
CPU time 316.8 seconds
Started Jan 21 07:59:04 PM PST 24
Finished Jan 21 08:04:22 PM PST 24
Peak memory 266564 kb
Host smart-d4f02296-146a-4451-855a-52efaf7369a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964425523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2964425523
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_intr.3489740327
Short name T227
Test name
Test status
Simulation time 148909272519 ps
CPU time 159.27 seconds
Started Jan 21 08:00:01 PM PST 24
Finished Jan 21 08:02:46 PM PST 24
Peak memory 254044 kb
Host smart-862bdf55-8313-4619-ad5e-84af33124d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489740327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intr.3489740327
Directory /workspace/21.spi_device_intr/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1034078662
Short name T313
Test name
Test status
Simulation time 67140125120 ps
CPU time 267.03 seconds
Started Jan 21 08:11:06 PM PST 24
Finished Jan 21 08:15:39 PM PST 24
Peak memory 264376 kb
Host smart-cd27f1aa-2d02-40a5-86da-f90858db8407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034078662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1034078662
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3745100805
Short name T221
Test name
Test status
Simulation time 153630644335 ps
CPU time 3038.92 seconds
Started Jan 21 07:54:58 PM PST 24
Finished Jan 21 08:45:39 PM PST 24
Peak memory 273544 kb
Host smart-d68ea24c-cdea-4283-9c20-d7d98149c6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745100805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3745100805
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_abort.634037717
Short name T562
Test name
Test status
Simulation time 15009063 ps
CPU time 0.77 seconds
Started Jan 21 07:58:38 PM PST 24
Finished Jan 21 07:58:40 PM PST 24
Peak memory 207076 kb
Host smart-f9d0c3a5-5e2f-4cac-b230-937cdecefd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634037717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_abort.634037717
Directory /workspace/17.spi_device_abort/latest

Test location /workspace/coverage/default/0.spi_device_rx_async_fifo_reset.2710937376
Short name T152
Test name
Test status
Simulation time 27524912 ps
CPU time 0.96 seconds
Started Jan 21 07:53:03 PM PST 24
Finished Jan 21 07:53:08 PM PST 24
Peak memory 208784 kb
Host smart-c365e795-5119-47af-838c-883873dbe7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710937376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_async_fifo_reset.2710937376
Directory /workspace/0.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_tx_async_fifo_reset.2877918023
Short name T164
Test name
Test status
Simulation time 21505456 ps
CPU time 0.85 seconds
Started Jan 21 07:53:07 PM PST 24
Finished Jan 21 07:53:11 PM PST 24
Peak memory 207652 kb
Host smart-b455c797-783d-4ca6-81e8-969eb34b28f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877918023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tx_async_fifo_reset.2877918023
Directory /workspace/0.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_upload.3832765323
Short name T218
Test name
Test status
Simulation time 826425241 ps
CPU time 7.46 seconds
Started Jan 21 07:57:54 PM PST 24
Finished Jan 21 07:58:04 PM PST 24
Peak memory 240628 kb
Host smart-7bd69ca1-97b7-4cbe-8eac-f6ce95760a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832765323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3832765323
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_dummy_item_extra_dly.3844427143
Short name T100
Test name
Test status
Simulation time 25914011783 ps
CPU time 368.52 seconds
Started Jan 21 07:58:09 PM PST 24
Finished Jan 21 08:04:18 PM PST 24
Peak memory 274340 kb
Host smart-e78c4155-95f9-4fae-b01d-813879e3f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844427143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_dummy_item_extra_dly.3844427143
Directory /workspace/16.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3916670638
Short name T193
Test name
Test status
Simulation time 1033228813 ps
CPU time 18.62 seconds
Started Jan 21 09:54:21 PM PST 24
Finished Jan 21 09:54:54 PM PST 24
Peak memory 215932 kb
Host smart-f63d7692-58a1-4da8-a3e4-3e3b3da74525
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916670638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3916670638
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2735160713
Short name T386
Test name
Test status
Simulation time 2793412051 ps
CPU time 14.66 seconds
Started Jan 21 09:54:17 PM PST 24
Finished Jan 21 09:54:48 PM PST 24
Peak memory 207844 kb
Host smart-453b05f1-0eb2-46a7-b8fe-88a56f9c187f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735160713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2735160713
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.597285142
Short name T427
Test name
Test status
Simulation time 144575896 ps
CPU time 1.28 seconds
Started Jan 21 09:54:14 PM PST 24
Finished Jan 21 09:54:33 PM PST 24
Peak memory 215896 kb
Host smart-3c2aca8f-c210-4806-96f2-27a4cb625421
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597285142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.597285142
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2206919976
Short name T195
Test name
Test status
Simulation time 83840315 ps
CPU time 2.24 seconds
Started Jan 21 09:54:21 PM PST 24
Finished Jan 21 09:54:38 PM PST 24
Peak memory 207752 kb
Host smart-97a3316a-ac5c-4c0c-b316-2932c07f0d13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206919976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
206919976
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3987155063
Short name T392
Test name
Test status
Simulation time 42339097 ps
CPU time 0.72 seconds
Started Jan 21 09:54:16 PM PST 24
Finished Jan 21 09:54:34 PM PST 24
Peak memory 204772 kb
Host smart-f564fb1c-a639-4b3c-97e6-327f64a82ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987155063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
987155063
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.635299100
Short name T194
Test name
Test status
Simulation time 54081561 ps
CPU time 4.61 seconds
Started Jan 21 09:54:15 PM PST 24
Finished Jan 21 09:54:37 PM PST 24
Peak memory 215904 kb
Host smart-ff539868-8cc2-427e-9af7-3df3b25c3e46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635299100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.635299100
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1057336455
Short name T377
Test name
Test status
Simulation time 205478788 ps
CPU time 12.75 seconds
Started Jan 21 09:54:12 PM PST 24
Finished Jan 21 09:54:42 PM PST 24
Peak memory 215876 kb
Host smart-34533995-47ca-4618-973e-ba10a57a38f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057336455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1057336455
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2456777598
Short name T186
Test name
Test status
Simulation time 165890181 ps
CPU time 4.3 seconds
Started Jan 21 09:54:20 PM PST 24
Finished Jan 21 09:54:40 PM PST 24
Peak memory 215936 kb
Host smart-8b2cf66e-cb70-4968-b388-f9d30e4c089d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456777598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2456777598
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4035835543
Short name T471
Test name
Test status
Simulation time 1021145526 ps
CPU time 20.73 seconds
Started Jan 21 09:54:19 PM PST 24
Finished Jan 21 09:54:56 PM PST 24
Peak memory 216952 kb
Host smart-a45f5840-2dd9-4667-a286-072e7e970d91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035835543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4035835543
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1303203789
Short name T397
Test name
Test status
Simulation time 3981151398 ps
CPU time 30.81 seconds
Started Jan 21 09:54:24 PM PST 24
Finished Jan 21 09:55:08 PM PST 24
Peak memory 207792 kb
Host smart-31eb4429-eda6-4b36-8085-cbb1837b8fe9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303203789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1303203789
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.67150007
Short name T78
Test name
Test status
Simulation time 86541759 ps
CPU time 1.51 seconds
Started Jan 21 09:54:20 PM PST 24
Finished Jan 21 09:54:37 PM PST 24
Peak memory 207716 kb
Host smart-ac314d01-8123-4c37-a15e-4062484931c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67150007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
hw_reset.67150007
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1072278109
Short name T459
Test name
Test status
Simulation time 16019399 ps
CPU time 1.36 seconds
Started Jan 21 09:54:30 PM PST 24
Finished Jan 21 09:54:45 PM PST 24
Peak memory 216956 kb
Host smart-3f9e2aa5-5871-4d53-8b05-7f2b679c6b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072278109 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1072278109
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3833316864
Short name T106
Test name
Test status
Simulation time 29562148 ps
CPU time 1.8 seconds
Started Jan 21 09:54:19 PM PST 24
Finished Jan 21 09:54:37 PM PST 24
Peak memory 215972 kb
Host smart-b7d452bf-f662-4f15-bdda-4a14b43a4011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833316864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
833316864
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3163248951
Short name T175
Test name
Test status
Simulation time 11982226 ps
CPU time 0.74 seconds
Started Jan 21 09:54:20 PM PST 24
Finished Jan 21 09:54:36 PM PST 24
Peak memory 204812 kb
Host smart-9deef447-d7fa-4030-a0d5-8efda069f2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163248951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
163248951
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2102688938
Short name T478
Test name
Test status
Simulation time 352549947 ps
CPU time 2.55 seconds
Started Jan 21 09:54:24 PM PST 24
Finished Jan 21 09:54:40 PM PST 24
Peak memory 215852 kb
Host smart-aadbb1d5-e1f7-4a40-b39c-20665067a7d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102688938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2102688938
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4007755316
Short name T433
Test name
Test status
Simulation time 348191442 ps
CPU time 6.37 seconds
Started Jan 21 09:54:24 PM PST 24
Finished Jan 21 09:54:44 PM PST 24
Peak memory 215864 kb
Host smart-df4d80be-0201-4b68-9548-973ffe56f266
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007755316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4007755316
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4217560174
Short name T414
Test name
Test status
Simulation time 457593103 ps
CPU time 2.17 seconds
Started Jan 21 09:54:20 PM PST 24
Finished Jan 21 09:54:38 PM PST 24
Peak memory 216004 kb
Host smart-f971db58-5492-405e-aa4e-0d7e286778a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217560174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4217560174
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2506660843
Short name T83
Test name
Test status
Simulation time 347197894 ps
CPU time 5.37 seconds
Started Jan 21 09:54:20 PM PST 24
Finished Jan 21 09:54:41 PM PST 24
Peak memory 216108 kb
Host smart-745f0fd1-6ea1-45e6-a6af-0ed2002fd7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506660843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
506660843
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3783183532
Short name T177
Test name
Test status
Simulation time 154116148 ps
CPU time 6.56 seconds
Started Jan 21 09:54:20 PM PST 24
Finished Jan 21 09:54:42 PM PST 24
Peak memory 216016 kb
Host smart-aed550c3-48de-4f38-86db-69786e1e25c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783183532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3783183532
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1334360523
Short name T409
Test name
Test status
Simulation time 182094433 ps
CPU time 1.52 seconds
Started Jan 21 09:55:28 PM PST 24
Finished Jan 21 09:55:41 PM PST 24
Peak memory 217736 kb
Host smart-95100577-4ef9-46b1-94b4-5bb239fc9b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334360523 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1334360523
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4246092276
Short name T183
Test name
Test status
Simulation time 95283456 ps
CPU time 1.88 seconds
Started Jan 21 10:14:45 PM PST 24
Finished Jan 21 10:14:58 PM PST 24
Peak memory 215900 kb
Host smart-f3dfddee-5adc-421a-b0de-995a67c36cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246092276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4246092276
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1408024305
Short name T209
Test name
Test status
Simulation time 96594108 ps
CPU time 0.71 seconds
Started Jan 21 11:20:48 PM PST 24
Finished Jan 21 11:20:57 PM PST 24
Peak memory 204920 kb
Host smart-c5d3fa38-e296-465f-9fd0-0147d6694e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408024305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1408024305
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2946733178
Short name T207
Test name
Test status
Simulation time 845600130 ps
CPU time 3.19 seconds
Started Jan 21 09:55:19 PM PST 24
Finished Jan 21 09:55:34 PM PST 24
Peak memory 215884 kb
Host smart-0776f0e4-77b6-41b6-a1c8-1a0dbaf974e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946733178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2946733178
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1545828100
Short name T403
Test name
Test status
Simulation time 289472962 ps
CPU time 2.39 seconds
Started Jan 21 10:38:22 PM PST 24
Finished Jan 21 10:38:26 PM PST 24
Peak memory 216136 kb
Host smart-c442804b-1203-4e37-9135-838437fea383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545828100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1545828100
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3775942759
Short name T391
Test name
Test status
Simulation time 442813859 ps
CPU time 8.54 seconds
Started Jan 21 10:30:40 PM PST 24
Finished Jan 21 10:30:53 PM PST 24
Peak memory 215992 kb
Host smart-5e7c2a74-e0a2-430b-8866-c419ba1677f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775942759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3775942759
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3758581355
Short name T475
Test name
Test status
Simulation time 43397074 ps
CPU time 1.52 seconds
Started Jan 21 09:55:27 PM PST 24
Finished Jan 21 09:55:41 PM PST 24
Peak memory 217276 kb
Host smart-06387541-fdcb-4793-99a5-c29d8e3a44d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758581355 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3758581355
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2889202040
Short name T428
Test name
Test status
Simulation time 38377443 ps
CPU time 1.5 seconds
Started Jan 21 09:55:32 PM PST 24
Finished Jan 21 09:55:44 PM PST 24
Peak memory 216004 kb
Host smart-4d4093c0-8e87-44de-88dc-a14bec07c39d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889202040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2889202040
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3607146884
Short name T395
Test name
Test status
Simulation time 15159418 ps
CPU time 0.77 seconds
Started Jan 21 09:55:30 PM PST 24
Finished Jan 21 09:55:42 PM PST 24
Peak memory 204752 kb
Host smart-c5c7968c-6cdf-4f21-8efe-64b66c1b6a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607146884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3607146884
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2892927587
Short name T171
Test name
Test status
Simulation time 104618037 ps
CPU time 1.92 seconds
Started Jan 21 09:55:30 PM PST 24
Finished Jan 21 09:55:44 PM PST 24
Peak memory 215900 kb
Host smart-aab8ae4d-43ab-4adc-a51b-86c3c715e394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892927587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2892927587
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3368986987
Short name T432
Test name
Test status
Simulation time 188278572 ps
CPU time 5.31 seconds
Started Jan 21 09:55:30 PM PST 24
Finished Jan 21 09:55:47 PM PST 24
Peak memory 216120 kb
Host smart-0c8c63c9-cc10-4159-b354-58ec004f6f03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368986987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3368986987
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1454010679
Short name T178
Test name
Test status
Simulation time 872307320 ps
CPU time 12.63 seconds
Started Jan 21 09:55:26 PM PST 24
Finished Jan 21 09:55:50 PM PST 24
Peak memory 216548 kb
Host smart-920ab53c-e428-4219-9029-ca776007b2b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454010679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1454010679
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1785088052
Short name T462
Test name
Test status
Simulation time 50078660 ps
CPU time 2.28 seconds
Started Jan 21 09:55:30 PM PST 24
Finished Jan 21 09:55:44 PM PST 24
Peak memory 217912 kb
Host smart-3315ad81-b777-47f2-affd-a4fc5e87b8c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785088052 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1785088052
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1320922378
Short name T394
Test name
Test status
Simulation time 420701890 ps
CPU time 1.98 seconds
Started Jan 21 09:55:31 PM PST 24
Finished Jan 21 09:55:44 PM PST 24
Peak memory 215968 kb
Host smart-db0959d2-1215-4949-803b-96e287186064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320922378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1320922378
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4091848329
Short name T383
Test name
Test status
Simulation time 14619968 ps
CPU time 0.74 seconds
Started Jan 21 09:55:29 PM PST 24
Finished Jan 21 09:55:41 PM PST 24
Peak memory 204816 kb
Host smart-1fc2b0cc-6157-4939-b11d-dc0362214030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091848329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4091848329
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3785828091
Short name T455
Test name
Test status
Simulation time 91342598 ps
CPU time 2.23 seconds
Started Jan 21 09:55:32 PM PST 24
Finished Jan 21 09:55:44 PM PST 24
Peak memory 215912 kb
Host smart-e887a54e-6ebc-4388-8eff-03d2776a0d2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785828091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3785828091
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.921185772
Short name T143
Test name
Test status
Simulation time 181400747 ps
CPU time 3.31 seconds
Started Jan 21 09:55:29 PM PST 24
Finished Jan 21 09:55:44 PM PST 24
Peak memory 216176 kb
Host smart-53dcc51e-5f91-45a8-8d08-ba8880fcd934
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921185772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.921185772
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2624104223
Short name T240
Test name
Test status
Simulation time 113780566 ps
CPU time 7.46 seconds
Started Jan 21 10:30:54 PM PST 24
Finished Jan 21 10:31:04 PM PST 24
Peak memory 215912 kb
Host smart-3c0e5f63-f00d-4ebb-a7de-7d3affd5db7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624104223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2624104223
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1642540526
Short name T457
Test name
Test status
Simulation time 162595928 ps
CPU time 2.65 seconds
Started Jan 21 09:55:35 PM PST 24
Finished Jan 21 09:55:47 PM PST 24
Peak memory 219228 kb
Host smart-bab6b961-dae9-4272-82ba-8c68d380032b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642540526 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1642540526
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1247086664
Short name T172
Test name
Test status
Simulation time 101592023 ps
CPU time 2.94 seconds
Started Jan 21 09:55:31 PM PST 24
Finished Jan 21 09:55:45 PM PST 24
Peak memory 215992 kb
Host smart-10203086-78f9-40cf-9896-2df2735ec614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247086664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1247086664
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1516223846
Short name T174
Test name
Test status
Simulation time 14458145 ps
CPU time 0.72 seconds
Started Jan 21 09:55:30 PM PST 24
Finished Jan 21 09:55:42 PM PST 24
Peak memory 204788 kb
Host smart-fbb9ff5e-53e9-4712-9c41-06170e1e3fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516223846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1516223846
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.701919141
Short name T430
Test name
Test status
Simulation time 441943398 ps
CPU time 5.23 seconds
Started Jan 21 09:55:27 PM PST 24
Finished Jan 21 09:55:43 PM PST 24
Peak memory 216272 kb
Host smart-4ef028dc-be74-47a3-a3ec-79868e84d3e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701919141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.701919141
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3068818604
Short name T135
Test name
Test status
Simulation time 624910254 ps
CPU time 8.05 seconds
Started Jan 21 09:55:28 PM PST 24
Finished Jan 21 09:55:47 PM PST 24
Peak memory 216788 kb
Host smart-43da5440-c20a-4e7d-accd-72c1e1472ec5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068818604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3068818604
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2405927684
Short name T399
Test name
Test status
Simulation time 90314478 ps
CPU time 2.56 seconds
Started Jan 21 09:55:36 PM PST 24
Finished Jan 21 09:55:47 PM PST 24
Peak memory 218752 kb
Host smart-904f913d-3753-4760-bd28-88212a766733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405927684 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2405927684
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.662698470
Short name T80
Test name
Test status
Simulation time 38838154 ps
CPU time 0.74 seconds
Started Jan 21 09:55:41 PM PST 24
Finished Jan 21 09:55:49 PM PST 24
Peak memory 204812 kb
Host smart-7c771cdf-afd3-4116-a590-24e8201c5d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662698470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.662698470
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.338397950
Short name T415
Test name
Test status
Simulation time 277132057 ps
CPU time 1.9 seconds
Started Jan 21 09:55:37 PM PST 24
Finished Jan 21 09:55:48 PM PST 24
Peak memory 207864 kb
Host smart-53503357-c1ea-4a9c-9114-c450993efacb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338397950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.338397950
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3687053282
Short name T141
Test name
Test status
Simulation time 362875789 ps
CPU time 4.95 seconds
Started Jan 21 09:55:41 PM PST 24
Finished Jan 21 09:55:53 PM PST 24
Peak memory 216188 kb
Host smart-b9eceb24-52f5-4e7a-90b7-55950679d5a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687053282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3687053282
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.142812907
Short name T241
Test name
Test status
Simulation time 1122432416 ps
CPU time 16.69 seconds
Started Jan 21 09:55:36 PM PST 24
Finished Jan 21 09:56:02 PM PST 24
Peak memory 215912 kb
Host smart-ef0f589d-744e-4f44-951c-513a1a67681d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142812907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.142812907
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1043197184
Short name T212
Test name
Test status
Simulation time 44005614 ps
CPU time 2.68 seconds
Started Jan 21 11:10:14 PM PST 24
Finished Jan 21 11:10:19 PM PST 24
Peak memory 219344 kb
Host smart-90037c6a-57aa-443b-99df-030cff89d174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043197184 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1043197184
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4079876717
Short name T441
Test name
Test status
Simulation time 35605902 ps
CPU time 1.26 seconds
Started Jan 21 09:55:34 PM PST 24
Finished Jan 21 09:55:45 PM PST 24
Peak memory 215924 kb
Host smart-b2828928-30d8-4005-9539-e4450afed23f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079876717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4079876717
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4096623825
Short name T382
Test name
Test status
Simulation time 26086792 ps
CPU time 0.73 seconds
Started Jan 21 10:23:48 PM PST 24
Finished Jan 21 10:23:53 PM PST 24
Peak memory 204832 kb
Host smart-bf11d3d8-6ff7-47f3-9eac-9777c6eca225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096623825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4096623825
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.557022532
Short name T211
Test name
Test status
Simulation time 628677598 ps
CPU time 2.15 seconds
Started Jan 21 09:55:35 PM PST 24
Finished Jan 21 09:55:47 PM PST 24
Peak memory 207768 kb
Host smart-443b6a27-37d7-4195-a86b-8ff4c0e9af01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557022532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.557022532
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4164710340
Short name T398
Test name
Test status
Simulation time 256463360 ps
CPU time 3.58 seconds
Started Jan 21 09:55:36 PM PST 24
Finished Jan 21 09:55:48 PM PST 24
Peak memory 216108 kb
Host smart-e9b3caac-557f-457d-b0f7-49070bf7bc1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164710340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4164710340
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.657940121
Short name T245
Test name
Test status
Simulation time 453298809 ps
CPU time 7.19 seconds
Started Jan 21 09:55:35 PM PST 24
Finished Jan 21 09:55:52 PM PST 24
Peak memory 215920 kb
Host smart-2e055d4a-b788-46e8-8f73-9097644eb64d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657940121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.657940121
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.324090515
Short name T379
Test name
Test status
Simulation time 23730410 ps
CPU time 1.78 seconds
Started Jan 21 09:55:44 PM PST 24
Finished Jan 21 09:55:53 PM PST 24
Peak memory 217440 kb
Host smart-e871a0d0-d934-4b5d-a02d-eda58d4fb71a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324090515 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.324090515
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1289554681
Short name T469
Test name
Test status
Simulation time 35663355 ps
CPU time 1.29 seconds
Started Jan 21 09:55:36 PM PST 24
Finished Jan 21 09:55:47 PM PST 24
Peak memory 207744 kb
Host smart-c5692aac-ee95-469a-b144-595f9ea95974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289554681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1289554681
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1328026366
Short name T228
Test name
Test status
Simulation time 14223775 ps
CPU time 0.74 seconds
Started Jan 21 09:55:35 PM PST 24
Finished Jan 21 09:55:45 PM PST 24
Peak memory 204820 kb
Host smart-a009f03b-beb6-4624-8aaf-e6e5af2d090a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328026366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1328026366
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3074653055
Short name T412
Test name
Test status
Simulation time 42796744 ps
CPU time 1.84 seconds
Started Jan 21 09:55:35 PM PST 24
Finished Jan 21 09:55:46 PM PST 24
Peak memory 215972 kb
Host smart-c679905b-ff32-4cec-b1ab-19f282384a41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074653055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3074653055
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.598071670
Short name T429
Test name
Test status
Simulation time 448303317 ps
CPU time 3.1 seconds
Started Jan 21 09:55:34 PM PST 24
Finished Jan 21 09:55:46 PM PST 24
Peak memory 216184 kb
Host smart-0594eeaa-e9a0-4d4c-9c6e-51610211fb63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598071670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.598071670
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1953966864
Short name T214
Test name
Test status
Simulation time 146723387 ps
CPU time 2.13 seconds
Started Jan 21 09:55:44 PM PST 24
Finished Jan 21 09:55:53 PM PST 24
Peak memory 218424 kb
Host smart-be3659f4-2c49-4757-9fde-ecdff1fc565a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953966864 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1953966864
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.853638295
Short name T192
Test name
Test status
Simulation time 167575323 ps
CPU time 1.3 seconds
Started Jan 21 09:55:44 PM PST 24
Finished Jan 21 09:55:52 PM PST 24
Peak memory 216040 kb
Host smart-f05b918f-a46e-41a4-a51f-c9d87afcfd67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853638295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.853638295
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3165535478
Short name T446
Test name
Test status
Simulation time 14324132 ps
CPU time 0.74 seconds
Started Jan 21 09:55:45 PM PST 24
Finished Jan 21 09:55:52 PM PST 24
Peak memory 204840 kb
Host smart-b679fd31-3863-4668-bc83-96366714139c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165535478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3165535478
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2468116329
Short name T452
Test name
Test status
Simulation time 1013723778 ps
CPU time 4.05 seconds
Started Jan 21 09:55:44 PM PST 24
Finished Jan 21 09:55:55 PM PST 24
Peak memory 215996 kb
Host smart-ae442fb1-7ce1-4a72-8189-04c6ff79dd60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468116329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2468116329
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.828260315
Short name T445
Test name
Test status
Simulation time 278474678 ps
CPU time 4.15 seconds
Started Jan 21 09:55:45 PM PST 24
Finished Jan 21 09:55:55 PM PST 24
Peak memory 216108 kb
Host smart-19e7ac0f-60fb-40ab-92ce-4742f455adf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828260315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.828260315
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2772002269
Short name T477
Test name
Test status
Simulation time 997353101 ps
CPU time 22.81 seconds
Started Jan 21 09:55:44 PM PST 24
Finished Jan 21 09:56:14 PM PST 24
Peak memory 216540 kb
Host smart-6e78ec5a-b07f-4538-ae1c-76598c9b6280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772002269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2772002269
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2368005454
Short name T436
Test name
Test status
Simulation time 135321321 ps
CPU time 1.27 seconds
Started Jan 21 09:55:51 PM PST 24
Finished Jan 21 09:55:57 PM PST 24
Peak memory 217228 kb
Host smart-7cc16eff-eb9b-40f0-9e91-c17054b62197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368005454 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2368005454
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4285448402
Short name T461
Test name
Test status
Simulation time 276862198 ps
CPU time 2.47 seconds
Started Jan 21 09:55:47 PM PST 24
Finished Jan 21 09:55:55 PM PST 24
Peak memory 215652 kb
Host smart-ea0ee117-d0d8-4fbc-87bc-71b23d5829e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285448402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4285448402
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2426687670
Short name T388
Test name
Test status
Simulation time 13143674 ps
CPU time 0.7 seconds
Started Jan 21 09:55:40 PM PST 24
Finished Jan 21 09:55:48 PM PST 24
Peak memory 204480 kb
Host smart-be21f92c-b75f-4ee0-987f-50b9392bdf80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426687670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2426687670
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.821273054
Short name T396
Test name
Test status
Simulation time 82295406 ps
CPU time 1.91 seconds
Started Jan 21 09:55:51 PM PST 24
Finished Jan 21 09:55:58 PM PST 24
Peak memory 215912 kb
Host smart-eea99094-ab61-43d8-aa1b-5b923aa44c04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821273054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.821273054
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4225546696
Short name T416
Test name
Test status
Simulation time 169865638 ps
CPU time 3.65 seconds
Started Jan 21 09:55:51 PM PST 24
Finished Jan 21 09:56:00 PM PST 24
Peak memory 217200 kb
Host smart-c5186a7b-0772-486d-b891-e0a6a0b60db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225546696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4225546696
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.359561980
Short name T176
Test name
Test status
Simulation time 775345124 ps
CPU time 18.05 seconds
Started Jan 21 09:55:43 PM PST 24
Finished Jan 21 09:56:08 PM PST 24
Peak memory 215956 kb
Host smart-6fcc84b5-2cc1-4cac-ade6-0ee5e27d7fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359561980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.359561980
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4124952312
Short name T458
Test name
Test status
Simulation time 85770655 ps
CPU time 1.78 seconds
Started Jan 21 09:55:43 PM PST 24
Finished Jan 21 09:55:52 PM PST 24
Peak memory 218364 kb
Host smart-3cea0095-553f-45ce-af30-992caf4ccf1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124952312 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4124952312
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2486261409
Short name T422
Test name
Test status
Simulation time 136724710 ps
CPU time 2.63 seconds
Started Jan 21 09:55:46 PM PST 24
Finished Jan 21 09:55:55 PM PST 24
Peak memory 215716 kb
Host smart-eb06023d-d84b-4d9c-83f3-44e807c05de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486261409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2486261409
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3336494681
Short name T216
Test name
Test status
Simulation time 51968138 ps
CPU time 0.76 seconds
Started Jan 21 09:55:45 PM PST 24
Finished Jan 21 09:55:52 PM PST 24
Peak memory 204756 kb
Host smart-0f80349a-27b6-4e09-93fb-0a5a6b9621b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336494681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3336494681
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3565629797
Short name T105
Test name
Test status
Simulation time 28524210 ps
CPU time 1.86 seconds
Started Jan 21 09:55:46 PM PST 24
Finished Jan 21 09:55:54 PM PST 24
Peak memory 215948 kb
Host smart-7bbde8fd-1671-4a24-899f-5129c4ba0d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565629797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3565629797
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1370910887
Short name T139
Test name
Test status
Simulation time 96184024 ps
CPU time 3.95 seconds
Started Jan 21 09:55:51 PM PST 24
Finished Jan 21 09:56:00 PM PST 24
Peak memory 216104 kb
Host smart-5d7de58d-293a-4dc5-b3a2-365a9d22eeb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370910887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1370910887
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1626887194
Short name T437
Test name
Test status
Simulation time 699956570 ps
CPU time 25.89 seconds
Started Jan 21 09:54:42 PM PST 24
Finished Jan 21 09:55:16 PM PST 24
Peak memory 215984 kb
Host smart-a0bc8c03-5d1f-4fe4-b341-1aded4f736d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626887194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1626887194
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.213373167
Short name T406
Test name
Test status
Simulation time 2266399692 ps
CPU time 24.87 seconds
Started Jan 21 09:54:41 PM PST 24
Finished Jan 21 09:55:15 PM PST 24
Peak memory 207820 kb
Host smart-51d41bef-b833-48a7-a391-66d90cbd0d97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213373167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.213373167
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1855896
Short name T407
Test name
Test status
Simulation time 50655910 ps
CPU time 1.48 seconds
Started Jan 21 09:54:36 PM PST 24
Finished Jan 21 09:54:49 PM PST 24
Peak memory 207776 kb
Host smart-1a71c49d-523c-48fe-ac85-83326be3d81d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_h
w_reset.1855896
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1328960832
Short name T384
Test name
Test status
Simulation time 92097135 ps
CPU time 2.64 seconds
Started Jan 21 09:54:35 PM PST 24
Finished Jan 21 09:54:49 PM PST 24
Peak memory 219248 kb
Host smart-5346c473-8052-42ab-a023-311daecd401d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328960832 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1328960832
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.908261287
Short name T190
Test name
Test status
Simulation time 20085927 ps
CPU time 1.31 seconds
Started Jan 21 09:54:44 PM PST 24
Finished Jan 21 09:54:53 PM PST 24
Peak memory 216040 kb
Host smart-dfbc1644-8f59-421c-8f89-08b77969d62d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908261287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.908261287
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2549236575
Short name T449
Test name
Test status
Simulation time 47765101 ps
CPU time 0.81 seconds
Started Jan 21 09:54:27 PM PST 24
Finished Jan 21 09:54:40 PM PST 24
Peak memory 204812 kb
Host smart-009ec446-f16a-41dd-b3bc-8697073034ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549236575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
549236575
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2719893643
Short name T188
Test name
Test status
Simulation time 731874252 ps
CPU time 4.89 seconds
Started Jan 21 11:12:33 PM PST 24
Finished Jan 21 11:12:39 PM PST 24
Peak memory 215952 kb
Host smart-b6723442-d4aa-489c-b1e8-fb29bbe921a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719893643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2719893643
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1530678092
Short name T440
Test name
Test status
Simulation time 243734752 ps
CPU time 14.58 seconds
Started Jan 21 09:54:27 PM PST 24
Finished Jan 21 09:54:54 PM PST 24
Peak memory 215864 kb
Host smart-2f596eb1-b2b5-4a76-9656-428c90aead73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530678092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1530678092
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1836514667
Short name T418
Test name
Test status
Simulation time 224152480 ps
CPU time 4.75 seconds
Started Jan 21 09:54:41 PM PST 24
Finished Jan 21 09:54:55 PM PST 24
Peak memory 215948 kb
Host smart-5d242af9-2264-4532-806c-a8bf46cc2bf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836514667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1836514667
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3065370249
Short name T444
Test name
Test status
Simulation time 822161447 ps
CPU time 5.75 seconds
Started Jan 21 09:54:28 PM PST 24
Finished Jan 21 09:54:46 PM PST 24
Peak memory 216168 kb
Host smart-f9eeb944-2c85-4128-b32e-a8633ad43ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065370249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
065370249
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.608021002
Short name T242
Test name
Test status
Simulation time 3440730082 ps
CPU time 23.02 seconds
Started Jan 21 09:54:29 PM PST 24
Finished Jan 21 09:55:06 PM PST 24
Peak memory 216304 kb
Host smart-5a424bea-7281-4e8e-990c-1e323e43af68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608021002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.608021002
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4194161103
Short name T426
Test name
Test status
Simulation time 26175485 ps
CPU time 0.74 seconds
Started Jan 21 10:58:00 PM PST 24
Finished Jan 21 10:58:03 PM PST 24
Peak memory 204932 kb
Host smart-66bbe3bc-f5d4-4cd3-9ebe-e00da59cf4ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194161103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4194161103
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1112278045
Short name T185
Test name
Test status
Simulation time 15897371 ps
CPU time 0.75 seconds
Started Jan 21 10:55:51 PM PST 24
Finished Jan 21 10:55:53 PM PST 24
Peak memory 204860 kb
Host smart-eac76b17-265c-43b0-a4f0-bc58299f1c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112278045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1112278045
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2850236836
Short name T378
Test name
Test status
Simulation time 39713309 ps
CPU time 0.72 seconds
Started Jan 21 09:55:51 PM PST 24
Finished Jan 21 09:55:56 PM PST 24
Peak memory 204808 kb
Host smart-15aab833-6d91-41ca-ad4b-8aeb85e95367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850236836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2850236836
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2868330907
Short name T381
Test name
Test status
Simulation time 13057665 ps
CPU time 0.7 seconds
Started Jan 21 09:55:53 PM PST 24
Finished Jan 21 09:55:58 PM PST 24
Peak memory 204768 kb
Host smart-b32335ef-f03b-4673-bc63-0b6823f4e1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868330907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2868330907
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3625713688
Short name T380
Test name
Test status
Simulation time 61870866 ps
CPU time 0.77 seconds
Started Jan 21 11:03:53 PM PST 24
Finished Jan 21 11:04:01 PM PST 24
Peak memory 204896 kb
Host smart-e5d1bb0d-20f9-41dc-ba00-248f186a8cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625713688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3625713688
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3779336153
Short name T473
Test name
Test status
Simulation time 26332518 ps
CPU time 0.74 seconds
Started Jan 21 09:55:50 PM PST 24
Finished Jan 21 09:55:55 PM PST 24
Peak memory 204804 kb
Host smart-512f1d22-beb1-4a7e-b8d4-7a840ee2ce05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779336153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3779336153
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2313856235
Short name T413
Test name
Test status
Simulation time 66449738 ps
CPU time 0.76 seconds
Started Jan 21 09:55:53 PM PST 24
Finished Jan 21 09:55:58 PM PST 24
Peak memory 204776 kb
Host smart-aab2e3d4-4329-4c06-b799-819c6cfd1e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313856235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2313856235
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1733886005
Short name T230
Test name
Test status
Simulation time 30294338 ps
CPU time 0.73 seconds
Started Jan 21 09:55:53 PM PST 24
Finished Jan 21 09:55:58 PM PST 24
Peak memory 204828 kb
Host smart-1c01601d-1432-4b8f-9cca-33ed2193defe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733886005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1733886005
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.829233734
Short name T187
Test name
Test status
Simulation time 2586184611 ps
CPU time 17.5 seconds
Started Jan 21 09:54:35 PM PST 24
Finished Jan 21 09:55:04 PM PST 24
Peak memory 207408 kb
Host smart-4ebf290e-6e1f-4158-ba5a-6a32bcf62b99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829233734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.829233734
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1313537311
Short name T479
Test name
Test status
Simulation time 6166823756 ps
CPU time 26.46 seconds
Started Jan 21 09:54:42 PM PST 24
Finished Jan 21 09:55:17 PM PST 24
Peak memory 216028 kb
Host smart-8da99d16-e1de-4909-a380-9581ed4e6572
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313537311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1313537311
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.862084369
Short name T146
Test name
Test status
Simulation time 76712830 ps
CPU time 1.09 seconds
Started Jan 21 09:54:41 PM PST 24
Finished Jan 21 09:54:51 PM PST 24
Peak memory 207592 kb
Host smart-bef6a690-db70-4750-8254-414afab57553
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862084369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.862084369
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2483613458
Short name T191
Test name
Test status
Simulation time 52444437 ps
CPU time 1.38 seconds
Started Jan 21 09:54:47 PM PST 24
Finished Jan 21 09:54:55 PM PST 24
Peak memory 217392 kb
Host smart-db666426-730f-4d09-8302-11638c39cb59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483613458 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2483613458
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.375568616
Short name T404
Test name
Test status
Simulation time 106922690 ps
CPU time 2.84 seconds
Started Jan 21 09:54:39 PM PST 24
Finished Jan 21 09:54:51 PM PST 24
Peak memory 215988 kb
Host smart-6be8299b-2c0d-4039-b5b0-94955088ea40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375568616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.375568616
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3787905446
Short name T419
Test name
Test status
Simulation time 45660619 ps
CPU time 0.85 seconds
Started Jan 21 09:54:38 PM PST 24
Finished Jan 21 09:54:49 PM PST 24
Peak memory 204796 kb
Host smart-df76153e-7f99-47c2-9dbb-c6a8014d6de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787905446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
787905446
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.717308325
Short name T450
Test name
Test status
Simulation time 294845362 ps
CPU time 2.86 seconds
Started Jan 21 09:54:36 PM PST 24
Finished Jan 21 09:54:50 PM PST 24
Peak memory 215912 kb
Host smart-cc1eb7ec-0fc5-4e55-83b5-7d16d772b153
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717308325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.717308325
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.557964347
Short name T451
Test name
Test status
Simulation time 719085528 ps
CPU time 14.78 seconds
Started Jan 21 09:54:37 PM PST 24
Finished Jan 21 09:55:02 PM PST 24
Peak memory 215884 kb
Host smart-3d79b09c-12aa-45f7-a777-a3617d0a6bdb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557964347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.557964347
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3619102004
Short name T389
Test name
Test status
Simulation time 521253198 ps
CPU time 3.51 seconds
Started Jan 21 09:54:36 PM PST 24
Finished Jan 21 09:54:51 PM PST 24
Peak memory 215932 kb
Host smart-9965b20a-bdfc-4b4d-a43d-235f6d1e77d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619102004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3619102004
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4110982043
Short name T476
Test name
Test status
Simulation time 43325787 ps
CPU time 1.56 seconds
Started Jan 21 09:54:34 PM PST 24
Finished Jan 21 09:54:47 PM PST 24
Peak memory 215920 kb
Host smart-febcc05c-e266-430d-b793-89ce9cd00ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110982043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
110982043
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3088616462
Short name T138
Test name
Test status
Simulation time 1339166658 ps
CPU time 15.24 seconds
Started Jan 21 09:54:37 PM PST 24
Finished Jan 21 09:55:03 PM PST 24
Peak memory 216060 kb
Host smart-33f1731a-7ce4-4810-9e85-f71e7d500b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088616462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3088616462
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4268281799
Short name T435
Test name
Test status
Simulation time 183356553 ps
CPU time 0.72 seconds
Started Jan 21 09:55:52 PM PST 24
Finished Jan 21 09:55:57 PM PST 24
Peak memory 204828 kb
Host smart-b827707d-aef8-40d4-9930-c8edac1969d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268281799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4268281799
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3178228316
Short name T400
Test name
Test status
Simulation time 43101274 ps
CPU time 0.75 seconds
Started Jan 21 11:08:40 PM PST 24
Finished Jan 21 11:08:42 PM PST 24
Peak memory 204900 kb
Host smart-566d308e-9724-4b50-991c-724092871ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178228316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3178228316
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3216056519
Short name T454
Test name
Test status
Simulation time 45262190 ps
CPU time 0.72 seconds
Started Jan 21 09:55:51 PM PST 24
Finished Jan 21 09:55:56 PM PST 24
Peak memory 204780 kb
Host smart-0b31cf19-c272-4201-bf7c-c0498b9b9fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216056519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3216056519
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3364202280
Short name T463
Test name
Test status
Simulation time 15226170 ps
CPU time 0.75 seconds
Started Jan 21 09:56:01 PM PST 24
Finished Jan 21 09:56:04 PM PST 24
Peak memory 204772 kb
Host smart-b68dd960-fcc8-486b-8c73-2aa063c8325f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364202280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3364202280
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1397981374
Short name T470
Test name
Test status
Simulation time 13446384 ps
CPU time 0.74 seconds
Started Jan 21 09:56:05 PM PST 24
Finished Jan 21 09:56:08 PM PST 24
Peak memory 204808 kb
Host smart-a7309824-41bd-4980-b762-b2d6652d67d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397981374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1397981374
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3135652798
Short name T213
Test name
Test status
Simulation time 157861125 ps
CPU time 0.78 seconds
Started Jan 21 09:56:08 PM PST 24
Finished Jan 21 09:56:12 PM PST 24
Peak memory 204832 kb
Host smart-4d670611-3cbc-4e66-81df-c973f486e638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135652798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3135652798
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3628909956
Short name T189
Test name
Test status
Simulation time 24134282 ps
CPU time 0.74 seconds
Started Jan 21 09:56:09 PM PST 24
Finished Jan 21 09:56:17 PM PST 24
Peak memory 204820 kb
Host smart-d95861d6-9bb2-402e-af0b-2af5ec7fd21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628909956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3628909956
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1502493811
Short name T79
Test name
Test status
Simulation time 14443919 ps
CPU time 0.71 seconds
Started Jan 21 09:56:05 PM PST 24
Finished Jan 21 09:56:08 PM PST 24
Peak memory 204848 kb
Host smart-7e407c23-47d3-4450-bbc2-4832ce80a089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502493811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1502493811
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.558293534
Short name T393
Test name
Test status
Simulation time 19692804 ps
CPU time 0.71 seconds
Started Jan 21 09:56:06 PM PST 24
Finished Jan 21 09:56:09 PM PST 24
Peak memory 204812 kb
Host smart-178e6dd5-9368-45a3-9891-6db741bbc8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558293534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.558293534
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1525610740
Short name T411
Test name
Test status
Simulation time 257455623 ps
CPU time 16.77 seconds
Started Jan 21 10:24:17 PM PST 24
Finished Jan 21 10:24:37 PM PST 24
Peak memory 216016 kb
Host smart-0ccd49e3-5b48-4580-b48e-223a04db0a98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525610740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1525610740
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.38617636
Short name T173
Test name
Test status
Simulation time 1617919554 ps
CPU time 25.28 seconds
Started Jan 21 10:24:28 PM PST 24
Finished Jan 21 10:24:57 PM PST 24
Peak memory 207900 kb
Host smart-8cfca547-8c8c-4e5b-a082-44bb8b71ff1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38617636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
bit_bash.38617636
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3578733127
Short name T144
Test name
Test status
Simulation time 95546171 ps
CPU time 1.52 seconds
Started Jan 21 09:54:49 PM PST 24
Finished Jan 21 09:54:56 PM PST 24
Peak memory 215908 kb
Host smart-b55e97c9-ef2e-41a2-8683-a0830261ecd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578733127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3578733127
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3951637213
Short name T465
Test name
Test status
Simulation time 177870907 ps
CPU time 2.03 seconds
Started Jan 21 09:54:52 PM PST 24
Finished Jan 21 09:54:59 PM PST 24
Peak memory 219312 kb
Host smart-7b4de497-9bca-479d-a043-751f031c59da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951637213 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3951637213
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2983142833
Short name T180
Test name
Test status
Simulation time 263125763 ps
CPU time 1.36 seconds
Started Jan 21 10:57:21 PM PST 24
Finished Jan 21 10:57:27 PM PST 24
Peak memory 215964 kb
Host smart-ba031cc5-460f-40c8-9bdf-9d171f60587b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983142833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
983142833
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2394895458
Short name T421
Test name
Test status
Simulation time 17624414 ps
CPU time 0.74 seconds
Started Jan 21 09:54:49 PM PST 24
Finished Jan 21 09:54:56 PM PST 24
Peak memory 204796 kb
Host smart-fe3ca6cd-5756-478d-bc66-1bc3e452d30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394895458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
394895458
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.66591742
Short name T84
Test name
Test status
Simulation time 152322308 ps
CPU time 2.97 seconds
Started Jan 21 09:54:48 PM PST 24
Finished Jan 21 09:54:57 PM PST 24
Peak memory 215884 kb
Host smart-a7374670-ec76-4bb5-8652-e6ebac88d257
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66591742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_d
evice_mem_partial_access.66591742
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3625731874
Short name T390
Test name
Test status
Simulation time 766921711 ps
CPU time 14.35 seconds
Started Jan 21 09:54:48 PM PST 24
Finished Jan 21 09:55:09 PM PST 24
Peak memory 215896 kb
Host smart-cb9df425-4ceb-495d-bce6-eaf9be418241
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625731874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3625731874
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2688846369
Short name T210
Test name
Test status
Simulation time 851422179 ps
CPU time 4.39 seconds
Started Jan 21 10:42:07 PM PST 24
Finished Jan 21 10:42:12 PM PST 24
Peak memory 215960 kb
Host smart-7fc5c843-53d4-4c5f-8bb7-913ad7c3ccce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688846369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2688846369
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1432602856
Short name T179
Test name
Test status
Simulation time 545436862 ps
CPU time 7.68 seconds
Started Jan 21 09:54:49 PM PST 24
Finished Jan 21 09:55:02 PM PST 24
Peak memory 216092 kb
Host smart-a46601d4-4420-4e30-93a0-ef73508061f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432602856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1432602856
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.564477677
Short name T442
Test name
Test status
Simulation time 50781104 ps
CPU time 0.79 seconds
Started Jan 21 09:56:04 PM PST 24
Finished Jan 21 09:56:08 PM PST 24
Peak memory 204792 kb
Host smart-aa18ec71-82ea-4e8e-b84f-48272a09c3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564477677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.564477677
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3452236453
Short name T408
Test name
Test status
Simulation time 13151125 ps
CPU time 0.71 seconds
Started Jan 21 09:56:05 PM PST 24
Finished Jan 21 09:56:08 PM PST 24
Peak memory 204840 kb
Host smart-08756456-c3c5-42e4-b80e-1b57aa23a3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452236453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3452236453
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2747537735
Short name T405
Test name
Test status
Simulation time 44715482 ps
CPU time 0.82 seconds
Started Jan 21 09:56:08 PM PST 24
Finished Jan 21 09:56:12 PM PST 24
Peak memory 204836 kb
Host smart-005d67f8-b3af-4259-9ebc-a65970cf4a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747537735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2747537735
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2590906910
Short name T401
Test name
Test status
Simulation time 32977654 ps
CPU time 0.8 seconds
Started Jan 21 09:56:06 PM PST 24
Finished Jan 21 09:56:10 PM PST 24
Peak memory 204804 kb
Host smart-dadd5bc5-c5da-48cc-aa30-6cfb88918430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590906910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2590906910
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2004041903
Short name T434
Test name
Test status
Simulation time 13969615 ps
CPU time 0.78 seconds
Started Jan 21 09:56:13 PM PST 24
Finished Jan 21 09:56:23 PM PST 24
Peak memory 204808 kb
Host smart-95405294-0746-4f68-a017-111afafea92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004041903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2004041903
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.340490574
Short name T410
Test name
Test status
Simulation time 15397938 ps
CPU time 0.77 seconds
Started Jan 21 09:56:08 PM PST 24
Finished Jan 21 09:56:12 PM PST 24
Peak memory 204804 kb
Host smart-0c715ec5-9bb9-4bdc-9ff9-78decf6b0bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340490574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.340490574
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2834041822
Short name T229
Test name
Test status
Simulation time 14200707 ps
CPU time 0.87 seconds
Started Jan 21 09:56:06 PM PST 24
Finished Jan 21 09:56:10 PM PST 24
Peak memory 204848 kb
Host smart-ca7364d2-b9f7-4d30-8a7c-b11e5247a1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834041822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2834041822
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2129068466
Short name T460
Test name
Test status
Simulation time 41621891 ps
CPU time 0.7 seconds
Started Jan 21 09:56:09 PM PST 24
Finished Jan 21 09:56:13 PM PST 24
Peak memory 204820 kb
Host smart-f24a260d-1033-4da2-8911-6213ea3dd3e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129068466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2129068466
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1299187516
Short name T417
Test name
Test status
Simulation time 37166122 ps
CPU time 0.74 seconds
Started Jan 21 09:56:06 PM PST 24
Finished Jan 21 09:56:09 PM PST 24
Peak memory 204780 kb
Host smart-583fc815-5765-4870-90bb-7bb8954acf17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299187516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1299187516
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1108137393
Short name T472
Test name
Test status
Simulation time 42689769 ps
CPU time 0.73 seconds
Started Jan 21 09:56:07 PM PST 24
Finished Jan 21 09:56:11 PM PST 24
Peak memory 204832 kb
Host smart-9126efc3-703e-43e1-929d-f06097ba4d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108137393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1108137393
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1309961512
Short name T82
Test name
Test status
Simulation time 120161792 ps
CPU time 3.3 seconds
Started Jan 21 09:54:59 PM PST 24
Finished Jan 21 09:55:07 PM PST 24
Peak memory 218272 kb
Host smart-feef7a57-724f-420f-ad54-ee8204e24bce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309961512 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1309961512
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4010778501
Short name T182
Test name
Test status
Simulation time 62909214 ps
CPU time 2.25 seconds
Started Jan 21 09:55:03 PM PST 24
Finished Jan 21 09:55:09 PM PST 24
Peak memory 215960 kb
Host smart-1518eec3-014a-4335-81e3-c7986f632b22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010778501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
010778501
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.813515927
Short name T466
Test name
Test status
Simulation time 79448006 ps
CPU time 2 seconds
Started Jan 21 09:55:03 PM PST 24
Finished Jan 21 09:55:09 PM PST 24
Peak memory 216012 kb
Host smart-c37cecc9-193d-4e09-bd28-b79c41bb3100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813515927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.813515927
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4109492060
Short name T431
Test name
Test status
Simulation time 124883689 ps
CPU time 3.7 seconds
Started Jan 21 10:57:22 PM PST 24
Finished Jan 21 10:57:31 PM PST 24
Peak memory 216168 kb
Host smart-c5ce62b2-59e8-4a2b-8a88-c44e1b542b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109492060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
109492060
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2114208978
Short name T467
Test name
Test status
Simulation time 661853484 ps
CPU time 7.76 seconds
Started Jan 21 10:35:03 PM PST 24
Finished Jan 21 10:35:15 PM PST 24
Peak memory 216032 kb
Host smart-eeae41e9-6686-46c8-9e9d-1e634a5b6690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114208978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2114208978
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.662217567
Short name T134
Test name
Test status
Simulation time 61647614 ps
CPU time 2.1 seconds
Started Jan 21 09:55:01 PM PST 24
Finished Jan 21 09:55:08 PM PST 24
Peak memory 219164 kb
Host smart-bce9d073-0fbc-441e-a566-bf01ede5c11f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662217567 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.662217567
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1753478382
Short name T424
Test name
Test status
Simulation time 62989602 ps
CPU time 1.98 seconds
Started Jan 21 09:55:00 PM PST 24
Finished Jan 21 09:55:07 PM PST 24
Peak memory 207736 kb
Host smart-e1b5d60c-7db9-4ba9-9cc4-01a11023f13b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753478382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
753478382
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3916617628
Short name T387
Test name
Test status
Simulation time 241627363 ps
CPU time 0.77 seconds
Started Jan 21 09:55:00 PM PST 24
Finished Jan 21 09:55:06 PM PST 24
Peak memory 204812 kb
Host smart-5522a4b5-7a89-4821-82d3-2e13a8c67dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916617628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
916617628
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1440630848
Short name T385
Test name
Test status
Simulation time 427608427 ps
CPU time 3.15 seconds
Started Jan 21 09:55:01 PM PST 24
Finished Jan 21 09:55:09 PM PST 24
Peak memory 216000 kb
Host smart-ccfc520a-ef99-4f64-b31e-c02cc841c089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440630848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1440630848
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2895358742
Short name T464
Test name
Test status
Simulation time 931191415 ps
CPU time 5.74 seconds
Started Jan 21 09:55:00 PM PST 24
Finished Jan 21 09:55:11 PM PST 24
Peak memory 216160 kb
Host smart-9f5d38b4-7ece-4620-a349-6bfc922524b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895358742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
895358742
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.47321130
Short name T468
Test name
Test status
Simulation time 157984390 ps
CPU time 6.63 seconds
Started Jan 21 09:54:59 PM PST 24
Finished Jan 21 09:55:08 PM PST 24
Peak memory 215912 kb
Host smart-4f6784d8-7615-41ae-a4b7-06b08d746e4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47321130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_t
l_intg_err.47321130
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.544357933
Short name T453
Test name
Test status
Simulation time 20469778 ps
CPU time 1.66 seconds
Started Jan 21 09:55:14 PM PST 24
Finished Jan 21 09:55:27 PM PST 24
Peak memory 217444 kb
Host smart-f0d89a29-ea15-4bea-9e91-99271134d270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544357933 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.544357933
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3557166906
Short name T196
Test name
Test status
Simulation time 40400578 ps
CPU time 2.57 seconds
Started Jan 21 11:15:23 PM PST 24
Finished Jan 21 11:15:27 PM PST 24
Peak memory 216016 kb
Host smart-7be80384-657f-4954-b62c-978c2617ce44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557166906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
557166906
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.328301666
Short name T443
Test name
Test status
Simulation time 15401957 ps
CPU time 0.8 seconds
Started Jan 21 09:54:58 PM PST 24
Finished Jan 21 09:55:00 PM PST 24
Peak memory 204784 kb
Host smart-6f581bae-bde9-47e3-b86f-9ba287324e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328301666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.328301666
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2624203680
Short name T402
Test name
Test status
Simulation time 219809628 ps
CPU time 4.59 seconds
Started Jan 21 09:55:10 PM PST 24
Finished Jan 21 09:55:22 PM PST 24
Peak memory 215920 kb
Host smart-901ad467-bd7c-49dd-abf7-355c9f67c2e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624203680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2624203680
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.200397131
Short name T145
Test name
Test status
Simulation time 65905214 ps
CPU time 2.14 seconds
Started Jan 21 10:29:46 PM PST 24
Finished Jan 21 10:29:51 PM PST 24
Peak memory 216228 kb
Host smart-fdaa9780-8584-4355-9655-ec18fb454e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200397131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.200397131
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3480102570
Short name T420
Test name
Test status
Simulation time 19806194 ps
CPU time 1.23 seconds
Started Jan 21 09:55:12 PM PST 24
Finished Jan 21 09:55:21 PM PST 24
Peak memory 216300 kb
Host smart-5ff8a40d-b584-48ae-bc4d-aead625e9d1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480102570 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3480102570
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1480776193
Short name T215
Test name
Test status
Simulation time 68207292 ps
CPU time 1.35 seconds
Started Jan 21 09:55:10 PM PST 24
Finished Jan 21 09:55:17 PM PST 24
Peak memory 207644 kb
Host smart-b44c80e2-de88-40c5-b2a0-8feb6d2d8736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480776193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
480776193
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.702748308
Short name T474
Test name
Test status
Simulation time 17488279 ps
CPU time 0.78 seconds
Started Jan 21 09:55:13 PM PST 24
Finished Jan 21 09:55:23 PM PST 24
Peak memory 204820 kb
Host smart-05401560-5b73-4593-885f-093e80a7384b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702748308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.702748308
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.504761102
Short name T423
Test name
Test status
Simulation time 924444659 ps
CPU time 4.96 seconds
Started Jan 21 09:55:09 PM PST 24
Finished Jan 21 09:55:21 PM PST 24
Peak memory 216000 kb
Host smart-6eed1d3f-0114-4680-b078-7c211aa1dfda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504761102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.504761102
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.81900995
Short name T438
Test name
Test status
Simulation time 59940192 ps
CPU time 4.93 seconds
Started Jan 21 09:55:12 PM PST 24
Finished Jan 21 09:55:25 PM PST 24
Peak memory 216112 kb
Host smart-36746973-2108-4fb0-b020-8bda41974082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81900995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.81900995
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1066234472
Short name T244
Test name
Test status
Simulation time 237342106 ps
CPU time 7.23 seconds
Started Jan 21 09:55:12 PM PST 24
Finished Jan 21 09:55:27 PM PST 24
Peak memory 216308 kb
Host smart-82f82e62-4828-40db-89a5-9874b2c46c77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066234472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1066234472
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2727449692
Short name T448
Test name
Test status
Simulation time 54623551 ps
CPU time 2.57 seconds
Started Jan 21 10:22:25 PM PST 24
Finished Jan 21 10:22:36 PM PST 24
Peak memory 219240 kb
Host smart-da2c60ca-4814-4287-b8a5-a4581e65f32c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727449692 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2727449692
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.202716834
Short name T181
Test name
Test status
Simulation time 68410831 ps
CPU time 2.59 seconds
Started Jan 21 10:23:40 PM PST 24
Finished Jan 21 10:23:49 PM PST 24
Peak memory 216020 kb
Host smart-bdd57b5b-4b80-46ef-a54e-846171ff860d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202716834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.202716834
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3472940953
Short name T439
Test name
Test status
Simulation time 25374515 ps
CPU time 0.75 seconds
Started Jan 21 09:55:11 PM PST 24
Finished Jan 21 09:55:19 PM PST 24
Peak memory 204812 kb
Host smart-33189dc0-4538-4623-99cb-5a717c7e1dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472940953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
472940953
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3835358141
Short name T447
Test name
Test status
Simulation time 168665473 ps
CPU time 4.3 seconds
Started Jan 21 09:55:12 PM PST 24
Finished Jan 21 09:55:26 PM PST 24
Peak memory 215940 kb
Host smart-f88bc314-e97f-4b02-be79-0492f20e567b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835358141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3835358141
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4021793935
Short name T142
Test name
Test status
Simulation time 51355477 ps
CPU time 3.76 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 10:18:18 PM PST 24
Peak memory 216096 kb
Host smart-31991b73-f850-481b-bdd7-7a1f31fab803
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021793935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
021793935
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2993111437
Short name T169
Test name
Test status
Simulation time 699466126 ps
CPU time 14.77 seconds
Started Jan 21 10:35:41 PM PST 24
Finished Jan 21 10:35:58 PM PST 24
Peak memory 216568 kb
Host smart-36255ce5-c70b-4c28-82d5-2dd35597b235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993111437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2993111437
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_abort.3468937102
Short name T864
Test name
Test status
Simulation time 40864157 ps
CPU time 0.77 seconds
Started Jan 21 07:53:12 PM PST 24
Finished Jan 21 07:53:14 PM PST 24
Peak memory 207272 kb
Host smart-1de01c8b-413a-4c94-babf-c2fc0de409f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468937102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_abort.3468937102
Directory /workspace/0.spi_device_abort/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2102389716
Short name T1521
Test name
Test status
Simulation time 106348649 ps
CPU time 0.73 seconds
Started Jan 21 07:53:07 PM PST 24
Finished Jan 21 07:53:10 PM PST 24
Peak memory 206912 kb
Host smart-2d2ee60b-1801-44ad-86bf-2e873bdf8ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102389716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
102389716
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_bit_transfer.4220157415
Short name T1650
Test name
Test status
Simulation time 903324079 ps
CPU time 2.29 seconds
Started Jan 21 07:53:19 PM PST 24
Finished Jan 21 07:53:23 PM PST 24
Peak memory 217252 kb
Host smart-a9460e19-2fe5-45be-b8f6-feca5c07d8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220157415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_bit_transfer.4220157415
Directory /workspace/0.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/0.spi_device_byte_transfer.282416341
Short name T550
Test name
Test status
Simulation time 183313919 ps
CPU time 3.22 seconds
Started Jan 21 07:53:11 PM PST 24
Finished Jan 21 07:53:16 PM PST 24
Peak memory 217248 kb
Host smart-60f212a1-ae0a-41db-97f0-7b976e4d6347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282416341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_byte_transfer.282416341
Directory /workspace/0.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3663213714
Short name T933
Test name
Test status
Simulation time 286511332 ps
CPU time 2.48 seconds
Started Jan 21 07:53:11 PM PST 24
Finished Jan 21 07:53:15 PM PST 24
Peak memory 218852 kb
Host smart-ebbd903c-8a1e-4153-ac7b-5ccf5238de93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663213714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3663213714
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2947230763
Short name T1506
Test name
Test status
Simulation time 18470408 ps
CPU time 0.79 seconds
Started Jan 21 07:53:02 PM PST 24
Finished Jan 21 07:53:05 PM PST 24
Peak memory 208044 kb
Host smart-7fe093e1-43b5-4ee7-8eaf-13cff23238c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947230763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2947230763
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.1491661161
Short name T512
Test name
Test status
Simulation time 214797431795 ps
CPU time 515.05 seconds
Started Jan 21 07:52:49 PM PST 24
Finished Jan 21 08:01:26 PM PST 24
Peak memory 263400 kb
Host smart-c2121ab1-757d-4760-8e8a-451b6821c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491661161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_dummy_item_extra_dly.1491661161
Directory /workspace/0.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/0.spi_device_extreme_fifo_size.3368102851
Short name T1471
Test name
Test status
Simulation time 72471083897 ps
CPU time 922.69 seconds
Started Jan 21 07:52:50 PM PST 24
Finished Jan 21 08:08:15 PM PST 24
Peak memory 220392 kb
Host smart-cc2395bf-ea4f-4ab5-b15e-07b9e9a21aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368102851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_extreme_fifo_size.3368102851
Directory /workspace/0.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/0.spi_device_fifo_full.807266764
Short name T573
Test name
Test status
Simulation time 158226263676 ps
CPU time 2079.33 seconds
Started Jan 21 07:52:54 PM PST 24
Finished Jan 21 08:27:36 PM PST 24
Peak memory 291140 kb
Host smart-138c6f8c-f04b-4abd-9727-4db56434a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807266764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_full.807266764
Directory /workspace/0.spi_device_fifo_full/latest

Test location /workspace/coverage/default/0.spi_device_fifo_underflow_overflow.2398608937
Short name T1072
Test name
Test status
Simulation time 1249090806347 ps
CPU time 564.49 seconds
Started Jan 21 07:52:51 PM PST 24
Finished Jan 21 08:02:17 PM PST 24
Peak memory 375628 kb
Host smart-6114a66c-36dd-4f0a-b21a-b76ad7618936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398608937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_underflow_overfl
ow.2398608937
Directory /workspace/0.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.254530658
Short name T777
Test name
Test status
Simulation time 21382500657 ps
CPU time 204.08 seconds
Started Jan 21 07:53:18 PM PST 24
Finished Jan 21 07:56:45 PM PST 24
Peak memory 283092 kb
Host smart-9cdc7c31-dd8f-41c7-86e7-bef5fc8ea8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254530658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.254530658
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2133180501
Short name T859
Test name
Test status
Simulation time 4699347494 ps
CPU time 15.08 seconds
Started Jan 21 07:53:00 PM PST 24
Finished Jan 21 07:53:18 PM PST 24
Peak memory 221112 kb
Host smart-e7cf5895-d4b8-43c6-92d1-0eef32a1b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133180501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2133180501
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intr.3553652227
Short name T1740
Test name
Test status
Simulation time 10725177928 ps
CPU time 50.72 seconds
Started Jan 21 07:52:50 PM PST 24
Finished Jan 21 07:53:43 PM PST 24
Peak memory 238584 kb
Host smart-7830470f-2014-4e16-9275-b984a6cd5958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553652227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intr.3553652227
Directory /workspace/0.spi_device_intr/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.935199459
Short name T286
Test name
Test status
Simulation time 522684166 ps
CPU time 3 seconds
Started Jan 21 07:53:14 PM PST 24
Finished Jan 21 07:53:19 PM PST 24
Peak memory 218756 kb
Host smart-ee04a3b9-58ca-4881-a2bb-a8a85a25f18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935199459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.935199459
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3046740909
Short name T1187
Test name
Test status
Simulation time 71958335 ps
CPU time 2.93 seconds
Started Jan 21 07:53:06 PM PST 24
Finished Jan 21 07:53:12 PM PST 24
Peak memory 234680 kb
Host smart-b7706a32-5d08-4692-ac20-52cd050660c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046740909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3046740909
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2134535649
Short name T21
Test name
Test status
Simulation time 12211306345 ps
CPU time 8.27 seconds
Started Jan 21 07:53:11 PM PST 24
Finished Jan 21 07:53:21 PM PST 24
Peak memory 219584 kb
Host smart-994638bd-676b-424f-9752-d4876569232b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134535649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2134535649
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_perf.1571843771
Short name T1708
Test name
Test status
Simulation time 22936886604 ps
CPU time 365.9 seconds
Started Jan 21 07:53:03 PM PST 24
Finished Jan 21 07:59:13 PM PST 24
Peak memory 302380 kb
Host smart-6c88c8e0-50c5-46fe-b593-40fab7ef551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571843771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_perf.1571843771
Directory /workspace/0.spi_device_perf/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3673193632
Short name T1778
Test name
Test status
Simulation time 30867322 ps
CPU time 0.75 seconds
Started Jan 21 07:52:58 PM PST 24
Finished Jan 21 07:53:04 PM PST 24
Peak memory 217084 kb
Host smart-9adcd01b-b35d-4770-a776-e2084fb24963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673193632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3673193632
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4061004260
Short name T1468
Test name
Test status
Simulation time 1605829032 ps
CPU time 6.62 seconds
Started Jan 21 07:53:03 PM PST 24
Finished Jan 21 07:53:14 PM PST 24
Peak memory 234980 kb
Host smart-6bf6f1e9-811e-4ee9-8896-275ba4b7a9ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4061004260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4061004260
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_rx_timeout.2922896772
Short name T867
Test name
Test status
Simulation time 358084763 ps
CPU time 4.76 seconds
Started Jan 21 07:53:01 PM PST 24
Finished Jan 21 07:53:08 PM PST 24
Peak memory 217228 kb
Host smart-1dc3526f-79fb-4a33-bd63-d5e8ecf407e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922896772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_timeout.2922896772
Directory /workspace/0.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/0.spi_device_smoke.2064756629
Short name T1518
Test name
Test status
Simulation time 56684822 ps
CPU time 1.17 seconds
Started Jan 21 07:52:50 PM PST 24
Finished Jan 21 07:52:52 PM PST 24
Peak memory 208436 kb
Host smart-c28cf712-c640-4fd1-97b8-bdbad60ebf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064756629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_smoke.2064756629
Directory /workspace/0.spi_device_smoke/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2564326824
Short name T155
Test name
Test status
Simulation time 299228193763 ps
CPU time 420.88 seconds
Started Jan 21 07:53:07 PM PST 24
Finished Jan 21 08:00:11 PM PST 24
Peak memory 271136 kb
Host smart-24f36afa-932a-4941-a879-d668fa1de45f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564326824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2564326824
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2418833211
Short name T1351
Test name
Test status
Simulation time 1116870492 ps
CPU time 3.91 seconds
Started Jan 21 07:53:11 PM PST 24
Finished Jan 21 07:53:17 PM PST 24
Peak memory 217412 kb
Host smart-2fa79bc2-5e31-4024-8ece-f0b5b4cba5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418833211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2418833211
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1751095801
Short name T1058
Test name
Test status
Simulation time 1220635706 ps
CPU time 2.81 seconds
Started Jan 21 07:53:02 PM PST 24
Finished Jan 21 07:53:07 PM PST 24
Peak memory 217180 kb
Host smart-2209fdb2-8fba-4a11-9c6a-90d67df562fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751095801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1751095801
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1728652146
Short name T1577
Test name
Test status
Simulation time 1093901258 ps
CPU time 2.22 seconds
Started Jan 21 07:53:19 PM PST 24
Finished Jan 21 07:53:23 PM PST 24
Peak memory 217308 kb
Host smart-cc2f9c14-3ef6-4cf5-8909-121d624ec22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728652146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1728652146
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.4284049223
Short name T828
Test name
Test status
Simulation time 276350035 ps
CPU time 1 seconds
Started Jan 21 07:53:04 PM PST 24
Finished Jan 21 07:53:09 PM PST 24
Peak memory 207276 kb
Host smart-ce970296-d316-450a-9ea0-fab9e538b83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284049223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4284049223
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_txrx.1733040288
Short name T1273
Test name
Test status
Simulation time 200236482664 ps
CPU time 2423.2 seconds
Started Jan 21 07:52:48 PM PST 24
Finished Jan 21 08:33:14 PM PST 24
Peak memory 257428 kb
Host smart-3dbf0af2-46bc-4ee6-80d0-27d4952b07d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733040288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_txrx.1733040288
Directory /workspace/0.spi_device_txrx/latest

Test location /workspace/coverage/default/0.spi_device_upload.2901559375
Short name T1713
Test name
Test status
Simulation time 7775696614 ps
CPU time 27.25 seconds
Started Jan 21 07:53:11 PM PST 24
Finished Jan 21 07:53:40 PM PST 24
Peak memory 223088 kb
Host smart-8b5f65bd-a186-4b6d-a7bc-6b271ee84c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901559375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2901559375
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_abort.170484039
Short name T1369
Test name
Test status
Simulation time 15240070 ps
CPU time 0.79 seconds
Started Jan 21 07:53:16 PM PST 24
Finished Jan 21 07:53:18 PM PST 24
Peak memory 207052 kb
Host smart-98868e7c-f8b2-460e-9fe2-61edc89cffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170484039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_abort.170484039
Directory /workspace/1.spi_device_abort/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1739431051
Short name T963
Test name
Test status
Simulation time 13263946 ps
CPU time 0.71 seconds
Started Jan 21 07:53:19 PM PST 24
Finished Jan 21 07:53:22 PM PST 24
Peak memory 206996 kb
Host smart-a2e8f905-75c4-4fb7-a741-d44ac4344351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739431051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
739431051
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_bit_transfer.3561396958
Short name T1060
Test name
Test status
Simulation time 221436190 ps
CPU time 2.47 seconds
Started Jan 21 07:53:16 PM PST 24
Finished Jan 21 07:53:21 PM PST 24
Peak memory 217272 kb
Host smart-20800e51-d2ab-4f66-87b8-b500a9ad483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561396958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_bit_transfer.3561396958
Directory /workspace/1.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/1.spi_device_byte_transfer.1058563343
Short name T650
Test name
Test status
Simulation time 51981172 ps
CPU time 2.22 seconds
Started Jan 21 07:53:17 PM PST 24
Finished Jan 21 07:53:22 PM PST 24
Peak memory 217152 kb
Host smart-dee26866-840b-47dd-a30d-619696579341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058563343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_byte_transfer.1058563343
Directory /workspace/1.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2636207039
Short name T316
Test name
Test status
Simulation time 1221941257 ps
CPU time 3.54 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 07:53:29 PM PST 24
Peak memory 225536 kb
Host smart-d4678993-cbf0-43bd-a6b9-99d78869dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636207039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2636207039
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1269615124
Short name T530
Test name
Test status
Simulation time 25844315 ps
CPU time 0.82 seconds
Started Jan 21 07:53:23 PM PST 24
Finished Jan 21 07:53:27 PM PST 24
Peak memory 207040 kb
Host smart-69b3b892-cb51-4806-8357-eec0c95c0aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269615124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1269615124
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_dummy_item_extra_dly.1269217736
Short name T1267
Test name
Test status
Simulation time 37974324468 ps
CPU time 186.28 seconds
Started Jan 21 07:53:12 PM PST 24
Finished Jan 21 07:56:20 PM PST 24
Peak memory 249512 kb
Host smart-81420ce0-b77e-4c14-a41e-64e99eeaf560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269217736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_dummy_item_extra_dly.1269217736
Directory /workspace/1.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/1.spi_device_extreme_fifo_size.2914394867
Short name T1681
Test name
Test status
Simulation time 7640068141 ps
CPU time 60.29 seconds
Started Jan 21 07:53:23 PM PST 24
Finished Jan 21 07:54:26 PM PST 24
Peak memory 233384 kb
Host smart-2dbc319e-941d-4c1b-bcfb-8a481e045de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914394867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_extreme_fifo_size.2914394867
Directory /workspace/1.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/1.spi_device_fifo_full.1503730832
Short name T1609
Test name
Test status
Simulation time 218982215215 ps
CPU time 811.45 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 08:06:55 PM PST 24
Peak memory 266328 kb
Host smart-c4e81227-21d3-448d-be02-150ac7ca4331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503730832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_full.1503730832
Directory /workspace/1.spi_device_fifo_full/latest

Test location /workspace/coverage/default/1.spi_device_fifo_underflow_overflow.91952505
Short name T55
Test name
Test status
Simulation time 461358706770 ps
CPU time 902.56 seconds
Started Jan 21 07:53:16 PM PST 24
Finished Jan 21 08:08:20 PM PST 24
Peak memory 437060 kb
Host smart-adfa122d-0d7a-4ece-8929-8c8865b96cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91952505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_underflow_overflow
.91952505
Directory /workspace/1.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3855724587
Short name T1065
Test name
Test status
Simulation time 12717011816 ps
CPU time 72.94 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 07:54:37 PM PST 24
Peak memory 250292 kb
Host smart-bfeff19a-d8b7-4888-b47b-5d4e28e2f72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855724587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3855724587
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1163609593
Short name T821
Test name
Test status
Simulation time 74133495639 ps
CPU time 178.87 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 07:56:24 PM PST 24
Peak memory 251540 kb
Host smart-4717b39f-3e4f-4f56-b37d-a7d138d5d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163609593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1163609593
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1902482516
Short name T1690
Test name
Test status
Simulation time 18680123803 ps
CPU time 214.99 seconds
Started Jan 21 09:01:16 PM PST 24
Finished Jan 21 09:05:15 PM PST 24
Peak memory 283044 kb
Host smart-7f223e10-6b2f-4e8e-bd48-d059b7723451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902482516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1902482516
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.620816438
Short name T767
Test name
Test status
Simulation time 20642574035 ps
CPU time 32.99 seconds
Started Jan 21 07:53:14 PM PST 24
Finished Jan 21 07:53:49 PM PST 24
Peak memory 246868 kb
Host smart-aa1d750e-5cd1-4db4-b3b7-46fa154345c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620816438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.620816438
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1119787469
Short name T965
Test name
Test status
Simulation time 254604993 ps
CPU time 2.97 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 07:53:28 PM PST 24
Peak memory 218744 kb
Host smart-030ce770-7635-4580-82b0-c9aac085c2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119787469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1119787469
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intr.674993300
Short name T1531
Test name
Test status
Simulation time 3417925281 ps
CPU time 18 seconds
Started Jan 21 07:53:21 PM PST 24
Finished Jan 21 07:53:41 PM PST 24
Peak memory 225488 kb
Host smart-65eaa8ee-7f10-48e9-85bd-96ca665f6cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674993300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intr.674993300
Directory /workspace/1.spi_device_intr/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1428204549
Short name T623
Test name
Test status
Simulation time 701317776 ps
CPU time 7.4 seconds
Started Jan 21 07:53:18 PM PST 24
Finished Jan 21 07:53:28 PM PST 24
Peak memory 237612 kb
Host smart-80a5b795-c2e5-4b9d-9331-202a13c14ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428204549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1428204549
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3527419453
Short name T614
Test name
Test status
Simulation time 27038651 ps
CPU time 1.04 seconds
Started Jan 21 07:53:14 PM PST 24
Finished Jan 21 07:53:17 PM PST 24
Peak memory 219368 kb
Host smart-d0c13332-ac27-4a5c-96cb-1486e741dc94
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527419453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3527419453
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3763651409
Short name T256
Test name
Test status
Simulation time 3963614867 ps
CPU time 10.82 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 07:53:36 PM PST 24
Peak memory 250128 kb
Host smart-1bacc75b-b3ec-42bd-95ba-c483738a62ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763651409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3763651409
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3197099764
Short name T1098
Test name
Test status
Simulation time 16893610125 ps
CPU time 14.31 seconds
Started Jan 21 07:53:23 PM PST 24
Finished Jan 21 07:53:41 PM PST 24
Peak memory 238876 kb
Host smart-0770846f-31a4-4f24-bb44-ed49dfe254bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197099764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3197099764
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_perf.3736147873
Short name T1186
Test name
Test status
Simulation time 38925641187 ps
CPU time 1453.3 seconds
Started Jan 21 07:53:16 PM PST 24
Finished Jan 21 08:17:32 PM PST 24
Peak memory 282896 kb
Host smart-b2b33d8b-0a1f-4258-896e-346c0b9b8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736147873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_perf.3736147873
Directory /workspace/1.spi_device_perf/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.2562600277
Short name T1510
Test name
Test status
Simulation time 37974060 ps
CPU time 0.75 seconds
Started Jan 21 07:53:23 PM PST 24
Finished Jan 21 07:53:27 PM PST 24
Peak memory 217104 kb
Host smart-4e7632eb-a06f-474b-b3f3-f8632f439c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562600277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.2562600277
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1192870226
Short name T574
Test name
Test status
Simulation time 827336429 ps
CPU time 4.45 seconds
Started Jan 21 07:53:23 PM PST 24
Finished Jan 21 07:53:31 PM PST 24
Peak memory 234820 kb
Host smart-050dc3b9-0108-4463-b438-0b214f3b7c02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1192870226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1192870226
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_rx_timeout.2941424467
Short name T961
Test name
Test status
Simulation time 669849357 ps
CPU time 6.5 seconds
Started Jan 21 07:53:17 PM PST 24
Finished Jan 21 07:53:26 PM PST 24
Peak memory 217184 kb
Host smart-8db56db5-6e5a-47d1-b5aa-11c2ab014602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941424467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_timeout.2941424467
Directory /workspace/1.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3723641181
Short name T109
Test name
Test status
Simulation time 33884115 ps
CPU time 1 seconds
Started Jan 21 07:53:13 PM PST 24
Finished Jan 21 07:53:16 PM PST 24
Peak memory 238520 kb
Host smart-539eacbd-5cab-45e5-8085-4899de632832
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723641181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3723641181
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_smoke.3889430895
Short name T1269
Test name
Test status
Simulation time 44506645 ps
CPU time 1.07 seconds
Started Jan 21 07:53:05 PM PST 24
Finished Jan 21 07:53:10 PM PST 24
Peak memory 208488 kb
Host smart-f27cf76a-e2aa-4f27-ada0-f5cfe9fc54a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889430895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_smoke.3889430895
Directory /workspace/1.spi_device_smoke/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3268967405
Short name T198
Test name
Test status
Simulation time 525549701362 ps
CPU time 2620.85 seconds
Started Jan 21 07:53:21 PM PST 24
Finished Jan 21 08:37:04 PM PST 24
Peak memory 273396 kb
Host smart-042c403d-405f-48f9-8374-0ba6cb3a0e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268967405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3268967405
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2273297455
Short name T654
Test name
Test status
Simulation time 8780778467 ps
CPU time 8.74 seconds
Started Jan 21 07:53:20 PM PST 24
Finished Jan 21 07:53:31 PM PST 24
Peak memory 221392 kb
Host smart-3f47fee9-9825-463f-9e69-b0859c3a492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273297455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2273297455
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3395439012
Short name T546
Test name
Test status
Simulation time 4929790387 ps
CPU time 17.76 seconds
Started Jan 21 07:53:13 PM PST 24
Finished Jan 21 07:53:33 PM PST 24
Peak memory 217292 kb
Host smart-56162c9d-1ef7-434c-8514-f60280099eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395439012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3395439012
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2743158478
Short name T988
Test name
Test status
Simulation time 36020091 ps
CPU time 1.1 seconds
Started Jan 21 07:53:20 PM PST 24
Finished Jan 21 07:53:24 PM PST 24
Peak memory 208860 kb
Host smart-bf1c1d45-153d-43b0-8d57-e384038cf850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743158478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2743158478
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.23447609
Short name T691
Test name
Test status
Simulation time 51551082 ps
CPU time 0.73 seconds
Started Jan 21 07:53:16 PM PST 24
Finished Jan 21 07:53:19 PM PST 24
Peak memory 207224 kb
Host smart-142ec91b-3688-400f-b200-bf8c07449ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23447609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.23447609
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tx_async_fifo_reset.3448857483
Short name T1619
Test name
Test status
Simulation time 107648350 ps
CPU time 0.79 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 07:53:25 PM PST 24
Peak memory 208704 kb
Host smart-5618f54e-d029-4745-a2c7-eccfb9c65e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448857483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tx_async_fifo_reset.3448857483
Directory /workspace/1.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_txrx.515869214
Short name T982
Test name
Test status
Simulation time 86474122913 ps
CPU time 126.92 seconds
Started Jan 21 07:53:13 PM PST 24
Finished Jan 21 07:55:21 PM PST 24
Peak memory 253200 kb
Host smart-1fa19092-7f32-4d7e-8879-8dfd600a82b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515869214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_txrx.515869214
Directory /workspace/1.spi_device_txrx/latest

Test location /workspace/coverage/default/1.spi_device_upload.869905426
Short name T533
Test name
Test status
Simulation time 4813318348 ps
CPU time 9.82 seconds
Started Jan 21 07:53:23 PM PST 24
Finished Jan 21 07:53:36 PM PST 24
Peak memory 231876 kb
Host smart-f5697d77-1d0a-4b8c-9b1e-a5f435630fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869905426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.869905426
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_abort.245943232
Short name T921
Test name
Test status
Simulation time 47801695 ps
CPU time 0.76 seconds
Started Jan 21 07:55:53 PM PST 24
Finished Jan 21 07:55:56 PM PST 24
Peak memory 207084 kb
Host smart-20f880c8-525c-4a62-846e-036d5530e5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245943232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_abort.245943232
Directory /workspace/10.spi_device_abort/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3369814941
Short name T556
Test name
Test status
Simulation time 11069958 ps
CPU time 0.7 seconds
Started Jan 21 07:56:02 PM PST 24
Finished Jan 21 07:56:03 PM PST 24
Peak memory 206904 kb
Host smart-86681c56-ac53-4f42-93eb-719e1f40e28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369814941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3369814941
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_bit_transfer.634209320
Short name T1429
Test name
Test status
Simulation time 206712667 ps
CPU time 2.51 seconds
Started Jan 21 07:55:40 PM PST 24
Finished Jan 21 07:55:44 PM PST 24
Peak memory 217196 kb
Host smart-59bb3e84-13ea-4a9e-88b9-2ff5a8c2036c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634209320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_bit_transfer.634209320
Directory /workspace/10.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/10.spi_device_byte_transfer.2986563389
Short name T1182
Test name
Test status
Simulation time 554210192 ps
CPU time 2.46 seconds
Started Jan 21 08:53:23 PM PST 24
Finished Jan 21 08:53:44 PM PST 24
Peak memory 217252 kb
Host smart-8c837695-1ee7-4492-80d7-9d6c1206db9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986563389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_byte_transfer.2986563389
Directory /workspace/10.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3519511280
Short name T1192
Test name
Test status
Simulation time 311249322 ps
CPU time 4.3 seconds
Started Jan 21 07:55:52 PM PST 24
Finished Jan 21 07:55:58 PM PST 24
Peak memory 237948 kb
Host smart-f3a1bbb5-a720-4aa9-a84e-645d34a2710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519511280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3519511280
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3673056163
Short name T1354
Test name
Test status
Simulation time 36080479 ps
CPU time 0.81 seconds
Started Jan 21 07:55:50 PM PST 24
Finished Jan 21 07:55:52 PM PST 24
Peak memory 208040 kb
Host smart-725d9656-d90d-4da5-b1cd-418dfabba110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673056163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3673056163
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.1365779706
Short name T811
Test name
Test status
Simulation time 56000863151 ps
CPU time 458.3 seconds
Started Jan 21 08:12:01 PM PST 24
Finished Jan 21 08:19:41 PM PST 24
Peak memory 280648 kb
Host smart-54be6bf9-9837-4394-b449-dcdd4dfaef82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365779706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_dummy_item_extra_dly.1365779706
Directory /workspace/10.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1360022059
Short name T159
Test name
Test status
Simulation time 11625800526 ps
CPU time 68.24 seconds
Started Jan 21 07:55:59 PM PST 24
Finished Jan 21 07:57:08 PM PST 24
Peak memory 255332 kb
Host smart-c2bc9b8c-bef1-477a-a5bd-9e34d7a4e9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360022059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1360022059
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2202713045
Short name T1457
Test name
Test status
Simulation time 36315545302 ps
CPU time 295.53 seconds
Started Jan 21 07:55:58 PM PST 24
Finished Jan 21 08:00:55 PM PST 24
Peak memory 266728 kb
Host smart-107e0bc8-b9b1-4315-849e-3bb71aeb9416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202713045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2202713045
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2765812681
Short name T368
Test name
Test status
Simulation time 38392066234 ps
CPU time 309.02 seconds
Started Jan 21 07:55:59 PM PST 24
Finished Jan 21 08:01:09 PM PST 24
Peak memory 258476 kb
Host smart-e61f0bc3-9e2c-4356-83bf-9e75b9eede4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765812681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2765812681
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3062554055
Short name T840
Test name
Test status
Simulation time 3022272943 ps
CPU time 9.73 seconds
Started Jan 21 07:55:59 PM PST 24
Finished Jan 21 07:56:09 PM PST 24
Peak memory 232332 kb
Host smart-5b6ea9b6-2740-47d6-92ae-e23e0b21bd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062554055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3062554055
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1270560770
Short name T34
Test name
Test status
Simulation time 201461080 ps
CPU time 2.83 seconds
Started Jan 21 07:55:55 PM PST 24
Finished Jan 21 07:55:59 PM PST 24
Peak memory 218548 kb
Host smart-e26654d2-86d9-4d0b-b8df-d9f1fc10778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270560770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1270560770
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intr.3120333553
Short name T1050
Test name
Test status
Simulation time 27629294884 ps
CPU time 96.85 seconds
Started Jan 21 07:55:43 PM PST 24
Finished Jan 21 07:57:21 PM PST 24
Peak memory 238408 kb
Host smart-67472cdb-5344-45b9-8515-d4e2f3cc84e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120333553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intr.3120333553
Directory /workspace/10.spi_device_intr/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3115451558
Short name T1268
Test name
Test status
Simulation time 16248355097 ps
CPU time 42.65 seconds
Started Jan 21 07:55:50 PM PST 24
Finished Jan 21 07:56:34 PM PST 24
Peak memory 232368 kb
Host smart-c6456d04-6065-4df6-b20b-097da560b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115451558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3115451558
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1352901178
Short name T1409
Test name
Test status
Simulation time 17297379 ps
CPU time 1.06 seconds
Started Jan 21 07:55:45 PM PST 24
Finished Jan 21 07:55:47 PM PST 24
Peak memory 219364 kb
Host smart-944ce751-7f30-409e-a65d-fbdba6c3bf23
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352901178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1352901178
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3138547686
Short name T1686
Test name
Test status
Simulation time 1051214245 ps
CPU time 3.2 seconds
Started Jan 21 07:55:53 PM PST 24
Finished Jan 21 07:55:58 PM PST 24
Peak memory 218716 kb
Host smart-03217ce4-d15d-46ae-b04f-da18f3526739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138547686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3138547686
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.949962
Short name T1314
Test name
Test status
Simulation time 39964601446 ps
CPU time 28.15 seconds
Started Jan 21 07:55:52 PM PST 24
Finished Jan 21 07:56:22 PM PST 24
Peak memory 232140 kb
Host smart-4d6f6bf1-dd87-4825-acc6-f3a5efb93117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.949962
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_perf.544289311
Short name T998
Test name
Test status
Simulation time 25609474591 ps
CPU time 1576.61 seconds
Started Jan 21 07:55:43 PM PST 24
Finished Jan 21 08:22:00 PM PST 24
Peak memory 300336 kb
Host smart-dd6bba93-0f2c-4157-b49f-8132cb1cfcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544289311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_perf.544289311
Directory /workspace/10.spi_device_perf/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2179847116
Short name T833
Test name
Test status
Simulation time 177789179 ps
CPU time 3.95 seconds
Started Jan 21 07:55:55 PM PST 24
Finished Jan 21 07:56:00 PM PST 24
Peak memory 234928 kb
Host smart-5f4b9faa-69e2-47c0-a467-dd882fee5d36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2179847116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2179847116
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.2665456522
Short name T1104
Test name
Test status
Simulation time 109910758 ps
CPU time 0.89 seconds
Started Jan 21 08:27:14 PM PST 24
Finished Jan 21 08:27:16 PM PST 24
Peak memory 208840 kb
Host smart-56dd9920-c6ca-455d-90fb-9c354eefac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665456522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_async_fifo_reset.2665456522
Directory /workspace/10.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_rx_timeout.492249673
Short name T538
Test name
Test status
Simulation time 607162970 ps
CPU time 5.96 seconds
Started Jan 21 07:55:43 PM PST 24
Finished Jan 21 07:55:50 PM PST 24
Peak memory 217200 kb
Host smart-66e21840-aad9-4f94-b0e7-0c5e1bd14188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492249673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_timeout.492249673
Directory /workspace/10.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/10.spi_device_smoke.1752634110
Short name T939
Test name
Test status
Simulation time 655855532 ps
CPU time 1.35 seconds
Started Jan 21 07:55:33 PM PST 24
Finished Jan 21 07:55:35 PM PST 24
Peak memory 217164 kb
Host smart-8c5f756a-2027-44f1-9fb4-ef31ff5c93a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752634110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_smoke.1752634110
Directory /workspace/10.spi_device_smoke/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2676631538
Short name T39
Test name
Test status
Simulation time 3331607034 ps
CPU time 26.87 seconds
Started Jan 21 07:55:44 PM PST 24
Finished Jan 21 07:56:11 PM PST 24
Peak memory 217316 kb
Host smart-31808a7b-6f03-4760-9da0-8c19674855d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676631538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2676631538
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1700897411
Short name T945
Test name
Test status
Simulation time 530809305 ps
CPU time 3.06 seconds
Started Jan 21 07:55:50 PM PST 24
Finished Jan 21 07:55:54 PM PST 24
Peak memory 217200 kb
Host smart-6217590c-2c6e-4571-b225-89eeac40fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700897411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1700897411
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1421725709
Short name T969
Test name
Test status
Simulation time 46279458 ps
CPU time 1.41 seconds
Started Jan 21 07:55:52 PM PST 24
Finished Jan 21 07:55:54 PM PST 24
Peak memory 217276 kb
Host smart-3434160d-c7f4-430d-a72a-2ef045cfc421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421725709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1421725709
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3370829317
Short name T1516
Test name
Test status
Simulation time 185521736 ps
CPU time 1.01 seconds
Started Jan 21 07:55:54 PM PST 24
Finished Jan 21 07:55:56 PM PST 24
Peak memory 208332 kb
Host smart-b343afa9-775b-4936-a450-d9928fe40e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370829317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3370829317
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.3098043350
Short name T95
Test name
Test status
Simulation time 17608534 ps
CPU time 0.81 seconds
Started Jan 21 07:55:54 PM PST 24
Finished Jan 21 07:55:56 PM PST 24
Peak memory 208720 kb
Host smart-6d687e2f-7375-40a2-a85b-d5750bf43197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098043350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tx_async_fifo_reset.3098043350
Directory /workspace/10.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_txrx.1908697818
Short name T1197
Test name
Test status
Simulation time 13761224984 ps
CPU time 133.56 seconds
Started Jan 21 08:29:35 PM PST 24
Finished Jan 21 08:31:50 PM PST 24
Peak memory 265804 kb
Host smart-d750bac1-470c-4cb2-ab4d-1b7746e9f4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908697818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_txrx.1908697818
Directory /workspace/10.spi_device_txrx/latest

Test location /workspace/coverage/default/10.spi_device_upload.3988118908
Short name T942
Test name
Test status
Simulation time 8139422985 ps
CPU time 23.86 seconds
Started Jan 21 07:55:54 PM PST 24
Finished Jan 21 07:56:19 PM PST 24
Peak memory 231092 kb
Host smart-be4f7b35-feb4-497c-99a0-2861b211502c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988118908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3988118908
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_abort.828280166
Short name T1245
Test name
Test status
Simulation time 38104703 ps
CPU time 0.76 seconds
Started Jan 21 07:56:14 PM PST 24
Finished Jan 21 07:56:16 PM PST 24
Peak memory 207116 kb
Host smart-fae461ab-c182-456d-92e7-b915d8f65e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828280166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_abort.828280166
Directory /workspace/11.spi_device_abort/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.321957842
Short name T1532
Test name
Test status
Simulation time 17327051 ps
CPU time 0.72 seconds
Started Jan 21 07:56:21 PM PST 24
Finished Jan 21 07:56:24 PM PST 24
Peak memory 206908 kb
Host smart-b0abf79d-108f-484e-9e4b-a94753b2f35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321957842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.321957842
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_bit_transfer.1944577713
Short name T545
Test name
Test status
Simulation time 260612069 ps
CPU time 2.57 seconds
Started Jan 21 07:56:07 PM PST 24
Finished Jan 21 07:56:10 PM PST 24
Peak memory 217188 kb
Host smart-88143650-3738-4f6b-8328-e89723e4cafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944577713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_bit_transfer.1944577713
Directory /workspace/11.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/11.spi_device_byte_transfer.1630802571
Short name T486
Test name
Test status
Simulation time 2317566364 ps
CPU time 2.88 seconds
Started Jan 21 07:56:06 PM PST 24
Finished Jan 21 07:56:10 PM PST 24
Peak memory 217296 kb
Host smart-8adb25e4-8916-4038-9ed1-311975193038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630802571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_byte_transfer.1630802571
Directory /workspace/11.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3817532464
Short name T1479
Test name
Test status
Simulation time 8604622545 ps
CPU time 10.27 seconds
Started Jan 21 07:56:14 PM PST 24
Finished Jan 21 07:56:25 PM PST 24
Peak memory 222820 kb
Host smart-2d9479f2-ee24-4472-9d28-273edff70c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817532464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3817532464
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1501082126
Short name T907
Test name
Test status
Simulation time 27707886 ps
CPU time 0.86 seconds
Started Jan 21 07:56:06 PM PST 24
Finished Jan 21 07:56:08 PM PST 24
Peak memory 208032 kb
Host smart-1188fac2-b685-4227-bc21-27a4050d2097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501082126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1501082126
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_dummy_item_extra_dly.3826412560
Short name T1019
Test name
Test status
Simulation time 67266426178 ps
CPU time 628.52 seconds
Started Jan 21 07:55:58 PM PST 24
Finished Jan 21 08:06:27 PM PST 24
Peak memory 273436 kb
Host smart-c52e108b-ea49-47cb-ab19-7ba0c8728e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826412560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_dummy_item_extra_dly.3826412560
Directory /workspace/11.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/11.spi_device_extreme_fifo_size.1846818321
Short name T628
Test name
Test status
Simulation time 107580930431 ps
CPU time 79 seconds
Started Jan 21 07:56:01 PM PST 24
Finished Jan 21 07:57:21 PM PST 24
Peak memory 225516 kb
Host smart-0cbcd284-dd6e-4a27-b4df-edb8d45fe375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846818321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_extreme_fifo_size.1846818321
Directory /workspace/11.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/11.spi_device_fifo_full.3166216232
Short name T866
Test name
Test status
Simulation time 62778935190 ps
CPU time 381.93 seconds
Started Jan 21 08:25:10 PM PST 24
Finished Jan 21 08:31:34 PM PST 24
Peak memory 309420 kb
Host smart-c02ce47d-030b-47c7-bf90-018c9dfc5ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166216232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_full.3166216232
Directory /workspace/11.spi_device_fifo_full/latest

Test location /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.4293625687
Short name T1589
Test name
Test status
Simulation time 270149002633 ps
CPU time 389.93 seconds
Started Jan 21 07:56:02 PM PST 24
Finished Jan 21 08:02:33 PM PST 24
Peak memory 391264 kb
Host smart-4582a6af-ceb2-41f9-8985-39b903c240b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293625687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_underflow_overf
low.4293625687
Directory /workspace/11.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1501110991
Short name T977
Test name
Test status
Simulation time 5966835303 ps
CPU time 38.36 seconds
Started Jan 21 07:56:26 PM PST 24
Finished Jan 21 07:57:05 PM PST 24
Peak memory 242028 kb
Host smart-ba231425-1759-4886-b77c-aa45937d6388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501110991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1501110991
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2005951366
Short name T45
Test name
Test status
Simulation time 33300571395 ps
CPU time 117.07 seconds
Started Jan 21 07:56:17 PM PST 24
Finished Jan 21 07:58:15 PM PST 24
Peak memory 262264 kb
Host smart-e0312e34-211a-461b-9d91-fd89fe646553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005951366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2005951366
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2382808061
Short name T354
Test name
Test status
Simulation time 66800335804 ps
CPU time 564.22 seconds
Started Jan 21 07:56:21 PM PST 24
Finished Jan 21 08:05:47 PM PST 24
Peak memory 270892 kb
Host smart-d0f05023-ae37-4434-8810-7c5e7e28f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382808061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2382808061
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.215609685
Short name T725
Test name
Test status
Simulation time 881969907 ps
CPU time 9.81 seconds
Started Jan 21 07:56:10 PM PST 24
Finished Jan 21 07:56:21 PM PST 24
Peak memory 239520 kb
Host smart-461c9680-05c8-409b-8701-76c4cc038259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215609685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.215609685
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2112010044
Short name T1710
Test name
Test status
Simulation time 5711305985 ps
CPU time 7.43 seconds
Started Jan 21 07:56:15 PM PST 24
Finished Jan 21 07:56:24 PM PST 24
Peak memory 242040 kb
Host smart-0d6e2e92-4dc4-4e79-b56f-f2c15304ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112010044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2112010044
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intr.1794168449
Short name T554
Test name
Test status
Simulation time 1901273523 ps
CPU time 9.69 seconds
Started Jan 21 07:56:02 PM PST 24
Finished Jan 21 07:56:12 PM PST 24
Peak memory 225404 kb
Host smart-08cc6d65-1e51-4da2-8b71-bf4fe70b7ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794168449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intr.1794168449
Directory /workspace/11.spi_device_intr/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1185217794
Short name T1614
Test name
Test status
Simulation time 3658252764 ps
CPU time 3.33 seconds
Started Jan 21 09:03:30 PM PST 24
Finished Jan 21 09:03:50 PM PST 24
Peak memory 218676 kb
Host smart-d7ae1574-8d83-444e-9ba5-bc4b60ae2e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185217794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1185217794
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3393195953
Short name T1780
Test name
Test status
Simulation time 18695494 ps
CPU time 1.14 seconds
Started Jan 21 07:56:10 PM PST 24
Finished Jan 21 07:56:12 PM PST 24
Peak memory 219304 kb
Host smart-ef016ba9-6c2b-4abd-beb5-a0144691f71e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393195953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3393195953
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1082616200
Short name T645
Test name
Test status
Simulation time 6579446958 ps
CPU time 20.83 seconds
Started Jan 21 07:56:11 PM PST 24
Finished Jan 21 07:56:32 PM PST 24
Peak memory 250192 kb
Host smart-d1264b68-4ae0-46d6-a0aa-a3eb5a156e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082616200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1082616200
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2360703715
Short name T1595
Test name
Test status
Simulation time 932838259 ps
CPU time 10.41 seconds
Started Jan 21 07:56:12 PM PST 24
Finished Jan 21 07:56:23 PM PST 24
Peak memory 241824 kb
Host smart-0328cd74-fe95-4f9a-94bc-a40c482e2fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360703715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2360703715
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_perf.3264458573
Short name T14
Test name
Test status
Simulation time 24646593415 ps
CPU time 1762.1 seconds
Started Jan 21 07:55:59 PM PST 24
Finished Jan 21 08:25:22 PM PST 24
Peak memory 282420 kb
Host smart-8e395c6f-6d8a-4ada-a154-ab48b224c85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264458573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_perf.3264458573
Directory /workspace/11.spi_device_perf/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.1773680438
Short name T1645
Test name
Test status
Simulation time 31017801 ps
CPU time 0.71 seconds
Started Jan 21 07:56:07 PM PST 24
Finished Jan 21 07:56:09 PM PST 24
Peak memory 217084 kb
Host smart-28e1430d-33df-40eb-b737-987fbc198580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773680438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.1773680438
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1668096400
Short name T842
Test name
Test status
Simulation time 1197787986 ps
CPU time 5.31 seconds
Started Jan 21 07:56:21 PM PST 24
Finished Jan 21 07:56:27 PM PST 24
Peak memory 235824 kb
Host smart-dee20567-6a32-4b9d-b5cc-4c339a645f18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1668096400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1668096400
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_rx_async_fifo_reset.47192366
Short name T1116
Test name
Test status
Simulation time 38997560 ps
CPU time 0.94 seconds
Started Jan 21 07:56:13 PM PST 24
Finished Jan 21 07:56:15 PM PST 24
Peak memory 208816 kb
Host smart-b472676d-e99e-4dc9-8597-5364c34c8102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47192366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_async_fifo_reset.47192366
Directory /workspace/11.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_rx_timeout.4094020654
Short name T505
Test name
Test status
Simulation time 1344424584 ps
CPU time 5.82 seconds
Started Jan 21 07:56:07 PM PST 24
Finished Jan 21 07:56:13 PM PST 24
Peak memory 217212 kb
Host smart-50803586-e34f-4eb3-81d9-94dfc8f10a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094020654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_timeout.4094020654
Directory /workspace/11.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/11.spi_device_smoke.3617576307
Short name T1582
Test name
Test status
Simulation time 58493821 ps
CPU time 1.2 seconds
Started Jan 21 07:56:02 PM PST 24
Finished Jan 21 07:56:04 PM PST 24
Peak memory 216944 kb
Host smart-c6a3ea9f-ebf5-4e1f-bca9-fa4f46e84ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617576307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_smoke.3617576307
Directory /workspace/11.spi_device_smoke/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1210411167
Short name T118
Test name
Test status
Simulation time 56441610636 ps
CPU time 54.73 seconds
Started Jan 21 07:56:08 PM PST 24
Finished Jan 21 07:57:04 PM PST 24
Peak memory 217468 kb
Host smart-fdad0a85-d675-41b5-af8c-76f75a3fbed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210411167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1210411167
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3903988730
Short name T50
Test name
Test status
Simulation time 916359581 ps
CPU time 4.52 seconds
Started Jan 21 07:56:09 PM PST 24
Finished Jan 21 07:56:15 PM PST 24
Peak memory 217248 kb
Host smart-70eed2e3-b642-41b0-937c-d2622bfae6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903988730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3903988730
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.108678107
Short name T1782
Test name
Test status
Simulation time 141932172 ps
CPU time 1.24 seconds
Started Jan 21 07:56:14 PM PST 24
Finished Jan 21 07:56:16 PM PST 24
Peak memory 217244 kb
Host smart-86003c73-f7f2-41fd-b926-bf54f646376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108678107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.108678107
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2777593593
Short name T1726
Test name
Test status
Simulation time 86949053 ps
CPU time 0.98 seconds
Started Jan 21 07:56:21 PM PST 24
Finished Jan 21 07:56:23 PM PST 24
Peak memory 207264 kb
Host smart-668dad07-eacb-40b1-9744-be4e662ecf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777593593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2777593593
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tx_async_fifo_reset.4167721029
Short name T952
Test name
Test status
Simulation time 14662665 ps
CPU time 0.81 seconds
Started Jan 21 07:56:13 PM PST 24
Finished Jan 21 07:56:14 PM PST 24
Peak memory 207736 kb
Host smart-8e2acca9-cc14-40f8-95eb-2c065e71cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167721029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tx_async_fifo_reset.4167721029
Directory /workspace/11.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_txrx.3754058500
Short name T845
Test name
Test status
Simulation time 105504155292 ps
CPU time 453 seconds
Started Jan 21 07:55:57 PM PST 24
Finished Jan 21 08:03:31 PM PST 24
Peak memory 315388 kb
Host smart-41265236-f93b-48a0-b7de-bd81c456d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754058500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_txrx.3754058500
Directory /workspace/11.spi_device_txrx/latest

Test location /workspace/coverage/default/11.spi_device_upload.3190325413
Short name T1048
Test name
Test status
Simulation time 8364720287 ps
CPU time 19.32 seconds
Started Jan 21 07:56:13 PM PST 24
Finished Jan 21 07:56:33 PM PST 24
Peak memory 231424 kb
Host smart-3f8a67e9-8059-4309-b5a9-2f5f6966306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190325413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3190325413
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_abort.4141717774
Short name T694
Test name
Test status
Simulation time 16657237 ps
CPU time 0.79 seconds
Started Jan 21 07:56:33 PM PST 24
Finished Jan 21 07:56:37 PM PST 24
Peak memory 207056 kb
Host smart-8939abcc-4e92-49c6-8dfb-87561372d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141717774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_abort.4141717774
Directory /workspace/12.spi_device_abort/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1177694844
Short name T1513
Test name
Test status
Simulation time 40483485 ps
CPU time 0.72 seconds
Started Jan 21 07:56:49 PM PST 24
Finished Jan 21 07:56:52 PM PST 24
Peak memory 206988 kb
Host smart-9fe7f3d7-6019-497d-ad1c-281e42de1426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177694844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1177694844
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_bit_transfer.3345649340
Short name T1285
Test name
Test status
Simulation time 132338752 ps
CPU time 2.12 seconds
Started Jan 21 07:56:34 PM PST 24
Finished Jan 21 07:56:38 PM PST 24
Peak memory 217220 kb
Host smart-ef4152d7-828d-4bf2-bedf-5b4d912ee8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345649340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_bit_transfer.3345649340
Directory /workspace/12.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/12.spi_device_byte_transfer.1044650999
Short name T805
Test name
Test status
Simulation time 82297906 ps
CPU time 3.06 seconds
Started Jan 21 07:56:28 PM PST 24
Finished Jan 21 07:56:37 PM PST 24
Peak memory 217300 kb
Host smart-1c9d8aa2-fcef-4df9-a91f-5cb03b56df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044650999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_byte_transfer.1044650999
Directory /workspace/12.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1011537573
Short name T1715
Test name
Test status
Simulation time 1672697683 ps
CPU time 4.49 seconds
Started Jan 21 07:56:39 PM PST 24
Finished Jan 21 07:56:46 PM PST 24
Peak memory 219940 kb
Host smart-065e486e-0757-4f9b-a1cc-135f1bba99ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011537573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1011537573
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2611903663
Short name T1140
Test name
Test status
Simulation time 24064547 ps
CPU time 0.8 seconds
Started Jan 21 07:56:27 PM PST 24
Finished Jan 21 07:56:32 PM PST 24
Peak memory 208024 kb
Host smart-48a9b912-a582-455a-9a69-d3f790a7daa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611903663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2611903663
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.1057693925
Short name T1244
Test name
Test status
Simulation time 38317854837 ps
CPU time 109.33 seconds
Started Jan 21 07:56:17 PM PST 24
Finished Jan 21 07:58:07 PM PST 24
Peak memory 256860 kb
Host smart-a5fe83e6-e6ca-47c7-a9ff-bdcec2056703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057693925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_dummy_item_extra_dly.1057693925
Directory /workspace/12.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/12.spi_device_extreme_fifo_size.604662880
Short name T981
Test name
Test status
Simulation time 1693322647 ps
CPU time 18.18 seconds
Started Jan 21 07:56:23 PM PST 24
Finished Jan 21 07:56:43 PM PST 24
Peak memory 225384 kb
Host smart-62c2559c-714b-4625-b606-a6a6ee170c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604662880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_extreme_fifo_size.604662880
Directory /workspace/12.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/12.spi_device_fifo_full.110344907
Short name T713
Test name
Test status
Simulation time 13327297808 ps
CPU time 328.39 seconds
Started Jan 21 07:56:26 PM PST 24
Finished Jan 21 08:01:56 PM PST 24
Peak memory 278404 kb
Host smart-41d3e862-74a3-4c1d-8796-6378ed04c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110344907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_full.110344907
Directory /workspace/12.spi_device_fifo_full/latest

Test location /workspace/coverage/default/12.spi_device_fifo_underflow_overflow.1508455084
Short name T1012
Test name
Test status
Simulation time 105133088678 ps
CPU time 335.76 seconds
Started Jan 21 07:56:21 PM PST 24
Finished Jan 21 08:01:57 PM PST 24
Peak memory 509896 kb
Host smart-92e80a12-8189-4b44-bf69-06f9ec3d8f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508455084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_underflow_overf
low.1508455084
Directory /workspace/12.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.411921540
Short name T1205
Test name
Test status
Simulation time 28375460593 ps
CPU time 64.99 seconds
Started Jan 21 07:56:44 PM PST 24
Finished Jan 21 07:57:50 PM PST 24
Peak memory 258356 kb
Host smart-570bc60c-44ee-448e-a771-5ae3f06465b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411921540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.411921540
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1311301287
Short name T1476
Test name
Test status
Simulation time 4363120760 ps
CPU time 74.12 seconds
Started Jan 21 07:56:49 PM PST 24
Finished Jan 21 07:58:05 PM PST 24
Peak memory 250348 kb
Host smart-63e13962-8cb1-4b43-be9c-b5e5fe225797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311301287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1311301287
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.873045970
Short name T756
Test name
Test status
Simulation time 98501556237 ps
CPU time 375.47 seconds
Started Jan 21 07:56:44 PM PST 24
Finished Jan 21 08:03:01 PM PST 24
Peak memory 262012 kb
Host smart-e1ef75db-5b3d-4842-9f39-64575d670a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873045970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.873045970
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.372256100
Short name T1769
Test name
Test status
Simulation time 4840275337 ps
CPU time 25.37 seconds
Started Jan 21 07:56:44 PM PST 24
Finished Jan 21 07:57:10 PM PST 24
Peak memory 250304 kb
Host smart-7c271295-afb8-43fa-af41-37e0e604d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372256100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.372256100
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2446439821
Short name T658
Test name
Test status
Simulation time 14384328268 ps
CPU time 13.54 seconds
Started Jan 21 07:56:45 PM PST 24
Finished Jan 21 07:56:59 PM PST 24
Peak memory 238324 kb
Host smart-0af92f3d-adc0-4518-8b4d-9f2da18a2dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446439821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2446439821
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intr.1674796018
Short name T740
Test name
Test status
Simulation time 14367689744 ps
CPU time 29.65 seconds
Started Jan 21 07:56:27 PM PST 24
Finished Jan 21 07:56:58 PM PST 24
Peak memory 221944 kb
Host smart-ed00d5a0-3741-4385-98d4-6f5d7785d6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674796018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intr.1674796018
Directory /workspace/12.spi_device_intr/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.872407770
Short name T1088
Test name
Test status
Simulation time 603517140 ps
CPU time 9.55 seconds
Started Jan 21 07:56:43 PM PST 24
Finished Jan 21 07:56:54 PM PST 24
Peak memory 232200 kb
Host smart-942ed23c-eaad-4e5a-a409-63bf07f8941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872407770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.872407770
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1917084947
Short name T2
Test name
Test status
Simulation time 340141166 ps
CPU time 1.06 seconds
Started Jan 21 07:56:26 PM PST 24
Finished Jan 21 07:56:28 PM PST 24
Peak memory 219348 kb
Host smart-c330c7f1-61ba-45ff-a64c-f6c7aa452283
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917084947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1917084947
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2644623162
Short name T1413
Test name
Test status
Simulation time 12569685318 ps
CPU time 18.75 seconds
Started Jan 21 07:56:45 PM PST 24
Finished Jan 21 07:57:05 PM PST 24
Peak memory 242068 kb
Host smart-1e18acc0-e86a-48d4-84d8-8999592b1f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644623162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2644623162
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3434795229
Short name T748
Test name
Test status
Simulation time 1221657966 ps
CPU time 7.14 seconds
Started Jan 21 07:56:42 PM PST 24
Finished Jan 21 07:56:50 PM PST 24
Peak memory 235288 kb
Host smart-e2696bf1-2ade-4adc-be56-7f69ace0e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434795229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3434795229
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_perf.1344252597
Short name T481
Test name
Test status
Simulation time 16035147511 ps
CPU time 472.69 seconds
Started Jan 21 07:56:29 PM PST 24
Finished Jan 21 08:04:29 PM PST 24
Peak memory 281444 kb
Host smart-dee7b18c-d59b-482f-83e7-c03da0a9a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344252597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_perf.1344252597
Directory /workspace/12.spi_device_perf/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3162227629
Short name T485
Test name
Test status
Simulation time 30347505 ps
CPU time 0.81 seconds
Started Jan 21 07:56:28 PM PST 24
Finished Jan 21 07:56:36 PM PST 24
Peak memory 217120 kb
Host smart-5c6eb307-1a6f-4abd-8373-8766dd32faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162227629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3162227629
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2992328594
Short name T202
Test name
Test status
Simulation time 1921912001 ps
CPU time 5.08 seconds
Started Jan 21 07:56:45 PM PST 24
Finished Jan 21 07:56:51 PM PST 24
Peak memory 234872 kb
Host smart-a2177d36-5a18-4f9f-a7af-d31d756ced75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2992328594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2992328594
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_rx_async_fifo_reset.62593442
Short name T1634
Test name
Test status
Simulation time 21732645 ps
CPU time 0.88 seconds
Started Jan 21 07:56:31 PM PST 24
Finished Jan 21 07:56:37 PM PST 24
Peak memory 208844 kb
Host smart-1555838f-9097-4aed-836c-ec7b6bf4748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62593442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_async_fifo_reset.62593442
Directory /workspace/12.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_rx_timeout.2192337509
Short name T706
Test name
Test status
Simulation time 720506241 ps
CPU time 5.85 seconds
Started Jan 21 07:56:26 PM PST 24
Finished Jan 21 07:56:33 PM PST 24
Peak memory 217172 kb
Host smart-ad802c3e-68bf-484e-8d74-667bd34e46b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192337509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_timeout.2192337509
Directory /workspace/12.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/12.spi_device_smoke.2990989724
Short name T912
Test name
Test status
Simulation time 116720751 ps
CPU time 0.92 seconds
Started Jan 21 07:56:21 PM PST 24
Finished Jan 21 07:56:23 PM PST 24
Peak memory 208208 kb
Host smart-efc21f30-3ed0-4028-b4e9-3f5a88f75918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990989724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_smoke.2990989724
Directory /workspace/12.spi_device_smoke/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2780648097
Short name T363
Test name
Test status
Simulation time 322019873240 ps
CPU time 5138.72 seconds
Started Jan 21 07:56:49 PM PST 24
Finished Jan 21 09:22:32 PM PST 24
Peak memory 373292 kb
Host smart-a1cb8d96-dc57-433f-81ea-b6192fa2c10d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780648097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2780648097
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3237831888
Short name T571
Test name
Test status
Simulation time 9019635485 ps
CPU time 35.9 seconds
Started Jan 21 07:56:34 PM PST 24
Finished Jan 21 07:57:12 PM PST 24
Peak memory 217336 kb
Host smart-e8b4e47d-6341-41fb-9a03-7feccac08d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237831888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3237831888
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2216359787
Short name T641
Test name
Test status
Simulation time 740092616 ps
CPU time 5.87 seconds
Started Jan 21 07:56:27 PM PST 24
Finished Jan 21 07:56:34 PM PST 24
Peak memory 217216 kb
Host smart-ba51f711-2922-4762-bc02-b320ad475d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216359787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2216359787
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1595269108
Short name T72
Test name
Test status
Simulation time 176730856 ps
CPU time 1.62 seconds
Started Jan 21 07:56:45 PM PST 24
Finished Jan 21 07:56:48 PM PST 24
Peak memory 217296 kb
Host smart-bd27ce87-3f33-4460-8d78-d9d3d50a5a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595269108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1595269108
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.912829933
Short name T1287
Test name
Test status
Simulation time 124625143 ps
CPU time 0.88 seconds
Started Jan 21 07:56:42 PM PST 24
Finished Jan 21 07:56:44 PM PST 24
Peak memory 207240 kb
Host smart-0850e542-2973-4457-8b4b-79128b6d4d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912829933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.912829933
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tx_async_fifo_reset.658537048
Short name T987
Test name
Test status
Simulation time 57416217 ps
CPU time 0.8 seconds
Started Jan 21 07:56:33 PM PST 24
Finished Jan 21 07:56:37 PM PST 24
Peak memory 207704 kb
Host smart-dfc6787f-e59a-46e1-b42f-1428c5fac8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658537048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tx_async_fifo_reset.658537048
Directory /workspace/12.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_txrx.2229240921
Short name T665
Test name
Test status
Simulation time 22785059947 ps
CPU time 238.21 seconds
Started Jan 21 09:22:11 PM PST 24
Finished Jan 21 09:26:12 PM PST 24
Peak memory 280624 kb
Host smart-2c3e7148-2c21-4808-84be-99d0a51fb036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229240921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_txrx.2229240921
Directory /workspace/12.spi_device_txrx/latest

Test location /workspace/coverage/default/12.spi_device_upload.2205258138
Short name T938
Test name
Test status
Simulation time 8329323146 ps
CPU time 15.36 seconds
Started Jan 21 07:56:45 PM PST 24
Finished Jan 21 07:57:02 PM PST 24
Peak memory 241648 kb
Host smart-20628c88-7d41-4ec2-a6bd-f3f3cfdd42c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205258138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2205258138
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_abort.2807339834
Short name T967
Test name
Test status
Simulation time 44765217 ps
CPU time 0.76 seconds
Started Jan 21 07:57:03 PM PST 24
Finished Jan 21 07:57:08 PM PST 24
Peak memory 207056 kb
Host smart-fa7064f0-5b9a-4efb-9ae3-abdfe6a2a424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807339834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_abort.2807339834
Directory /workspace/13.spi_device_abort/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.823785808
Short name T769
Test name
Test status
Simulation time 22367737 ps
CPU time 0.73 seconds
Started Jan 21 07:57:07 PM PST 24
Finished Jan 21 07:57:10 PM PST 24
Peak memory 206952 kb
Host smart-8dad2ac4-51fe-4f2d-8fc1-d34b8f7a7d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823785808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.823785808
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_bit_transfer.2381387151
Short name T778
Test name
Test status
Simulation time 177356706 ps
CPU time 2.51 seconds
Started Jan 21 07:56:53 PM PST 24
Finished Jan 21 07:57:02 PM PST 24
Peak memory 217152 kb
Host smart-138cfd67-cea4-4358-8496-160d4a8ef67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381387151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_bit_transfer.2381387151
Directory /workspace/13.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/13.spi_device_byte_transfer.1416357529
Short name T1254
Test name
Test status
Simulation time 217852471 ps
CPU time 3.2 seconds
Started Jan 21 07:56:57 PM PST 24
Finished Jan 21 07:57:04 PM PST 24
Peak memory 217176 kb
Host smart-a713f2d9-9e45-4846-8615-4677f56f08ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416357529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_byte_transfer.1416357529
Directory /workspace/13.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2838559675
Short name T1063
Test name
Test status
Simulation time 476986100 ps
CPU time 2.81 seconds
Started Jan 21 07:57:03 PM PST 24
Finished Jan 21 07:57:10 PM PST 24
Peak memory 225488 kb
Host smart-2b1f3d7b-2abf-4942-8bf1-5cfd3c7f8c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838559675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2838559675
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1976251436
Short name T980
Test name
Test status
Simulation time 52277558 ps
CPU time 0.84 seconds
Started Jan 21 08:31:32 PM PST 24
Finished Jan 21 08:31:36 PM PST 24
Peak memory 208096 kb
Host smart-bfdb6904-0ac5-46c2-bec6-688b6f13c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976251436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1976251436
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_dummy_item_extra_dly.4166068036
Short name T1264
Test name
Test status
Simulation time 130926694544 ps
CPU time 350.35 seconds
Started Jan 21 07:56:48 PM PST 24
Finished Jan 21 08:02:40 PM PST 24
Peak memory 275956 kb
Host smart-e9b90bc2-c398-418a-b6de-03fac707a80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166068036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_dummy_item_extra_dly.4166068036
Directory /workspace/13.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/13.spi_device_extreme_fifo_size.3361144341
Short name T1721
Test name
Test status
Simulation time 76323201674 ps
CPU time 3527.58 seconds
Started Jan 21 07:56:49 PM PST 24
Finished Jan 21 08:55:39 PM PST 24
Peak memory 225484 kb
Host smart-1dbecaae-6b5a-4c66-97e2-d73dff00c38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361144341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_extreme_fifo_size.3361144341
Directory /workspace/13.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/13.spi_device_fifo_full.1732643279
Short name T652
Test name
Test status
Simulation time 361801046291 ps
CPU time 559.83 seconds
Started Jan 21 07:56:49 PM PST 24
Finished Jan 21 08:06:12 PM PST 24
Peak memory 250140 kb
Host smart-97dbaa98-e975-4d41-ba86-810280a91354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732643279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_full.1732643279
Directory /workspace/13.spi_device_fifo_full/latest

Test location /workspace/coverage/default/13.spi_device_fifo_underflow_overflow.2003780423
Short name T62
Test name
Test status
Simulation time 32560945830 ps
CPU time 303.53 seconds
Started Jan 21 07:56:53 PM PST 24
Finished Jan 21 08:02:03 PM PST 24
Peak memory 427640 kb
Host smart-ae27a691-64ef-43c7-9484-3c66ab2c9cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003780423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_underflow_overf
low.2003780423
Directory /workspace/13.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3569953817
Short name T1359
Test name
Test status
Simulation time 5450739042 ps
CPU time 88.64 seconds
Started Jan 21 07:57:02 PM PST 24
Finished Jan 21 07:58:35 PM PST 24
Peak memory 266608 kb
Host smart-d790a543-7f25-4805-8a27-16da502eaf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569953817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3569953817
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3476350650
Short name T261
Test name
Test status
Simulation time 5486508561 ps
CPU time 153.51 seconds
Started Jan 21 08:21:20 PM PST 24
Finished Jan 21 08:23:54 PM PST 24
Peak memory 274908 kb
Host smart-04b1b68e-88bf-44b5-9466-9137e96bd54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476350650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3476350650
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2626433314
Short name T283
Test name
Test status
Simulation time 15583213544 ps
CPU time 59.94 seconds
Started Jan 21 07:57:02 PM PST 24
Finished Jan 21 07:58:06 PM PST 24
Peak memory 258632 kb
Host smart-05129506-0a2d-41e5-b439-3afe22daedb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626433314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2626433314
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.921324724
Short name T944
Test name
Test status
Simulation time 620130886 ps
CPU time 7.46 seconds
Started Jan 21 07:57:00 PM PST 24
Finished Jan 21 07:57:12 PM PST 24
Peak memory 241960 kb
Host smart-37a59d8f-3db8-4d24-b8c6-2eeddfea8872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921324724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.921324724
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2537988372
Short name T1288
Test name
Test status
Simulation time 4136265191 ps
CPU time 8.24 seconds
Started Jan 21 07:57:03 PM PST 24
Finished Jan 21 07:57:16 PM PST 24
Peak memory 221416 kb
Host smart-dc6bdfa4-7355-4c6a-bf4b-e591a12a28b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537988372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2537988372
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intr.1070873117
Short name T943
Test name
Test status
Simulation time 8196335023 ps
CPU time 43.14 seconds
Started Jan 21 07:56:59 PM PST 24
Finished Jan 21 07:57:45 PM PST 24
Peak memory 233604 kb
Host smart-46de2276-bb0e-4a0f-8593-72cbf76e4029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070873117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intr.1070873117
Directory /workspace/13.spi_device_intr/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1521722505
Short name T25
Test name
Test status
Simulation time 9747709764 ps
CPU time 15.84 seconds
Started Jan 21 07:57:06 PM PST 24
Finished Jan 21 07:57:24 PM PST 24
Peak memory 255012 kb
Host smart-eb66d96a-16ac-42f3-ab01-71dea854d669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521722505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1521722505
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2015868596
Short name T1330
Test name
Test status
Simulation time 60478777 ps
CPU time 1.08 seconds
Started Jan 21 07:56:55 PM PST 24
Finished Jan 21 07:57:02 PM PST 24
Peak memory 219392 kb
Host smart-4cb701cd-396c-4ef4-a9c4-c9e506dddb37
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015868596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2015868596
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.638155862
Short name T342
Test name
Test status
Simulation time 3732890663 ps
CPU time 12.38 seconds
Started Jan 21 07:57:00 PM PST 24
Finished Jan 21 07:57:18 PM PST 24
Peak memory 221732 kb
Host smart-68e7f99d-aa70-4845-9770-31b5a2e526ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638155862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.638155862
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3743834795
Short name T273
Test name
Test status
Simulation time 3248397212 ps
CPU time 7.62 seconds
Started Jan 21 07:57:03 PM PST 24
Finished Jan 21 07:57:15 PM PST 24
Peak memory 239808 kb
Host smart-9b93584d-63ed-4da2-b535-15eb604b50e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743834795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3743834795
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_perf.955757057
Short name T871
Test name
Test status
Simulation time 74231044519 ps
CPU time 500.97 seconds
Started Jan 21 07:56:59 PM PST 24
Finished Jan 21 08:05:23 PM PST 24
Peak memory 300516 kb
Host smart-7e9ccbe9-6ab4-4d63-87d3-063eaddf0ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955757057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_perf.955757057
Directory /workspace/13.spi_device_perf/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1458694099
Short name T514
Test name
Test status
Simulation time 19033106 ps
CPU time 0.77 seconds
Started Jan 21 07:56:53 PM PST 24
Finished Jan 21 07:57:00 PM PST 24
Peak memory 217020 kb
Host smart-4caed3f9-2e63-44a5-9ecb-f1bc356598c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458694099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1458694099
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2370437670
Short name T1680
Test name
Test status
Simulation time 8734071890 ps
CPU time 7.83 seconds
Started Jan 21 07:57:01 PM PST 24
Finished Jan 21 07:57:14 PM PST 24
Peak memory 234992 kb
Host smart-6199d479-95cb-47b9-8a9e-1b20a7276cc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2370437670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2370437670
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_rx_async_fifo_reset.1122732769
Short name T817
Test name
Test status
Simulation time 45825939 ps
CPU time 0.94 seconds
Started Jan 21 07:56:54 PM PST 24
Finished Jan 21 07:57:01 PM PST 24
Peak memory 208772 kb
Host smart-245f5702-ff9b-4312-be39-860f49877414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122732769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_async_fifo_reset.1122732769
Directory /workspace/13.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_rx_timeout.3700725493
Short name T1017
Test name
Test status
Simulation time 763166927 ps
CPU time 7.07 seconds
Started Jan 21 07:56:52 PM PST 24
Finished Jan 21 07:57:01 PM PST 24
Peak memory 217196 kb
Host smart-2c8914dc-21ed-4bca-a4ed-cac9fe39d600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700725493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_timeout.3700725493
Directory /workspace/13.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/13.spi_device_smoke.3459650562
Short name T794
Test name
Test status
Simulation time 87013825 ps
CPU time 1.02 seconds
Started Jan 21 07:56:49 PM PST 24
Finished Jan 21 07:56:52 PM PST 24
Peak memory 208300 kb
Host smart-b5ec23de-0520-4917-bd74-a4a1b21d9838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459650562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_smoke.3459650562
Directory /workspace/13.spi_device_smoke/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3845386312
Short name T1161
Test name
Test status
Simulation time 4704703619 ps
CPU time 16.33 seconds
Started Jan 21 07:56:52 PM PST 24
Finished Jan 21 07:57:10 PM PST 24
Peak memory 217516 kb
Host smart-f1758a32-14e9-43f4-bf86-55dd040717cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845386312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3845386312
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2282820659
Short name T1353
Test name
Test status
Simulation time 8134841384 ps
CPU time 26.63 seconds
Started Jan 21 07:56:51 PM PST 24
Finished Jan 21 07:57:21 PM PST 24
Peak memory 217304 kb
Host smart-d64e12ec-231c-4ce3-bf36-fbaeef354c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282820659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2282820659
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4028415025
Short name T1118
Test name
Test status
Simulation time 189251844 ps
CPU time 2.26 seconds
Started Jan 21 08:21:33 PM PST 24
Finished Jan 21 08:21:38 PM PST 24
Peak memory 217228 kb
Host smart-346b86a8-3f2b-499e-821c-13cca2bb3559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028415025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4028415025
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4157093854
Short name T1599
Test name
Test status
Simulation time 184669589 ps
CPU time 0.99 seconds
Started Jan 21 07:57:02 PM PST 24
Finished Jan 21 07:57:08 PM PST 24
Peak memory 208376 kb
Host smart-52e6b482-6b86-48ab-90ff-e3311a2d786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157093854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4157093854
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.384399828
Short name T1007
Test name
Test status
Simulation time 17773578 ps
CPU time 0.83 seconds
Started Jan 21 08:54:33 PM PST 24
Finished Jan 21 08:54:40 PM PST 24
Peak memory 208804 kb
Host smart-55bdd694-a7be-461f-9502-186b7a787b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384399828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tx_async_fifo_reset.384399828
Directory /workspace/13.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_txrx.1642829873
Short name T717
Test name
Test status
Simulation time 54948080023 ps
CPU time 479.73 seconds
Started Jan 21 07:56:52 PM PST 24
Finished Jan 21 08:04:54 PM PST 24
Peak memory 266484 kb
Host smart-f12a9499-8dfd-439f-a584-1f8fe3ce6695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642829873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_txrx.1642829873
Directory /workspace/13.spi_device_txrx/latest

Test location /workspace/coverage/default/13.spi_device_upload.1553653961
Short name T532
Test name
Test status
Simulation time 9119700822 ps
CPU time 14.14 seconds
Started Jan 21 07:57:05 PM PST 24
Finished Jan 21 07:57:21 PM PST 24
Peak memory 219488 kb
Host smart-a63cc942-9c4c-4b86-a2cc-d5be3784d387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553653961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1553653961
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_abort.1256994994
Short name T1199
Test name
Test status
Simulation time 17340065 ps
CPU time 0.82 seconds
Started Jan 21 07:57:24 PM PST 24
Finished Jan 21 07:57:29 PM PST 24
Peak memory 207124 kb
Host smart-b2a0c4d0-ada2-4224-9187-f8c2e781c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256994994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_abort.1256994994
Directory /workspace/14.spi_device_abort/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3729706330
Short name T1410
Test name
Test status
Simulation time 50065311 ps
CPU time 0.74 seconds
Started Jan 21 07:57:21 PM PST 24
Finished Jan 21 07:57:25 PM PST 24
Peak memory 206952 kb
Host smart-382ccf6c-a9fc-4c4f-b02e-37f8207a37e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729706330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3729706330
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_bit_transfer.3846653930
Short name T1127
Test name
Test status
Simulation time 1066689053 ps
CPU time 2.6 seconds
Started Jan 21 07:57:14 PM PST 24
Finished Jan 21 07:57:24 PM PST 24
Peak memory 217116 kb
Host smart-3d590bef-cacf-470a-9ebd-ec61a1da7a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846653930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_bit_transfer.3846653930
Directory /workspace/14.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/14.spi_device_byte_transfer.124742669
Short name T723
Test name
Test status
Simulation time 387034836 ps
CPU time 2.24 seconds
Started Jan 21 07:57:11 PM PST 24
Finished Jan 21 07:57:16 PM PST 24
Peak memory 217216 kb
Host smart-28917362-3502-4e34-a6ea-86e0e01d9699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124742669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_byte_transfer.124742669
Directory /workspace/14.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3449201924
Short name T330
Test name
Test status
Simulation time 1020094181 ps
CPU time 3.46 seconds
Started Jan 21 07:57:21 PM PST 24
Finished Jan 21 07:57:28 PM PST 24
Peak memory 219140 kb
Host smart-6cf8cb08-97ba-47a2-b8f0-a4c123c26114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449201924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3449201924
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3811203758
Short name T568
Test name
Test status
Simulation time 17178631 ps
CPU time 0.8 seconds
Started Jan 21 07:57:10 PM PST 24
Finished Jan 21 07:57:14 PM PST 24
Peak memory 208060 kb
Host smart-d3cd82b5-0301-4e43-905d-71c0fa195a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811203758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3811203758
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_dummy_item_extra_dly.1037788743
Short name T891
Test name
Test status
Simulation time 208936299180 ps
CPU time 474.49 seconds
Started Jan 21 07:57:08 PM PST 24
Finished Jan 21 08:05:06 PM PST 24
Peak memory 273692 kb
Host smart-4cc0f367-d205-4023-bf05-b3c9cd8e3a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037788743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_dummy_item_extra_dly.1037788743
Directory /workspace/14.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/14.spi_device_extreme_fifo_size.2728575564
Short name T521
Test name
Test status
Simulation time 68414384483 ps
CPU time 1118.25 seconds
Started Jan 21 07:57:05 PM PST 24
Finished Jan 21 08:15:46 PM PST 24
Peak memory 219828 kb
Host smart-06777586-f86e-4ef4-b1cb-87ef5ebfddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728575564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_extreme_fifo_size.2728575564
Directory /workspace/14.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/14.spi_device_fifo_full.1840746606
Short name T1581
Test name
Test status
Simulation time 69895896667 ps
CPU time 718.8 seconds
Started Jan 21 07:57:08 PM PST 24
Finished Jan 21 08:09:10 PM PST 24
Peak memory 304752 kb
Host smart-8dbf376d-7f13-47b7-80b7-87fe261ca526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840746606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_full.1840746606
Directory /workspace/14.spi_device_fifo_full/latest

Test location /workspace/coverage/default/14.spi_device_fifo_underflow_overflow.2127511546
Short name T765
Test name
Test status
Simulation time 251553526331 ps
CPU time 418.6 seconds
Started Jan 21 07:57:07 PM PST 24
Finished Jan 21 08:04:08 PM PST 24
Peak memory 348156 kb
Host smart-1e817e7c-0dc7-4488-b77e-35d9719a427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127511546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_underflow_overf
low.2127511546
Directory /workspace/14.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2488302585
Short name T1400
Test name
Test status
Simulation time 2512355012 ps
CPU time 29.8 seconds
Started Jan 21 07:57:22 PM PST 24
Finished Jan 21 07:57:57 PM PST 24
Peak memory 249428 kb
Host smart-1f830cbb-f917-416c-aae8-0530abaa0e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488302585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2488302585
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1574382447
Short name T906
Test name
Test status
Simulation time 7931138135 ps
CPU time 127.22 seconds
Started Jan 21 07:57:25 PM PST 24
Finished Jan 21 07:59:36 PM PST 24
Peak memory 266688 kb
Host smart-3fa80cef-5ef4-4cf2-b51f-565ace6c75f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574382447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1574382447
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1637880999
Short name T351
Test name
Test status
Simulation time 392555438434 ps
CPU time 628.41 seconds
Started Jan 21 07:57:23 PM PST 24
Finished Jan 21 08:07:56 PM PST 24
Peak memory 268208 kb
Host smart-0a67fcae-d82b-4a6b-8af8-17d6d4bda25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637880999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1637880999
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2870025376
Short name T984
Test name
Test status
Simulation time 7464858903 ps
CPU time 23.8 seconds
Started Jan 21 07:57:25 PM PST 24
Finished Jan 21 07:57:53 PM PST 24
Peak memory 233844 kb
Host smart-d0496930-124c-41c9-a982-ce85c78c47da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870025376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2870025376
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2091308136
Short name T1384
Test name
Test status
Simulation time 579499500 ps
CPU time 2.78 seconds
Started Jan 21 07:57:22 PM PST 24
Finished Jan 21 07:57:30 PM PST 24
Peak memory 225072 kb
Host smart-42daf93a-c1ce-4ddd-b5b6-25d58ec8b8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091308136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2091308136
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intr.3664341415
Short name T672
Test name
Test status
Simulation time 18540280700 ps
CPU time 69.08 seconds
Started Jan 21 07:57:11 PM PST 24
Finished Jan 21 07:58:23 PM PST 24
Peak memory 232644 kb
Host smart-c491ef4e-6048-49d5-b11e-5572ea102418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664341415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intr.3664341415
Directory /workspace/14.spi_device_intr/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2677851594
Short name T653
Test name
Test status
Simulation time 135691602 ps
CPU time 3.37 seconds
Started Jan 21 07:57:29 PM PST 24
Finished Jan 21 07:57:34 PM PST 24
Peak memory 234908 kb
Host smart-c75d341b-6839-4e27-93d1-1bcbf60214d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677851594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2677851594
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2246913807
Short name T1674
Test name
Test status
Simulation time 99781033 ps
CPU time 1.07 seconds
Started Jan 21 07:57:06 PM PST 24
Finished Jan 21 07:57:09 PM PST 24
Peak memory 219204 kb
Host smart-3ff1f338-4780-4637-8d54-cb2703868414
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246913807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2246913807
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3726805507
Short name T1573
Test name
Test status
Simulation time 18832590211 ps
CPU time 26.98 seconds
Started Jan 21 07:57:22 PM PST 24
Finished Jan 21 07:57:54 PM PST 24
Peak memory 233700 kb
Host smart-d828f2f3-fee5-4707-901b-df9ee095e990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726805507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3726805507
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3324624637
Short name T838
Test name
Test status
Simulation time 180209375 ps
CPU time 4.7 seconds
Started Jan 21 07:57:24 PM PST 24
Finished Jan 21 07:57:33 PM PST 24
Peak memory 239072 kb
Host smart-19df4bb3-eff8-4b81-888a-d47a6574128d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324624637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3324624637
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_perf.3634660638
Short name T632
Test name
Test status
Simulation time 12882001094 ps
CPU time 362.01 seconds
Started Jan 21 07:57:07 PM PST 24
Finished Jan 21 08:03:12 PM PST 24
Peak memory 283964 kb
Host smart-f07f957c-89b9-4195-8761-b2a22058a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634660638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_perf.3634660638
Directory /workspace/14.spi_device_perf/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2128369157
Short name T960
Test name
Test status
Simulation time 28383415 ps
CPU time 0.75 seconds
Started Jan 21 07:57:19 PM PST 24
Finished Jan 21 07:57:24 PM PST 24
Peak memory 217108 kb
Host smart-0730ac8f-3215-4c0d-8f3e-9544f5921101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128369157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2128369157
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4029695501
Short name T1687
Test name
Test status
Simulation time 1576111944 ps
CPU time 6.25 seconds
Started Jan 21 07:57:23 PM PST 24
Finished Jan 21 07:57:34 PM PST 24
Peak memory 234580 kb
Host smart-50332637-6d7f-4396-854d-51c26c244c2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4029695501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4029695501
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_rx_async_fifo_reset.1430066279
Short name T607
Test name
Test status
Simulation time 52202501 ps
CPU time 1 seconds
Started Jan 21 07:57:21 PM PST 24
Finished Jan 21 07:57:26 PM PST 24
Peak memory 208704 kb
Host smart-44c5c079-7f67-4031-b087-44b78f02b535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430066279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_async_fifo_reset.1430066279
Directory /workspace/14.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_rx_timeout.2414107616
Short name T1745
Test name
Test status
Simulation time 788466118 ps
CPU time 6.62 seconds
Started Jan 21 07:57:07 PM PST 24
Finished Jan 21 07:57:17 PM PST 24
Peak memory 217192 kb
Host smart-1d7cd60c-91ef-4438-b0fe-18f693219765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414107616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_timeout.2414107616
Directory /workspace/14.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/14.spi_device_smoke.1623620035
Short name T1436
Test name
Test status
Simulation time 42420961 ps
CPU time 1.37 seconds
Started Jan 21 07:57:11 PM PST 24
Finished Jan 21 07:57:15 PM PST 24
Peak memory 217112 kb
Host smart-39ece4c9-c6bd-4b1c-b530-e5e7b7c3f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623620035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_smoke.1623620035
Directory /workspace/14.spi_device_smoke/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2970768561
Short name T743
Test name
Test status
Simulation time 2765837241 ps
CPU time 39.83 seconds
Started Jan 21 07:57:15 PM PST 24
Finished Jan 21 07:58:02 PM PST 24
Peak memory 217332 kb
Host smart-5bc1bd44-fd5b-4401-9fa3-ad2c91362fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970768561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2970768561
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.902885142
Short name T1507
Test name
Test status
Simulation time 273971840 ps
CPU time 1.14 seconds
Started Jan 21 07:57:17 PM PST 24
Finished Jan 21 07:57:24 PM PST 24
Peak memory 207960 kb
Host smart-2dccff29-4d74-4312-b211-006e61c8cf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902885142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.902885142
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1485436980
Short name T899
Test name
Test status
Simulation time 109883300 ps
CPU time 1.39 seconds
Started Jan 21 07:57:22 PM PST 24
Finished Jan 21 07:57:28 PM PST 24
Peak memory 217308 kb
Host smart-46c61f52-bc54-4f05-9989-a8c3807376d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485436980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1485436980
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1276949604
Short name T1597
Test name
Test status
Simulation time 19963338 ps
CPU time 0.78 seconds
Started Jan 21 07:57:23 PM PST 24
Finished Jan 21 07:57:29 PM PST 24
Peak memory 207212 kb
Host smart-98854588-5eb1-40e0-8b56-66b6b1d348b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276949604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1276949604
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tx_async_fifo_reset.1466749116
Short name T1711
Test name
Test status
Simulation time 17520929 ps
CPU time 0.85 seconds
Started Jan 21 07:57:22 PM PST 24
Finished Jan 21 07:57:28 PM PST 24
Peak memory 207672 kb
Host smart-f133d8bb-f658-48e5-a08c-ea5d99b7afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466749116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tx_async_fifo_reset.1466749116
Directory /workspace/14.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_txrx.3304702503
Short name T1393
Test name
Test status
Simulation time 98556081443 ps
CPU time 1346.36 seconds
Started Jan 21 07:57:09 PM PST 24
Finished Jan 21 08:19:39 PM PST 24
Peak memory 254268 kb
Host smart-d633c9a8-34aa-4775-9f6c-b79ecdb1ddff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304702503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_txrx.3304702503
Directory /workspace/14.spi_device_txrx/latest

Test location /workspace/coverage/default/14.spi_device_upload.1640007863
Short name T1733
Test name
Test status
Simulation time 1009151353 ps
CPU time 5.71 seconds
Started Jan 21 07:57:23 PM PST 24
Finished Jan 21 07:57:34 PM PST 24
Peak memory 221108 kb
Host smart-2d8bf851-8ca3-4459-94e6-e8bb0f35bd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640007863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1640007863
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_abort.595709420
Short name T1231
Test name
Test status
Simulation time 25038410 ps
CPU time 0.83 seconds
Started Jan 21 07:57:55 PM PST 24
Finished Jan 21 07:57:58 PM PST 24
Peak memory 207000 kb
Host smart-2af22056-11b7-4594-b631-17913b1bdfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595709420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_abort.595709420
Directory /workspace/15.spi_device_abort/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2216175291
Short name T1612
Test name
Test status
Simulation time 22794307 ps
CPU time 0.75 seconds
Started Jan 21 07:58:12 PM PST 24
Finished Jan 21 07:58:14 PM PST 24
Peak memory 206980 kb
Host smart-8a36e6b2-058a-454a-9e49-13be55b67a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216175291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2216175291
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_bit_transfer.2791228256
Short name T1716
Test name
Test status
Simulation time 164031492 ps
CPU time 2.26 seconds
Started Jan 21 07:57:43 PM PST 24
Finished Jan 21 07:57:46 PM PST 24
Peak memory 217256 kb
Host smart-8a8f26cf-f64f-4ffe-90da-ca4526720c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791228256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_bit_transfer.2791228256
Directory /workspace/15.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/15.spi_device_byte_transfer.2077296471
Short name T1163
Test name
Test status
Simulation time 673200583 ps
CPU time 4.35 seconds
Started Jan 21 07:57:48 PM PST 24
Finished Jan 21 07:57:54 PM PST 24
Peak memory 217236 kb
Host smart-92bc6207-4236-459b-91f1-f9fa983b573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077296471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_byte_transfer.2077296471
Directory /workspace/15.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.531635981
Short name T923
Test name
Test status
Simulation time 139117508 ps
CPU time 2.6 seconds
Started Jan 21 07:57:56 PM PST 24
Finished Jan 21 07:58:02 PM PST 24
Peak memory 219048 kb
Host smart-8f48b11e-414c-464d-a537-7c8904bab665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531635981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.531635981
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1064482097
Short name T1202
Test name
Test status
Simulation time 16326589 ps
CPU time 0.81 seconds
Started Jan 21 07:57:48 PM PST 24
Finished Jan 21 07:57:50 PM PST 24
Peak memory 207036 kb
Host smart-9ce355c5-cf0d-491b-8888-f50a03c41527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064482097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1064482097
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_dummy_item_extra_dly.2775845285
Short name T1689
Test name
Test status
Simulation time 319416713432 ps
CPU time 361.74 seconds
Started Jan 21 07:57:36 PM PST 24
Finished Jan 21 08:03:40 PM PST 24
Peak memory 281056 kb
Host smart-9582c283-f563-45bc-9c90-f35ba78ea09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775845285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_dummy_item_extra_dly.2775845285
Directory /workspace/15.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/15.spi_device_extreme_fifo_size.2375590262
Short name T1367
Test name
Test status
Simulation time 168290491217 ps
CPU time 363.82 seconds
Started Jan 21 07:57:33 PM PST 24
Finished Jan 21 08:03:38 PM PST 24
Peak memory 218456 kb
Host smart-2d47305d-b1a3-404f-b378-8345c3647cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375590262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_extreme_fifo_size.2375590262
Directory /workspace/15.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/15.spi_device_fifo_full.3267847057
Short name T1271
Test name
Test status
Simulation time 112912475294 ps
CPU time 1143.54 seconds
Started Jan 21 07:57:35 PM PST 24
Finished Jan 21 08:16:41 PM PST 24
Peak memory 303824 kb
Host smart-7f96b3db-de44-4da3-9715-ac5280fd6a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267847057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_full.3267847057
Directory /workspace/15.spi_device_fifo_full/latest

Test location /workspace/coverage/default/15.spi_device_fifo_underflow_overflow.654765805
Short name T656
Test name
Test status
Simulation time 24761728556 ps
CPU time 223.9 seconds
Started Jan 21 07:57:31 PM PST 24
Finished Jan 21 08:01:16 PM PST 24
Peak memory 325960 kb
Host smart-a636a34c-5b83-42a0-b8e1-811db247c193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654765805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_underflow_overfl
ow.654765805
Directory /workspace/15.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2313390831
Short name T1142
Test name
Test status
Simulation time 53892852754 ps
CPU time 222.45 seconds
Started Jan 21 07:57:59 PM PST 24
Finished Jan 21 08:01:44 PM PST 24
Peak memory 250708 kb
Host smart-f7e7804f-e5de-4dd7-aa78-24e2d72ee4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313390831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2313390831
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.366913164
Short name T27
Test name
Test status
Simulation time 103199730490 ps
CPU time 314.72 seconds
Started Jan 21 07:57:58 PM PST 24
Finished Jan 21 08:03:15 PM PST 24
Peak memory 269552 kb
Host smart-7231605e-b00e-473a-99e1-ef616168c2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366913164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.366913164
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3202483550
Short name T692
Test name
Test status
Simulation time 1760207308 ps
CPU time 5.99 seconds
Started Jan 21 07:57:57 PM PST 24
Finished Jan 21 07:58:06 PM PST 24
Peak memory 241956 kb
Host smart-8356006b-fffd-4891-a2ef-f47ac1c75948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202483550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3202483550
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intr.1165256824
Short name T681
Test name
Test status
Simulation time 22191404626 ps
CPU time 28.6 seconds
Started Jan 21 07:57:43 PM PST 24
Finished Jan 21 07:58:13 PM PST 24
Peak memory 235344 kb
Host smart-dc59dab3-d41d-486c-89bd-1436deee30bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165256824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intr.1165256824
Directory /workspace/15.spi_device_intr/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1625057278
Short name T1647
Test name
Test status
Simulation time 28754832210 ps
CPU time 38.51 seconds
Started Jan 21 07:57:57 PM PST 24
Finished Jan 21 07:58:38 PM PST 24
Peak memory 250844 kb
Host smart-9441db7b-a1b1-4c4a-ac88-ec64f8824818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625057278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1625057278
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3838270876
Short name T1275
Test name
Test status
Simulation time 30621137 ps
CPU time 1.12 seconds
Started Jan 21 07:57:44 PM PST 24
Finished Jan 21 07:57:46 PM PST 24
Peak memory 219572 kb
Host smart-39030a8a-4771-42c9-b742-8b98b365cc15
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838270876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3838270876
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.200480824
Short name T1195
Test name
Test status
Simulation time 1547715608 ps
CPU time 7.83 seconds
Started Jan 21 07:57:58 PM PST 24
Finished Jan 21 07:58:08 PM PST 24
Peak memory 241956 kb
Host smart-0590d801-0147-4c13-85fb-690dbd9dedec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200480824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.200480824
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3208098165
Short name T597
Test name
Test status
Simulation time 358338716 ps
CPU time 3.18 seconds
Started Jan 21 07:57:55 PM PST 24
Finished Jan 21 07:58:01 PM PST 24
Peak memory 233760 kb
Host smart-8dec6aa2-db9f-4b20-a86c-e32ad02a6a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208098165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3208098165
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_perf.4174243872
Short name T1739
Test name
Test status
Simulation time 39785089983 ps
CPU time 770.14 seconds
Started Jan 21 07:57:49 PM PST 24
Finished Jan 21 08:10:41 PM PST 24
Peak memory 285456 kb
Host smart-cd7f7129-7353-4c30-a6f8-8a5d320b6c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174243872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_perf.4174243872
Directory /workspace/15.spi_device_perf/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2001376216
Short name T42
Test name
Test status
Simulation time 16469196 ps
CPU time 0.76 seconds
Started Jan 21 07:57:43 PM PST 24
Finished Jan 21 07:57:45 PM PST 24
Peak memory 217092 kb
Host smart-044b9999-1545-4e7f-abbe-dd56c795d86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001376216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2001376216
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2251471734
Short name T699
Test name
Test status
Simulation time 2685361306 ps
CPU time 5.8 seconds
Started Jan 21 07:58:01 PM PST 24
Finished Jan 21 07:58:08 PM PST 24
Peak memory 234988 kb
Host smart-6e97f616-6647-465d-9093-fc5c80606855
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2251471734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2251471734
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_rx_async_fifo_reset.1816482413
Short name T1332
Test name
Test status
Simulation time 102349201 ps
CPU time 0.96 seconds
Started Jan 21 07:57:59 PM PST 24
Finished Jan 21 07:58:03 PM PST 24
Peak memory 208808 kb
Host smart-c4754dac-506f-4049-b5d4-7a1b6d66d5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816482413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_async_fifo_reset.1816482413
Directory /workspace/15.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_rx_timeout.961700637
Short name T1537
Test name
Test status
Simulation time 1571209287 ps
CPU time 6 seconds
Started Jan 21 07:57:44 PM PST 24
Finished Jan 21 07:57:51 PM PST 24
Peak memory 217252 kb
Host smart-32a82ecd-2e56-4e9e-951d-b21f4a34a174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961700637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_timeout.961700637
Directory /workspace/15.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/15.spi_device_smoke.2284154846
Short name T744
Test name
Test status
Simulation time 221641433 ps
CPU time 1.19 seconds
Started Jan 21 07:57:33 PM PST 24
Finished Jan 21 07:57:35 PM PST 24
Peak memory 208356 kb
Host smart-5cac0cb0-0e07-4278-bbf1-f0e58d841917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284154846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_smoke.2284154846
Directory /workspace/15.spi_device_smoke/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.436973114
Short name T1144
Test name
Test status
Simulation time 9133043496 ps
CPU time 43.77 seconds
Started Jan 21 07:57:44 PM PST 24
Finished Jan 21 07:58:28 PM PST 24
Peak memory 217368 kb
Host smart-38f0ea61-fecd-4469-889c-928d8f3b613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436973114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.436973114
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1322486304
Short name T976
Test name
Test status
Simulation time 8779478940 ps
CPU time 28.97 seconds
Started Jan 21 07:57:44 PM PST 24
Finished Jan 21 07:58:14 PM PST 24
Peak memory 217312 kb
Host smart-1c06d447-080a-457e-8447-965d57db7401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322486304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1322486304
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.184123907
Short name T1651
Test name
Test status
Simulation time 27121631 ps
CPU time 1.05 seconds
Started Jan 21 07:57:58 PM PST 24
Finished Jan 21 07:58:01 PM PST 24
Peak memory 208812 kb
Host smart-a1e44045-0e1a-4c25-852d-190bd033dda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184123907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.184123907
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2602651432
Short name T1057
Test name
Test status
Simulation time 233591715 ps
CPU time 1.1 seconds
Started Jan 21 07:57:55 PM PST 24
Finished Jan 21 07:57:58 PM PST 24
Peak memory 207368 kb
Host smart-74f881e9-91b7-493b-b648-fc5340f79e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602651432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2602651432
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tx_async_fifo_reset.383767069
Short name T1311
Test name
Test status
Simulation time 18080821 ps
CPU time 0.81 seconds
Started Jan 21 07:57:57 PM PST 24
Finished Jan 21 07:58:00 PM PST 24
Peak memory 207736 kb
Host smart-a2d5fb44-e1f8-4197-bf36-87fd3c8b553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383767069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tx_async_fifo_reset.383767069
Directory /workspace/15.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_txrx.4208081541
Short name T775
Test name
Test status
Simulation time 91706192237 ps
CPU time 232.12 seconds
Started Jan 21 07:57:35 PM PST 24
Finished Jan 21 08:01:30 PM PST 24
Peak memory 291032 kb
Host smart-26de5643-3854-4245-8396-97ef6fee3790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208081541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_txrx.4208081541
Directory /workspace/15.spi_device_txrx/latest

Test location /workspace/coverage/default/16.spi_device_abort.4170401994
Short name T799
Test name
Test status
Simulation time 15605420 ps
CPU time 0.81 seconds
Started Jan 21 07:58:14 PM PST 24
Finished Jan 21 07:58:17 PM PST 24
Peak memory 207072 kb
Host smart-303f0008-130e-4166-8c62-014b85942d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170401994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_abort.4170401994
Directory /workspace/16.spi_device_abort/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.475886845
Short name T1592
Test name
Test status
Simulation time 33106243 ps
CPU time 0.73 seconds
Started Jan 21 08:05:14 PM PST 24
Finished Jan 21 08:05:16 PM PST 24
Peak memory 206924 kb
Host smart-d3e5f0f3-05e1-40a1-9b27-7296eff5b251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475886845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.475886845
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_bit_transfer.3341570449
Short name T1293
Test name
Test status
Simulation time 255123117 ps
CPU time 3.06 seconds
Started Jan 21 07:58:09 PM PST 24
Finished Jan 21 07:58:13 PM PST 24
Peak memory 217180 kb
Host smart-1abc317a-a29a-4d7e-97a8-073efd49d1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341570449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_bit_transfer.3341570449
Directory /workspace/16.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/16.spi_device_byte_transfer.2071921500
Short name T1014
Test name
Test status
Simulation time 1190263138 ps
CPU time 3.91 seconds
Started Jan 21 07:58:14 PM PST 24
Finished Jan 21 07:58:20 PM PST 24
Peak memory 217176 kb
Host smart-3ada52c9-2f98-4043-b09e-9800458ba968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071921500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_byte_transfer.2071921500
Directory /workspace/16.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1757468112
Short name T338
Test name
Test status
Simulation time 21103228214 ps
CPU time 9.53 seconds
Started Jan 21 08:52:37 PM PST 24
Finished Jan 21 08:53:15 PM PST 24
Peak memory 221472 kb
Host smart-df66d52b-ef5c-4eee-8a4f-598dd5ddd8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757468112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1757468112
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.605516138
Short name T1316
Test name
Test status
Simulation time 17239078 ps
CPU time 0.83 seconds
Started Jan 21 07:58:16 PM PST 24
Finished Jan 21 07:58:19 PM PST 24
Peak memory 207044 kb
Host smart-9646adb2-25e8-4c31-8d56-3cfa91f0d428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605516138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.605516138
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_extreme_fifo_size.3174240687
Short name T57
Test name
Test status
Simulation time 317180089026 ps
CPU time 1808.51 seconds
Started Jan 21 07:58:13 PM PST 24
Finished Jan 21 08:28:24 PM PST 24
Peak memory 219408 kb
Host smart-17378028-ab16-408f-be33-2e4e98ba5d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174240687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_extreme_fifo_size.3174240687
Directory /workspace/16.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/16.spi_device_fifo_full.962003141
Short name T616
Test name
Test status
Simulation time 58465946722 ps
CPU time 576.36 seconds
Started Jan 21 07:58:13 PM PST 24
Finished Jan 21 08:07:52 PM PST 24
Peak memory 288216 kb
Host smart-31685322-cddb-4691-b241-6e8fef7dc817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962003141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_full.962003141
Directory /workspace/16.spi_device_fifo_full/latest

Test location /workspace/coverage/default/16.spi_device_fifo_underflow_overflow.2398388256
Short name T787
Test name
Test status
Simulation time 204628392508 ps
CPU time 473.58 seconds
Started Jan 21 07:58:12 PM PST 24
Finished Jan 21 08:06:07 PM PST 24
Peak memory 395528 kb
Host smart-7c3c3b58-5c42-41ff-8cbe-179cc20c020e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398388256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_underflow_overf
low.2398388256
Directory /workspace/16.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.426015457
Short name T676
Test name
Test status
Simulation time 11998873574 ps
CPU time 65.19 seconds
Started Jan 21 08:13:10 PM PST 24
Finished Jan 21 08:14:16 PM PST 24
Peak memory 250248 kb
Host smart-b3eb20a6-f7ce-466c-9f4a-25f9b6a5dec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426015457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.426015457
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.594870224
Short name T1368
Test name
Test status
Simulation time 34543566668 ps
CPU time 109.74 seconds
Started Jan 21 08:25:06 PM PST 24
Finished Jan 21 08:27:00 PM PST 24
Peak memory 251388 kb
Host smart-7af0dd4f-50d0-4836-90ce-9db6b3de9e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594870224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.594870224
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3071352667
Short name T44
Test name
Test status
Simulation time 33813396845 ps
CPU time 147.52 seconds
Started Jan 21 10:05:23 PM PST 24
Finished Jan 21 10:07:54 PM PST 24
Peak memory 267736 kb
Host smart-44a277bc-89a0-4e22-9670-f0ea2ecd7afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071352667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3071352667
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.482880717
Short name T369
Test name
Test status
Simulation time 17518544432 ps
CPU time 33.38 seconds
Started Jan 21 07:58:17 PM PST 24
Finished Jan 21 07:58:52 PM PST 24
Peak memory 240588 kb
Host smart-6165b0c4-a416-4a40-972d-b66ac85de110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482880717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.482880717
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.167389379
Short name T302
Test name
Test status
Simulation time 1128788987 ps
CPU time 7.17 seconds
Started Jan 21 08:27:15 PM PST 24
Finished Jan 21 08:27:23 PM PST 24
Peak memory 225512 kb
Host smart-b1eb64b7-8650-4d35-94fb-fcd125529aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167389379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.167389379
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intr.3914279761
Short name T606
Test name
Test status
Simulation time 13016973758 ps
CPU time 25.34 seconds
Started Jan 21 07:58:12 PM PST 24
Finished Jan 21 07:58:39 PM PST 24
Peak memory 225672 kb
Host smart-7dc415c5-9fc4-440d-845e-3a8a97e3b158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914279761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intr.3914279761
Directory /workspace/16.spi_device_intr/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2689896481
Short name T1775
Test name
Test status
Simulation time 3121861540 ps
CPU time 10.57 seconds
Started Jan 21 07:58:17 PM PST 24
Finished Jan 21 07:58:29 PM PST 24
Peak memory 221168 kb
Host smart-4fa051cc-c555-4a52-99c8-a0fbf9befef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689896481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2689896481
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1003874431
Short name T1685
Test name
Test status
Simulation time 54486268 ps
CPU time 1.11 seconds
Started Jan 21 07:58:13 PM PST 24
Finished Jan 21 07:58:16 PM PST 24
Peak memory 219356 kb
Host smart-0d511235-c066-4425-b3e3-f2c2b622df38
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003874431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1003874431
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2587882755
Short name T26
Test name
Test status
Simulation time 1654986237 ps
CPU time 9.04 seconds
Started Jan 21 08:23:54 PM PST 24
Finished Jan 21 08:24:03 PM PST 24
Peak memory 241752 kb
Host smart-6c2605b6-deae-4ebc-ab62-1355da3a06b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587882755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2587882755
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.387097061
Short name T1226
Test name
Test status
Simulation time 4305195246 ps
CPU time 16.62 seconds
Started Jan 21 08:11:38 PM PST 24
Finished Jan 21 08:11:58 PM PST 24
Peak memory 220084 kb
Host smart-b68888ee-dbf5-4648-a48d-2a671dd1e34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387097061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.387097061
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_perf.2922692500
Short name T526
Test name
Test status
Simulation time 47923013502 ps
CPU time 327.09 seconds
Started Jan 21 07:58:16 PM PST 24
Finished Jan 21 08:03:45 PM PST 24
Peak memory 241460 kb
Host smart-619404f7-e1c3-4137-bd21-f20d945fb780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922692500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_perf.2922692500
Directory /workspace/16.spi_device_perf/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1295295119
Short name T1119
Test name
Test status
Simulation time 23624348 ps
CPU time 0.82 seconds
Started Jan 21 07:58:13 PM PST 24
Finished Jan 21 07:58:16 PM PST 24
Peak memory 217052 kb
Host smart-e7f85bdf-38a8-4585-b677-d6230af4a340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295295119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1295295119
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1010777942
Short name T1096
Test name
Test status
Simulation time 315930921 ps
CPU time 3.67 seconds
Started Jan 21 07:58:17 PM PST 24
Finished Jan 21 07:58:23 PM PST 24
Peak memory 234528 kb
Host smart-2a07395a-2ff9-49a2-b127-d555a924b679
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1010777942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1010777942
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_rx_async_fifo_reset.311058109
Short name T1389
Test name
Test status
Simulation time 85093600 ps
CPU time 0.91 seconds
Started Jan 21 08:45:05 PM PST 24
Finished Jan 21 08:45:07 PM PST 24
Peak memory 208796 kb
Host smart-049ecbf9-0b86-4b4b-b34e-93ce7730bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311058109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_async_fifo_reset.311058109
Directory /workspace/16.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_rx_timeout.1079975343
Short name T1181
Test name
Test status
Simulation time 2256977762 ps
CPU time 6.7 seconds
Started Jan 21 07:58:10 PM PST 24
Finished Jan 21 07:58:18 PM PST 24
Peak memory 217156 kb
Host smart-2812b367-ac6b-42e3-8372-0ed3e83a93e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079975343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_timeout.1079975343
Directory /workspace/16.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/16.spi_device_smoke.287012087
Short name T1168
Test name
Test status
Simulation time 23584898 ps
CPU time 1.15 seconds
Started Jan 21 07:58:11 PM PST 24
Finished Jan 21 07:58:14 PM PST 24
Peak memory 208744 kb
Host smart-52fe6e1d-30d4-4a7a-9923-614e76733bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287012087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_smoke.287012087
Directory /workspace/16.spi_device_smoke/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3587749848
Short name T955
Test name
Test status
Simulation time 3435305294 ps
CPU time 17.67 seconds
Started Jan 21 07:58:11 PM PST 24
Finished Jan 21 07:58:30 PM PST 24
Peak memory 217624 kb
Host smart-9dfc0363-38a8-442a-9870-5e7a84de1e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587749848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3587749848
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3126859470
Short name T572
Test name
Test status
Simulation time 6243366014 ps
CPU time 5.46 seconds
Started Jan 21 08:22:21 PM PST 24
Finished Jan 21 08:22:28 PM PST 24
Peak memory 217344 kb
Host smart-435e975d-d60a-4645-838d-fa4a32c4a849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126859470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3126859470
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1499332068
Short name T788
Test name
Test status
Simulation time 415155501 ps
CPU time 2.55 seconds
Started Jan 21 07:58:08 PM PST 24
Finished Jan 21 07:58:12 PM PST 24
Peak memory 217224 kb
Host smart-643ab659-f43c-4799-b32e-afaa471e76d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499332068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1499332068
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1172390753
Short name T649
Test name
Test status
Simulation time 285174818 ps
CPU time 1.08 seconds
Started Jan 21 07:58:09 PM PST 24
Finished Jan 21 07:58:11 PM PST 24
Peak memory 207264 kb
Host smart-0f7951fd-25b4-4d88-ad1a-cb622a3a837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172390753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1172390753
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tx_async_fifo_reset.1511052345
Short name T660
Test name
Test status
Simulation time 30886677 ps
CPU time 0.82 seconds
Started Jan 21 07:58:09 PM PST 24
Finished Jan 21 07:58:11 PM PST 24
Peak memory 207676 kb
Host smart-a5a3dd73-c455-4167-949e-d247ab036176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511052345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tx_async_fifo_reset.1511052345
Directory /workspace/16.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_txrx.2666041733
Short name T633
Test name
Test status
Simulation time 12357312064 ps
CPU time 133.14 seconds
Started Jan 21 07:58:17 PM PST 24
Finished Jan 21 08:00:32 PM PST 24
Peak memory 253484 kb
Host smart-210a8bcd-6da9-469e-ac53-899bb9631026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666041733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_txrx.2666041733
Directory /workspace/16.spi_device_txrx/latest

Test location /workspace/coverage/default/16.spi_device_upload.253969253
Short name T339
Test name
Test status
Simulation time 1193536164 ps
CPU time 5.46 seconds
Started Jan 21 07:58:19 PM PST 24
Finished Jan 21 07:58:26 PM PST 24
Peak memory 219604 kb
Host smart-ad3f1037-ad5b-42ec-8a39-bf86eca2ca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253969253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.253969253
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2824223569
Short name T993
Test name
Test status
Simulation time 15118033 ps
CPU time 0.75 seconds
Started Jan 21 07:58:57 PM PST 24
Finished Jan 21 07:58:59 PM PST 24
Peak memory 206932 kb
Host smart-ca350a68-2695-4114-9cee-63e0e4110bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824223569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2824223569
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_bit_transfer.2507966841
Short name T860
Test name
Test status
Simulation time 2515835626 ps
CPU time 3.07 seconds
Started Jan 21 07:58:39 PM PST 24
Finished Jan 21 07:58:43 PM PST 24
Peak memory 217236 kb
Host smart-88beab2a-232d-4ef6-aed4-cc176d8bd711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507966841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_bit_transfer.2507966841
Directory /workspace/17.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/17.spi_device_byte_transfer.3083512687
Short name T66
Test name
Test status
Simulation time 206068371 ps
CPU time 2.78 seconds
Started Jan 21 08:50:59 PM PST 24
Finished Jan 21 08:51:39 PM PST 24
Peak memory 217180 kb
Host smart-333a24fb-5a09-4c0c-9ee2-22d4ccfc5897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083512687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_byte_transfer.3083512687
Directory /workspace/17.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3936003619
Short name T70
Test name
Test status
Simulation time 49885814 ps
CPU time 2.85 seconds
Started Jan 21 07:58:45 PM PST 24
Finished Jan 21 07:58:49 PM PST 24
Peak memory 233836 kb
Host smart-f7f336a9-5557-4fdc-abf8-a7119f3ccd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936003619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3936003619
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2048320291
Short name T1501
Test name
Test status
Simulation time 39331986 ps
CPU time 0.77 seconds
Started Jan 21 07:58:28 PM PST 24
Finished Jan 21 07:58:30 PM PST 24
Peak memory 207052 kb
Host smart-0ee213e7-4706-4532-9f60-de67773fd58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048320291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2048320291
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_dummy_item_extra_dly.3980694317
Short name T1373
Test name
Test status
Simulation time 329823347753 ps
CPU time 826.89 seconds
Started Jan 21 07:58:32 PM PST 24
Finished Jan 21 08:12:21 PM PST 24
Peak memory 260064 kb
Host smart-76ec6c39-719b-4f98-9c17-8c6f36914b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980694317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_dummy_item_extra_dly.3980694317
Directory /workspace/17.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/17.spi_device_extreme_fifo_size.28676701
Short name T820
Test name
Test status
Simulation time 82583163268 ps
CPU time 975.8 seconds
Started Jan 21 07:58:18 PM PST 24
Finished Jan 21 08:14:36 PM PST 24
Peak memory 221784 kb
Host smart-e63bceba-9165-4129-a3cf-535254049bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28676701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_extreme_fifo_size.28676701
Directory /workspace/17.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/17.spi_device_fifo_full.421009252
Short name T1604
Test name
Test status
Simulation time 35015894348 ps
CPU time 307.51 seconds
Started Jan 21 08:24:01 PM PST 24
Finished Jan 21 08:29:09 PM PST 24
Peak memory 255260 kb
Host smart-e8faeb0d-3760-4e0a-b78a-df7ab92bced0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421009252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_full.421009252
Directory /workspace/17.spi_device_fifo_full/latest

Test location /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.2835960029
Short name T1344
Test name
Test status
Simulation time 93699680607 ps
CPU time 404.93 seconds
Started Jan 21 09:10:10 PM PST 24
Finished Jan 21 09:17:14 PM PST 24
Peak memory 403628 kb
Host smart-e4fde3b7-f0ab-4121-8090-0a9567e94fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835960029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_underflow_overf
low.2835960029
Directory /workspace/17.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.866593094
Short name T1610
Test name
Test status
Simulation time 769228572753 ps
CPU time 419.44 seconds
Started Jan 21 07:58:47 PM PST 24
Finished Jan 21 08:05:47 PM PST 24
Peak memory 266252 kb
Host smart-d88613c7-9c0d-46ea-b5b1-37ca2df268ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866593094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.866593094
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1501125676
Short name T113
Test name
Test status
Simulation time 17904777057 ps
CPU time 28.81 seconds
Started Jan 21 07:58:44 PM PST 24
Finished Jan 21 07:59:14 PM PST 24
Peak memory 242080 kb
Host smart-e73cefb8-bb88-4f2b-8f86-746eb0e10baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501125676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1501125676
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3208772384
Short name T832
Test name
Test status
Simulation time 84138796 ps
CPU time 3.89 seconds
Started Jan 21 07:58:44 PM PST 24
Finished Jan 21 07:58:49 PM PST 24
Peak memory 238948 kb
Host smart-cf5019a5-5bdd-4a5b-b8db-96d36e77d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208772384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3208772384
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intr.744216677
Short name T1011
Test name
Test status
Simulation time 19756003395 ps
CPU time 71.87 seconds
Started Jan 21 07:58:28 PM PST 24
Finished Jan 21 07:59:41 PM PST 24
Peak memory 233680 kb
Host smart-692d12dd-94c0-4a3f-bf27-df4c586fc1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744216677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intr.744216677
Directory /workspace/17.spi_device_intr/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1871908886
Short name T1183
Test name
Test status
Simulation time 5783759487 ps
CPU time 10.46 seconds
Started Jan 21 07:58:46 PM PST 24
Finished Jan 21 07:58:58 PM PST 24
Peak memory 258412 kb
Host smart-1b0358d5-8474-48d0-989d-01f8f087780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871908886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1871908886
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1607718838
Short name T1472
Test name
Test status
Simulation time 27288873 ps
CPU time 1.09 seconds
Started Jan 21 07:58:28 PM PST 24
Finished Jan 21 07:58:30 PM PST 24
Peak memory 219368 kb
Host smart-ffc0cc48-45f6-4fa9-bdf2-f3f8760cf4db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607718838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1607718838
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.343289385
Short name T1094
Test name
Test status
Simulation time 230778630 ps
CPU time 3.04 seconds
Started Jan 21 07:58:47 PM PST 24
Finished Jan 21 07:58:51 PM PST 24
Peak memory 234752 kb
Host smart-360f591c-563a-498a-ae2f-91e095d72428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343289385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.343289385
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3190336306
Short name T600
Test name
Test status
Simulation time 4569804500 ps
CPU time 22.27 seconds
Started Jan 21 07:58:36 PM PST 24
Finished Jan 21 07:59:00 PM PST 24
Peak memory 229996 kb
Host smart-81491c30-93cd-4fb3-be78-f1694a67b1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190336306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3190336306
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_perf.1445105930
Short name T1177
Test name
Test status
Simulation time 22503954831 ps
CPU time 310.31 seconds
Started Jan 21 07:58:27 PM PST 24
Finished Jan 21 08:03:39 PM PST 24
Peak memory 240604 kb
Host smart-61e98672-4891-4e23-9d60-7a734f9e3c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445105930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_perf.1445105930
Directory /workspace/17.spi_device_perf/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3753503399
Short name T1128
Test name
Test status
Simulation time 44981930 ps
CPU time 0.76 seconds
Started Jan 21 07:58:29 PM PST 24
Finished Jan 21 07:58:31 PM PST 24
Peak memory 217112 kb
Host smart-9fd51ad9-5683-4f48-91c2-d62ef0ea445c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753503399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3753503399
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4031531481
Short name T835
Test name
Test status
Simulation time 210743170 ps
CPU time 5.11 seconds
Started Jan 21 07:58:50 PM PST 24
Finished Jan 21 07:58:56 PM PST 24
Peak memory 234868 kb
Host smart-d19bbc4b-b339-4eb8-b54c-a7a9e8aeabfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4031531481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4031531481
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_rx_async_fifo_reset.1564334565
Short name T1557
Test name
Test status
Simulation time 128852020 ps
CPU time 0.92 seconds
Started Jan 21 07:58:36 PM PST 24
Finished Jan 21 07:58:38 PM PST 24
Peak memory 208996 kb
Host smart-e993b874-4702-4b38-b688-6af50d7afe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564334565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_async_fifo_reset.1564334565
Directory /workspace/17.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_rx_timeout.2410362737
Short name T1747
Test name
Test status
Simulation time 1238385140 ps
CPU time 5.14 seconds
Started Jan 21 07:58:29 PM PST 24
Finished Jan 21 07:58:35 PM PST 24
Peak memory 217232 kb
Host smart-13467387-7715-4395-8b2a-46a87133856c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410362737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_timeout.2410362737
Directory /workspace/17.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/17.spi_device_smoke.330861734
Short name T492
Test name
Test status
Simulation time 172101354 ps
CPU time 0.95 seconds
Started Jan 21 08:34:18 PM PST 24
Finished Jan 21 08:34:20 PM PST 24
Peak memory 208768 kb
Host smart-72a2684f-b0ba-47b7-a94a-66a2ce612fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330861734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_smoke.330861734
Directory /workspace/17.spi_device_smoke/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.927588454
Short name T1087
Test name
Test status
Simulation time 300956217539 ps
CPU time 3643.17 seconds
Started Jan 21 07:58:50 PM PST 24
Finished Jan 21 08:59:34 PM PST 24
Peak memory 534108 kb
Host smart-8c1613ae-79d3-4db7-9f59-43a791964b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927588454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.927588454
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.146792880
Short name T374
Test name
Test status
Simulation time 1803693296 ps
CPU time 25.1 seconds
Started Jan 21 07:58:36 PM PST 24
Finished Jan 21 07:59:03 PM PST 24
Peak memory 220608 kb
Host smart-55a8054b-4ab5-4cc0-8669-a035ecbed68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146792880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.146792880
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1335432127
Short name T1442
Test name
Test status
Simulation time 34965512088 ps
CPU time 21.89 seconds
Started Jan 21 07:58:28 PM PST 24
Finished Jan 21 07:58:51 PM PST 24
Peak memory 217316 kb
Host smart-0fff2322-6ad7-4c98-ae26-1b5f30f441a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335432127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1335432127
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.331028569
Short name T1082
Test name
Test status
Simulation time 16585285 ps
CPU time 0.84 seconds
Started Jan 21 07:58:39 PM PST 24
Finished Jan 21 07:58:41 PM PST 24
Peak memory 207316 kb
Host smart-0953723c-e5e4-4349-b7df-67cfb04577e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331028569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.331028569
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2882781763
Short name T1350
Test name
Test status
Simulation time 79287493 ps
CPU time 0.99 seconds
Started Jan 21 07:58:37 PM PST 24
Finished Jan 21 07:58:39 PM PST 24
Peak memory 207500 kb
Host smart-39ade8d8-1b2e-4604-9d10-958bd1775213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882781763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2882781763
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tx_async_fifo_reset.3819532637
Short name T1108
Test name
Test status
Simulation time 20962864 ps
CPU time 0.81 seconds
Started Jan 21 07:58:39 PM PST 24
Finished Jan 21 07:58:41 PM PST 24
Peak memory 208764 kb
Host smart-cfaaa4aa-3a1e-4f2c-a690-76d1ecd50132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819532637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tx_async_fifo_reset.3819532637
Directory /workspace/17.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_txrx.3183059487
Short name T1376
Test name
Test status
Simulation time 56204980105 ps
CPU time 381.86 seconds
Started Jan 21 07:58:17 PM PST 24
Finished Jan 21 08:04:41 PM PST 24
Peak memory 318412 kb
Host smart-24cde83a-8fab-4508-bc10-ff912b1cd5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183059487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_txrx.3183059487
Directory /workspace/17.spi_device_txrx/latest

Test location /workspace/coverage/default/17.spi_device_upload.3917789994
Short name T1092
Test name
Test status
Simulation time 572999997 ps
CPU time 8.87 seconds
Started Jan 21 07:58:47 PM PST 24
Finished Jan 21 07:58:57 PM PST 24
Peak memory 248204 kb
Host smart-30785951-58a9-4216-b3ab-5d1e365b1944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917789994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3917789994
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_abort.4283727924
Short name T1517
Test name
Test status
Simulation time 31599032 ps
CPU time 0.82 seconds
Started Jan 21 07:59:01 PM PST 24
Finished Jan 21 07:59:03 PM PST 24
Peak memory 207100 kb
Host smart-008cf91a-9b34-4e42-a8fb-112c931b2f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283727924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_abort.4283727924
Directory /workspace/18.spi_device_abort/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4206696048
Short name T1567
Test name
Test status
Simulation time 34752511 ps
CPU time 0.78 seconds
Started Jan 21 07:59:05 PM PST 24
Finished Jan 21 07:59:07 PM PST 24
Peak memory 206972 kb
Host smart-14cc1ab4-8154-43c0-84ce-ef6ce416724b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206696048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4206696048
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_bit_transfer.3524659376
Short name T1743
Test name
Test status
Simulation time 501947562 ps
CPU time 2.45 seconds
Started Jan 21 07:59:03 PM PST 24
Finished Jan 21 07:59:07 PM PST 24
Peak memory 217184 kb
Host smart-5c48947b-fe7e-45f9-bb74-c369360a96e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524659376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_bit_transfer.3524659376
Directory /workspace/18.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/18.spi_device_byte_transfer.3552923754
Short name T663
Test name
Test status
Simulation time 58075552 ps
CPU time 2.53 seconds
Started Jan 21 07:59:03 PM PST 24
Finished Jan 21 07:59:07 PM PST 24
Peak memory 217224 kb
Host smart-9e138d36-dbb6-4ad7-a622-b6c0ff4d50d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552923754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_byte_transfer.3552923754
Directory /workspace/18.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.40001823
Short name T705
Test name
Test status
Simulation time 230350364 ps
CPU time 4.11 seconds
Started Jan 21 07:59:06 PM PST 24
Finished Jan 21 07:59:12 PM PST 24
Peak memory 238932 kb
Host smart-0f8c7aa2-e13f-40b0-bdc0-85ea163c2258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40001823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.40001823
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2433492697
Short name T99
Test name
Test status
Simulation time 16485101 ps
CPU time 0.82 seconds
Started Jan 21 07:58:52 PM PST 24
Finished Jan 21 07:58:54 PM PST 24
Peak memory 207000 kb
Host smart-0eb00cd1-e8e1-4cb1-b0fb-c53e67335e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433492697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2433492697
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_dummy_item_extra_dly.1146355717
Short name T1621
Test name
Test status
Simulation time 105287315881 ps
CPU time 481.52 seconds
Started Jan 21 07:58:57 PM PST 24
Finished Jan 21 08:07:00 PM PST 24
Peak memory 254168 kb
Host smart-396f99c0-a38b-4ea6-9560-2ecdb8c800dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146355717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_dummy_item_extra_dly.1146355717
Directory /workspace/18.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/18.spi_device_extreme_fifo_size.3807684964
Short name T1215
Test name
Test status
Simulation time 45726057086 ps
CPU time 91.49 seconds
Started Jan 21 07:58:53 PM PST 24
Finished Jan 21 08:00:25 PM PST 24
Peak memory 223832 kb
Host smart-18c7bd75-5b1b-4036-b8c0-9489011bf53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807684964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_extreme_fifo_size.3807684964
Directory /workspace/18.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/18.spi_device_fifo_full.3327133609
Short name T646
Test name
Test status
Simulation time 781164369961 ps
CPU time 1826.13 seconds
Started Jan 21 07:58:51 PM PST 24
Finished Jan 21 08:29:18 PM PST 24
Peak memory 268036 kb
Host smart-ed91c976-7201-470c-8372-5ff2992de5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327133609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_full.3327133609
Directory /workspace/18.spi_device_fifo_full/latest

Test location /workspace/coverage/default/18.spi_device_fifo_underflow_overflow.3191718198
Short name T1171
Test name
Test status
Simulation time 10994132509 ps
CPU time 172.7 seconds
Started Jan 21 07:58:54 PM PST 24
Finished Jan 21 08:01:47 PM PST 24
Peak memory 329852 kb
Host smart-0fefdd29-0ee1-4040-b981-28a26e45c71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191718198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_underflow_overf
low.3191718198
Directory /workspace/18.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3381623102
Short name T303
Test name
Test status
Simulation time 19789003431 ps
CPU time 136.91 seconds
Started Jan 21 07:59:05 PM PST 24
Finished Jan 21 08:01:23 PM PST 24
Peak memory 238112 kb
Host smart-8cb16e5e-990f-4121-9f33-2184cbc5e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381623102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3381623102
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1626503169
Short name T1404
Test name
Test status
Simulation time 55708944358 ps
CPU time 68.91 seconds
Started Jan 21 07:59:03 PM PST 24
Finished Jan 21 08:00:13 PM PST 24
Peak memory 252464 kb
Host smart-622076dc-478d-445d-929c-ec7ef37e7441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626503169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1626503169
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.175142640
Short name T1765
Test name
Test status
Simulation time 1161209010 ps
CPU time 3.03 seconds
Started Jan 21 07:58:58 PM PST 24
Finished Jan 21 07:59:02 PM PST 24
Peak memory 225084 kb
Host smart-cd92e0f3-0553-4ecc-8764-7b1911a8c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175142640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.175142640
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intr.1505431757
Short name T680
Test name
Test status
Simulation time 9980950456 ps
CPU time 48.16 seconds
Started Jan 21 07:58:53 PM PST 24
Finished Jan 21 07:59:42 PM PST 24
Peak memory 233824 kb
Host smart-eb217d12-61d5-42bf-b5a1-de7861a48708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505431757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intr.1505431757
Directory /workspace/18.spi_device_intr/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2069194823
Short name T1467
Test name
Test status
Simulation time 1449589990 ps
CPU time 8.75 seconds
Started Jan 21 07:58:59 PM PST 24
Finished Jan 21 07:59:09 PM PST 24
Peak memory 219944 kb
Host smart-296c5969-6300-4627-92a3-29fd14080037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069194823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2069194823
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2814614874
Short name T966
Test name
Test status
Simulation time 90152823 ps
CPU time 1.09 seconds
Started Jan 21 07:58:55 PM PST 24
Finished Jan 21 07:58:58 PM PST 24
Peak memory 219396 kb
Host smart-36bd89a3-28e0-4d81-b762-8bc4a1ef3c4e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814614874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2814614874
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2829950646
Short name T264
Test name
Test status
Simulation time 1826761630 ps
CPU time 6.32 seconds
Started Jan 21 07:58:58 PM PST 24
Finished Jan 21 07:59:06 PM PST 24
Peak memory 220300 kb
Host smart-8697760a-3d17-4e3c-8708-30f007863182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829950646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2829950646
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2475784442
Short name T1045
Test name
Test status
Simulation time 18769710424 ps
CPU time 25.34 seconds
Started Jan 21 07:59:01 PM PST 24
Finished Jan 21 07:59:28 PM PST 24
Peak memory 242100 kb
Host smart-6ae30c19-fb2c-4403-9033-4b85fd250e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475784442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2475784442
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_perf.218058051
Short name T587
Test name
Test status
Simulation time 307805980327 ps
CPU time 3061.94 seconds
Started Jan 21 07:58:55 PM PST 24
Finished Jan 21 08:49:58 PM PST 24
Peak memory 266548 kb
Host smart-bd2c08fe-d540-4168-b045-8a68576a2b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218058051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_perf.218058051
Directory /workspace/18.spi_device_perf/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3481348495
Short name T1561
Test name
Test status
Simulation time 23351818 ps
CPU time 0.77 seconds
Started Jan 21 07:59:03 PM PST 24
Finished Jan 21 07:59:05 PM PST 24
Peak memory 217052 kb
Host smart-21414043-53ae-481f-81c3-b9d051869a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481348495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3481348495
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2190747594
Short name T902
Test name
Test status
Simulation time 4224758571 ps
CPU time 5.72 seconds
Started Jan 21 07:59:04 PM PST 24
Finished Jan 21 07:59:11 PM PST 24
Peak memory 219028 kb
Host smart-61dc5432-f639-46d4-90c4-368256524b14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2190747594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2190747594
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_rx_async_fifo_reset.2160718632
Short name T149
Test name
Test status
Simulation time 48562130 ps
CPU time 0.95 seconds
Started Jan 21 07:58:59 PM PST 24
Finished Jan 21 07:59:01 PM PST 24
Peak memory 208820 kb
Host smart-4ff4c2ef-57ec-4ef2-97a3-2e5481926d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160718632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_async_fifo_reset.2160718632
Directory /workspace/18.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_rx_timeout.1327627533
Short name T1053
Test name
Test status
Simulation time 1903848384 ps
CPU time 6.24 seconds
Started Jan 21 07:58:54 PM PST 24
Finished Jan 21 07:59:02 PM PST 24
Peak memory 217212 kb
Host smart-efe1ed46-82ae-4120-bff1-380c7cb87a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327627533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_timeout.1327627533
Directory /workspace/18.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/18.spi_device_smoke.1886397383
Short name T1310
Test name
Test status
Simulation time 77885823 ps
CPU time 1.03 seconds
Started Jan 21 07:58:54 PM PST 24
Finished Jan 21 07:58:57 PM PST 24
Peak memory 208768 kb
Host smart-a3b08ecc-e18b-4361-9ed8-55c6847dadf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886397383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_smoke.1886397383
Directory /workspace/18.spi_device_smoke/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2261293927
Short name T253
Test name
Test status
Simulation time 103397010752 ps
CPU time 1796.54 seconds
Started Jan 21 07:59:05 PM PST 24
Finished Jan 21 08:29:03 PM PST 24
Peak memory 400088 kb
Host smart-938c36ec-7bd9-4c18-a443-51acdcb34270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261293927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2261293927
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1713712038
Short name T1445
Test name
Test status
Simulation time 1636931296 ps
CPU time 16.05 seconds
Started Jan 21 07:58:57 PM PST 24
Finished Jan 21 07:59:14 PM PST 24
Peak memory 217360 kb
Host smart-035ec017-07a7-40d5-9806-1fe8457c7c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713712038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1713712038
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4281469977
Short name T1006
Test name
Test status
Simulation time 18609461562 ps
CPU time 9.41 seconds
Started Jan 21 07:59:03 PM PST 24
Finished Jan 21 07:59:14 PM PST 24
Peak memory 219428 kb
Host smart-55ed5b6b-1a2b-4911-9673-b9b164bd1bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281469977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4281469977
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.363860447
Short name T1470
Test name
Test status
Simulation time 60244993 ps
CPU time 1.17 seconds
Started Jan 21 07:58:59 PM PST 24
Finished Jan 21 07:59:01 PM PST 24
Peak memory 217256 kb
Host smart-1f984d90-d427-49d6-a250-2c064ca95e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363860447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.363860447
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.81526900
Short name T703
Test name
Test status
Simulation time 83633750 ps
CPU time 1.08 seconds
Started Jan 21 07:59:02 PM PST 24
Finished Jan 21 07:59:05 PM PST 24
Peak memory 207384 kb
Host smart-069fd554-2e57-4a65-8ff0-21aec2e382c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81526900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.81526900
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tx_async_fifo_reset.533864515
Short name T1498
Test name
Test status
Simulation time 18933787 ps
CPU time 0.82 seconds
Started Jan 21 07:59:01 PM PST 24
Finished Jan 21 07:59:03 PM PST 24
Peak memory 207716 kb
Host smart-010e8ca6-2e6c-4f9e-a37d-60591fa6ebc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533864515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tx_async_fifo_reset.533864515
Directory /workspace/18.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_txrx.1457968296
Short name T800
Test name
Test status
Simulation time 18811138989 ps
CPU time 211.75 seconds
Started Jan 21 07:58:56 PM PST 24
Finished Jan 21 08:02:29 PM PST 24
Peak memory 274732 kb
Host smart-1f15dbbb-c8c4-4621-befe-8c66d42c3dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457968296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_txrx.1457968296
Directory /workspace/18.spi_device_txrx/latest

Test location /workspace/coverage/default/18.spi_device_upload.643170402
Short name T284
Test name
Test status
Simulation time 4117451463 ps
CPU time 5.41 seconds
Started Jan 21 07:59:07 PM PST 24
Finished Jan 21 07:59:13 PM PST 24
Peak memory 241300 kb
Host smart-24197084-06fe-4428-ba5d-e97629d3910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643170402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.643170402
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_abort.1689693148
Short name T1126
Test name
Test status
Simulation time 15957429 ps
CPU time 0.78 seconds
Started Jan 21 07:59:27 PM PST 24
Finished Jan 21 07:59:29 PM PST 24
Peak memory 207044 kb
Host smart-3951b629-9a65-4892-aa1c-ee3061aed204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689693148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_abort.1689693148
Directory /workspace/19.spi_device_abort/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4236779410
Short name T1487
Test name
Test status
Simulation time 69196954 ps
CPU time 0.73 seconds
Started Jan 21 07:59:34 PM PST 24
Finished Jan 21 07:59:36 PM PST 24
Peak memory 206996 kb
Host smart-0feaacba-6952-4df9-a832-356e73fab580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236779410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4236779410
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_bit_transfer.4013163234
Short name T1296
Test name
Test status
Simulation time 724210014 ps
CPU time 3.4 seconds
Started Jan 21 07:59:26 PM PST 24
Finished Jan 21 07:59:30 PM PST 24
Peak memory 217196 kb
Host smart-8541e5d4-df32-41e0-b740-e68da0fefcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013163234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_bit_transfer.4013163234
Directory /workspace/19.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/19.spi_device_byte_transfer.493148211
Short name T1463
Test name
Test status
Simulation time 129198383 ps
CPU time 2.98 seconds
Started Jan 21 07:59:17 PM PST 24
Finished Jan 21 07:59:20 PM PST 24
Peak memory 217232 kb
Host smart-9ecb842d-65f2-4400-96ce-822d192c2986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493148211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_byte_transfer.493148211
Directory /workspace/19.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3457672365
Short name T839
Test name
Test status
Simulation time 171160922 ps
CPU time 3.25 seconds
Started Jan 21 08:27:12 PM PST 24
Finished Jan 21 08:27:16 PM PST 24
Peak memory 241760 kb
Host smart-136e62a6-894c-4f12-b1fe-a2abccc6cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457672365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3457672365
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2248622274
Short name T564
Test name
Test status
Simulation time 42413223 ps
CPU time 0.81 seconds
Started Jan 21 07:59:11 PM PST 24
Finished Jan 21 07:59:13 PM PST 24
Peak memory 208060 kb
Host smart-433cf6dc-b171-4695-9805-72942370b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248622274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2248622274
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_dummy_item_extra_dly.918677453
Short name T629
Test name
Test status
Simulation time 104882257548 ps
CPU time 259.35 seconds
Started Jan 21 07:59:12 PM PST 24
Finished Jan 21 08:03:32 PM PST 24
Peak memory 266652 kb
Host smart-5014e199-7ea4-45dd-b0e0-fea28d2e1307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918677453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_dummy_item_extra_dly.918677453
Directory /workspace/19.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/19.spi_device_fifo_full.1964540330
Short name T1337
Test name
Test status
Simulation time 43210353307 ps
CPU time 2659.76 seconds
Started Jan 21 07:59:06 PM PST 24
Finished Jan 21 08:43:28 PM PST 24
Peak memory 257552 kb
Host smart-6182cc9f-0753-4d89-b007-f90fc9f97cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964540330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_full.1964540330
Directory /workspace/19.spi_device_fifo_full/latest

Test location /workspace/coverage/default/19.spi_device_fifo_underflow_overflow.3978270104
Short name T1707
Test name
Test status
Simulation time 87205497438 ps
CPU time 464.38 seconds
Started Jan 21 07:59:07 PM PST 24
Finished Jan 21 08:06:53 PM PST 24
Peak memory 509332 kb
Host smart-396062a3-cc7a-45c7-b322-0ad2747fb2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978270104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_underflow_overf
low.3978270104
Directory /workspace/19.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1088086168
Short name T524
Test name
Test status
Simulation time 9164908922 ps
CPU time 12.55 seconds
Started Jan 21 09:11:41 PM PST 24
Finished Jan 21 09:11:58 PM PST 24
Peak memory 240652 kb
Host smart-dbeaffa9-8dcf-47e8-b860-a7d34910ee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088086168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1088086168
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3559226135
Short name T819
Test name
Test status
Simulation time 70700553954 ps
CPU time 264.62 seconds
Started Jan 21 08:54:42 PM PST 24
Finished Jan 21 08:59:13 PM PST 24
Peak memory 258484 kb
Host smart-219cc98a-b509-49d3-b09e-610be7cda833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559226135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3559226135
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1452612097
Short name T1633
Test name
Test status
Simulation time 23842422260 ps
CPU time 24.9 seconds
Started Jan 21 07:59:35 PM PST 24
Finished Jan 21 08:00:00 PM PST 24
Peak memory 239748 kb
Host smart-e660ebf0-f4d4-40dd-a994-7b07f4c75438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452612097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1452612097
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3345247252
Short name T689
Test name
Test status
Simulation time 53919142 ps
CPU time 3.14 seconds
Started Jan 21 07:59:32 PM PST 24
Finished Jan 21 07:59:36 PM PST 24
Peak memory 234732 kb
Host smart-d23b5c25-179e-4aea-b9a1-9c18c7858b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345247252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3345247252
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.225124319
Short name T1216
Test name
Test status
Simulation time 5364335776 ps
CPU time 17.76 seconds
Started Jan 21 07:59:25 PM PST 24
Finished Jan 21 07:59:44 PM PST 24
Peak memory 249292 kb
Host smart-7a299763-c79f-4124-bf3b-7a4515c0b5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225124319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.225124319
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3093834039
Short name T915
Test name
Test status
Simulation time 14598049 ps
CPU time 1.19 seconds
Started Jan 21 07:59:19 PM PST 24
Finished Jan 21 07:59:21 PM PST 24
Peak memory 219328 kb
Host smart-f1e9816f-6521-4b4d-8f2e-8714efbd6568
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093834039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3093834039
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1772929484
Short name T1460
Test name
Test status
Simulation time 3040606710 ps
CPU time 14.1 seconds
Started Jan 21 07:59:28 PM PST 24
Finished Jan 21 07:59:43 PM PST 24
Peak memory 236520 kb
Host smart-9773b42d-5575-44aa-acdc-59a7b97299ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772929484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1772929484
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3105601034
Short name T1718
Test name
Test status
Simulation time 8331069434 ps
CPU time 11.34 seconds
Started Jan 21 07:59:28 PM PST 24
Finished Jan 21 07:59:40 PM PST 24
Peak memory 237220 kb
Host smart-b5f3623f-1302-4125-89b2-8ba4702338c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105601034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3105601034
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_perf.2932522236
Short name T1408
Test name
Test status
Simulation time 416878323248 ps
CPU time 1231.03 seconds
Started Jan 21 07:59:10 PM PST 24
Finished Jan 21 08:19:43 PM PST 24
Peak memory 281736 kb
Host smart-b86265c8-0430-435f-b1d2-65b9cbf8c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932522236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_perf.2932522236
Directory /workspace/19.spi_device_perf/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3306857102
Short name T751
Test name
Test status
Simulation time 41014459 ps
CPU time 0.76 seconds
Started Jan 21 07:59:19 PM PST 24
Finished Jan 21 07:59:20 PM PST 24
Peak memory 217124 kb
Host smart-92b4f365-39f9-4d50-9445-24e72b05ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306857102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3306857102
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4266424879
Short name T1303
Test name
Test status
Simulation time 714374506 ps
CPU time 3.71 seconds
Started Jan 21 07:59:35 PM PST 24
Finished Jan 21 07:59:39 PM PST 24
Peak memory 220320 kb
Host smart-6eae9808-41b2-467c-9d55-1d9259f492dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4266424879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4266424879
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_rx_async_fifo_reset.3851312348
Short name T1066
Test name
Test status
Simulation time 300715311 ps
CPU time 1.01 seconds
Started Jan 21 07:59:25 PM PST 24
Finished Jan 21 07:59:27 PM PST 24
Peak memory 208832 kb
Host smart-03896dc3-02ac-4727-81d2-b36520622c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851312348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_async_fifo_reset.3851312348
Directory /workspace/19.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_rx_timeout.1843334569
Short name T1635
Test name
Test status
Simulation time 507710269 ps
CPU time 6.04 seconds
Started Jan 21 07:59:23 PM PST 24
Finished Jan 21 07:59:30 PM PST 24
Peak memory 217252 kb
Host smart-f4a4cf05-aa24-4c35-b4af-daab0c5c9c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843334569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_timeout.1843334569
Directory /workspace/19.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/19.spi_device_smoke.952883910
Short name T1744
Test name
Test status
Simulation time 140279865 ps
CPU time 1.26 seconds
Started Jan 21 07:59:03 PM PST 24
Finished Jan 21 07:59:06 PM PST 24
Peak memory 208472 kb
Host smart-b86e7470-df07-4d36-b6bd-32c2228d2457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952883910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_smoke.952883910
Directory /workspace/19.spi_device_smoke/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.275648527
Short name T617
Test name
Test status
Simulation time 24441009934 ps
CPU time 100.24 seconds
Started Jan 21 07:59:20 PM PST 24
Finished Jan 21 08:01:02 PM PST 24
Peak memory 222288 kb
Host smart-8a10a442-f7af-4b51-b3d7-447006f8f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275648527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.275648527
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.915488464
Short name T918
Test name
Test status
Simulation time 19876297334 ps
CPU time 15.09 seconds
Started Jan 21 07:59:22 PM PST 24
Finished Jan 21 07:59:39 PM PST 24
Peak memory 217352 kb
Host smart-4354749b-ac44-4af7-b740-204e833d26ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915488464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.915488464
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1691129468
Short name T1308
Test name
Test status
Simulation time 467884704 ps
CPU time 7.69 seconds
Started Jan 21 07:59:27 PM PST 24
Finished Jan 21 07:59:36 PM PST 24
Peak memory 217284 kb
Host smart-51971928-7548-4ff2-9738-a0a6daf99751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691129468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1691129468
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2539058752
Short name T1781
Test name
Test status
Simulation time 88614319 ps
CPU time 0.82 seconds
Started Jan 21 07:59:30 PM PST 24
Finished Jan 21 07:59:32 PM PST 24
Peak memory 207432 kb
Host smart-0d2e7f19-ed05-4ff0-b612-29ede031965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539058752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2539058752
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tx_async_fifo_reset.4095717903
Short name T1283
Test name
Test status
Simulation time 56181441 ps
CPU time 0.79 seconds
Started Jan 21 07:59:29 PM PST 24
Finished Jan 21 07:59:31 PM PST 24
Peak memory 208896 kb
Host smart-bd4f5257-e817-4fff-9c35-e141242dd616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095717903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tx_async_fifo_reset.4095717903
Directory /workspace/19.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_txrx.2114287851
Short name T950
Test name
Test status
Simulation time 63367242720 ps
CPU time 255.68 seconds
Started Jan 21 07:59:02 PM PST 24
Finished Jan 21 08:03:20 PM PST 24
Peak memory 283100 kb
Host smart-3e86fec1-77d8-4d1e-9c45-92aca2dc9977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114287851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_txrx.2114287851
Directory /workspace/19.spi_device_txrx/latest

Test location /workspace/coverage/default/19.spi_device_upload.2271338210
Short name T1402
Test name
Test status
Simulation time 2639760413 ps
CPU time 7.33 seconds
Started Jan 21 07:59:35 PM PST 24
Finished Jan 21 07:59:44 PM PST 24
Peak memory 220000 kb
Host smart-84530afb-2c92-40f8-ace5-1c64d6e65eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271338210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2271338210
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_abort.3562599621
Short name T523
Test name
Test status
Simulation time 21085863 ps
CPU time 0.78 seconds
Started Jan 21 07:53:32 PM PST 24
Finished Jan 21 07:53:37 PM PST 24
Peak memory 207080 kb
Host smart-6d68c2e5-bf8c-4670-9173-f03cf08d2179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562599621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_abort.3562599621
Directory /workspace/2.spi_device_abort/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3506036992
Short name T1728
Test name
Test status
Simulation time 11245915 ps
CPU time 0.74 seconds
Started Jan 21 07:53:40 PM PST 24
Finished Jan 21 07:53:44 PM PST 24
Peak memory 206940 kb
Host smart-4e960612-8732-47b2-ba99-4e14f3b63337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506036992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
506036992
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_bit_transfer.2651887087
Short name T1375
Test name
Test status
Simulation time 472623196 ps
CPU time 2.48 seconds
Started Jan 21 07:53:34 PM PST 24
Finished Jan 21 07:53:41 PM PST 24
Peak memory 217296 kb
Host smart-74d2a440-5351-4402-ae89-dcae65a1c43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651887087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_bit_transfer.2651887087
Directory /workspace/2.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/2.spi_device_byte_transfer.1793287903
Short name T994
Test name
Test status
Simulation time 205360451 ps
CPU time 2.83 seconds
Started Jan 21 07:53:23 PM PST 24
Finished Jan 21 07:53:29 PM PST 24
Peak memory 217184 kb
Host smart-ee657199-a98d-440b-aefc-c17534be34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793287903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_byte_transfer.1793287903
Directory /workspace/2.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1278941603
Short name T1046
Test name
Test status
Simulation time 156561709 ps
CPU time 4.06 seconds
Started Jan 21 07:53:34 PM PST 24
Finished Jan 21 07:53:44 PM PST 24
Peak memory 239468 kb
Host smart-bd5bd087-f247-478e-b173-e6d66535851c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278941603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1278941603
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.139302711
Short name T489
Test name
Test status
Simulation time 21980063 ps
CPU time 0.86 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 07:53:25 PM PST 24
Peak memory 207956 kb
Host smart-5def255b-5866-4041-b284-ef5f5563fc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139302711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.139302711
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_dummy_item_extra_dly.1104201050
Short name T513
Test name
Test status
Simulation time 42828269475 ps
CPU time 324.59 seconds
Started Jan 21 07:53:21 PM PST 24
Finished Jan 21 07:58:48 PM PST 24
Peak memory 299256 kb
Host smart-1bc1895c-5837-4f00-8a78-2e384cb2b8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104201050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_dummy_item_extra_dly.1104201050
Directory /workspace/2.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/2.spi_device_extreme_fifo_size.3273135016
Short name T1336
Test name
Test status
Simulation time 47496472936 ps
CPU time 846.2 seconds
Started Jan 21 07:53:23 PM PST 24
Finished Jan 21 08:07:33 PM PST 24
Peak memory 225564 kb
Host smart-63a52645-b94e-4ede-81b4-4b66d7e4dd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273135016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_extreme_fifo_size.3273135016
Directory /workspace/2.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/2.spi_device_fifo_full.2194017432
Short name T1461
Test name
Test status
Simulation time 56952465790 ps
CPU time 862.79 seconds
Started Jan 21 07:53:26 PM PST 24
Finished Jan 21 08:07:50 PM PST 24
Peak memory 306160 kb
Host smart-4443dc04-7bfb-49dc-a8a5-9b05d94c453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194017432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_full.2194017432
Directory /workspace/2.spi_device_fifo_full/latest

Test location /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.792399908
Short name T990
Test name
Test status
Simulation time 61418882125 ps
CPU time 227.52 seconds
Started Jan 21 07:53:21 PM PST 24
Finished Jan 21 07:57:11 PM PST 24
Peak memory 379468 kb
Host smart-23f7ae49-9a89-47c9-bcd3-4d05f12ab586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792399908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_underflow_overflo
w.792399908
Directory /workspace/2.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1418782776
Short name T1580
Test name
Test status
Simulation time 15964296043 ps
CPU time 52.24 seconds
Started Jan 21 07:53:42 PM PST 24
Finished Jan 21 07:54:36 PM PST 24
Peak memory 242024 kb
Host smart-83d76498-22ce-4d03-a6b4-71760f7dfb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418782776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1418782776
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1359459557
Short name T913
Test name
Test status
Simulation time 15294893741 ps
CPU time 126.61 seconds
Started Jan 21 07:53:41 PM PST 24
Finished Jan 21 07:55:50 PM PST 24
Peak memory 237876 kb
Host smart-9fc11dbb-cd07-4cdd-8b88-74d47a2e0bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359459557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1359459557
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3765906258
Short name T321
Test name
Test status
Simulation time 189364842997 ps
CPU time 375.53 seconds
Started Jan 21 07:53:39 PM PST 24
Finished Jan 21 07:59:58 PM PST 24
Peak memory 264600 kb
Host smart-548b978e-52d1-4063-8f27-b3dc339073e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765906258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3765906258
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2477490483
Short name T204
Test name
Test status
Simulation time 740412512 ps
CPU time 12.58 seconds
Started Jan 21 07:53:46 PM PST 24
Finished Jan 21 07:54:02 PM PST 24
Peak memory 248196 kb
Host smart-3771e246-b092-4b00-a4a6-d96fb996b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477490483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2477490483
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.941383480
Short name T824
Test name
Test status
Simulation time 1663660339 ps
CPU time 8.08 seconds
Started Jan 21 07:53:33 PM PST 24
Finished Jan 21 07:53:45 PM PST 24
Peak memory 221144 kb
Host smart-06b01b35-3dea-4c63-83e0-70eca925692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941383480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.941383480
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intr.897942218
Short name T1695
Test name
Test status
Simulation time 25505532759 ps
CPU time 70.44 seconds
Started Jan 21 07:53:22 PM PST 24
Finished Jan 21 07:54:35 PM PST 24
Peak memory 233592 kb
Host smart-ef476b44-64c8-41c5-902d-53e1d190c728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897942218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intr.897942218
Directory /workspace/2.spi_device_intr/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1753906966
Short name T1301
Test name
Test status
Simulation time 17078772558 ps
CPU time 13.55 seconds
Started Jan 21 07:53:36 PM PST 24
Finished Jan 21 07:53:54 PM PST 24
Peak memory 220028 kb
Host smart-be6c4bcc-1008-44d8-a270-12cb19fc8488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753906966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1753906966
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2426424771
Short name T558
Test name
Test status
Simulation time 27736054 ps
CPU time 1.06 seconds
Started Jan 21 07:53:25 PM PST 24
Finished Jan 21 07:53:28 PM PST 24
Peak memory 219376 kb
Host smart-f199acd1-a33f-45a4-a364-cca9de9b64ef
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426424771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2426424771
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4178477039
Short name T1305
Test name
Test status
Simulation time 7403089492 ps
CPU time 6.05 seconds
Started Jan 21 07:53:31 PM PST 24
Finished Jan 21 07:53:42 PM PST 24
Peak memory 219076 kb
Host smart-047a6edc-788a-46ec-b2c8-977048cbb5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178477039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4178477039
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1051619473
Short name T332
Test name
Test status
Simulation time 6627311345 ps
CPU time 10.61 seconds
Started Jan 21 07:53:37 PM PST 24
Finished Jan 21 07:53:52 PM PST 24
Peak memory 245068 kb
Host smart-ae91cda6-9707-46af-96a4-908908485d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051619473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1051619473
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_perf.1008705396
Short name T487
Test name
Test status
Simulation time 26794357865 ps
CPU time 1834.41 seconds
Started Jan 21 08:35:42 PM PST 24
Finished Jan 21 09:06:18 PM PST 24
Peak memory 266460 kb
Host smart-9f6dbec7-7595-4e12-b1f7-5d53dde656dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008705396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_perf.1008705396
Directory /workspace/2.spi_device_perf/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.4253190532
Short name T1143
Test name
Test status
Simulation time 28722238 ps
CPU time 0.73 seconds
Started Jan 21 07:53:24 PM PST 24
Finished Jan 21 07:53:28 PM PST 24
Peak memory 217088 kb
Host smart-05620ddc-2632-414c-8ebd-cda3812eae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253190532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.4253190532
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2375928537
Short name T1525
Test name
Test status
Simulation time 1487273779 ps
CPU time 7.09 seconds
Started Jan 21 07:53:37 PM PST 24
Finished Jan 21 07:53:49 PM PST 24
Peak memory 234776 kb
Host smart-39eed8a8-c95b-4542-b11b-6f47ca4afd3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2375928537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2375928537
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_rx_async_fifo_reset.13716545
Short name T147
Test name
Test status
Simulation time 45874084 ps
CPU time 0.96 seconds
Started Jan 21 07:53:36 PM PST 24
Finished Jan 21 07:53:42 PM PST 24
Peak memory 208788 kb
Host smart-60c73389-67de-4169-97dc-b70c4d5080d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13716545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_async_fifo_reset.13716545
Directory /workspace/2.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_rx_timeout.1084811235
Short name T528
Test name
Test status
Simulation time 1634577338 ps
CPU time 6.62 seconds
Started Jan 21 09:22:46 PM PST 24
Finished Jan 21 09:22:56 PM PST 24
Peak memory 217180 kb
Host smart-35dbdeaa-75ac-44eb-aa08-bc9ac1aea9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084811235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_timeout.1084811235
Directory /workspace/2.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.330084867
Short name T111
Test name
Test status
Simulation time 110735906 ps
CPU time 1.25 seconds
Started Jan 21 08:51:06 PM PST 24
Finished Jan 21 08:51:53 PM PST 24
Peak memory 238552 kb
Host smart-60b367a7-cfc4-43c9-90af-76b1da6298df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330084867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.330084867
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_smoke.862867245
Short name T1569
Test name
Test status
Simulation time 93763320 ps
CPU time 1.32 seconds
Started Jan 21 07:53:16 PM PST 24
Finished Jan 21 07:53:19 PM PST 24
Peak memory 217244 kb
Host smart-9d366ae8-8cfd-49d6-941f-cf6b064b38d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862867245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_smoke.862867245
Directory /workspace/2.spi_device_smoke/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2914163555
Short name T1562
Test name
Test status
Simulation time 1176386896563 ps
CPU time 886.32 seconds
Started Jan 21 07:53:47 PM PST 24
Finished Jan 21 08:08:36 PM PST 24
Peak memory 348720 kb
Host smart-9a98ce16-5a6d-4727-a101-c76ed21dfc34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914163555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2914163555
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.673358806
Short name T1224
Test name
Test status
Simulation time 4187270205 ps
CPU time 35.18 seconds
Started Jan 21 07:53:32 PM PST 24
Finished Jan 21 07:54:11 PM PST 24
Peak memory 217652 kb
Host smart-0d6576e4-ab39-481d-84d1-1e6ef559b34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673358806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.673358806
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1247611921
Short name T1759
Test name
Test status
Simulation time 6132898972 ps
CPU time 7.91 seconds
Started Jan 21 07:53:36 PM PST 24
Finished Jan 21 07:53:49 PM PST 24
Peak memory 217328 kb
Host smart-fa8ecf96-c66d-4b6a-a54e-1b4635c6ab22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247611921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1247611921
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1619032747
Short name T1505
Test name
Test status
Simulation time 17521820 ps
CPU time 0.93 seconds
Started Jan 21 07:53:36 PM PST 24
Finished Jan 21 07:53:42 PM PST 24
Peak memory 208040 kb
Host smart-522d0a7b-24f4-4f59-8966-0ff56492aa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619032747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1619032747
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2242143299
Short name T827
Test name
Test status
Simulation time 26029908 ps
CPU time 0.8 seconds
Started Jan 21 07:53:37 PM PST 24
Finished Jan 21 07:53:42 PM PST 24
Peak memory 207216 kb
Host smart-6330ff12-8895-4522-814a-b8ff7d8151f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242143299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2242143299
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tx_async_fifo_reset.318231967
Short name T1560
Test name
Test status
Simulation time 17482607 ps
CPU time 0.8 seconds
Started Jan 21 07:53:40 PM PST 24
Finished Jan 21 07:53:43 PM PST 24
Peak memory 207708 kb
Host smart-a4f8f5dc-912c-415b-bd17-62b559e09ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318231967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tx_async_fifo_reset.318231967
Directory /workspace/2.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_txrx.3452638543
Short name T1170
Test name
Test status
Simulation time 86387091914 ps
CPU time 160.48 seconds
Started Jan 21 08:20:14 PM PST 24
Finished Jan 21 08:22:57 PM PST 24
Peak memory 266308 kb
Host smart-e423d15f-82e0-4355-b942-04aaacafc179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452638543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_txrx.3452638543
Directory /workspace/2.spi_device_txrx/latest

Test location /workspace/coverage/default/2.spi_device_upload.2143852371
Short name T1018
Test name
Test status
Simulation time 391397805 ps
CPU time 5.52 seconds
Started Jan 21 07:53:40 PM PST 24
Finished Jan 21 07:53:48 PM PST 24
Peak memory 219500 kb
Host smart-c7ca1bc8-b2d4-4ca9-8b7b-14e3b67a21b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143852371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2143852371
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_abort.83014201
Short name T688
Test name
Test status
Simulation time 28880492 ps
CPU time 0.75 seconds
Started Jan 21 07:59:54 PM PST 24
Finished Jan 21 08:00:03 PM PST 24
Peak memory 207084 kb
Host smart-f39b5c40-45f5-4754-80ee-5d567b103f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83014201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_abort.83014201
Directory /workspace/20.spi_device_abort/latest

Test location /workspace/coverage/default/20.spi_device_bit_transfer.2808397709
Short name T1262
Test name
Test status
Simulation time 350004446 ps
CPU time 2.64 seconds
Started Jan 21 07:59:53 PM PST 24
Finished Jan 21 08:00:05 PM PST 24
Peak memory 217156 kb
Host smart-5233b55a-7b28-4c5c-a4fc-104c8fc2c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808397709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_bit_transfer.2808397709
Directory /workspace/20.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/20.spi_device_byte_transfer.2604873000
Short name T1767
Test name
Test status
Simulation time 629380834 ps
CPU time 3.26 seconds
Started Jan 21 07:59:44 PM PST 24
Finished Jan 21 07:59:49 PM PST 24
Peak memory 217160 kb
Host smart-244fcf6f-a4f9-4cad-be40-a153802f05aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604873000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_byte_transfer.2604873000
Directory /workspace/20.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2558863821
Short name T894
Test name
Test status
Simulation time 1917715731 ps
CPU time 5.46 seconds
Started Jan 21 07:59:51 PM PST 24
Finished Jan 21 08:00:04 PM PST 24
Peak memory 218504 kb
Host smart-9c346e43-3ced-488b-a751-2f883d404680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558863821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2558863821
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.109413387
Short name T1555
Test name
Test status
Simulation time 20086057 ps
CPU time 0.83 seconds
Started Jan 21 07:59:50 PM PST 24
Finished Jan 21 07:59:52 PM PST 24
Peak memory 208040 kb
Host smart-50fe0fd5-6a29-461d-9d48-0937e3cec67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109413387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.109413387
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.2120797481
Short name T1212
Test name
Test status
Simulation time 335840124003 ps
CPU time 522.72 seconds
Started Jan 21 07:59:45 PM PST 24
Finished Jan 21 08:08:29 PM PST 24
Peak memory 239792 kb
Host smart-4c6d6c1a-608b-40f4-8fb9-ebf72c7c3a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120797481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_dummy_item_extra_dly.2120797481
Directory /workspace/20.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/20.spi_device_extreme_fifo_size.2192630860
Short name T599
Test name
Test status
Simulation time 70468756086 ps
CPU time 4019.73 seconds
Started Jan 21 07:59:46 PM PST 24
Finished Jan 21 09:06:48 PM PST 24
Peak memory 217396 kb
Host smart-8885fd7f-f914-48fd-b86f-7823c8677c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192630860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_extreme_fifo_size.2192630860
Directory /workspace/20.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/20.spi_device_fifo_full.571363648
Short name T1266
Test name
Test status
Simulation time 129064239612 ps
CPU time 415.03 seconds
Started Jan 21 07:59:44 PM PST 24
Finished Jan 21 08:06:40 PM PST 24
Peak memory 267276 kb
Host smart-5597e4e8-7d2c-496b-a69e-4a19f58a7db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571363648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_full.571363648
Directory /workspace/20.spi_device_fifo_full/latest

Test location /workspace/coverage/default/20.spi_device_fifo_underflow_overflow.3905346855
Short name T1719
Test name
Test status
Simulation time 59955894381 ps
CPU time 310.58 seconds
Started Jan 21 07:59:50 PM PST 24
Finished Jan 21 08:05:02 PM PST 24
Peak memory 421012 kb
Host smart-7a81dee1-e4d7-4abc-ba58-e38cf5a69e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905346855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_underflow_overf
low.3905346855
Directory /workspace/20.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3368365633
Short name T1125
Test name
Test status
Simulation time 50077064988 ps
CPU time 29.98 seconds
Started Jan 21 07:59:52 PM PST 24
Finished Jan 21 08:00:29 PM PST 24
Peak memory 237928 kb
Host smart-500e522e-3b06-4a49-82ab-0b95f4e99954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368365633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3368365633
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3283570883
Short name T1678
Test name
Test status
Simulation time 16583764374 ps
CPU time 162.94 seconds
Started Jan 21 07:59:52 PM PST 24
Finished Jan 21 08:02:42 PM PST 24
Peak memory 263868 kb
Host smart-75d61601-95ea-4e13-9feb-29cdc81af544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283570883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3283570883
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3196668702
Short name T851
Test name
Test status
Simulation time 168567774 ps
CPU time 3.75 seconds
Started Jan 21 07:59:53 PM PST 24
Finished Jan 21 08:00:06 PM PST 24
Peak memory 219488 kb
Host smart-bf620630-b65d-4799-9322-4bc052c504b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196668702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3196668702
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intr.2083080555
Short name T222
Test name
Test status
Simulation time 30511455734 ps
CPU time 45.48 seconds
Started Jan 21 07:59:45 PM PST 24
Finished Jan 21 08:00:31 PM PST 24
Peak memory 233976 kb
Host smart-cfc54af0-5d99-4dd0-a330-6a15b79e18c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083080555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intr.2083080555
Directory /workspace/20.spi_device_intr/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1264218295
Short name T271
Test name
Test status
Simulation time 16169156293 ps
CPU time 49.5 seconds
Started Jan 21 07:59:51 PM PST 24
Finished Jan 21 08:00:48 PM PST 24
Peak memory 256884 kb
Host smart-a9088bf7-a330-48f2-9024-a21799f5fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264218295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1264218295
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.789562935
Short name T881
Test name
Test status
Simulation time 2704666016 ps
CPU time 8.89 seconds
Started Jan 21 07:59:51 PM PST 24
Finished Jan 21 08:00:01 PM PST 24
Peak memory 219044 kb
Host smart-0d7e3d5c-1b7b-4118-b6c4-5870a2ae6386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789562935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.789562935
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1403982194
Short name T1329
Test name
Test status
Simulation time 91901933702 ps
CPU time 28.56 seconds
Started Jan 21 07:59:52 PM PST 24
Finished Jan 21 08:00:29 PM PST 24
Peak memory 221240 kb
Host smart-422f9b93-93d0-4319-8a59-68d3e43a43ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403982194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1403982194
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_perf.893342802
Short name T1475
Test name
Test status
Simulation time 25253386937 ps
CPU time 404.95 seconds
Started Jan 21 07:59:47 PM PST 24
Finished Jan 21 08:06:33 PM PST 24
Peak memory 257748 kb
Host smart-af5ef47e-0342-473c-a6d9-b3832673b20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893342802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_perf.893342802
Directory /workspace/20.spi_device_perf/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3084657584
Short name T1042
Test name
Test status
Simulation time 341672168 ps
CPU time 4.68 seconds
Started Jan 21 07:59:51 PM PST 24
Finished Jan 21 08:00:03 PM PST 24
Peak memory 234948 kb
Host smart-0fc24a68-b988-4827-b10c-d95e96efe6c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3084657584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3084657584
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_rx_async_fifo_reset.3161290141
Short name T1591
Test name
Test status
Simulation time 60300248 ps
CPU time 0.9 seconds
Started Jan 21 07:59:54 PM PST 24
Finished Jan 21 08:00:03 PM PST 24
Peak memory 208824 kb
Host smart-06dc2d5e-7be2-4f4d-a9be-9b3ec6d18dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161290141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_async_fifo_reset.3161290141
Directory /workspace/20.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_rx_timeout.1790621366
Short name T1387
Test name
Test status
Simulation time 649840347 ps
CPU time 5.6 seconds
Started Jan 21 07:59:45 PM PST 24
Finished Jan 21 07:59:52 PM PST 24
Peak memory 217176 kb
Host smart-9a42b318-5263-4222-a738-da708732bac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790621366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_timeout.1790621366
Directory /workspace/20.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/20.spi_device_smoke.2500360608
Short name T937
Test name
Test status
Simulation time 45718101 ps
CPU time 1.09 seconds
Started Jan 21 07:59:36 PM PST 24
Finished Jan 21 07:59:38 PM PST 24
Peak memory 208496 kb
Host smart-5384cd1a-7464-4b32-8eca-f58fe1852fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500360608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_smoke.2500360608
Directory /workspace/20.spi_device_smoke/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4005573912
Short name T156
Test name
Test status
Simulation time 270221471701 ps
CPU time 573.98 seconds
Started Jan 21 08:00:02 PM PST 24
Finished Jan 21 08:09:41 PM PST 24
Peak memory 414120 kb
Host smart-89803577-e23e-42a7-9da0-9392c75f957b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005573912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4005573912
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1452651042
Short name T124
Test name
Test status
Simulation time 11393242538 ps
CPU time 50.05 seconds
Started Jan 21 07:59:50 PM PST 24
Finished Jan 21 08:00:42 PM PST 24
Peak memory 217472 kb
Host smart-fcd0b840-26dd-489c-a795-fd081c58aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452651042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1452651042
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2128918639
Short name T163
Test name
Test status
Simulation time 1750817719 ps
CPU time 6.84 seconds
Started Jan 21 07:59:51 PM PST 24
Finished Jan 21 07:59:59 PM PST 24
Peak memory 217188 kb
Host smart-b37c98c8-c46d-41f2-abc3-e09b0c6d69f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128918639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2128918639
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2385409915
Short name T683
Test name
Test status
Simulation time 126519128 ps
CPU time 3.45 seconds
Started Jan 21 07:59:51 PM PST 24
Finished Jan 21 08:00:02 PM PST 24
Peak memory 217288 kb
Host smart-a97fe907-ac78-4018-8d73-b546bfa12f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385409915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2385409915
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3661640503
Short name T1204
Test name
Test status
Simulation time 116437231 ps
CPU time 1.01 seconds
Started Jan 21 07:59:52 PM PST 24
Finished Jan 21 08:00:00 PM PST 24
Peak memory 208336 kb
Host smart-dd26a97a-dcdd-48ca-b801-85d7cad944a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661640503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3661640503
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tx_async_fifo_reset.4130745987
Short name T908
Test name
Test status
Simulation time 74307069 ps
CPU time 0.85 seconds
Started Jan 21 07:59:49 PM PST 24
Finished Jan 21 07:59:52 PM PST 24
Peak memory 207692 kb
Host smart-8a18135d-9218-457f-bda5-1ed2b2dcda24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130745987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tx_async_fifo_reset.4130745987
Directory /workspace/20.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_txrx.2956727088
Short name T1020
Test name
Test status
Simulation time 253466906734 ps
CPU time 574.51 seconds
Started Jan 21 07:59:44 PM PST 24
Finished Jan 21 08:09:20 PM PST 24
Peak memory 262436 kb
Host smart-e08cc25b-896b-435e-bff1-d0b5b40817c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956727088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_txrx.2956727088
Directory /workspace/20.spi_device_txrx/latest

Test location /workspace/coverage/default/20.spi_device_upload.468670862
Short name T1754
Test name
Test status
Simulation time 5896289284 ps
CPU time 19.05 seconds
Started Jan 21 07:59:51 PM PST 24
Finished Jan 21 08:00:18 PM PST 24
Peak memory 242004 kb
Host smart-654a9a4b-3983-45c2-b74c-456584d80c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468670862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.468670862
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_abort.855271362
Short name T510
Test name
Test status
Simulation time 78220849 ps
CPU time 0.79 seconds
Started Jan 21 08:00:12 PM PST 24
Finished Jan 21 08:00:14 PM PST 24
Peak memory 207108 kb
Host smart-90afcd32-c63c-46ea-8a1a-d8338cb7a913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855271362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_abort.855271362
Directory /workspace/21.spi_device_abort/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1979082555
Short name T1346
Test name
Test status
Simulation time 44596507 ps
CPU time 0.71 seconds
Started Jan 21 08:00:27 PM PST 24
Finished Jan 21 08:00:33 PM PST 24
Peak memory 206956 kb
Host smart-48572eff-2124-464d-9bde-a4e1b30c25c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979082555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1979082555
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_bit_transfer.754791567
Short name T850
Test name
Test status
Simulation time 1061061130 ps
CPU time 3.31 seconds
Started Jan 21 08:00:09 PM PST 24
Finished Jan 21 08:00:14 PM PST 24
Peak memory 217164 kb
Host smart-4ee93239-d41a-4ac9-80da-2e98259f3f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754791567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_bit_transfer.754791567
Directory /workspace/21.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/21.spi_device_byte_transfer.275050831
Short name T983
Test name
Test status
Simulation time 142488071 ps
CPU time 2.89 seconds
Started Jan 21 08:00:08 PM PST 24
Finished Jan 21 08:00:12 PM PST 24
Peak memory 217176 kb
Host smart-6cb3f387-5760-4c78-a7f6-3b07fec9519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275050831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_byte_transfer.275050831
Directory /workspace/21.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.651602433
Short name T1390
Test name
Test status
Simulation time 4346757119 ps
CPU time 6.25 seconds
Started Jan 21 08:00:21 PM PST 24
Finished Jan 21 08:00:29 PM PST 24
Peak memory 238720 kb
Host smart-ece5ac38-8777-4ba3-812a-fa4adba668cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651602433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.651602433
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1219772767
Short name T1003
Test name
Test status
Simulation time 22191170 ps
CPU time 0.83 seconds
Started Jan 21 08:00:08 PM PST 24
Finished Jan 21 08:00:11 PM PST 24
Peak memory 208032 kb
Host smart-26168b60-53cc-4c65-9945-9dcf0bb82b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219772767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1219772767
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_dummy_item_extra_dly.2497858198
Short name T1731
Test name
Test status
Simulation time 156779875537 ps
CPU time 272.87 seconds
Started Jan 21 07:59:55 PM PST 24
Finished Jan 21 08:04:35 PM PST 24
Peak memory 269948 kb
Host smart-9bcaa263-e43a-4ad2-b167-ae98f9bfca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497858198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_dummy_item_extra_dly.2497858198
Directory /workspace/21.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/21.spi_device_extreme_fifo_size.2456768728
Short name T1135
Test name
Test status
Simulation time 106052218071 ps
CPU time 767.73 seconds
Started Jan 21 07:59:56 PM PST 24
Finished Jan 21 08:12:50 PM PST 24
Peak memory 225568 kb
Host smart-fddfca7e-9f90-48e5-bdc9-3c5ca779c6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456768728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_extreme_fifo_size.2456768728
Directory /workspace/21.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/21.spi_device_fifo_full.2491809117
Short name T499
Test name
Test status
Simulation time 24356941086 ps
CPU time 1306.74 seconds
Started Jan 21 07:59:55 PM PST 24
Finished Jan 21 08:21:49 PM PST 24
Peak memory 289628 kb
Host smart-7a4e7fcd-644d-46b1-8552-32c972961ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491809117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_full.2491809117
Directory /workspace/21.spi_device_fifo_full/latest

Test location /workspace/coverage/default/21.spi_device_fifo_underflow_overflow.1771329513
Short name T1352
Test name
Test status
Simulation time 149871245936 ps
CPU time 725.57 seconds
Started Jan 21 08:00:02 PM PST 24
Finished Jan 21 08:12:13 PM PST 24
Peak memory 469008 kb
Host smart-27a84af7-26d8-4f0c-8b46-cec79b86c93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771329513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_underflow_overf
low.1771329513
Directory /workspace/21.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.365634516
Short name T263
Test name
Test status
Simulation time 36996857079 ps
CPU time 313.68 seconds
Started Jan 21 08:00:23 PM PST 24
Finished Jan 21 08:05:39 PM PST 24
Peak memory 257096 kb
Host smart-4178f4d7-784c-4b34-a1d5-f8a601d09c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365634516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.365634516
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1742957758
Short name T1419
Test name
Test status
Simulation time 47541455470 ps
CPU time 360.19 seconds
Started Jan 21 08:00:24 PM PST 24
Finished Jan 21 08:06:31 PM PST 24
Peak memory 255412 kb
Host smart-51556f18-1cdb-43a4-bd89-b91bbe24cfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742957758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1742957758
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1548073698
Short name T372
Test name
Test status
Simulation time 6063699493 ps
CPU time 37.85 seconds
Started Jan 21 08:00:24 PM PST 24
Finished Jan 21 08:01:09 PM PST 24
Peak memory 241948 kb
Host smart-1b151158-7e73-4f26-bcde-fbc73d98354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548073698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1548073698
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2622477515
Short name T309
Test name
Test status
Simulation time 322361022 ps
CPU time 4.02 seconds
Started Jan 21 08:00:20 PM PST 24
Finished Jan 21 08:00:26 PM PST 24
Peak memory 233972 kb
Host smart-5cd70c5c-4aa4-4426-8878-b4d2d304fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622477515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2622477515
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.250619911
Short name T1200
Test name
Test status
Simulation time 5175818818 ps
CPU time 17.97 seconds
Started Jan 21 08:00:19 PM PST 24
Finished Jan 21 08:00:39 PM PST 24
Peak memory 223544 kb
Host smart-e837e5cc-ee87-4775-ba98-d3340b03315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250619911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.250619911
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.46506199
Short name T1672
Test name
Test status
Simulation time 1314598192 ps
CPU time 9.39 seconds
Started Jan 21 08:00:11 PM PST 24
Finished Jan 21 08:00:22 PM PST 24
Peak memory 230948 kb
Host smart-900327cf-0922-4119-88f5-2d0e37b716a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46506199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.46506199
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2348487545
Short name T747
Test name
Test status
Simulation time 5614105869 ps
CPU time 8.58 seconds
Started Jan 21 08:00:12 PM PST 24
Finished Jan 21 08:00:21 PM PST 24
Peak memory 225608 kb
Host smart-368e5ce0-1057-445b-8c1d-e6be3156b3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348487545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2348487545
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_perf.4282681946
Short name T869
Test name
Test status
Simulation time 67624588774 ps
CPU time 670.69 seconds
Started Jan 21 08:00:03 PM PST 24
Finished Jan 21 08:11:18 PM PST 24
Peak memory 282648 kb
Host smart-429d10b0-6354-4b7c-8e4f-f44794197b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282681946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_perf.4282681946
Directory /workspace/21.spi_device_perf/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1588918519
Short name T1646
Test name
Test status
Simulation time 121664997 ps
CPU time 3.57 seconds
Started Jan 21 08:00:21 PM PST 24
Finished Jan 21 08:00:26 PM PST 24
Peak memory 221192 kb
Host smart-10bf6638-f132-4812-9008-4b10581b5077
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1588918519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1588918519
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_rx_async_fifo_reset.1042642952
Short name T1700
Test name
Test status
Simulation time 39449020 ps
CPU time 0.9 seconds
Started Jan 21 08:00:10 PM PST 24
Finished Jan 21 08:00:13 PM PST 24
Peak memory 208796 kb
Host smart-ea8edab8-976d-4a04-bcd6-ad6c098cc382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042642952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_async_fifo_reset.1042642952
Directory /workspace/21.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_rx_timeout.3299479284
Short name T1542
Test name
Test status
Simulation time 9912465839 ps
CPU time 5.95 seconds
Started Jan 21 08:00:08 PM PST 24
Finished Jan 21 08:00:16 PM PST 24
Peak memory 217264 kb
Host smart-c916c5c4-9494-4bc1-b32b-812f89afc0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299479284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_timeout.3299479284
Directory /workspace/21.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/21.spi_device_smoke.1172517398
Short name T484
Test name
Test status
Simulation time 36256667 ps
CPU time 1.02 seconds
Started Jan 21 08:00:02 PM PST 24
Finished Jan 21 08:00:08 PM PST 24
Peak memory 208180 kb
Host smart-736cfe16-5eeb-4fbc-9788-3bdfc958e10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172517398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_smoke.1172517398
Directory /workspace/21.spi_device_smoke/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3620223752
Short name T783
Test name
Test status
Simulation time 5624534885 ps
CPU time 46.81 seconds
Started Jan 21 08:00:08 PM PST 24
Finished Jan 21 08:00:56 PM PST 24
Peak memory 217764 kb
Host smart-e913829e-ff61-4fb7-80d0-b86f776e6ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620223752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3620223752
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3884639731
Short name T1444
Test name
Test status
Simulation time 55129423874 ps
CPU time 41.08 seconds
Started Jan 21 08:00:07 PM PST 24
Finished Jan 21 08:00:50 PM PST 24
Peak memory 217292 kb
Host smart-1fab0239-d685-4753-b5c3-54ef64b52142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884639731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3884639731
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2491820927
Short name T1158
Test name
Test status
Simulation time 87193192 ps
CPU time 1.78 seconds
Started Jan 21 08:00:21 PM PST 24
Finished Jan 21 08:00:24 PM PST 24
Peak memory 217212 kb
Host smart-243a2cdd-28e4-4799-bea9-a384afcd5981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491820927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2491820927
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4223645176
Short name T738
Test name
Test status
Simulation time 204110809 ps
CPU time 0.9 seconds
Started Jan 21 08:00:15 PM PST 24
Finished Jan 21 08:00:17 PM PST 24
Peak memory 208376 kb
Host smart-9f443a78-ad7c-491c-b9b5-5b408f46db04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223645176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4223645176
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tx_async_fifo_reset.4154500098
Short name T1596
Test name
Test status
Simulation time 28127884 ps
CPU time 0.76 seconds
Started Jan 21 08:00:04 PM PST 24
Finished Jan 21 08:00:08 PM PST 24
Peak memory 208728 kb
Host smart-d4aa83c1-42a2-4ae5-8d20-297022ef478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154500098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tx_async_fifo_reset.4154500098
Directory /workspace/21.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_txrx.593875627
Short name T700
Test name
Test status
Simulation time 22666987421 ps
CPU time 316.21 seconds
Started Jan 21 07:59:53 PM PST 24
Finished Jan 21 08:05:18 PM PST 24
Peak memory 284996 kb
Host smart-df77e173-2460-40b5-b65f-cdecfe7c0cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593875627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_txrx.593875627
Directory /workspace/21.spi_device_txrx/latest

Test location /workspace/coverage/default/21.spi_device_upload.4194795029
Short name T1757
Test name
Test status
Simulation time 2486199750 ps
CPU time 9.36 seconds
Started Jan 21 08:00:21 PM PST 24
Finished Jan 21 08:00:33 PM PST 24
Peak memory 220432 kb
Host smart-925463bc-5cb1-4687-80f9-e197b5eae7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194795029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4194795029
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_abort.2777544045
Short name T92
Test name
Test status
Simulation time 26022174 ps
CPU time 0.81 seconds
Started Jan 21 08:00:45 PM PST 24
Finished Jan 21 08:00:50 PM PST 24
Peak memory 206996 kb
Host smart-f3241c0c-ed09-47ee-9fb4-0e34ead8940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777544045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_abort.2777544045
Directory /workspace/22.spi_device_abort/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.36034800
Short name T1184
Test name
Test status
Simulation time 12281112 ps
CPU time 0.74 seconds
Started Jan 21 08:00:56 PM PST 24
Finished Jan 21 08:01:08 PM PST 24
Peak memory 206916 kb
Host smart-800bf175-a884-4f35-aca3-4f86fde36fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36034800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.36034800
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_bit_transfer.231188840
Short name T1
Test name
Test status
Simulation time 2331738351 ps
CPU time 3.22 seconds
Started Jan 21 08:00:44 PM PST 24
Finished Jan 21 08:00:49 PM PST 24
Peak memory 217268 kb
Host smart-3fb7fe0c-6a57-4897-b98f-55946d21ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231188840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_bit_transfer.231188840
Directory /workspace/22.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/22.spi_device_byte_transfer.2350415953
Short name T1630
Test name
Test status
Simulation time 179541554 ps
CPU time 3.34 seconds
Started Jan 21 08:00:38 PM PST 24
Finished Jan 21 08:00:44 PM PST 24
Peak memory 217156 kb
Host smart-56efe4e8-4ba2-46c5-8908-faf46ea9a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350415953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_byte_transfer.2350415953
Directory /workspace/22.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1281407603
Short name T925
Test name
Test status
Simulation time 508919759 ps
CPU time 3.81 seconds
Started Jan 21 08:00:53 PM PST 24
Finished Jan 21 08:01:03 PM PST 24
Peak memory 219020 kb
Host smart-8a7b73c8-668b-4b27-994a-14d7bb2052a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281407603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1281407603
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1687426477
Short name T1038
Test name
Test status
Simulation time 40298913 ps
CPU time 0.8 seconds
Started Jan 21 08:00:31 PM PST 24
Finished Jan 21 08:00:37 PM PST 24
Peak memory 208024 kb
Host smart-4e44a79f-83c1-47b0-906b-9b7eb0c0987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687426477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1687426477
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_dummy_item_extra_dly.4098047492
Short name T1756
Test name
Test status
Simulation time 44037336610 ps
CPU time 386.75 seconds
Started Jan 21 08:00:23 PM PST 24
Finished Jan 21 08:06:52 PM PST 24
Peak memory 261776 kb
Host smart-3129053d-6bb5-4e2e-861c-1f4b546b77e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098047492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_dummy_item_extra_dly.4098047492
Directory /workspace/22.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/22.spi_device_extreme_fifo_size.1493607242
Short name T1270
Test name
Test status
Simulation time 2303144712 ps
CPU time 37.78 seconds
Started Jan 21 08:00:28 PM PST 24
Finished Jan 21 08:01:10 PM PST 24
Peak memory 241900 kb
Host smart-d66439a5-b631-4b67-93ce-c60406ab5c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493607242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_extreme_fifo_size.1493607242
Directory /workspace/22.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/22.spi_device_fifo_full.3342771301
Short name T1299
Test name
Test status
Simulation time 24031467842 ps
CPU time 591.33 seconds
Started Jan 21 08:00:26 PM PST 24
Finished Jan 21 08:10:24 PM PST 24
Peak memory 299784 kb
Host smart-fb4894f0-c4f1-449e-b02f-28954ecfad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342771301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_full.3342771301
Directory /workspace/22.spi_device_fifo_full/latest

Test location /workspace/coverage/default/22.spi_device_fifo_underflow_overflow.1851404274
Short name T59
Test name
Test status
Simulation time 178226629747 ps
CPU time 532.6 seconds
Started Jan 21 08:00:30 PM PST 24
Finished Jan 21 08:09:27 PM PST 24
Peak memory 436824 kb
Host smart-61393b94-d0a8-46c6-a202-6851db44d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851404274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_underflow_overf
low.1851404274
Directory /workspace/22.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2865313245
Short name T708
Test name
Test status
Simulation time 47730301752 ps
CPU time 61.75 seconds
Started Jan 21 08:00:53 PM PST 24
Finished Jan 21 08:02:01 PM PST 24
Peak memory 250192 kb
Host smart-ad1f52b7-d3e3-4eb0-89ef-ae6ab8784755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865313245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2865313245
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2518630208
Short name T651
Test name
Test status
Simulation time 683481724473 ps
CPU time 537.34 seconds
Started Jan 21 08:00:53 PM PST 24
Finished Jan 21 08:09:55 PM PST 24
Peak memory 261408 kb
Host smart-4216fef0-df45-4d99-80e3-3d84ef80fde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518630208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2518630208
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.494746339
Short name T631
Test name
Test status
Simulation time 1137088634 ps
CPU time 17.12 seconds
Started Jan 21 08:00:51 PM PST 24
Finished Jan 21 08:01:11 PM PST 24
Peak memory 256400 kb
Host smart-1d2c5e4e-e87e-4283-b190-5ec4dde36e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494746339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.494746339
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intr.1151507665
Short name T1091
Test name
Test status
Simulation time 9934250527 ps
CPU time 48.71 seconds
Started Jan 21 08:00:31 PM PST 24
Finished Jan 21 08:01:25 PM PST 24
Peak memory 241196 kb
Host smart-a00dec12-e4d3-4767-8322-8e65b39358be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151507665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intr.1151507665
Directory /workspace/22.spi_device_intr/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2133459637
Short name T825
Test name
Test status
Simulation time 8629892776 ps
CPU time 17.92 seconds
Started Jan 21 08:00:52 PM PST 24
Finished Jan 21 08:01:12 PM PST 24
Peak memory 229320 kb
Host smart-baf29988-f115-45b2-ac13-222989927b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133459637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2133459637
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1345739406
Short name T366
Test name
Test status
Simulation time 46876716 ps
CPU time 3.29 seconds
Started Jan 21 08:00:52 PM PST 24
Finished Jan 21 08:00:58 PM PST 24
Peak memory 238852 kb
Host smart-6e09ed04-f2f5-42d3-9279-97d40050c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345739406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1345739406
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.987352121
Short name T493
Test name
Test status
Simulation time 179847594 ps
CPU time 3.57 seconds
Started Jan 21 08:00:51 PM PST 24
Finished Jan 21 08:00:58 PM PST 24
Peak memory 234808 kb
Host smart-8a8888d2-0821-43f3-96d8-a7207ffc3fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987352121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.987352121
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_perf.2077786275
Short name T1343
Test name
Test status
Simulation time 8799330653 ps
CPU time 345.77 seconds
Started Jan 21 08:00:30 PM PST 24
Finished Jan 21 08:06:19 PM PST 24
Peak memory 286332 kb
Host smart-a7dbcf32-fd70-456b-b3b6-dd1de7f0241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077786275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_perf.2077786275
Directory /workspace/22.spi_device_perf/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4115997014
Short name T1260
Test name
Test status
Simulation time 1761505753 ps
CPU time 6.15 seconds
Started Jan 21 08:00:53 PM PST 24
Finished Jan 21 08:01:04 PM PST 24
Peak memory 234832 kb
Host smart-99ae6dc6-5150-4ce7-b09f-8facfa9927e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4115997014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4115997014
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_rx_async_fifo_reset.4042775725
Short name T1137
Test name
Test status
Simulation time 23743984 ps
CPU time 0.92 seconds
Started Jan 21 08:00:45 PM PST 24
Finished Jan 21 08:00:50 PM PST 24
Peak memory 208780 kb
Host smart-b3f92a36-de83-43bb-bcbb-814f07d45689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042775725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_async_fifo_reset.4042775725
Directory /workspace/22.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_rx_timeout.17107275
Short name T791
Test name
Test status
Simulation time 3033802337 ps
CPU time 6.9 seconds
Started Jan 21 08:00:43 PM PST 24
Finished Jan 21 08:00:51 PM PST 24
Peak memory 217416 kb
Host smart-2c6299f0-4a2e-4dea-836d-22004de84348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17107275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_timeout.17107275
Directory /workspace/22.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/22.spi_device_smoke.4177162354
Short name T1377
Test name
Test status
Simulation time 54387048 ps
CPU time 1.14 seconds
Started Jan 21 08:00:28 PM PST 24
Finished Jan 21 08:00:34 PM PST 24
Peak memory 216920 kb
Host smart-0d574ff2-4a26-49bd-ab9f-6fe3a39824d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177162354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_smoke.4177162354
Directory /workspace/22.spi_device_smoke/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.423010759
Short name T314
Test name
Test status
Simulation time 150305422213 ps
CPU time 1235.61 seconds
Started Jan 21 08:00:49 PM PST 24
Finished Jan 21 08:21:27 PM PST 24
Peak memory 339520 kb
Host smart-5e4e6952-bb48-4f7e-8c37-bd2fd55aad78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423010759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.423010759
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.754474560
Short name T1323
Test name
Test status
Simulation time 4504942550 ps
CPU time 53.51 seconds
Started Jan 21 08:00:42 PM PST 24
Finished Jan 21 08:01:37 PM PST 24
Peak memory 217604 kb
Host smart-5fbe0490-3291-43e4-9c9b-e167d6ad789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754474560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.754474560
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4179121636
Short name T786
Test name
Test status
Simulation time 3601409623 ps
CPU time 9.96 seconds
Started Jan 21 08:00:42 PM PST 24
Finished Jan 21 08:00:54 PM PST 24
Peak memory 217236 kb
Host smart-c357ab94-3d52-4d61-8429-efb748fbf4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179121636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4179121636
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3383881650
Short name T1371
Test name
Test status
Simulation time 105341727 ps
CPU time 2.18 seconds
Started Jan 21 08:00:42 PM PST 24
Finished Jan 21 08:00:46 PM PST 24
Peak memory 217288 kb
Host smart-0213a761-9d5f-4e74-aeaa-ab8d2ceeb965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383881650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3383881650
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3358300526
Short name T734
Test name
Test status
Simulation time 208444301 ps
CPU time 0.89 seconds
Started Jan 21 08:00:46 PM PST 24
Finished Jan 21 08:00:50 PM PST 24
Peak memory 207256 kb
Host smart-ee27449f-b841-46be-992b-d9e9ff9c520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358300526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3358300526
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tx_async_fifo_reset.416451563
Short name T96
Test name
Test status
Simulation time 47534643 ps
CPU time 0.78 seconds
Started Jan 21 08:00:44 PM PST 24
Finished Jan 21 08:00:46 PM PST 24
Peak memory 208668 kb
Host smart-bc0a57ae-1225-4548-a9e2-d003f018f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416451563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tx_async_fifo_reset.416451563
Directory /workspace/22.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_txrx.2406039014
Short name T1423
Test name
Test status
Simulation time 88635749379 ps
CPU time 213.87 seconds
Started Jan 21 08:00:23 PM PST 24
Finished Jan 21 08:03:59 PM PST 24
Peak memory 289984 kb
Host smart-c9a18dd2-202a-4a27-b7aa-0557e01b86d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406039014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_txrx.2406039014
Directory /workspace/22.spi_device_txrx/latest

Test location /workspace/coverage/default/22.spi_device_upload.731333410
Short name T940
Test name
Test status
Simulation time 829208769 ps
CPU time 10.15 seconds
Started Jan 21 08:00:51 PM PST 24
Finished Jan 21 08:01:04 PM PST 24
Peak memory 234656 kb
Host smart-b4df1e46-17f1-408e-8d78-7882ab6e6840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731333410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.731333410
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_abort.1604408814
Short name T1571
Test name
Test status
Simulation time 63380678 ps
CPU time 0.76 seconds
Started Jan 21 08:01:03 PM PST 24
Finished Jan 21 08:01:11 PM PST 24
Peak memory 207124 kb
Host smart-dfa552fa-b116-466c-b55e-e7fa573aabe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604408814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_abort.1604408814
Directory /workspace/23.spi_device_abort/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1489888639
Short name T1703
Test name
Test status
Simulation time 11229164 ps
CPU time 0.75 seconds
Started Jan 21 08:27:08 PM PST 24
Finished Jan 21 08:27:10 PM PST 24
Peak memory 206948 kb
Host smart-30ae4124-dbf6-40ce-a994-5d58adf69bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489888639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1489888639
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_bit_transfer.189880504
Short name T1028
Test name
Test status
Simulation time 280682380 ps
CPU time 2.54 seconds
Started Jan 21 08:01:03 PM PST 24
Finished Jan 21 08:01:13 PM PST 24
Peak memory 217152 kb
Host smart-c20b3116-0464-40af-aa4c-b3b160cc0e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189880504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_bit_transfer.189880504
Directory /workspace/23.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/23.spi_device_byte_transfer.857117696
Short name T603
Test name
Test status
Simulation time 339096173 ps
CPU time 3.08 seconds
Started Jan 21 08:00:56 PM PST 24
Finished Jan 21 08:01:10 PM PST 24
Peak memory 217180 kb
Host smart-2c2eea24-4340-4a7d-9dd4-e5f7aca93c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857117696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_byte_transfer.857117696
Directory /workspace/23.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2192282123
Short name T310
Test name
Test status
Simulation time 1459704727 ps
CPU time 4.45 seconds
Started Jan 21 08:01:18 PM PST 24
Finished Jan 21 08:01:24 PM PST 24
Peak memory 238740 kb
Host smart-54096046-61e9-4e74-879f-65782aa01541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192282123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2192282123
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2110032515
Short name T1418
Test name
Test status
Simulation time 80150264 ps
CPU time 0.79 seconds
Started Jan 21 08:01:00 PM PST 24
Finished Jan 21 08:01:08 PM PST 24
Peak memory 208024 kb
Host smart-c985db63-286a-45db-8ee7-2e21286d64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110032515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2110032515
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_dummy_item_extra_dly.3846109833
Short name T1102
Test name
Test status
Simulation time 56006557486 ps
CPU time 461.37 seconds
Started Jan 21 08:00:56 PM PST 24
Finished Jan 21 08:08:49 PM PST 24
Peak memory 307532 kb
Host smart-b904a1d4-f503-4307-9e49-d3589405fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846109833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_dummy_item_extra_dly.3846109833
Directory /workspace/23.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/23.spi_device_extreme_fifo_size.977244519
Short name T220
Test name
Test status
Simulation time 841140768154 ps
CPU time 908.61 seconds
Started Jan 21 08:32:52 PM PST 24
Finished Jan 21 08:48:01 PM PST 24
Peak memory 220116 kb
Host smart-14acd25e-ac11-4b30-b0a5-4efa7c088983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977244519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_extreme_fifo_size.977244519
Directory /workspace/23.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/23.spi_device_fifo_full.2825444553
Short name T300
Test name
Test status
Simulation time 47231993640 ps
CPU time 387.88 seconds
Started Jan 21 08:43:50 PM PST 24
Finished Jan 21 08:50:21 PM PST 24
Peak memory 253384 kb
Host smart-de60092e-0291-4373-99cc-7624c4c668ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825444553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_full.2825444553
Directory /workspace/23.spi_device_fifo_full/latest

Test location /workspace/coverage/default/23.spi_device_fifo_underflow_overflow.2323758099
Short name T1491
Test name
Test status
Simulation time 360045457636 ps
CPU time 340.98 seconds
Started Jan 21 08:00:57 PM PST 24
Finished Jan 21 08:06:48 PM PST 24
Peak memory 429548 kb
Host smart-1c6ea5b3-92a5-438d-9597-a341b7587961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323758099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_underflow_overf
low.2323758099
Directory /workspace/23.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1306094625
Short name T266
Test name
Test status
Simulation time 10305573262 ps
CPU time 36.74 seconds
Started Jan 21 08:01:22 PM PST 24
Finished Jan 21 08:02:00 PM PST 24
Peak memory 250240 kb
Host smart-a2ea754d-65bb-4340-b729-093ed08d2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306094625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1306094625
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.305777671
Short name T328
Test name
Test status
Simulation time 21849827690 ps
CPU time 180.01 seconds
Started Jan 21 08:01:17 PM PST 24
Finished Jan 21 08:04:19 PM PST 24
Peak memory 251388 kb
Host smart-0313231b-290c-4bfa-a1c2-cd2cb4e0277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305777671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.305777671
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3889935041
Short name T31
Test name
Test status
Simulation time 45706042094 ps
CPU time 116.31 seconds
Started Jan 21 08:01:20 PM PST 24
Finished Jan 21 08:03:18 PM PST 24
Peak memory 270144 kb
Host smart-228e488a-05d5-4a7f-9fe7-aef9e3331b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889935041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3889935041
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2815930374
Short name T898
Test name
Test status
Simulation time 13993635000 ps
CPU time 15.69 seconds
Started Jan 21 08:01:19 PM PST 24
Finished Jan 21 08:01:37 PM PST 24
Peak memory 233692 kb
Host smart-84ecb42f-eae1-4fa5-a3dc-0fda798c0bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815930374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2815930374
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.22980208
Short name T721
Test name
Test status
Simulation time 600859157 ps
CPU time 4.15 seconds
Started Jan 21 08:01:15 PM PST 24
Finished Jan 21 08:01:22 PM PST 24
Peak memory 241732 kb
Host smart-9b5d56ac-4e46-4588-b47d-7075ddaf9c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22980208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.22980208
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intr.1995664112
Short name T1210
Test name
Test status
Simulation time 75535487718 ps
CPU time 71.98 seconds
Started Jan 21 08:01:00 PM PST 24
Finished Jan 21 08:02:19 PM PST 24
Peak memory 234772 kb
Host smart-ccb77b14-5e35-4197-bee1-a183c384f83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995664112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intr.1995664112
Directory /workspace/23.spi_device_intr/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4126889597
Short name T1036
Test name
Test status
Simulation time 1818103449 ps
CPU time 10.07 seconds
Started Jan 21 08:01:15 PM PST 24
Finished Jan 21 08:01:27 PM PST 24
Peak memory 230104 kb
Host smart-45ef48af-8ccc-491a-83b1-ce45eadf4974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126889597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4126889597
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3939950477
Short name T1026
Test name
Test status
Simulation time 2433997966 ps
CPU time 7.07 seconds
Started Jan 21 08:01:15 PM PST 24
Finished Jan 21 08:01:24 PM PST 24
Peak memory 241020 kb
Host smart-3846538c-5109-490f-bc04-46d7dedc3e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939950477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3939950477
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4271752458
Short name T522
Test name
Test status
Simulation time 613610156 ps
CPU time 5.43 seconds
Started Jan 21 08:01:15 PM PST 24
Finished Jan 21 08:01:23 PM PST 24
Peak memory 225572 kb
Host smart-6d38d98f-2609-46d5-83b0-453a34b95a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271752458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4271752458
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_perf.2451137973
Short name T1000
Test name
Test status
Simulation time 33503705200 ps
CPU time 795.49 seconds
Started Jan 21 08:00:57 PM PST 24
Finished Jan 21 08:14:23 PM PST 24
Peak memory 273820 kb
Host smart-bb03f336-9fd4-4f9d-b1f8-4abdffbc69d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451137973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_perf.2451137973
Directory /workspace/23.spi_device_perf/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4288051183
Short name T752
Test name
Test status
Simulation time 186450482 ps
CPU time 3.77 seconds
Started Jan 21 08:01:20 PM PST 24
Finished Jan 21 08:01:26 PM PST 24
Peak memory 219360 kb
Host smart-96a8861e-0c95-47f3-8ac0-0f19a8a52672
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4288051183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4288051183
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_rx_async_fifo_reset.165924984
Short name T97
Test name
Test status
Simulation time 28477585 ps
CPU time 0.9 seconds
Started Jan 21 08:01:03 PM PST 24
Finished Jan 21 08:01:11 PM PST 24
Peak memory 208824 kb
Host smart-0db5cbff-ca46-4280-9f45-dff09b573406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165924984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_async_fifo_reset.165924984
Directory /workspace/23.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_rx_timeout.2339259648
Short name T732
Test name
Test status
Simulation time 2387104134 ps
CPU time 6.38 seconds
Started Jan 21 08:23:14 PM PST 24
Finished Jan 21 08:23:21 PM PST 24
Peak memory 217260 kb
Host smart-2488c9a6-dafa-4bcd-a4d6-01c49019c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339259648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_timeout.2339259648
Directory /workspace/23.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/23.spi_device_smoke.2151405359
Short name T1600
Test name
Test status
Simulation time 150578358 ps
CPU time 1.12 seconds
Started Jan 21 08:49:47 PM PST 24
Finished Jan 21 08:50:13 PM PST 24
Peak memory 208420 kb
Host smart-9609eef2-e3f8-4243-b090-988066c5bcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151405359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_smoke.2151405359
Directory /workspace/23.spi_device_smoke/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.391781783
Short name T853
Test name
Test status
Simulation time 39105520828 ps
CPU time 86.42 seconds
Started Jan 21 08:01:03 PM PST 24
Finished Jan 21 08:02:37 PM PST 24
Peak memory 217448 kb
Host smart-81c59a9c-94a6-46c2-83ac-bdc19b034ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391781783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.391781783
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.503914458
Short name T1097
Test name
Test status
Simulation time 19761863715 ps
CPU time 16.39 seconds
Started Jan 21 08:01:03 PM PST 24
Finished Jan 21 08:01:26 PM PST 24
Peak memory 217344 kb
Host smart-bab7bca7-0c2e-4758-a8c1-f16a5329b470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503914458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.503914458
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2897547713
Short name T1653
Test name
Test status
Simulation time 162518547 ps
CPU time 1.76 seconds
Started Jan 21 08:01:11 PM PST 24
Finished Jan 21 08:01:17 PM PST 24
Peak memory 217328 kb
Host smart-b269d257-03e6-4c31-8fa1-9e6b5c5120af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897547713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2897547713
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4294772377
Short name T879
Test name
Test status
Simulation time 54011923 ps
CPU time 0.99 seconds
Started Jan 21 08:01:14 PM PST 24
Finished Jan 21 08:01:18 PM PST 24
Peak memory 208336 kb
Host smart-0bf82910-439c-4438-9311-a37c017edcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294772377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4294772377
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tx_async_fifo_reset.765428338
Short name T165
Test name
Test status
Simulation time 13759116 ps
CPU time 0.79 seconds
Started Jan 21 08:01:03 PM PST 24
Finished Jan 21 08:01:11 PM PST 24
Peak memory 208684 kb
Host smart-32f7f3cf-b284-4617-85ac-5715c6946097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765428338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tx_async_fifo_reset.765428338
Directory /workspace/23.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_txrx.1894186927
Short name T1587
Test name
Test status
Simulation time 112917974145 ps
CPU time 248.26 seconds
Started Jan 21 08:00:58 PM PST 24
Finished Jan 21 08:05:16 PM PST 24
Peak memory 261424 kb
Host smart-490ff688-3fa0-44f2-a9da-6f213b6356a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894186927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_txrx.1894186927
Directory /workspace/23.spi_device_txrx/latest

Test location /workspace/coverage/default/23.spi_device_upload.4286741633
Short name T1738
Test name
Test status
Simulation time 69765830271 ps
CPU time 21.65 seconds
Started Jan 21 08:01:16 PM PST 24
Finished Jan 21 08:01:40 PM PST 24
Peak memory 247844 kb
Host smart-a43e123e-e564-4873-808f-cfe0d5294889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286741633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4286741633
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_abort.90157505
Short name T1523
Test name
Test status
Simulation time 16648752 ps
CPU time 0.76 seconds
Started Jan 21 08:01:42 PM PST 24
Finished Jan 21 08:01:44 PM PST 24
Peak memory 207000 kb
Host smart-c6613b7b-6fda-4aab-a9fd-8155ed5573a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90157505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_abort.90157505
Directory /workspace/24.spi_device_abort/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2075463088
Short name T117
Test name
Test status
Simulation time 26580146 ps
CPU time 0.77 seconds
Started Jan 21 08:02:02 PM PST 24
Finished Jan 21 08:02:06 PM PST 24
Peak memory 206912 kb
Host smart-ec3d5d80-2da6-4505-8c7f-6eb613431b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075463088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2075463088
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_bit_transfer.1483459000
Short name T946
Test name
Test status
Simulation time 207806177 ps
CPU time 2.36 seconds
Started Jan 21 08:01:33 PM PST 24
Finished Jan 21 08:01:36 PM PST 24
Peak memory 217180 kb
Host smart-ab11d050-320f-49de-ba0a-e7b62da0c69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483459000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_bit_transfer.1483459000
Directory /workspace/24.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/24.spi_device_byte_transfer.1626485421
Short name T1447
Test name
Test status
Simulation time 109286492 ps
CPU time 2.84 seconds
Started Jan 21 08:01:37 PM PST 24
Finished Jan 21 08:01:41 PM PST 24
Peak memory 217216 kb
Host smart-32242d0f-faf4-4962-a312-7b330bd5f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626485421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_byte_transfer.1626485421
Directory /workspace/24.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.852071009
Short name T305
Test name
Test status
Simulation time 1479895724 ps
CPU time 7.23 seconds
Started Jan 21 08:01:59 PM PST 24
Finished Jan 21 08:02:09 PM PST 24
Peak memory 221504 kb
Host smart-67556132-37ff-4793-aa88-4320c6202a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852071009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.852071009
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3012570820
Short name T1030
Test name
Test status
Simulation time 12247673 ps
CPU time 0.79 seconds
Started Jan 21 08:01:25 PM PST 24
Finished Jan 21 08:01:27 PM PST 24
Peak memory 207028 kb
Host smart-3f64a8b4-7d37-4d7d-994c-c5e8c0308ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012570820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3012570820
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_dummy_item_extra_dly.4105513478
Short name T796
Test name
Test status
Simulation time 91779603987 ps
CPU time 417.81 seconds
Started Jan 21 08:01:26 PM PST 24
Finished Jan 21 08:08:25 PM PST 24
Peak memory 282248 kb
Host smart-e5e2968a-f762-4681-b8ca-024e5b90b920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105513478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_dummy_item_extra_dly.4105513478
Directory /workspace/24.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/24.spi_device_extreme_fifo_size.2359188464
Short name T1211
Test name
Test status
Simulation time 4287080291 ps
CPU time 25.46 seconds
Started Jan 21 08:01:28 PM PST 24
Finished Jan 21 08:01:54 PM PST 24
Peak memory 233688 kb
Host smart-9865006a-7531-4e73-8282-53de46fd5319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359188464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_extreme_fifo_size.2359188464
Directory /workspace/24.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/24.spi_device_fifo_full.1903628285
Short name T1611
Test name
Test status
Simulation time 27619237446 ps
CPU time 348.98 seconds
Started Jan 21 08:01:21 PM PST 24
Finished Jan 21 08:07:11 PM PST 24
Peak memory 282352 kb
Host smart-033d3441-cfd1-4495-807f-7fa174a0d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903628285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_full.1903628285
Directory /workspace/24.spi_device_fifo_full/latest

Test location /workspace/coverage/default/24.spi_device_fifo_underflow_overflow.4011229222
Short name T1398
Test name
Test status
Simulation time 31992877475 ps
CPU time 265.51 seconds
Started Jan 21 08:01:26 PM PST 24
Finished Jan 21 08:05:52 PM PST 24
Peak memory 341400 kb
Host smart-c56ea9c0-1130-4aa9-97db-c797108e8448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011229222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_underflow_overf
low.4011229222
Directory /workspace/24.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.429030636
Short name T252
Test name
Test status
Simulation time 95193722424 ps
CPU time 251.67 seconds
Started Jan 21 08:01:55 PM PST 24
Finished Jan 21 08:06:08 PM PST 24
Peak memory 266636 kb
Host smart-ce93a2be-2f53-49ab-b931-44ab4ef7f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429030636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.429030636
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.110792617
Short name T954
Test name
Test status
Simulation time 29098972921 ps
CPU time 290.3 seconds
Started Jan 21 08:02:00 PM PST 24
Finished Jan 21 08:06:54 PM PST 24
Peak memory 256324 kb
Host smart-e52d8bf7-1e74-463a-8d74-8daeec9effd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110792617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.110792617
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3200039864
Short name T1524
Test name
Test status
Simulation time 9988899429 ps
CPU time 26.73 seconds
Started Jan 21 08:01:54 PM PST 24
Finished Jan 21 08:02:22 PM PST 24
Peak memory 254764 kb
Host smart-11f29d68-e5b5-4f6f-9c64-1d64b7bec380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200039864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3200039864
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2692806006
Short name T735
Test name
Test status
Simulation time 20156318100 ps
CPU time 18.09 seconds
Started Jan 21 08:01:49 PM PST 24
Finished Jan 21 08:02:10 PM PST 24
Peak memory 242040 kb
Host smart-c0f21c37-1756-4605-85e2-3c7a549d61ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692806006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2692806006
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2078908494
Short name T1155
Test name
Test status
Simulation time 1814023510 ps
CPU time 5.22 seconds
Started Jan 21 08:01:42 PM PST 24
Finished Jan 21 08:01:48 PM PST 24
Peak memory 219000 kb
Host smart-8a9cfe3d-e1d0-43ad-b892-6e73d26c632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078908494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2078908494
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.451339895
Short name T593
Test name
Test status
Simulation time 35400623174 ps
CPU time 18.73 seconds
Started Jan 21 08:01:44 PM PST 24
Finished Jan 21 08:02:06 PM PST 24
Peak memory 225660 kb
Host smart-1a481dc3-3765-402b-a46a-3bf559ef48ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451339895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.451339895
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4106577060
Short name T17
Test name
Test status
Simulation time 226147143 ps
CPU time 2.71 seconds
Started Jan 21 08:01:44 PM PST 24
Finished Jan 21 08:01:50 PM PST 24
Peak memory 219300 kb
Host smart-ff17e3ef-f4a0-4cf1-9d50-8d8f84adc007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106577060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4106577060
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_perf.4104499045
Short name T583
Test name
Test status
Simulation time 34873190289 ps
CPU time 1264.86 seconds
Started Jan 21 08:01:24 PM PST 24
Finished Jan 21 08:22:30 PM PST 24
Peak memory 241252 kb
Host smart-ff65f2b3-3f31-49f0-b11e-81fbf76f04c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104499045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_perf.4104499045
Directory /workspace/24.spi_device_perf/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1144235735
Short name T1056
Test name
Test status
Simulation time 1188346441 ps
CPU time 6.79 seconds
Started Jan 21 08:01:52 PM PST 24
Finished Jan 21 08:02:00 PM PST 24
Peak memory 234940 kb
Host smart-e57c095b-06db-4b58-bf03-ca09cebb777d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1144235735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1144235735
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_rx_async_fifo_reset.3236099827
Short name T1062
Test name
Test status
Simulation time 47654100 ps
CPU time 0.87 seconds
Started Jan 21 08:01:44 PM PST 24
Finished Jan 21 08:01:49 PM PST 24
Peak memory 208804 kb
Host smart-3c7f3955-a90c-40ff-8ee8-eda3d981c0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236099827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_async_fifo_reset.3236099827
Directory /workspace/24.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_rx_timeout.2215324398
Short name T69
Test name
Test status
Simulation time 842889843 ps
CPU time 6.4 seconds
Started Jan 21 08:01:36 PM PST 24
Finished Jan 21 08:01:44 PM PST 24
Peak memory 217200 kb
Host smart-f0923234-bb5e-4538-9ced-0c38b44457cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215324398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_timeout.2215324398
Directory /workspace/24.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/24.spi_device_smoke.3984868848
Short name T1559
Test name
Test status
Simulation time 100506017 ps
CPU time 1.33 seconds
Started Jan 21 08:01:19 PM PST 24
Finished Jan 21 08:01:23 PM PST 24
Peak memory 217208 kb
Host smart-d3379edf-e1b2-41dc-86cf-60366d5df10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984868848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_smoke.3984868848
Directory /workspace/24.spi_device_smoke/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2347728904
Short name T844
Test name
Test status
Simulation time 777937064 ps
CPU time 9.85 seconds
Started Jan 21 08:01:35 PM PST 24
Finished Jan 21 08:01:46 PM PST 24
Peak memory 217312 kb
Host smart-360cb8a2-eaba-451a-80aa-7a7d937fc1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347728904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2347728904
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2575907512
Short name T861
Test name
Test status
Simulation time 3454789474 ps
CPU time 11.7 seconds
Started Jan 21 08:01:33 PM PST 24
Finished Jan 21 08:01:46 PM PST 24
Peak memory 217284 kb
Host smart-35263ae2-a1b5-4ae4-8cf8-666e21e23073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575907512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2575907512
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3376435993
Short name T1762
Test name
Test status
Simulation time 1011639405 ps
CPU time 8.18 seconds
Started Jan 21 08:01:49 PM PST 24
Finished Jan 21 08:02:00 PM PST 24
Peak memory 217296 kb
Host smart-b7fd0225-d495-4d4d-a558-e869d5dbea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376435993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3376435993
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1387729776
Short name T1605
Test name
Test status
Simulation time 92731492 ps
CPU time 1.07 seconds
Started Jan 21 08:01:49 PM PST 24
Finished Jan 21 08:01:53 PM PST 24
Peak memory 208332 kb
Host smart-11f42537-ab0d-4369-9c4e-684534080c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387729776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1387729776
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tx_async_fifo_reset.1242019405
Short name T669
Test name
Test status
Simulation time 52585422 ps
CPU time 0.77 seconds
Started Jan 21 08:01:33 PM PST 24
Finished Jan 21 08:01:35 PM PST 24
Peak memory 208784 kb
Host smart-055152e1-4f82-499d-8883-cdf3387e7ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242019405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tx_async_fifo_reset.1242019405
Directory /workspace/24.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_txrx.615732589
Short name T1221
Test name
Test status
Simulation time 47520793705 ps
CPU time 385.27 seconds
Started Jan 21 08:01:18 PM PST 24
Finished Jan 21 08:07:45 PM PST 24
Peak memory 267944 kb
Host smart-91b94164-b1f9-424f-b86a-9ba92b377b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615732589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_txrx.615732589
Directory /workspace/24.spi_device_txrx/latest

Test location /workspace/coverage/default/24.spi_device_upload.2635539868
Short name T1024
Test name
Test status
Simulation time 10882976292 ps
CPU time 19.79 seconds
Started Jan 21 08:01:57 PM PST 24
Finished Jan 21 08:02:18 PM PST 24
Peak memory 220080 kb
Host smart-8925b88a-9f92-4c00-a431-74fddbe987ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635539868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2635539868
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_abort.1972742633
Short name T1106
Test name
Test status
Simulation time 91329693 ps
CPU time 0.76 seconds
Started Jan 21 08:02:24 PM PST 24
Finished Jan 21 08:02:28 PM PST 24
Peak memory 207076 kb
Host smart-d3eba2aa-a8f7-44fc-81b5-bc8f6949d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972742633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_abort.1972742633
Directory /workspace/25.spi_device_abort/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1848891990
Short name T103
Test name
Test status
Simulation time 15954600 ps
CPU time 0.74 seconds
Started Jan 21 08:02:21 PM PST 24
Finished Jan 21 08:02:26 PM PST 24
Peak memory 206976 kb
Host smart-3b9d4fec-52cf-42b3-b372-4dd57b7af427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848891990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1848891990
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_bit_transfer.791647753
Short name T875
Test name
Test status
Simulation time 127880411 ps
CPU time 2.86 seconds
Started Jan 21 08:02:09 PM PST 24
Finished Jan 21 08:02:14 PM PST 24
Peak memory 217192 kb
Host smart-e6fd72d8-c6e7-47a5-9d09-71c79e941119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791647753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_bit_transfer.791647753
Directory /workspace/25.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/25.spi_device_byte_transfer.1828583569
Short name T916
Test name
Test status
Simulation time 228225640 ps
CPU time 3.61 seconds
Started Jan 21 08:02:06 PM PST 24
Finished Jan 21 08:02:11 PM PST 24
Peak memory 217216 kb
Host smart-bf2f53b5-3ab0-40a0-b49c-8ecb2d8cd93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828583569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_byte_transfer.1828583569
Directory /workspace/25.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3262770179
Short name T1536
Test name
Test status
Simulation time 187515770 ps
CPU time 3.25 seconds
Started Jan 21 08:02:17 PM PST 24
Finished Jan 21 08:02:25 PM PST 24
Peak memory 238300 kb
Host smart-1717f762-529b-4419-96d5-84bce1df2eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262770179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3262770179
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.19280597
Short name T1494
Test name
Test status
Simulation time 60688096 ps
CPU time 0.81 seconds
Started Jan 21 08:02:07 PM PST 24
Finished Jan 21 08:02:09 PM PST 24
Peak memory 207016 kb
Host smart-c6c03406-5864-48d8-ae47-78e10e1b18f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19280597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.19280597
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_dummy_item_extra_dly.4273473849
Short name T1374
Test name
Test status
Simulation time 84010501904 ps
CPU time 242.24 seconds
Started Jan 21 08:02:08 PM PST 24
Finished Jan 21 08:06:13 PM PST 24
Peak memory 321364 kb
Host smart-df17cd26-60a4-4574-8f26-8f4d5604a7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273473849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_dummy_item_extra_dly.4273473849
Directory /workspace/25.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/25.spi_device_extreme_fifo_size.3313950447
Short name T712
Test name
Test status
Simulation time 139797449513 ps
CPU time 2156.05 seconds
Started Jan 21 08:02:08 PM PST 24
Finished Jan 21 08:38:06 PM PST 24
Peak memory 218352 kb
Host smart-2bf32099-e437-4ece-9cac-0859e616e563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313950447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_extreme_fifo_size.3313950447
Directory /workspace/25.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/25.spi_device_fifo_full.1004321850
Short name T1089
Test name
Test status
Simulation time 65975807500 ps
CPU time 585.6 seconds
Started Jan 21 08:02:05 PM PST 24
Finished Jan 21 08:11:53 PM PST 24
Peak memory 266532 kb
Host smart-ac0e698b-86ad-4494-a5df-990f186ba709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004321850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_full.1004321850
Directory /workspace/25.spi_device_fifo_full/latest

Test location /workspace/coverage/default/25.spi_device_fifo_underflow_overflow.661066571
Short name T1326
Test name
Test status
Simulation time 466103277457 ps
CPU time 661.89 seconds
Started Jan 21 08:02:12 PM PST 24
Finished Jan 21 08:13:15 PM PST 24
Peak memory 450032 kb
Host smart-c2e07de2-cb80-4740-b5e1-26fb15647883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661066571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_underflow_overfl
ow.661066571
Directory /workspace/25.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3007108164
Short name T237
Test name
Test status
Simulation time 83811599254 ps
CPU time 178.18 seconds
Started Jan 21 08:02:20 PM PST 24
Finished Jan 21 08:05:22 PM PST 24
Peak memory 250296 kb
Host smart-a70f23e1-ab1e-4176-b7c9-f256b08de730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007108164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3007108164
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3419790711
Short name T270
Test name
Test status
Simulation time 6675946019 ps
CPU time 71.54 seconds
Started Jan 21 08:02:19 PM PST 24
Finished Jan 21 08:03:34 PM PST 24
Peak memory 253056 kb
Host smart-be32d3da-41fe-47ca-bcfd-a2fde4b8648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419790711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3419790711
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.120472366
Short name T1617
Test name
Test status
Simulation time 270118802297 ps
CPU time 566.71 seconds
Started Jan 21 08:02:20 PM PST 24
Finished Jan 21 08:11:50 PM PST 24
Peak memory 270416 kb
Host smart-a9561a9b-454d-4a27-a496-7f1e892f3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120472366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.120472366
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2512920878
Short name T1659
Test name
Test status
Simulation time 6625742478 ps
CPU time 20.56 seconds
Started Jan 21 08:02:24 PM PST 24
Finished Jan 21 08:02:48 PM PST 24
Peak memory 237128 kb
Host smart-7c9a5814-5a5b-4458-ae53-0b4b260c0db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512920878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2512920878
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2046523199
Short name T823
Test name
Test status
Simulation time 667906262 ps
CPU time 4.02 seconds
Started Jan 21 08:02:24 PM PST 24
Finished Jan 21 08:02:31 PM PST 24
Peak memory 233940 kb
Host smart-6ace369f-2570-4090-b701-c77845629a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046523199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2046523199
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intr.1587337162
Short name T1153
Test name
Test status
Simulation time 2624631171 ps
CPU time 15.52 seconds
Started Jan 21 08:02:04 PM PST 24
Finished Jan 21 08:02:22 PM PST 24
Peak memory 217268 kb
Host smart-29ac5637-9dcd-4068-b926-4d34ccc4a301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587337162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intr.1587337162
Directory /workspace/25.spi_device_intr/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.880981957
Short name T73
Test name
Test status
Simulation time 4930818367 ps
CPU time 16.2 seconds
Started Jan 21 08:02:19 PM PST 24
Finished Jan 21 08:02:39 PM PST 24
Peak memory 242044 kb
Host smart-f0ca9f45-106f-4668-99f6-6a05b313c2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880981957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.880981957
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1625884941
Short name T289
Test name
Test status
Simulation time 12439046260 ps
CPU time 25.78 seconds
Started Jan 21 08:02:19 PM PST 24
Finished Jan 21 08:02:48 PM PST 24
Peak memory 242044 kb
Host smart-c36de668-fd73-4f5b-8f85-50cdd1dea91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625884941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1625884941
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_perf.2196398554
Short name T581
Test name
Test status
Simulation time 19141781166 ps
CPU time 679.9 seconds
Started Jan 21 08:02:04 PM PST 24
Finished Jan 21 08:13:25 PM PST 24
Peak memory 254272 kb
Host smart-c7e04199-7077-44c5-8da8-c3a30540204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196398554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_perf.2196398554
Directory /workspace/25.spi_device_perf/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1759287852
Short name T1492
Test name
Test status
Simulation time 100293310 ps
CPU time 3.98 seconds
Started Jan 21 08:02:19 PM PST 24
Finished Jan 21 08:02:26 PM PST 24
Peak memory 234868 kb
Host smart-d92a3655-4db3-43eb-bb6d-f99ac82b0922
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1759287852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1759287852
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_rx_async_fifo_reset.2671620339
Short name T829
Test name
Test status
Simulation time 20565988 ps
CPU time 0.92 seconds
Started Jan 21 08:02:20 PM PST 24
Finished Jan 21 08:02:24 PM PST 24
Peak memory 208832 kb
Host smart-bb2177bf-303c-4a8d-b3d1-7c5d88a9a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671620339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_async_fifo_reset.2671620339
Directory /workspace/25.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_rx_timeout.1589537101
Short name T132
Test name
Test status
Simulation time 2373717661 ps
CPU time 5.56 seconds
Started Jan 21 08:02:12 PM PST 24
Finished Jan 21 08:02:20 PM PST 24
Peak memory 217264 kb
Host smart-7f3d0032-99dc-498a-ab7a-379e5d90d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589537101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_timeout.1589537101
Directory /workspace/25.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/25.spi_device_smoke.3008535156
Short name T1766
Test name
Test status
Simulation time 88280617 ps
CPU time 1.07 seconds
Started Jan 21 08:01:55 PM PST 24
Finished Jan 21 08:01:58 PM PST 24
Peak memory 208404 kb
Host smart-f9c89a4b-ffbf-4f06-8a0d-39d0ce3a8f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008535156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_smoke.3008535156
Directory /workspace/25.spi_device_smoke/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1609911042
Short name T347
Test name
Test status
Simulation time 223837746943 ps
CPU time 795.35 seconds
Started Jan 21 08:02:20 PM PST 24
Finished Jan 21 08:15:39 PM PST 24
Peak memory 304960 kb
Host smart-bd49295f-8e34-4fca-bc1f-9142c4bb4d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609911042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1609911042
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1877035713
Short name T595
Test name
Test status
Simulation time 15085020338 ps
CPU time 11.23 seconds
Started Jan 21 08:02:12 PM PST 24
Finished Jan 21 08:02:25 PM PST 24
Peak memory 217456 kb
Host smart-db05e0ee-f65c-4660-b2c0-5b3e5dd00fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877035713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1877035713
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3050451350
Short name T1541
Test name
Test status
Simulation time 1527601652 ps
CPU time 9.06 seconds
Started Jan 21 08:02:09 PM PST 24
Finished Jan 21 08:02:21 PM PST 24
Peak memory 217144 kb
Host smart-f223f3b6-5535-4d2c-93a2-fb228d9bb465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050451350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3050451350
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.845958037
Short name T726
Test name
Test status
Simulation time 24292852 ps
CPU time 1.01 seconds
Started Jan 21 08:02:20 PM PST 24
Finished Jan 21 08:02:24 PM PST 24
Peak memory 208336 kb
Host smart-e3d0d84a-fcba-4cb6-80d6-8ed49247bbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845958037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.845958037
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2603552152
Short name T776
Test name
Test status
Simulation time 144461542 ps
CPU time 0.89 seconds
Started Jan 21 08:02:19 PM PST 24
Finished Jan 21 08:02:24 PM PST 24
Peak memory 207252 kb
Host smart-ae8ddd7f-a574-4cf3-901e-faea02c5a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603552152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2603552152
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tx_async_fifo_reset.2211585111
Short name T1180
Test name
Test status
Simulation time 28558244 ps
CPU time 0.8 seconds
Started Jan 21 08:02:08 PM PST 24
Finished Jan 21 08:02:12 PM PST 24
Peak memory 207672 kb
Host smart-d9224392-947a-4be3-abfd-02103bee693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211585111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tx_async_fifo_reset.2211585111
Directory /workspace/25.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_txrx.1270201838
Short name T1764
Test name
Test status
Simulation time 47257660469 ps
CPU time 673.88 seconds
Started Jan 21 08:02:07 PM PST 24
Finished Jan 21 08:13:22 PM PST 24
Peak memory 305296 kb
Host smart-6b8cb678-62e9-47c9-899c-e2496d173b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270201838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_txrx.1270201838
Directory /workspace/25.spi_device_txrx/latest

Test location /workspace/coverage/default/25.spi_device_upload.1220799785
Short name T1453
Test name
Test status
Simulation time 6982640038 ps
CPU time 6.76 seconds
Started Jan 21 08:02:21 PM PST 24
Finished Jan 21 08:02:31 PM PST 24
Peak memory 220396 kb
Host smart-29f9bfe4-18fc-4316-9f92-4cd5dfacf433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220799785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1220799785
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_abort.2914422253
Short name T1477
Test name
Test status
Simulation time 16216800 ps
CPU time 0.76 seconds
Started Jan 21 08:02:43 PM PST 24
Finished Jan 21 08:02:45 PM PST 24
Peak memory 207120 kb
Host smart-4fe53620-08aa-4761-bf01-fb06987f1ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914422253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_abort.2914422253
Directory /workspace/26.spi_device_abort/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1347667321
Short name T1755
Test name
Test status
Simulation time 17128374 ps
CPU time 0.74 seconds
Started Jan 21 08:02:54 PM PST 24
Finished Jan 21 08:03:26 PM PST 24
Peak memory 206980 kb
Host smart-487cd1d8-14f7-4d85-8eb9-4aaf5a860d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347667321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1347667321
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_byte_transfer.670869350
Short name T1737
Test name
Test status
Simulation time 474959663 ps
CPU time 2.94 seconds
Started Jan 21 08:02:29 PM PST 24
Finished Jan 21 08:02:34 PM PST 24
Peak memory 217224 kb
Host smart-25fb9b54-447b-4a22-9a27-6a883ec75f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670869350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_byte_transfer.670869350
Directory /workspace/26.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2073585083
Short name T949
Test name
Test status
Simulation time 10823493362 ps
CPU time 11.05 seconds
Started Jan 21 08:02:40 PM PST 24
Finished Jan 21 08:02:53 PM PST 24
Peak memory 239260 kb
Host smart-d5ef1be6-9fff-48c5-90f8-b2dc8a45a2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073585083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2073585083
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.45466828
Short name T1499
Test name
Test status
Simulation time 42972672 ps
CPU time 0.77 seconds
Started Jan 21 08:02:34 PM PST 24
Finished Jan 21 08:02:36 PM PST 24
Peak memory 207024 kb
Host smart-bb04e265-8e00-49bb-8994-121204968d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45466828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.45466828
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_dummy_item_extra_dly.3134270014
Short name T504
Test name
Test status
Simulation time 65706387446 ps
CPU time 740.1 seconds
Started Jan 21 08:02:28 PM PST 24
Finished Jan 21 08:14:50 PM PST 24
Peak memory 251088 kb
Host smart-bdb63f21-abb0-4576-a564-658772573ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134270014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_dummy_item_extra_dly.3134270014
Directory /workspace/26.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/26.spi_device_extreme_fifo_size.1007772205
Short name T1547
Test name
Test status
Simulation time 52263199966 ps
CPU time 2571.04 seconds
Started Jan 21 08:02:32 PM PST 24
Finished Jan 21 08:45:25 PM PST 24
Peak memory 218444 kb
Host smart-ac601dd1-05b7-4030-a436-377eca0b713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007772205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_extreme_fifo_size.1007772205
Directory /workspace/26.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/26.spi_device_fifo_full.931553021
Short name T1504
Test name
Test status
Simulation time 59574951672 ps
CPU time 895.46 seconds
Started Jan 21 08:02:34 PM PST 24
Finished Jan 21 08:17:31 PM PST 24
Peak memory 264096 kb
Host smart-db2a30a0-9f68-433a-b127-c0776d2419af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931553021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_full.931553021
Directory /workspace/26.spi_device_fifo_full/latest

Test location /workspace/coverage/default/26.spi_device_fifo_underflow_overflow.2840780001
Short name T1664
Test name
Test status
Simulation time 30831337817 ps
CPU time 546.78 seconds
Started Jan 21 08:02:34 PM PST 24
Finished Jan 21 08:11:43 PM PST 24
Peak memory 452280 kb
Host smart-38ed6295-6022-4332-a602-0463da7a926d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840780001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_underflow_overf
low.2840780001
Directory /workspace/26.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3753532933
Short name T1174
Test name
Test status
Simulation time 7333747552 ps
CPU time 34.42 seconds
Started Jan 21 08:02:42 PM PST 24
Finished Jan 21 08:03:18 PM PST 24
Peak memory 234844 kb
Host smart-7a83d3cb-7a89-4c1d-b99e-f46d9eabfb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753532933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3753532933
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1543226400
Short name T1730
Test name
Test status
Simulation time 2013913871 ps
CPU time 9.15 seconds
Started Jan 21 08:02:43 PM PST 24
Finished Jan 21 08:02:53 PM PST 24
Peak memory 239856 kb
Host smart-8c18ebb4-c4e8-47e0-a23d-883f34e8ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543226400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1543226400
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intr.988898222
Short name T1696
Test name
Test status
Simulation time 5474867463 ps
CPU time 32.03 seconds
Started Jan 21 08:02:34 PM PST 24
Finished Jan 21 08:03:07 PM PST 24
Peak memory 225488 kb
Host smart-43964f33-d0a2-4773-9c0c-ec50f131e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988898222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intr.988898222
Directory /workspace/26.spi_device_intr/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1557288672
Short name T23
Test name
Test status
Simulation time 787176556 ps
CPU time 9.19 seconds
Started Jan 21 08:02:47 PM PST 24
Finished Jan 21 08:03:32 PM PST 24
Peak memory 221192 kb
Host smart-ee8c92b0-7f26-49dd-9c78-ebb6a1e3eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557288672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1557288672
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.578992886
Short name T259
Test name
Test status
Simulation time 7403327451 ps
CPU time 12.87 seconds
Started Jan 21 08:02:48 PM PST 24
Finished Jan 21 08:03:38 PM PST 24
Peak memory 248600 kb
Host smart-ab723122-5c6c-4840-a815-89b820f9e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578992886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.578992886
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1956141764
Short name T1623
Test name
Test status
Simulation time 51802949326 ps
CPU time 25.72 seconds
Started Jan 21 08:02:48 PM PST 24
Finished Jan 21 08:03:51 PM PST 24
Peak memory 219476 kb
Host smart-65132973-de31-4e18-8f08-fda72cc5f462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956141764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1956141764
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_perf.1305804246
Short name T168
Test name
Test status
Simulation time 20362380326 ps
CPU time 299.3 seconds
Started Jan 21 08:02:32 PM PST 24
Finished Jan 21 08:07:34 PM PST 24
Peak memory 269708 kb
Host smart-87bd1e4e-298d-4072-9023-d29d72cfb98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305804246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_perf.1305804246
Directory /workspace/26.spi_device_perf/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2605925461
Short name T741
Test name
Test status
Simulation time 16507566144 ps
CPU time 6.45 seconds
Started Jan 21 08:02:49 PM PST 24
Finished Jan 21 08:03:32 PM PST 24
Peak memory 221732 kb
Host smart-868999f5-13c0-451c-b389-01f2cd0a99cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2605925461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2605925461
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_rx_async_fifo_reset.1918211291
Short name T98
Test name
Test status
Simulation time 149709839 ps
CPU time 0.91 seconds
Started Jan 21 08:02:41 PM PST 24
Finished Jan 21 08:02:44 PM PST 24
Peak memory 208836 kb
Host smart-dfb51234-a574-42f7-aaae-05a655991ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918211291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_async_fifo_reset.1918211291
Directory /workspace/26.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_rx_timeout.3285109861
Short name T133
Test name
Test status
Simulation time 570479131 ps
CPU time 5.22 seconds
Started Jan 21 08:02:31 PM PST 24
Finished Jan 21 08:02:37 PM PST 24
Peak memory 217212 kb
Host smart-f6019bdd-1dad-40d8-bd5e-4eaf4e35137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285109861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_timeout.3285109861
Directory /workspace/26.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/26.spi_device_smoke.768861625
Short name T1450
Test name
Test status
Simulation time 178033711 ps
CPU time 1.29 seconds
Started Jan 21 08:02:33 PM PST 24
Finished Jan 21 08:02:36 PM PST 24
Peak memory 217172 kb
Host smart-4a37e790-52b1-49f4-a272-9a4326257a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768861625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_smoke.768861625
Directory /workspace/26.spi_device_smoke/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4122208598
Short name T373
Test name
Test status
Simulation time 4026134883 ps
CPU time 58.11 seconds
Started Jan 21 08:02:41 PM PST 24
Finished Jan 21 08:03:41 PM PST 24
Peak memory 217636 kb
Host smart-24c3ad8b-8a61-449a-9599-04ae0ffeac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122208598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4122208598
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.382020518
Short name T612
Test name
Test status
Simulation time 6576183002 ps
CPU time 19.5 seconds
Started Jan 21 08:02:35 PM PST 24
Finished Jan 21 08:02:55 PM PST 24
Peak memory 217252 kb
Host smart-b97f76fd-b510-41f8-9264-5e4f065782e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382020518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.382020518
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2770012140
Short name T542
Test name
Test status
Simulation time 342589464 ps
CPU time 1.17 seconds
Started Jan 21 08:02:40 PM PST 24
Finished Jan 21 08:02:42 PM PST 24
Peak memory 208332 kb
Host smart-b0befd5f-cf26-4b3a-b81e-b64903e4d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770012140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2770012140
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.316268388
Short name T539
Test name
Test status
Simulation time 231705312 ps
CPU time 1.07 seconds
Started Jan 21 08:02:41 PM PST 24
Finished Jan 21 08:02:44 PM PST 24
Peak memory 208364 kb
Host smart-cfb0aacd-7cac-4e56-8854-aab7a364a3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316268388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.316268388
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tx_async_fifo_reset.964530464
Short name T1533
Test name
Test status
Simulation time 40416660 ps
CPU time 0.8 seconds
Started Jan 21 08:02:39 PM PST 24
Finished Jan 21 08:02:42 PM PST 24
Peak memory 207668 kb
Host smart-39b97491-9f4e-4289-9266-9bcf48e252e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964530464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tx_async_fifo_reset.964530464
Directory /workspace/26.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_txrx.1726620001
Short name T1134
Test name
Test status
Simulation time 360953029128 ps
CPU time 869.6 seconds
Started Jan 21 08:02:31 PM PST 24
Finished Jan 21 08:17:02 PM PST 24
Peak memory 319148 kb
Host smart-73d1a53c-bb72-44ce-bb4c-3af1e59d6046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726620001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_txrx.1726620001
Directory /workspace/26.spi_device_txrx/latest

Test location /workspace/coverage/default/26.spi_device_upload.3534701649
Short name T1070
Test name
Test status
Simulation time 9494651905 ps
CPU time 34.4 seconds
Started Jan 21 08:02:48 PM PST 24
Finished Jan 21 08:04:00 PM PST 24
Peak memory 225324 kb
Host smart-5d275116-9af4-4401-8b94-4d1981e2bf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534701649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3534701649
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_abort.1772911131
Short name T90
Test name
Test status
Simulation time 41345440 ps
CPU time 0.78 seconds
Started Jan 21 08:03:21 PM PST 24
Finished Jan 21 08:03:31 PM PST 24
Peak memory 207100 kb
Host smart-dc1aa656-f6df-40c0-8de2-d90cb5616e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772911131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_abort.1772911131
Directory /workspace/27.spi_device_abort/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3890721174
Short name T1388
Test name
Test status
Simulation time 40905896 ps
CPU time 0.76 seconds
Started Jan 21 08:03:22 PM PST 24
Finished Jan 21 08:03:31 PM PST 24
Peak memory 206928 kb
Host smart-43dd7194-003e-4996-bccb-117b907769db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890721174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3890721174
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_byte_transfer.968290773
Short name T1001
Test name
Test status
Simulation time 1247257277 ps
CPU time 3.32 seconds
Started Jan 21 08:02:56 PM PST 24
Finished Jan 21 08:03:29 PM PST 24
Peak memory 217176 kb
Host smart-e76d5744-e4a8-494f-8872-2c6d1493c06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968290773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_byte_transfer.968290773
Directory /workspace/27.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3421612176
Short name T919
Test name
Test status
Simulation time 760603585 ps
CPU time 4.16 seconds
Started Jan 21 08:03:20 PM PST 24
Finished Jan 21 08:03:34 PM PST 24
Peak memory 225544 kb
Host smart-9c21cc8f-3491-4524-bd03-ded8f6d1ca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421612176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3421612176
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2432986778
Short name T1724
Test name
Test status
Simulation time 17568601 ps
CPU time 0.8 seconds
Started Jan 21 08:02:59 PM PST 24
Finished Jan 21 08:03:26 PM PST 24
Peak memory 208048 kb
Host smart-049483ee-5a91-4dee-bcf9-3664239b3292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432986778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2432986778
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_dummy_item_extra_dly.1616088459
Short name T992
Test name
Test status
Simulation time 70246186466 ps
CPU time 1415.06 seconds
Started Jan 21 08:03:00 PM PST 24
Finished Jan 21 08:27:00 PM PST 24
Peak memory 303232 kb
Host smart-c5a97603-2c93-43e0-a671-23b3aa18705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616088459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_dummy_item_extra_dly.1616088459
Directory /workspace/27.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/27.spi_device_extreme_fifo_size.333449629
Short name T1590
Test name
Test status
Simulation time 223740038377 ps
CPU time 2338.63 seconds
Started Jan 21 08:02:57 PM PST 24
Finished Jan 21 08:42:24 PM PST 24
Peak memory 219828 kb
Host smart-6636498f-3f11-4be4-a163-0e36a26a056d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333449629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_extreme_fifo_size.333449629
Directory /workspace/27.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/27.spi_device_fifo_full.2213132295
Short name T924
Test name
Test status
Simulation time 152388782250 ps
CPU time 1195.82 seconds
Started Jan 21 08:02:48 PM PST 24
Finished Jan 21 08:23:22 PM PST 24
Peak memory 271412 kb
Host smart-b674fb6d-170d-44e5-9314-b25d8c1d8dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213132295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_full.2213132295
Directory /workspace/27.spi_device_fifo_full/latest

Test location /workspace/coverage/default/27.spi_device_fifo_underflow_overflow.3121893740
Short name T1133
Test name
Test status
Simulation time 95001390766 ps
CPU time 309.03 seconds
Started Jan 21 08:02:46 PM PST 24
Finished Jan 21 08:08:27 PM PST 24
Peak memory 359352 kb
Host smart-5366a177-e250-4620-b755-b36b8b658a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121893740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_underflow_overf
low.3121893740
Directory /workspace/27.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2858706388
Short name T355
Test name
Test status
Simulation time 91140895108 ps
CPU time 287.68 seconds
Started Jan 21 08:03:23 PM PST 24
Finished Jan 21 08:08:22 PM PST 24
Peak memory 274456 kb
Host smart-f9681c3c-23d1-464a-98b1-b7ddba69393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858706388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2858706388
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3295191399
Short name T364
Test name
Test status
Simulation time 327972292452 ps
CPU time 350.95 seconds
Started Jan 21 08:03:21 PM PST 24
Finished Jan 21 08:09:21 PM PST 24
Peak memory 270400 kb
Host smart-d6aaa3bd-3bcb-4e1b-aa49-4418a4e5cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295191399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3295191399
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4053922067
Short name T356
Test name
Test status
Simulation time 110055215386 ps
CPU time 268.19 seconds
Started Jan 21 08:03:18 PM PST 24
Finished Jan 21 08:07:57 PM PST 24
Peak memory 283156 kb
Host smart-84b0af15-ce3b-42dc-b5d3-278922584fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053922067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4053922067
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1203105771
Short name T1034
Test name
Test status
Simulation time 6339186803 ps
CPU time 37.91 seconds
Started Jan 21 08:03:26 PM PST 24
Finished Jan 21 08:04:14 PM PST 24
Peak memory 248120 kb
Host smart-12eaac4b-a57a-4f54-8e29-43df39fdf71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203105771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1203105771
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2884087917
Short name T957
Test name
Test status
Simulation time 4308422813 ps
CPU time 14.89 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:44 PM PST 24
Peak memory 240640 kb
Host smart-e56b55dc-08c6-4d26-8e8e-0ba2fe5c02b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884087917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2884087917
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intr.720385849
Short name T770
Test name
Test status
Simulation time 28455336685 ps
CPU time 62.18 seconds
Started Jan 21 08:02:56 PM PST 24
Finished Jan 21 08:04:27 PM PST 24
Peak memory 240776 kb
Host smart-19affa2d-cee6-4885-b544-bfe78eeea7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720385849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intr.720385849
Directory /workspace/27.spi_device_intr/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1994001899
Short name T1427
Test name
Test status
Simulation time 4426321525 ps
CPU time 20.25 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:50 PM PST 24
Peak memory 230956 kb
Host smart-5c301ab0-d8b1-4668-94f2-d633b5207bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994001899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1994001899
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3662773851
Short name T972
Test name
Test status
Simulation time 6692764098 ps
CPU time 6.97 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:36 PM PST 24
Peak memory 221124 kb
Host smart-150c096c-6cb3-4a2b-bfd2-8367a0f420dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662773851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3662773851
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.951984016
Short name T666
Test name
Test status
Simulation time 641128779 ps
CPU time 9.49 seconds
Started Jan 21 08:03:29 PM PST 24
Finished Jan 21 08:03:47 PM PST 24
Peak memory 232920 kb
Host smart-a0da5b7e-020d-4654-a1a9-7e586b28af6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951984016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.951984016
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_perf.2884282390
Short name T1401
Test name
Test status
Simulation time 57991363829 ps
CPU time 392.72 seconds
Started Jan 21 08:02:59 PM PST 24
Finished Jan 21 08:09:58 PM PST 24
Peak memory 266048 kb
Host smart-ae758c95-6a7c-46b5-8510-dc7ae1d63fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884282390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_perf.2884282390
Directory /workspace/27.spi_device_perf/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2773393127
Short name T1640
Test name
Test status
Simulation time 2945933837 ps
CPU time 5.54 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:34 PM PST 24
Peak memory 235056 kb
Host smart-61ca1367-79ad-4ec5-8628-162cb96f4428
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2773393127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2773393127
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_rx_async_fifo_reset.4240623057
Short name T1015
Test name
Test status
Simulation time 54374824 ps
CPU time 0.89 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:31 PM PST 24
Peak memory 208832 kb
Host smart-b0b8f1e4-502c-48e1-9a30-a46e321413a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240623057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_async_fifo_reset.4240623057
Directory /workspace/27.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_rx_timeout.586001668
Short name T1324
Test name
Test status
Simulation time 3969118684 ps
CPU time 7.51 seconds
Started Jan 21 08:02:58 PM PST 24
Finished Jan 21 08:03:33 PM PST 24
Peak memory 217272 kb
Host smart-4fce73f2-b0ff-4ae6-b0e1-34e27f1007c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586001668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_timeout.586001668
Directory /workspace/27.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/27.spi_device_smoke.2826582169
Short name T8
Test name
Test status
Simulation time 112533885 ps
CPU time 1.12 seconds
Started Jan 21 08:02:49 PM PST 24
Finished Jan 21 08:03:27 PM PST 24
Peak memory 208524 kb
Host smart-7aa4ccc4-2fda-46ad-82a0-4e6d911f8eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826582169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_smoke.2826582169
Directory /workspace/27.spi_device_smoke/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.154182279
Short name T154
Test name
Test status
Simulation time 51266650840 ps
CPU time 825.2 seconds
Started Jan 21 08:03:18 PM PST 24
Finished Jan 21 08:17:14 PM PST 24
Peak memory 415100 kb
Host smart-3e4e4b21-6b23-4dee-a25f-8bf91e91a440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154182279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.154182279
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1861656445
Short name T1201
Test name
Test status
Simulation time 90715265563 ps
CPU time 49.81 seconds
Started Jan 21 08:02:57 PM PST 24
Finished Jan 21 08:04:15 PM PST 24
Peak memory 217548 kb
Host smart-6397cba2-ca75-4bf3-964b-bf02b1570d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861656445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1861656445
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3223273545
Short name T1435
Test name
Test status
Simulation time 1199597852 ps
CPU time 3.52 seconds
Started Jan 21 08:02:59 PM PST 24
Finished Jan 21 08:03:29 PM PST 24
Peak memory 217104 kb
Host smart-31b59b1d-985c-4e6b-9a6f-b69a94285e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223273545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3223273545
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.274244746
Short name T1252
Test name
Test status
Simulation time 56194376 ps
CPU time 1.14 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:30 PM PST 24
Peak memory 208424 kb
Host smart-be2ffd7c-4f05-47ae-bc85-a1b0b4a05787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274244746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.274244746
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4207336859
Short name T1235
Test name
Test status
Simulation time 842257472 ps
CPU time 0.96 seconds
Started Jan 21 08:03:26 PM PST 24
Finished Jan 21 08:03:36 PM PST 24
Peak memory 207276 kb
Host smart-901f392e-48ad-4920-9917-72026df8e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207336859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4207336859
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tx_async_fifo_reset.1806156616
Short name T1236
Test name
Test status
Simulation time 16487989 ps
CPU time 0.77 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:30 PM PST 24
Peak memory 207728 kb
Host smart-5602f82a-6469-438a-ac47-9e5bc06262b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806156616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tx_async_fifo_reset.1806156616
Directory /workspace/27.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_txrx.549245322
Short name T1083
Test name
Test status
Simulation time 305285140644 ps
CPU time 1303.79 seconds
Started Jan 21 08:02:51 PM PST 24
Finished Jan 21 08:25:09 PM PST 24
Peak memory 289372 kb
Host smart-bc07b8e4-59e6-44e1-bd58-10f5724f33bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549245322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_txrx.549245322
Directory /workspace/27.spi_device_txrx/latest

Test location /workspace/coverage/default/27.spi_device_upload.3684496646
Short name T272
Test name
Test status
Simulation time 3997485703 ps
CPU time 13.99 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:43 PM PST 24
Peak memory 225796 kb
Host smart-31f13398-b85f-4628-bb94-435432001b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684496646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3684496646
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_abort.587831951
Short name T771
Test name
Test status
Simulation time 15396144 ps
CPU time 0.78 seconds
Started Jan 21 08:03:26 PM PST 24
Finished Jan 21 08:03:36 PM PST 24
Peak memory 207100 kb
Host smart-6671b82b-18aa-4d8a-9313-b6715713d478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587831951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_abort.587831951
Directory /workspace/28.spi_device_abort/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2329223187
Short name T997
Test name
Test status
Simulation time 47637145 ps
CPU time 0.74 seconds
Started Jan 21 08:03:56 PM PST 24
Finished Jan 21 08:03:59 PM PST 24
Peak memory 206944 kb
Host smart-8d7754b4-9725-4877-9a4a-c07f97a5159b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329223187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2329223187
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_bit_transfer.1573075314
Short name T1265
Test name
Test status
Simulation time 2286239094 ps
CPU time 2.45 seconds
Started Jan 21 08:03:25 PM PST 24
Finished Jan 21 08:03:37 PM PST 24
Peak memory 217252 kb
Host smart-eacf955b-ad5c-4cd2-bc61-8cb4fd667cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573075314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_bit_transfer.1573075314
Directory /workspace/28.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/28.spi_device_byte_transfer.2160239924
Short name T1051
Test name
Test status
Simulation time 126948549 ps
CPU time 2.42 seconds
Started Jan 21 08:03:26 PM PST 24
Finished Jan 21 08:03:38 PM PST 24
Peak memory 217228 kb
Host smart-c6b4d158-217b-4fd9-81ba-67a0d3e4b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160239924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_byte_transfer.2160239924
Directory /workspace/28.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.4160117989
Short name T714
Test name
Test status
Simulation time 19337223507 ps
CPU time 15.54 seconds
Started Jan 21 08:03:34 PM PST 24
Finished Jan 21 08:04:05 PM PST 24
Peak memory 225624 kb
Host smart-7a57f08c-1b0a-4fe3-bfb1-89412f930586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160117989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4160117989
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2415405528
Short name T1459
Test name
Test status
Simulation time 67704595 ps
CPU time 0.8 seconds
Started Jan 21 08:03:26 PM PST 24
Finished Jan 21 08:03:36 PM PST 24
Peak memory 208096 kb
Host smart-85436bbc-9384-4a09-8dab-760da506be58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415405528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2415405528
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_dummy_item_extra_dly.2922675493
Short name T299
Test name
Test status
Simulation time 66127777750 ps
CPU time 1257.51 seconds
Started Jan 21 08:03:21 PM PST 24
Finished Jan 21 08:24:28 PM PST 24
Peak memory 304372 kb
Host smart-74050184-2dca-4efd-9f40-443a3ad9fb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922675493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_dummy_item_extra_dly.2922675493
Directory /workspace/28.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/28.spi_device_extreme_fifo_size.2063221737
Short name T1295
Test name
Test status
Simulation time 73242987320 ps
CPU time 867.89 seconds
Started Jan 21 08:03:21 PM PST 24
Finished Jan 21 08:17:58 PM PST 24
Peak memory 219444 kb
Host smart-636d8f9f-2598-4564-8c4a-6a436a5ed231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063221737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_extreme_fifo_size.2063221737
Directory /workspace/28.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/28.spi_device_fifo_full.3055420532
Short name T1111
Test name
Test status
Simulation time 43371514652 ps
CPU time 1041.82 seconds
Started Jan 21 08:03:24 PM PST 24
Finished Jan 21 08:20:56 PM PST 24
Peak memory 292548 kb
Host smart-8ad6a3ce-dba7-4ccf-8673-b3a294206674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055420532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_full.3055420532
Directory /workspace/28.spi_device_fifo_full/latest

Test location /workspace/coverage/default/28.spi_device_fifo_underflow_overflow.1374224272
Short name T1701
Test name
Test status
Simulation time 35346145199 ps
CPU time 224.07 seconds
Started Jan 21 08:03:21 PM PST 24
Finished Jan 21 08:07:14 PM PST 24
Peak memory 348424 kb
Host smart-d4625a43-70c4-4feb-9b76-1a9a52704887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374224272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_underflow_overf
low.1374224272
Directory /workspace/28.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2936443735
Short name T7
Test name
Test status
Simulation time 4438171134 ps
CPU time 92.86 seconds
Started Jan 21 08:03:51 PM PST 24
Finished Jan 21 08:05:27 PM PST 24
Peak memory 274100 kb
Host smart-c4483acf-1cb5-4f3e-91ab-b30636b153f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936443735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2936443735
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2684927904
Short name T349
Test name
Test status
Simulation time 392216577395 ps
CPU time 740.54 seconds
Started Jan 21 08:03:58 PM PST 24
Finished Jan 21 08:16:20 PM PST 24
Peak memory 284528 kb
Host smart-5192e118-15b6-4b98-8d3a-8276d66472b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684927904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2684927904
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3095412371
Short name T1004
Test name
Test status
Simulation time 7404253821 ps
CPU time 79.42 seconds
Started Jan 21 08:04:01 PM PST 24
Finished Jan 21 08:05:22 PM PST 24
Peak memory 266628 kb
Host smart-e73065d8-47da-4695-b019-4c2ecef3712e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095412371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3095412371
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2379663319
Short name T371
Test name
Test status
Simulation time 2009245480 ps
CPU time 11.78 seconds
Started Jan 21 08:03:38 PM PST 24
Finished Jan 21 08:04:04 PM PST 24
Peak memory 225052 kb
Host smart-f5a21013-a282-4aaa-afbc-ec9f4e2933c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379663319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2379663319
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1157603585
Short name T809
Test name
Test status
Simulation time 2123805449 ps
CPU time 7.95 seconds
Started Jan 21 08:03:36 PM PST 24
Finished Jan 21 08:03:59 PM PST 24
Peak memory 239180 kb
Host smart-0d893877-2de2-48c0-ab83-fcff0b72e5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157603585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1157603585
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intr.3458904979
Short name T125
Test name
Test status
Simulation time 13232402545 ps
CPU time 31.27 seconds
Started Jan 21 08:03:23 PM PST 24
Finished Jan 21 08:04:05 PM PST 24
Peak memory 232992 kb
Host smart-a4c4f2b5-f9de-47eb-afbf-174be07a5e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458904979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intr.3458904979
Directory /workspace/28.spi_device_intr/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2452276687
Short name T813
Test name
Test status
Simulation time 486805804 ps
CPU time 3.69 seconds
Started Jan 21 08:03:36 PM PST 24
Finished Jan 21 08:03:54 PM PST 24
Peak memory 226732 kb
Host smart-276e6cc5-2f8a-4ca1-93e1-239458ab1060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452276687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2452276687
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1686037642
Short name T323
Test name
Test status
Simulation time 75048974360 ps
CPU time 50.2 seconds
Started Jan 21 08:03:33 PM PST 24
Finished Jan 21 08:04:38 PM PST 24
Peak memory 241080 kb
Host smart-d6c8dc4f-e81e-4558-b176-3f5d22709691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686037642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1686037642
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2898524310
Short name T1583
Test name
Test status
Simulation time 7011522623 ps
CPU time 25.81 seconds
Started Jan 21 08:03:38 PM PST 24
Finished Jan 21 08:04:18 PM PST 24
Peak memory 250304 kb
Host smart-9959912c-ec01-4f9b-8232-93d5998ce124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898524310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2898524310
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_perf.3425430328
Short name T877
Test name
Test status
Simulation time 298312923640 ps
CPU time 327.73 seconds
Started Jan 21 08:03:23 PM PST 24
Finished Jan 21 08:09:02 PM PST 24
Peak memory 233360 kb
Host smart-50d3aa7f-ea69-4b7d-9c3e-4732ac11ff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425430328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_perf.3425430328
Directory /workspace/28.spi_device_perf/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1088438171
Short name T882
Test name
Test status
Simulation time 488408166 ps
CPU time 5.03 seconds
Started Jan 21 08:03:50 PM PST 24
Finished Jan 21 08:03:59 PM PST 24
Peak memory 236324 kb
Host smart-d57057cf-2ef0-4eb9-b9bc-9c80acb9cf3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1088438171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1088438171
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_rx_async_fifo_reset.2288503295
Short name T1551
Test name
Test status
Simulation time 162882919 ps
CPU time 0.89 seconds
Started Jan 21 08:03:24 PM PST 24
Finished Jan 21 08:03:35 PM PST 24
Peak memory 208796 kb
Host smart-65459795-6584-4607-91f6-8e318de35a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288503295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_async_fifo_reset.2288503295
Directory /workspace/28.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_rx_timeout.2551185180
Short name T520
Test name
Test status
Simulation time 2179409045 ps
CPU time 6.35 seconds
Started Jan 21 08:03:22 PM PST 24
Finished Jan 21 08:03:39 PM PST 24
Peak memory 217308 kb
Host smart-4a1a6adb-ec36-4eb2-abc6-b24de795a999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551185180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_timeout.2551185180
Directory /workspace/28.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/28.spi_device_smoke.2532813017
Short name T1644
Test name
Test status
Simulation time 119699468 ps
CPU time 1.19 seconds
Started Jan 21 08:03:19 PM PST 24
Finished Jan 21 08:03:30 PM PST 24
Peak memory 216948 kb
Host smart-d8fc23d8-28ba-4ec4-9d77-ff8c094f9d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532813017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_smoke.2532813017
Directory /workspace/28.spi_device_smoke/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2017723143
Short name T122
Test name
Test status
Simulation time 389114174 ps
CPU time 2.72 seconds
Started Jan 21 08:03:28 PM PST 24
Finished Jan 21 08:03:40 PM PST 24
Peak memory 219796 kb
Host smart-8975f091-a1bb-46fd-a4a4-78dcc6130faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017723143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2017723143
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1636592759
Short name T1758
Test name
Test status
Simulation time 55424282038 ps
CPU time 26.01 seconds
Started Jan 21 08:03:23 PM PST 24
Finished Jan 21 08:04:00 PM PST 24
Peak memory 217296 kb
Host smart-ee124a88-94b8-4f30-9665-29cd5fd28097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636592759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1636592759
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2914180754
Short name T772
Test name
Test status
Simulation time 74567450 ps
CPU time 2.27 seconds
Started Jan 21 08:03:35 PM PST 24
Finished Jan 21 08:03:52 PM PST 24
Peak memory 209148 kb
Host smart-4da0c934-0391-479e-9f47-f14f01167109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914180754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2914180754
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2228975342
Short name T1229
Test name
Test status
Simulation time 299816836 ps
CPU time 1.23 seconds
Started Jan 21 08:03:33 PM PST 24
Finished Jan 21 08:03:49 PM PST 24
Peak memory 208348 kb
Host smart-a549b9cd-0980-455e-84ad-085695827d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228975342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2228975342
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tx_async_fifo_reset.1872940311
Short name T1422
Test name
Test status
Simulation time 15436207 ps
CPU time 0.81 seconds
Started Jan 21 08:03:26 PM PST 24
Finished Jan 21 08:03:36 PM PST 24
Peak memory 207680 kb
Host smart-c73e58db-61ae-4114-a280-7cab8605d82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872940311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tx_async_fifo_reset.1872940311
Directory /workspace/28.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_txrx.3576564032
Short name T1673
Test name
Test status
Simulation time 61101176771 ps
CPU time 1116.71 seconds
Started Jan 21 08:03:18 PM PST 24
Finished Jan 21 08:22:05 PM PST 24
Peak memory 270068 kb
Host smart-1cca4745-751e-487c-9f7a-b7cbabd866b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576564032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_txrx.3576564032
Directory /workspace/28.spi_device_txrx/latest

Test location /workspace/coverage/default/28.spi_device_upload.2477070752
Short name T1497
Test name
Test status
Simulation time 7223247104 ps
CPU time 14.04 seconds
Started Jan 21 08:03:32 PM PST 24
Finished Jan 21 08:04:00 PM PST 24
Peak memory 234888 kb
Host smart-7e5895ce-5be7-4ab5-bbe9-2d24fd129cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477070752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2477070752
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_abort.2961569861
Short name T93
Test name
Test status
Simulation time 34610463 ps
CPU time 0.79 seconds
Started Jan 21 08:04:44 PM PST 24
Finished Jan 21 08:04:46 PM PST 24
Peak memory 207052 kb
Host smart-839a7ca7-646c-462e-8e4a-bec868c8f739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961569861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_abort.2961569861
Directory /workspace/29.spi_device_abort/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.940900319
Short name T102
Test name
Test status
Simulation time 19013394 ps
CPU time 0.74 seconds
Started Jan 21 08:04:48 PM PST 24
Finished Jan 21 08:04:50 PM PST 24
Peak memory 206980 kb
Host smart-660ed508-e64b-497e-a7cb-77d047bca02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940900319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.940900319
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_bit_transfer.4069228762
Short name T644
Test name
Test status
Simulation time 793095042 ps
CPU time 2.46 seconds
Started Jan 21 08:04:17 PM PST 24
Finished Jan 21 08:04:23 PM PST 24
Peak memory 217244 kb
Host smart-91ec60df-0663-45f0-9a9d-eba18c2c145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069228762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_bit_transfer.4069228762
Directory /workspace/29.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/29.spi_device_byte_transfer.271584275
Short name T1241
Test name
Test status
Simulation time 140609419 ps
CPU time 2.89 seconds
Started Jan 21 08:04:11 PM PST 24
Finished Jan 21 08:04:16 PM PST 24
Peak memory 217260 kb
Host smart-f0d89661-abba-44a6-85c5-3c3e7c08520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271584275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_byte_transfer.271584275
Directory /workspace/29.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1899376455
Short name T847
Test name
Test status
Simulation time 1545293321 ps
CPU time 7.79 seconds
Started Jan 21 08:04:39 PM PST 24
Finished Jan 21 08:04:48 PM PST 24
Peak memory 225532 kb
Host smart-a02404a2-e3fb-43bc-a04b-a32360cf5e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899376455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1899376455
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3752378386
Short name T525
Test name
Test status
Simulation time 71448614 ps
CPU time 0.8 seconds
Started Jan 21 08:04:12 PM PST 24
Finished Jan 21 08:04:19 PM PST 24
Peak memory 208044 kb
Host smart-78ca2331-5f5c-4ff2-94a5-dc76a0e3ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752378386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3752378386
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_dummy_item_extra_dly.3703881404
Short name T1049
Test name
Test status
Simulation time 43335028742 ps
CPU time 1053.76 seconds
Started Jan 21 08:03:56 PM PST 24
Finished Jan 21 08:21:31 PM PST 24
Peak memory 250096 kb
Host smart-21eabad1-a95d-4967-92db-e16174fd2028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703881404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_dummy_item_extra_dly.3703881404
Directory /workspace/29.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/29.spi_device_extreme_fifo_size.4025161064
Short name T1549
Test name
Test status
Simulation time 42180853348 ps
CPU time 760.72 seconds
Started Jan 21 08:03:59 PM PST 24
Finished Jan 21 08:16:43 PM PST 24
Peak memory 225520 kb
Host smart-46f45d83-974f-4d09-bac3-21d8aa4623e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025161064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_extreme_fifo_size.4025161064
Directory /workspace/29.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/29.spi_device_fifo_full.889820528
Short name T1394
Test name
Test status
Simulation time 90204284973 ps
CPU time 533.23 seconds
Started Jan 21 08:03:56 PM PST 24
Finished Jan 21 08:12:51 PM PST 24
Peak memory 257580 kb
Host smart-1dea03d0-3ca1-41ac-94f3-c067bdeede5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889820528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_full.889820528
Directory /workspace/29.spi_device_fifo_full/latest

Test location /workspace/coverage/default/29.spi_device_fifo_underflow_overflow.517773665
Short name T1694
Test name
Test status
Simulation time 15507976086 ps
CPU time 193.07 seconds
Started Jan 21 08:03:57 PM PST 24
Finished Jan 21 08:07:12 PM PST 24
Peak memory 322708 kb
Host smart-0cd7f12c-0fb0-428d-8c46-d8800237d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517773665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_underflow_overfl
ow.517773665
Directory /workspace/29.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2893714753
Short name T1729
Test name
Test status
Simulation time 151760685248 ps
CPU time 300.96 seconds
Started Jan 21 08:04:47 PM PST 24
Finished Jan 21 08:09:49 PM PST 24
Peak memory 251396 kb
Host smart-9fd4b188-2e57-4b59-b01b-31dedc182b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893714753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2893714753
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1298795077
Short name T236
Test name
Test status
Simulation time 245013768777 ps
CPU time 466.05 seconds
Started Jan 21 08:04:48 PM PST 24
Finished Jan 21 08:12:35 PM PST 24
Peak memory 266660 kb
Host smart-a01f5b76-6586-431d-a7f4-2a953aff05f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298795077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1298795077
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.211461400
Short name T1451
Test name
Test status
Simulation time 835393078 ps
CPU time 19.18 seconds
Started Jan 21 08:04:37 PM PST 24
Finished Jan 21 08:04:58 PM PST 24
Peak memory 232132 kb
Host smart-588fa32a-78b7-440d-8224-801cc04999b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211461400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.211461400
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.664394469
Short name T1286
Test name
Test status
Simulation time 564246676 ps
CPU time 4.88 seconds
Started Jan 21 08:04:44 PM PST 24
Finished Jan 21 08:04:50 PM PST 24
Peak memory 239328 kb
Host smart-ea18e96d-a7a4-4ae1-80a4-6c96b65855d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664394469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.664394469
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intr.1054980664
Short name T225
Test name
Test status
Simulation time 39639976904 ps
CPU time 102.86 seconds
Started Jan 21 08:03:55 PM PST 24
Finished Jan 21 08:05:40 PM PST 24
Peak memory 245056 kb
Host smart-003f349b-bc90-495c-8c11-b28dcac54358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054980664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intr.1054980664
Directory /workspace/29.spi_device_intr/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1068396247
Short name T1648
Test name
Test status
Simulation time 51613240685 ps
CPU time 17.3 seconds
Started Jan 21 08:04:38 PM PST 24
Finished Jan 21 08:04:57 PM PST 24
Peak memory 228832 kb
Host smart-2004f5db-8596-4e32-8c97-1ddf1207b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068396247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1068396247
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4275858463
Short name T257
Test name
Test status
Simulation time 15353200348 ps
CPU time 44.88 seconds
Started Jan 21 08:04:44 PM PST 24
Finished Jan 21 08:05:30 PM PST 24
Peak memory 239540 kb
Host smart-f8ce5086-a370-4238-9d57-43a0034bdde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275858463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4275858463
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3858904581
Short name T333
Test name
Test status
Simulation time 624646099 ps
CPU time 4.52 seconds
Started Jan 21 08:04:42 PM PST 24
Finished Jan 21 08:04:47 PM PST 24
Peak memory 234736 kb
Host smart-99ccb477-2c35-4eb3-b479-53d09ebfa05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858904581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3858904581
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_perf.1185489726
Short name T596
Test name
Test status
Simulation time 5050838974 ps
CPU time 171.05 seconds
Started Jan 21 08:04:12 PM PST 24
Finished Jan 21 08:07:10 PM PST 24
Peak memory 268208 kb
Host smart-92da7601-cc12-47a8-8bd4-cb2468970b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185489726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_perf.1185489726
Directory /workspace/29.spi_device_perf/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.736301812
Short name T862
Test name
Test status
Simulation time 717614867 ps
CPU time 5.04 seconds
Started Jan 21 08:04:45 PM PST 24
Finished Jan 21 08:04:51 PM PST 24
Peak memory 234932 kb
Host smart-2eaf426e-e2a0-4141-824b-a6e0d7188101
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=736301812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.736301812
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_rx_async_fifo_reset.818735607
Short name T1213
Test name
Test status
Simulation time 44401635 ps
CPU time 0.88 seconds
Started Jan 21 08:04:10 PM PST 24
Finished Jan 21 08:04:13 PM PST 24
Peak memory 208812 kb
Host smart-5f5153ab-1383-41b8-9a09-a9978efc6036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818735607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_async_fifo_reset.818735607
Directory /workspace/29.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_rx_timeout.4179632707
Short name T1021
Test name
Test status
Simulation time 437512923 ps
CPU time 5.12 seconds
Started Jan 21 08:04:12 PM PST 24
Finished Jan 21 08:04:22 PM PST 24
Peak memory 217248 kb
Host smart-36ade628-b693-4973-acf5-9bf054544538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179632707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_timeout.4179632707
Directory /workspace/29.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/29.spi_device_smoke.1086672160
Short name T1473
Test name
Test status
Simulation time 114249779 ps
CPU time 1.12 seconds
Started Jan 21 08:03:58 PM PST 24
Finished Jan 21 08:04:01 PM PST 24
Peak memory 216904 kb
Host smart-09bdd034-2d0f-4771-956d-dc28da80af45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086672160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_smoke.1086672160
Directory /workspace/29.spi_device_smoke/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2103603102
Short name T1169
Test name
Test status
Simulation time 94910220179 ps
CPU time 414.74 seconds
Started Jan 21 08:49:07 PM PST 24
Finished Jan 21 08:56:08 PM PST 24
Peak memory 359892 kb
Host smart-d6f44ea1-480f-4ead-b709-c1c12941591b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103603102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2103603102
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.735907239
Short name T901
Test name
Test status
Simulation time 14157339968 ps
CPU time 46.36 seconds
Started Jan 21 08:04:18 PM PST 24
Finished Jan 21 08:05:08 PM PST 24
Peak memory 223260 kb
Host smart-f9e3dc9a-d4c4-460e-bf06-bceb716b5ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735907239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.735907239
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3604453051
Short name T1240
Test name
Test status
Simulation time 2564041960 ps
CPU time 2.09 seconds
Started Jan 21 08:04:17 PM PST 24
Finished Jan 21 08:04:23 PM PST 24
Peak memory 208860 kb
Host smart-dd91890f-d9b0-498b-a5ea-e5e9c0f2b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604453051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3604453051
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3036317743
Short name T793
Test name
Test status
Simulation time 316303868 ps
CPU time 7.2 seconds
Started Jan 21 08:04:36 PM PST 24
Finished Jan 21 08:04:46 PM PST 24
Peak memory 217284 kb
Host smart-9f5f26be-e247-4cb1-a82f-6a4fd64f081d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036317743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3036317743
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.4035745196
Short name T1399
Test name
Test status
Simulation time 62219350 ps
CPU time 0.79 seconds
Started Jan 21 08:04:37 PM PST 24
Finished Jan 21 08:04:40 PM PST 24
Peak memory 207236 kb
Host smart-942399b7-9f8a-4f0c-a1bc-b936beb26026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035745196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.4035745196
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tx_async_fifo_reset.672922594
Short name T814
Test name
Test status
Simulation time 51420408 ps
CPU time 0.8 seconds
Started Jan 21 08:04:15 PM PST 24
Finished Jan 21 08:04:22 PM PST 24
Peak memory 208684 kb
Host smart-d18d3657-12b1-4fd8-a1c9-7f655ab8af28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672922594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tx_async_fifo_reset.672922594
Directory /workspace/29.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_txrx.3574887651
Short name T529
Test name
Test status
Simulation time 173985278274 ps
CPU time 775.08 seconds
Started Jan 21 08:03:58 PM PST 24
Finished Jan 21 08:16:55 PM PST 24
Peak memory 256128 kb
Host smart-19d0af0c-9f24-461c-815d-2cfa4bae71ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574887651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_txrx.3574887651
Directory /workspace/29.spi_device_txrx/latest

Test location /workspace/coverage/default/29.spi_device_upload.3871918043
Short name T1699
Test name
Test status
Simulation time 2198834369 ps
CPU time 4.98 seconds
Started Jan 21 08:04:39 PM PST 24
Finished Jan 21 08:04:45 PM PST 24
Peak memory 234832 kb
Host smart-751d4788-59e6-400f-8665-53d18f9d49ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871918043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3871918043
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_abort.2741087707
Short name T91
Test name
Test status
Simulation time 20169305 ps
CPU time 0.75 seconds
Started Jan 21 07:53:43 PM PST 24
Finished Jan 21 07:53:47 PM PST 24
Peak memory 207096 kb
Host smart-f2a7b896-b678-459f-b2a0-9ab573306596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741087707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_abort.2741087707
Directory /workspace/3.spi_device_abort/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2321703247
Short name T858
Test name
Test status
Simulation time 57173044 ps
CPU time 0.72 seconds
Started Jan 21 07:53:42 PM PST 24
Finished Jan 21 07:53:46 PM PST 24
Peak memory 206952 kb
Host smart-9f3d3a09-20e0-41e7-bd07-981d221f5f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321703247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
321703247
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_bit_transfer.3452277930
Short name T1751
Test name
Test status
Simulation time 241814355 ps
CPU time 2.75 seconds
Started Jan 21 07:53:43 PM PST 24
Finished Jan 21 07:53:49 PM PST 24
Peak memory 217232 kb
Host smart-cd727e6f-fb5c-4c0a-9c55-f3d2d21165e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452277930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_bit_transfer.3452277930
Directory /workspace/3.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/3.spi_device_byte_transfer.3704667798
Short name T1101
Test name
Test status
Simulation time 693637029 ps
CPU time 3.03 seconds
Started Jan 21 07:53:43 PM PST 24
Finished Jan 21 07:53:48 PM PST 24
Peak memory 217264 kb
Host smart-2d063e5f-3375-42cd-bede-fff5f895fc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704667798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_byte_transfer.3704667798
Directory /workspace/3.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2916811698
Short name T1629
Test name
Test status
Simulation time 264629595 ps
CPU time 3.22 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:54:06 PM PST 24
Peak memory 219088 kb
Host smart-3b422804-5b4c-42b1-9a27-bbcc488da333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916811698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2916811698
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2310759977
Short name T1679
Test name
Test status
Simulation time 21734250 ps
CPU time 0.82 seconds
Started Jan 21 07:53:41 PM PST 24
Finished Jan 21 07:53:44 PM PST 24
Peak memory 208068 kb
Host smart-c9dcc858-d286-438d-a28a-827c9d6daba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310759977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2310759977
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_extreme_fifo_size.1227377357
Short name T1493
Test name
Test status
Simulation time 211169582651 ps
CPU time 765.76 seconds
Started Jan 21 09:12:13 PM PST 24
Finished Jan 21 09:25:02 PM PST 24
Peak memory 219700 kb
Host smart-8aef2801-dc6c-4b3b-97b5-f8f6264333b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227377357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_extreme_fifo_size.1227377357
Directory /workspace/3.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/3.spi_device_fifo_full.2763543292
Short name T578
Test name
Test status
Simulation time 17765686512 ps
CPU time 480.86 seconds
Started Jan 21 07:53:40 PM PST 24
Finished Jan 21 08:01:44 PM PST 24
Peak memory 310408 kb
Host smart-97354234-cd4a-4a29-95f9-913bf16a0b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763543292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_full.2763543292
Directory /workspace/3.spi_device_fifo_full/latest

Test location /workspace/coverage/default/3.spi_device_fifo_underflow_overflow.1341895666
Short name T795
Test name
Test status
Simulation time 181642224054 ps
CPU time 354.32 seconds
Started Jan 21 07:53:37 PM PST 24
Finished Jan 21 07:59:36 PM PST 24
Peak memory 338532 kb
Host smart-bec4f054-b5c6-44d0-8830-fd593f5b17f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341895666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_underflow_overfl
ow.1341895666
Directory /workspace/3.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3186971177
Short name T359
Test name
Test status
Simulation time 9060350336 ps
CPU time 68.09 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:55:11 PM PST 24
Peak memory 254312 kb
Host smart-9b0c6026-8762-4377-bf54-d12ffbaae39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186971177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3186971177
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1579082036
Short name T1154
Test name
Test status
Simulation time 48837875193 ps
CPU time 251.17 seconds
Started Jan 21 08:13:55 PM PST 24
Finished Jan 21 08:18:08 PM PST 24
Peak memory 268332 kb
Host smart-c207ffa5-2695-4a50-86ae-61d5661ac7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579082036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1579082036
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.354653570
Short name T1178
Test name
Test status
Simulation time 31550307637 ps
CPU time 73.53 seconds
Started Jan 21 07:53:44 PM PST 24
Finished Jan 21 07:55:01 PM PST 24
Peak memory 224780 kb
Host smart-643f24cc-a4c0-4a3e-bdff-b2941b3a2ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354653570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
354653570
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3816201401
Short name T947
Test name
Test status
Simulation time 10727029760 ps
CPU time 31.25 seconds
Started Jan 21 07:53:50 PM PST 24
Finished Jan 21 07:54:25 PM PST 24
Peak memory 225580 kb
Host smart-7fdef902-349c-46ff-826f-841d9b128d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816201401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3816201401
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3282841168
Short name T619
Test name
Test status
Simulation time 487752719 ps
CPU time 7.07 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:54:10 PM PST 24
Peak memory 222388 kb
Host smart-e2f686c8-7860-4e00-bba2-e86f8cf45997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282841168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3282841168
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intr.1850770048
Short name T36
Test name
Test status
Simulation time 9331884162 ps
CPU time 40.69 seconds
Started Jan 21 08:58:41 PM PST 24
Finished Jan 21 08:59:51 PM PST 24
Peak memory 225560 kb
Host smart-dc427108-345d-41a8-bb76-350ce6b78dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850770048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intr.1850770048
Directory /workspace/3.spi_device_intr/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.96823911
Short name T115
Test name
Test status
Simulation time 274747943 ps
CPU time 3.72 seconds
Started Jan 21 07:53:47 PM PST 24
Finished Jan 21 07:53:54 PM PST 24
Peak memory 225524 kb
Host smart-c8bb8f63-a55c-43f8-8ec6-2056edd39ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96823911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.96823911
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3673643282
Short name T1478
Test name
Test status
Simulation time 93650830 ps
CPU time 1.09 seconds
Started Jan 21 08:25:17 PM PST 24
Finished Jan 21 08:25:25 PM PST 24
Peak memory 219264 kb
Host smart-771ef3d8-b286-40eb-b6f0-f73c1c776be7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673643282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3673643282
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1911678156
Short name T1602
Test name
Test status
Simulation time 28655453756 ps
CPU time 25.24 seconds
Started Jan 21 07:53:47 PM PST 24
Finished Jan 21 07:54:15 PM PST 24
Peak memory 242052 kb
Host smart-56f72dd2-5d62-4f69-ad0d-6547637a07ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911678156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1911678156
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1281415680
Short name T1073
Test name
Test status
Simulation time 9871706260 ps
CPU time 27.78 seconds
Started Jan 21 07:53:47 PM PST 24
Finished Jan 21 07:54:18 PM PST 24
Peak memory 220140 kb
Host smart-108032bd-03b2-435e-a033-160b0e06d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281415680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1281415680
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_perf.1357461058
Short name T1675
Test name
Test status
Simulation time 55520725922 ps
CPU time 707.71 seconds
Started Jan 21 09:12:16 PM PST 24
Finished Jan 21 09:24:08 PM PST 24
Peak memory 269796 kb
Host smart-ac70e154-6d08-4dab-a63d-6bed7017ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357461058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_perf.1357461058
Directory /workspace/3.spi_device_perf/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.4059320836
Short name T4
Test name
Test status
Simulation time 45661598 ps
CPU time 0.72 seconds
Started Jan 21 07:53:42 PM PST 24
Finished Jan 21 07:53:45 PM PST 24
Peak memory 217000 kb
Host smart-591f240c-2e2a-4a16-8d95-fa6264ff357b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059320836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.4059320836
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.889075226
Short name T900
Test name
Test status
Simulation time 224299115 ps
CPU time 4.16 seconds
Started Jan 21 07:53:46 PM PST 24
Finished Jan 21 07:53:54 PM PST 24
Peak memory 219168 kb
Host smart-a6fa9246-80ab-4422-b242-a04cf2008c11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=889075226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.889075226
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_rx_timeout.747364716
Short name T932
Test name
Test status
Simulation time 373201500 ps
CPU time 4.8 seconds
Started Jan 21 08:46:26 PM PST 24
Finished Jan 21 08:47:18 PM PST 24
Peak memory 217200 kb
Host smart-94e3e746-7c7e-46c6-a8ac-f56aeb5d469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747364716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_timeout.747364716
Directory /workspace/3.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2743347352
Short name T108
Test name
Test status
Simulation time 61522535 ps
CPU time 0.99 seconds
Started Jan 21 07:53:51 PM PST 24
Finished Jan 21 07:53:54 PM PST 24
Peak memory 238504 kb
Host smart-057943b6-6ab5-439d-bb9f-05ab62485658
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743347352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2743347352
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_smoke.3768136214
Short name T246
Test name
Test status
Simulation time 26881510 ps
CPU time 0.95 seconds
Started Jan 21 07:53:41 PM PST 24
Finished Jan 21 07:53:44 PM PST 24
Peak memory 208176 kb
Host smart-99646f2a-75fc-427d-8762-347e8f2f7333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768136214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_smoke.3768136214
Directory /workspace/3.spi_device_smoke/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2118776132
Short name T1322
Test name
Test status
Simulation time 9829838657 ps
CPU time 31.96 seconds
Started Jan 21 08:43:53 PM PST 24
Finished Jan 21 08:44:26 PM PST 24
Peak memory 217412 kb
Host smart-2150c2bd-d03e-4579-8ed1-fb1c6a4aabe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118776132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2118776132
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1465887572
Short name T1448
Test name
Test status
Simulation time 6753447565 ps
CPU time 7.91 seconds
Started Jan 21 07:53:42 PM PST 24
Finished Jan 21 07:53:53 PM PST 24
Peak memory 217204 kb
Host smart-7d94b7ac-e255-4887-b056-c420b7e0eb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465887572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1465887572
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3673152879
Short name T1482
Test name
Test status
Simulation time 118777608 ps
CPU time 2.67 seconds
Started Jan 21 07:53:43 PM PST 24
Finished Jan 21 07:53:48 PM PST 24
Peak memory 217272 kb
Host smart-eea37bcf-dbd6-4828-a368-e79f7f44a04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673152879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3673152879
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3313585073
Short name T639
Test name
Test status
Simulation time 173431175 ps
CPU time 1.03 seconds
Started Jan 21 07:53:48 PM PST 24
Finished Jan 21 07:53:52 PM PST 24
Peak memory 208296 kb
Host smart-f24dab92-dd76-46eb-95c0-1cd3db01b278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313585073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3313585073
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tx_async_fifo_reset.3865519642
Short name T878
Test name
Test status
Simulation time 22083645 ps
CPU time 0.8 seconds
Started Jan 21 08:50:59 PM PST 24
Finished Jan 21 08:51:37 PM PST 24
Peak memory 207712 kb
Host smart-a6b47643-90b6-4678-96fc-df40057069c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865519642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tx_async_fifo_reset.3865519642
Directory /workspace/3.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_txrx.3013171821
Short name T1165
Test name
Test status
Simulation time 79416085950 ps
CPU time 371.84 seconds
Started Jan 21 07:53:42 PM PST 24
Finished Jan 21 07:59:57 PM PST 24
Peak memory 282708 kb
Host smart-4505f378-c2aa-4c31-895d-98761947b29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013171821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_txrx.3013171821
Directory /workspace/3.spi_device_txrx/latest

Test location /workspace/coverage/default/3.spi_device_upload.906063128
Short name T1746
Test name
Test status
Simulation time 829745982 ps
CPU time 5.1 seconds
Started Jan 21 07:53:49 PM PST 24
Finished Jan 21 07:53:57 PM PST 24
Peak memory 239328 kb
Host smart-7577c534-8164-452e-8a78-7a950cfa0bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906063128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.906063128
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_abort.2210784903
Short name T1722
Test name
Test status
Simulation time 15538052 ps
CPU time 0.78 seconds
Started Jan 21 08:24:04 PM PST 24
Finished Jan 21 08:24:06 PM PST 24
Peak memory 207120 kb
Host smart-44a3725d-eade-4d88-80f5-dc64d03b06c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210784903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_abort.2210784903
Directory /workspace/30.spi_device_abort/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2609692827
Short name T515
Test name
Test status
Simulation time 42757868 ps
CPU time 0.77 seconds
Started Jan 21 08:08:47 PM PST 24
Finished Jan 21 08:08:50 PM PST 24
Peak memory 206976 kb
Host smart-29b84c58-340e-45da-bc91-a14c77475db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609692827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2609692827
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_bit_transfer.180471193
Short name T690
Test name
Test status
Simulation time 452738296 ps
CPU time 4.07 seconds
Started Jan 21 08:08:37 PM PST 24
Finished Jan 21 08:08:43 PM PST 24
Peak memory 217212 kb
Host smart-f6074a9d-b330-4a86-8d77-773e3f29ca23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180471193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_bit_transfer.180471193
Directory /workspace/30.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/30.spi_device_byte_transfer.2119408847
Short name T482
Test name
Test status
Simulation time 376781405 ps
CPU time 2.81 seconds
Started Jan 21 08:08:40 PM PST 24
Finished Jan 21 08:08:44 PM PST 24
Peak memory 217192 kb
Host smart-35993472-4ec7-4967-900c-7a2fa1679ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119408847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_byte_transfer.2119408847
Directory /workspace/30.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1925341551
Short name T1415
Test name
Test status
Simulation time 118973866 ps
CPU time 3.74 seconds
Started Jan 21 08:08:52 PM PST 24
Finished Jan 21 08:08:57 PM PST 24
Peak memory 234824 kb
Host smart-159f22e6-a10f-4f11-95c4-2d60d60b928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925341551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1925341551
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3399144275
Short name T1483
Test name
Test status
Simulation time 17402089 ps
CPU time 0.87 seconds
Started Jan 21 08:04:55 PM PST 24
Finished Jan 21 08:05:01 PM PST 24
Peak memory 207036 kb
Host smart-a2cc5f5a-e3aa-438b-ab64-3f57125cfdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399144275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3399144275
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_dummy_item_extra_dly.3282290697
Short name T761
Test name
Test status
Simulation time 42417987086 ps
CPU time 1059.52 seconds
Started Jan 21 08:04:48 PM PST 24
Finished Jan 21 08:22:29 PM PST 24
Peak memory 250088 kb
Host smart-b65fa2ed-a109-49dd-87f0-3fe8b451a818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282290697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_dummy_item_extra_dly.3282290697
Directory /workspace/30.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/30.spi_device_extreme_fifo_size.1035210439
Short name T637
Test name
Test status
Simulation time 53743521786 ps
CPU time 3056.67 seconds
Started Jan 21 08:04:49 PM PST 24
Finished Jan 21 08:55:47 PM PST 24
Peak memory 224584 kb
Host smart-4e514078-9958-4dbd-a99d-8f37534ddb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035210439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_extreme_fifo_size.1035210439
Directory /workspace/30.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/30.spi_device_fifo_full.1521907142
Short name T511
Test name
Test status
Simulation time 113259485215 ps
CPU time 327.15 seconds
Started Jan 21 08:04:48 PM PST 24
Finished Jan 21 08:10:17 PM PST 24
Peak memory 294240 kb
Host smart-db13dc80-0a06-4d78-858a-3643e9523746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521907142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_full.1521907142
Directory /workspace/30.spi_device_fifo_full/latest

Test location /workspace/coverage/default/30.spi_device_fifo_underflow_overflow.1972461678
Short name T806
Test name
Test status
Simulation time 51539987542 ps
CPU time 196.89 seconds
Started Jan 21 08:04:55 PM PST 24
Finished Jan 21 08:08:17 PM PST 24
Peak memory 340212 kb
Host smart-ac78e519-d28e-4cb8-a28f-21128daaa34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972461678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_underflow_overf
low.1972461678
Directory /workspace/30.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1101631459
Short name T1564
Test name
Test status
Simulation time 3844987567 ps
CPU time 22.78 seconds
Started Jan 21 08:08:47 PM PST 24
Finished Jan 21 08:09:12 PM PST 24
Peak memory 220936 kb
Host smart-55e9acd6-aaab-4e88-bd33-3d76e5608bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101631459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1101631459
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.922628704
Short name T1773
Test name
Test status
Simulation time 604546364279 ps
CPU time 662.51 seconds
Started Jan 21 08:08:48 PM PST 24
Finished Jan 21 08:19:52 PM PST 24
Peak memory 267044 kb
Host smart-3986b19f-4f7b-4652-81b0-67f2f52d434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922628704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.922628704
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.964079019
Short name T1099
Test name
Test status
Simulation time 1444571393 ps
CPU time 11.23 seconds
Started Jan 21 08:57:24 PM PST 24
Finished Jan 21 08:58:03 PM PST 24
Peak memory 254684 kb
Host smart-936c377a-f492-4254-a258-a1f4e8d59d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964079019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.964079019
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1267915251
Short name T716
Test name
Test status
Simulation time 3314523758 ps
CPU time 4.32 seconds
Started Jan 21 08:31:54 PM PST 24
Finished Jan 21 08:31:59 PM PST 24
Peak memory 238656 kb
Host smart-06b0a3ea-622c-44fa-88a6-4c307559b4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267915251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1267915251
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intr.1505443261
Short name T818
Test name
Test status
Simulation time 40173477348 ps
CPU time 42.67 seconds
Started Jan 21 08:04:51 PM PST 24
Finished Jan 21 08:05:36 PM PST 24
Peak memory 241648 kb
Host smart-2ddf992f-4497-4e49-b8d2-79a817778bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505443261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intr.1505443261
Directory /workspace/30.spi_device_intr/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1276116913
Short name T1667
Test name
Test status
Simulation time 3319945619 ps
CPU time 12.27 seconds
Started Jan 21 08:08:50 PM PST 24
Finished Jan 21 08:09:05 PM PST 24
Peak memory 235000 kb
Host smart-1c64063a-8211-4f7c-8fc3-8736cd385585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276116913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1276116913
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1593761832
Short name T322
Test name
Test status
Simulation time 122625578 ps
CPU time 4.19 seconds
Started Jan 21 08:08:37 PM PST 24
Finished Jan 21 08:08:42 PM PST 24
Peak memory 241136 kb
Host smart-d869e589-d42e-48d1-96e2-2849768f2389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593761832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1593761832
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.742600464
Short name T1054
Test name
Test status
Simulation time 22084200390 ps
CPU time 21.1 seconds
Started Jan 21 08:08:37 PM PST 24
Finished Jan 21 08:08:59 PM PST 24
Peak memory 245336 kb
Host smart-bfe58787-7160-4418-9ae7-92c8aeb83b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742600464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.742600464
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_perf.1796445991
Short name T930
Test name
Test status
Simulation time 34542184423 ps
CPU time 217.02 seconds
Started Jan 21 08:04:50 PM PST 24
Finished Jan 21 08:08:29 PM PST 24
Peak memory 249804 kb
Host smart-cd4c4fb1-46d8-48e0-ab11-22c1f7669e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796445991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_perf.1796445991
Directory /workspace/30.spi_device_perf/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1108297408
Short name T727
Test name
Test status
Simulation time 1718722133 ps
CPU time 4.42 seconds
Started Jan 21 08:08:48 PM PST 24
Finished Jan 21 08:08:54 PM PST 24
Peak memory 234840 kb
Host smart-8c07266e-3e56-4d0a-8be9-5c49cb1c62d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1108297408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1108297408
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.469600977
Short name T1121
Test name
Test status
Simulation time 256966184 ps
CPU time 0.92 seconds
Started Jan 21 08:08:38 PM PST 24
Finished Jan 21 08:08:40 PM PST 24
Peak memory 208828 kb
Host smart-31ecbb62-e59f-4a46-9a2a-be90e11307b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469600977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_async_fifo_reset.469600977
Directory /workspace/30.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_rx_timeout.3493728527
Short name T543
Test name
Test status
Simulation time 655827334 ps
CPU time 5.53 seconds
Started Jan 21 08:08:39 PM PST 24
Finished Jan 21 08:08:45 PM PST 24
Peak memory 217268 kb
Host smart-76f58742-be26-4c41-aeab-f1ca22c9a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493728527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_timeout.3493728527
Directory /workspace/30.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/30.spi_device_smoke.343000073
Short name T1638
Test name
Test status
Simulation time 43992182 ps
CPU time 1.09 seconds
Started Jan 21 08:04:49 PM PST 24
Finished Jan 21 08:04:52 PM PST 24
Peak memory 208524 kb
Host smart-bdcd5196-69dc-4d58-8640-9c89256c3413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343000073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_smoke.343000073
Directory /workspace/30.spi_device_smoke/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3815005737
Short name T936
Test name
Test status
Simulation time 73114284705 ps
CPU time 99.42 seconds
Started Jan 21 08:08:42 PM PST 24
Finished Jan 21 08:10:22 PM PST 24
Peak memory 217372 kb
Host smart-5e9f9820-7a2a-4fec-98ac-3cea5abaed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815005737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3815005737
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4083356687
Short name T613
Test name
Test status
Simulation time 2992181051 ps
CPU time 13.9 seconds
Started Jan 21 08:08:42 PM PST 24
Finished Jan 21 08:08:57 PM PST 24
Peak memory 217204 kb
Host smart-0370950a-cd06-40ca-a3c4-12a31be8e9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083356687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4083356687
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.391404375
Short name T1358
Test name
Test status
Simulation time 127681231 ps
CPU time 1.75 seconds
Started Jan 21 08:08:38 PM PST 24
Finished Jan 21 08:08:41 PM PST 24
Peak memory 217348 kb
Host smart-9bcf44f4-c3ca-49d4-bab4-09fd869525da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391404375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.391404375
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.98380993
Short name T1253
Test name
Test status
Simulation time 104722754 ps
CPU time 1.1 seconds
Started Jan 21 08:08:40 PM PST 24
Finished Jan 21 08:08:42 PM PST 24
Peak memory 208244 kb
Host smart-054002cb-be72-4257-bf68-304a74baa5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98380993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.98380993
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tx_async_fifo_reset.4046276282
Short name T590
Test name
Test status
Simulation time 17369766 ps
CPU time 0.78 seconds
Started Jan 21 08:08:42 PM PST 24
Finished Jan 21 08:08:44 PM PST 24
Peak memory 207656 kb
Host smart-0f2cf21d-9d4d-443a-94c9-ef56d97e19d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046276282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tx_async_fifo_reset.4046276282
Directory /workspace/30.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_txrx.406539159
Short name T667
Test name
Test status
Simulation time 49657855526 ps
CPU time 133.3 seconds
Started Jan 21 08:04:50 PM PST 24
Finished Jan 21 08:07:05 PM PST 24
Peak memory 267780 kb
Host smart-f4040f0b-69bb-4608-b21a-f3eeac95d377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406539159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_txrx.406539159
Directory /workspace/30.spi_device_txrx/latest

Test location /workspace/coverage/default/30.spi_device_upload.4194637009
Short name T219
Test name
Test status
Simulation time 1206189185 ps
CPU time 4.76 seconds
Started Jan 21 08:08:50 PM PST 24
Finished Jan 21 08:08:57 PM PST 24
Peak memory 219244 kb
Host smart-2c5f4055-519c-4fa3-ab66-fc8e456e44b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194637009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4194637009
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_abort.4057243250
Short name T536
Test name
Test status
Simulation time 41749924 ps
CPU time 0.79 seconds
Started Jan 21 08:09:03 PM PST 24
Finished Jan 21 08:09:08 PM PST 24
Peak memory 207104 kb
Host smart-0605ad32-4c04-49ef-a08c-8efd29aa8f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057243250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_abort.4057243250
Directory /workspace/31.spi_device_abort/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.234638998
Short name T789
Test name
Test status
Simulation time 11975449 ps
CPU time 0.76 seconds
Started Jan 21 08:09:47 PM PST 24
Finished Jan 21 08:09:49 PM PST 24
Peak memory 207004 kb
Host smart-15db0843-a9f1-46e0-a57b-4dcea831e5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234638998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.234638998
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_bit_transfer.1190489732
Short name T37
Test name
Test status
Simulation time 171133350 ps
CPU time 2.88 seconds
Started Jan 21 08:09:02 PM PST 24
Finished Jan 21 08:09:09 PM PST 24
Peak memory 217208 kb
Host smart-361280ec-8ac8-4ef7-98f1-6dd908e3bdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190489732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_bit_transfer.1190489732
Directory /workspace/31.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/31.spi_device_byte_transfer.1282980897
Short name T781
Test name
Test status
Simulation time 150235966 ps
CPU time 3.06 seconds
Started Jan 21 08:09:04 PM PST 24
Finished Jan 21 08:09:12 PM PST 24
Peak memory 217228 kb
Host smart-dd68f2d0-0fce-47ff-bec7-25abc8ab89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282980897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_byte_transfer.1282980897
Directory /workspace/31.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1110292411
Short name T306
Test name
Test status
Simulation time 2728356298 ps
CPU time 6.73 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:09:57 PM PST 24
Peak memory 219712 kb
Host smart-4669c484-5d1a-4961-a1ea-e33a6dbf15a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110292411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1110292411
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2356962297
Short name T508
Test name
Test status
Simulation time 14119426 ps
CPU time 0.79 seconds
Started Jan 21 08:09:00 PM PST 24
Finished Jan 21 08:09:05 PM PST 24
Peak memory 207032 kb
Host smart-bc75992a-2755-46d6-8315-999ab7fbadcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356962297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2356962297
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_dummy_item_extra_dly.3591911044
Short name T711
Test name
Test status
Simulation time 75870492139 ps
CPU time 330.32 seconds
Started Jan 21 08:08:48 PM PST 24
Finished Jan 21 08:14:20 PM PST 24
Peak memory 265312 kb
Host smart-934c2daa-70eb-4d5c-a305-b51acb9125f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591911044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_dummy_item_extra_dly.3591911044
Directory /workspace/31.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/31.spi_device_extreme_fifo_size.2665378846
Short name T555
Test name
Test status
Simulation time 77600814342 ps
CPU time 1033.94 seconds
Started Jan 21 08:08:49 PM PST 24
Finished Jan 21 08:26:06 PM PST 24
Peak memory 225368 kb
Host smart-e0600327-a43e-4064-a99a-70822819aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665378846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_extreme_fifo_size.2665378846
Directory /workspace/31.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/31.spi_device_fifo_full.1296212429
Short name T605
Test name
Test status
Simulation time 64926492302 ps
CPU time 3562.11 seconds
Started Jan 21 08:08:48 PM PST 24
Finished Jan 21 09:08:12 PM PST 24
Peak memory 302748 kb
Host smart-8fa20054-2982-4a11-86b8-a3a2531db814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296212429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_full.1296212429
Directory /workspace/31.spi_device_fifo_full/latest

Test location /workspace/coverage/default/31.spi_device_fifo_underflow_overflow.3664371470
Short name T880
Test name
Test status
Simulation time 351883384211 ps
CPU time 526.24 seconds
Started Jan 21 08:08:51 PM PST 24
Finished Jan 21 08:17:39 PM PST 24
Peak memory 376676 kb
Host smart-6c0993d6-633d-4a52-946d-d39d276a2c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664371470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_underflow_overf
low.3664371470
Directory /workspace/31.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3320486825
Short name T1570
Test name
Test status
Simulation time 116292681036 ps
CPU time 829.52 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:23:41 PM PST 24
Peak memory 282996 kb
Host smart-348b8a54-1d52-460d-a453-df0be70e98d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320486825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3320486825
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3658558716
Short name T1040
Test name
Test status
Simulation time 16764514125 ps
CPU time 119.25 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:11:51 PM PST 24
Peak memory 250288 kb
Host smart-f1baf256-27ba-4b66-a75c-c4779dc61a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658558716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3658558716
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.958449356
Short name T1005
Test name
Test status
Simulation time 12275793803 ps
CPU time 81.47 seconds
Started Jan 21 08:09:46 PM PST 24
Finished Jan 21 08:11:09 PM PST 24
Peak memory 251340 kb
Host smart-bc8f85d0-924f-461d-8160-163499e61ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958449356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.958449356
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.244113448
Short name T1683
Test name
Test status
Simulation time 78340496 ps
CPU time 3.28 seconds
Started Jan 21 08:09:50 PM PST 24
Finished Jan 21 08:09:56 PM PST 24
Peak memory 220412 kb
Host smart-5ed58292-bcf7-4279-85d0-9ebfa9faf093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244113448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.244113448
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intr.2032022428
Short name T697
Test name
Test status
Simulation time 12123306077 ps
CPU time 60.6 seconds
Started Jan 21 08:09:02 PM PST 24
Finished Jan 21 08:10:07 PM PST 24
Peak memory 240620 kb
Host smart-6358d601-98b6-4082-bf17-20e632acdfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032022428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intr.2032022428
Directory /workspace/31.spi_device_intr/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.852899849
Short name T327
Test name
Test status
Simulation time 11661459121 ps
CPU time 15.07 seconds
Started Jan 21 08:09:47 PM PST 24
Finished Jan 21 08:10:03 PM PST 24
Peak memory 240992 kb
Host smart-18b13f8b-2fb5-4139-8496-dcab8e6ef027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852899849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.852899849
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3299452777
Short name T1736
Test name
Test status
Simulation time 458088596 ps
CPU time 7.31 seconds
Started Jan 21 08:09:04 PM PST 24
Finished Jan 21 08:09:16 PM PST 24
Peak memory 236748 kb
Host smart-9c6ae9ae-f48d-4284-a84c-ef3d363638e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299452777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3299452777
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1646451849
Short name T1333
Test name
Test status
Simulation time 9745413322 ps
CPU time 6.42 seconds
Started Jan 21 08:09:01 PM PST 24
Finished Jan 21 08:09:11 PM PST 24
Peak memory 239780 kb
Host smart-85e853d8-0394-43f9-ae8b-02c9835b292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646451849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1646451849
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_perf.1448583667
Short name T13
Test name
Test status
Simulation time 12357714907 ps
CPU time 309.55 seconds
Started Jan 21 08:09:02 PM PST 24
Finished Jan 21 08:14:15 PM PST 24
Peak memory 267856 kb
Host smart-7fb41d59-0a7b-4986-98da-04d25c15be5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448583667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_perf.1448583667
Directory /workspace/31.spi_device_perf/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.888184965
Short name T1167
Test name
Test status
Simulation time 1445866100 ps
CPU time 5.76 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:09:57 PM PST 24
Peak memory 236320 kb
Host smart-e6144a1a-6322-49eb-b605-99b9bca9047c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=888184965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.888184965
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_rx_async_fifo_reset.1984415092
Short name T1198
Test name
Test status
Simulation time 48426124 ps
CPU time 0.92 seconds
Started Jan 21 08:09:02 PM PST 24
Finished Jan 21 08:09:07 PM PST 24
Peak memory 208788 kb
Host smart-002e359b-ad97-4963-b910-3db02baca6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984415092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_async_fifo_reset.1984415092
Directory /workspace/31.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_rx_timeout.2018585983
Short name T598
Test name
Test status
Simulation time 5660588520 ps
CPU time 4.94 seconds
Started Jan 21 08:09:01 PM PST 24
Finished Jan 21 08:09:10 PM PST 24
Peak memory 217316 kb
Host smart-00ac11f4-3ba6-4565-ab88-5b2c8457e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018585983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_timeout.2018585983
Directory /workspace/31.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/31.spi_device_smoke.441644630
Short name T715
Test name
Test status
Simulation time 62753899 ps
CPU time 1.03 seconds
Started Jan 21 08:08:46 PM PST 24
Finished Jan 21 08:08:50 PM PST 24
Peak memory 208268 kb
Host smart-39005182-40d4-40ad-bd3c-033a08c7eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441644630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_smoke.441644630
Directory /workspace/31.spi_device_smoke/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2827668439
Short name T1355
Test name
Test status
Simulation time 11476635278 ps
CPU time 89.31 seconds
Started Jan 21 08:09:02 PM PST 24
Finished Jan 21 08:10:35 PM PST 24
Peak memory 217548 kb
Host smart-e5701a44-b5aa-4c1b-bc2a-ebd8987f6eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827668439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2827668439
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3829589970
Short name T1449
Test name
Test status
Simulation time 3515983941 ps
CPU time 6.61 seconds
Started Jan 21 08:09:03 PM PST 24
Finished Jan 21 08:09:15 PM PST 24
Peak memory 217232 kb
Host smart-473471c9-440e-410d-b24f-d69960b03f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829589970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3829589970
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.867746366
Short name T1656
Test name
Test status
Simulation time 113739623 ps
CPU time 1.38 seconds
Started Jan 21 08:09:04 PM PST 24
Finished Jan 21 08:09:11 PM PST 24
Peak memory 208612 kb
Host smart-1b112a70-2b9a-4e85-94d1-c4ddb98ab501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867746366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.867746366
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1884284334
Short name T1508
Test name
Test status
Simulation time 274758241 ps
CPU time 1.04 seconds
Started Jan 21 08:09:03 PM PST 24
Finished Jan 21 08:09:08 PM PST 24
Peak memory 207236 kb
Host smart-ab0e8f96-989f-45b2-922b-d7237939503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884284334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1884284334
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tx_async_fifo_reset.3460898500
Short name T1734
Test name
Test status
Simulation time 19239892 ps
CPU time 0.79 seconds
Started Jan 21 08:09:03 PM PST 24
Finished Jan 21 08:09:07 PM PST 24
Peak memory 207732 kb
Host smart-72fd21f2-afd4-469c-b7ec-0db0d1b56a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460898500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tx_async_fifo_reset.3460898500
Directory /workspace/31.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_txrx.1101316812
Short name T1575
Test name
Test status
Simulation time 32672057087 ps
CPU time 273.76 seconds
Started Jan 21 08:08:49 PM PST 24
Finished Jan 21 08:13:26 PM PST 24
Peak memory 272492 kb
Host smart-b4d9d900-39b4-49d5-9f81-749e9d5975b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101316812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_txrx.1101316812
Directory /workspace/31.spi_device_txrx/latest

Test location /workspace/coverage/default/31.spi_device_upload.1697906703
Short name T1290
Test name
Test status
Simulation time 204518998 ps
CPU time 3.65 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:09:55 PM PST 24
Peak memory 226516 kb
Host smart-ceef9c83-1da3-4b2a-867c-4312ee08ecc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697906703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1697906703
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_abort.3956592979
Short name T1339
Test name
Test status
Simulation time 16403309 ps
CPU time 0.82 seconds
Started Jan 21 08:10:10 PM PST 24
Finished Jan 21 08:10:14 PM PST 24
Peak memory 207048 kb
Host smart-553fadab-9371-4592-b692-872a14d6b03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956592979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_abort.3956592979
Directory /workspace/32.spi_device_abort/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.268662786
Short name T1465
Test name
Test status
Simulation time 13503659 ps
CPU time 0.73 seconds
Started Jan 21 08:10:11 PM PST 24
Finished Jan 21 08:10:16 PM PST 24
Peak memory 206944 kb
Host smart-7af1f257-2b01-4f36-9c2d-d86edd134202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268662786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.268662786
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_bit_transfer.2000409107
Short name T1039
Test name
Test status
Simulation time 81030732 ps
CPU time 2.33 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:09:53 PM PST 24
Peak memory 217208 kb
Host smart-bea9960b-b5e4-41d3-88cf-e89c2fd0b9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000409107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_bit_transfer.2000409107
Directory /workspace/32.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/32.spi_device_byte_transfer.992043426
Short name T684
Test name
Test status
Simulation time 251132033 ps
CPU time 3.05 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:09:54 PM PST 24
Peak memory 217152 kb
Host smart-150362ae-9bd6-4050-ba70-733059506433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992043426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_byte_transfer.992043426
Directory /workspace/32.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4028731522
Short name T576
Test name
Test status
Simulation time 5873139255 ps
CPU time 5.52 seconds
Started Jan 21 08:10:07 PM PST 24
Finished Jan 21 08:10:15 PM PST 24
Peak memory 238356 kb
Host smart-4361a5c8-f9d3-4f34-ae73-5b56027bacc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028731522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4028731522
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.617503582
Short name T1593
Test name
Test status
Simulation time 44728449 ps
CPU time 0.77 seconds
Started Jan 21 08:09:47 PM PST 24
Finished Jan 21 08:09:50 PM PST 24
Peak memory 207016 kb
Host smart-09105c49-2c6e-4799-b6e3-63083e5bccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617503582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.617503582
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_dummy_item_extra_dly.3159942817
Short name T1122
Test name
Test status
Simulation time 185961311061 ps
CPU time 224.78 seconds
Started Jan 21 08:09:48 PM PST 24
Finished Jan 21 08:13:34 PM PST 24
Peak memory 269752 kb
Host smart-5f79bc3e-f5f1-45c8-84a0-0cc7f0b38356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159942817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_dummy_item_extra_dly.3159942817
Directory /workspace/32.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/32.spi_device_extreme_fifo_size.45769775
Short name T1486
Test name
Test status
Simulation time 246690728983 ps
CPU time 3199.15 seconds
Started Jan 21 08:09:46 PM PST 24
Finished Jan 21 09:03:07 PM PST 24
Peak memory 220424 kb
Host smart-f2d66680-3a59-42cc-b596-3e2ac679a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45769775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_extreme_fifo_size.45769775
Directory /workspace/32.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/32.spi_device_fifo_full.3660768230
Short name T630
Test name
Test status
Simulation time 147216378056 ps
CPU time 3210.68 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 09:03:22 PM PST 24
Peak memory 274576 kb
Host smart-aa2f74c9-6f5e-48e6-b294-3ab780dda567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660768230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_full.3660768230
Directory /workspace/32.spi_device_fifo_full/latest

Test location /workspace/coverage/default/32.spi_device_fifo_underflow_overflow.2225248949
Short name T61
Test name
Test status
Simulation time 107636345335 ps
CPU time 320.81 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:15:12 PM PST 24
Peak memory 445204 kb
Host smart-1dd5938a-7cc8-44b8-9dc0-be736e8dbbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225248949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_underflow_overf
low.2225248949
Directory /workspace/32.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2291951497
Short name T362
Test name
Test status
Simulation time 131472200320 ps
CPU time 114.99 seconds
Started Jan 21 08:10:12 PM PST 24
Finished Jan 21 08:12:12 PM PST 24
Peak memory 257752 kb
Host smart-739ddd44-b5b3-4712-aac0-c6b054cedc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291951497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2291951497
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2567551568
Short name T1776
Test name
Test status
Simulation time 7294782710 ps
CPU time 57.11 seconds
Started Jan 21 08:10:14 PM PST 24
Finished Jan 21 08:11:16 PM PST 24
Peak memory 238072 kb
Host smart-3423d135-0dad-40fd-bf80-e0916f975a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567551568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2567551568
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2789703667
Short name T1282
Test name
Test status
Simulation time 70549177819 ps
CPU time 526.66 seconds
Started Jan 21 08:10:14 PM PST 24
Finished Jan 21 08:19:06 PM PST 24
Peak memory 264396 kb
Host smart-492c6a02-2010-4668-afa9-aefa6d3f2575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789703667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2789703667
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1764161142
Short name T1586
Test name
Test status
Simulation time 837157080 ps
CPU time 12.39 seconds
Started Jan 21 08:10:11 PM PST 24
Finished Jan 21 08:10:28 PM PST 24
Peak memory 240140 kb
Host smart-f9759645-a7bb-4d8f-999b-deece7bc6a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764161142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1764161142
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.813776327
Short name T1076
Test name
Test status
Simulation time 262536437 ps
CPU time 3.88 seconds
Started Jan 21 08:10:08 PM PST 24
Finished Jan 21 08:10:15 PM PST 24
Peak memory 240972 kb
Host smart-d2a719cb-157e-4ddf-8b97-f61c15300426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813776327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.813776327
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intr.3202944888
Short name T65
Test name
Test status
Simulation time 9865912461 ps
CPU time 71.63 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:11:04 PM PST 24
Peak memory 241260 kb
Host smart-f559a705-798b-42a8-96d7-e70468c4706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202944888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intr.3202944888
Directory /workspace/32.spi_device_intr/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3598315190
Short name T812
Test name
Test status
Simulation time 13108141647 ps
CPU time 22.1 seconds
Started Jan 21 08:10:07 PM PST 24
Finished Jan 21 08:10:30 PM PST 24
Peak memory 250244 kb
Host smart-f03043c9-8ab2-4d38-8100-fb067df2418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598315190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3598315190
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1538680064
Short name T1753
Test name
Test status
Simulation time 319993581 ps
CPU time 4.53 seconds
Started Jan 21 08:10:13 PM PST 24
Finished Jan 21 08:10:23 PM PST 24
Peak memory 218876 kb
Host smart-123281eb-3deb-4b9e-b752-be951b08870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538680064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1538680064
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3779892031
Short name T1676
Test name
Test status
Simulation time 4072391050 ps
CPU time 8.88 seconds
Started Jan 21 08:10:13 PM PST 24
Finished Jan 21 08:10:28 PM PST 24
Peak memory 231692 kb
Host smart-c7b024ae-2c07-4c48-b039-5810261060c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779892031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3779892031
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_perf.2370475055
Short name T1300
Test name
Test status
Simulation time 14852011917 ps
CPU time 299.1 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:14:51 PM PST 24
Peak memory 279276 kb
Host smart-b0629fe5-a823-44bd-b31d-52c3e0790630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370475055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_perf.2370475055
Directory /workspace/32.spi_device_perf/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2893102256
Short name T970
Test name
Test status
Simulation time 429919106 ps
CPU time 4.83 seconds
Started Jan 21 08:10:20 PM PST 24
Finished Jan 21 08:10:29 PM PST 24
Peak memory 221280 kb
Host smart-5aa6c8c5-9d98-4915-a0dc-f51e2f7667b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2893102256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2893102256
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_rx_async_fifo_reset.3637960161
Short name T626
Test name
Test status
Simulation time 133948173 ps
CPU time 0.91 seconds
Started Jan 21 08:10:12 PM PST 24
Finished Jan 21 08:10:18 PM PST 24
Peak memory 208796 kb
Host smart-83e4063e-d911-4f3d-996b-bd98fdf08492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637960161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_async_fifo_reset.3637960161
Directory /workspace/32.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_rx_timeout.4188930392
Short name T985
Test name
Test status
Simulation time 747413444 ps
CPU time 7.25 seconds
Started Jan 21 08:09:47 PM PST 24
Finished Jan 21 08:09:56 PM PST 24
Peak memory 217212 kb
Host smart-5411fe50-a142-4a15-961e-82d2c78d3887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188930392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_timeout.4188930392
Directory /workspace/32.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/32.spi_device_smoke.1709490474
Short name T1779
Test name
Test status
Simulation time 50262890 ps
CPU time 1.21 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:09:52 PM PST 24
Peak memory 216948 kb
Host smart-99ef3889-dfd5-4eb9-8acf-a7b5da0f5fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709490474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_smoke.1709490474
Directory /workspace/32.spi_device_smoke/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.333687687
Short name T1139
Test name
Test status
Simulation time 10335762128 ps
CPU time 34.57 seconds
Started Jan 21 08:09:47 PM PST 24
Finished Jan 21 08:10:23 PM PST 24
Peak memory 217516 kb
Host smart-9c72bf36-3662-4790-b0e0-c8e2c52f2a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333687687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.333687687
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1928523459
Short name T1246
Test name
Test status
Simulation time 15785405809 ps
CPU time 20.56 seconds
Started Jan 21 08:09:47 PM PST 24
Finished Jan 21 08:10:09 PM PST 24
Peak memory 217604 kb
Host smart-cd2a6189-2c5e-4dc5-a856-1543e324a726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928523459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1928523459
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1804122027
Short name T1059
Test name
Test status
Simulation time 294758771 ps
CPU time 4.24 seconds
Started Jan 21 08:10:09 PM PST 24
Finished Jan 21 08:10:17 PM PST 24
Peak memory 217244 kb
Host smart-484d2213-3559-440c-91e2-58f696cc1c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804122027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1804122027
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3840512020
Short name T1013
Test name
Test status
Simulation time 287251533 ps
CPU time 0.93 seconds
Started Jan 21 08:10:11 PM PST 24
Finished Jan 21 08:10:16 PM PST 24
Peak memory 207256 kb
Host smart-7d97c5db-ef91-4286-9f72-7e3bafc7f873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840512020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3840512020
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tx_async_fifo_reset.623553092
Short name T167
Test name
Test status
Simulation time 26469594 ps
CPU time 0.77 seconds
Started Jan 21 08:09:49 PM PST 24
Finished Jan 21 08:09:52 PM PST 24
Peak memory 208696 kb
Host smart-fd3bdab6-6a96-46fe-877a-19c826a153df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623553092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tx_async_fifo_reset.623553092
Directory /workspace/32.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_txrx.3177768977
Short name T1206
Test name
Test status
Simulation time 62584858019 ps
CPU time 920.84 seconds
Started Jan 21 08:09:50 PM PST 24
Finished Jan 21 08:25:13 PM PST 24
Peak memory 280004 kb
Host smart-6515db9d-37d8-4140-ad3d-1de1a60b8562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177768977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_txrx.3177768977
Directory /workspace/32.spi_device_txrx/latest

Test location /workspace/coverage/default/32.spi_device_upload.2511591433
Short name T792
Test name
Test status
Simulation time 108174933189 ps
CPU time 41.03 seconds
Started Jan 21 08:10:08 PM PST 24
Finished Jan 21 08:10:53 PM PST 24
Peak memory 258408 kb
Host smart-19f30e3c-12fd-49d2-894a-6086d51ae773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511591433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2511591433
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_abort.1663995242
Short name T1725
Test name
Test status
Simulation time 16443792 ps
CPU time 0.79 seconds
Started Jan 21 08:10:28 PM PST 24
Finished Jan 21 08:10:31 PM PST 24
Peak memory 207060 kb
Host smart-30fd38b3-9c5c-40fb-80b4-616bbaccea78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663995242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_abort.1663995242
Directory /workspace/33.spi_device_abort/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1005947627
Short name T968
Test name
Test status
Simulation time 23702248 ps
CPU time 0.73 seconds
Started Jan 21 08:10:28 PM PST 24
Finished Jan 21 08:10:31 PM PST 24
Peak memory 206964 kb
Host smart-e0ae1075-fed2-45be-a567-eb2f7f999fcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005947627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1005947627
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_bit_transfer.1198093379
Short name T580
Test name
Test status
Simulation time 692842242 ps
CPU time 2.4 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:31 PM PST 24
Peak memory 217164 kb
Host smart-660f8f2f-3039-42ab-8762-f560e4151958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198093379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_bit_transfer.1198093379
Directory /workspace/33.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/33.spi_device_byte_transfer.1088838730
Short name T1771
Test name
Test status
Simulation time 151670873 ps
CPU time 3.38 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:32 PM PST 24
Peak memory 217192 kb
Host smart-7b02ce5e-58c2-479f-80a0-585bc05fcd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088838730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_byte_transfer.1088838730
Directory /workspace/33.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.156843268
Short name T137
Test name
Test status
Simulation time 111407897 ps
CPU time 2.72 seconds
Started Jan 21 08:10:32 PM PST 24
Finished Jan 21 08:10:39 PM PST 24
Peak memory 218680 kb
Host smart-1a31e25f-8e82-47de-b4e1-6f8bb0732373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156843268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.156843268
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2223606576
Short name T500
Test name
Test status
Simulation time 47254755 ps
CPU time 0.85 seconds
Started Jan 21 08:10:33 PM PST 24
Finished Jan 21 08:10:38 PM PST 24
Peak memory 207992 kb
Host smart-c50e0d27-16d8-4c49-b77e-19d4e12e4e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223606576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2223606576
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_dummy_item_extra_dly.1908901151
Short name T826
Test name
Test status
Simulation time 62496802357 ps
CPU time 256.57 seconds
Started Jan 21 08:10:19 PM PST 24
Finished Jan 21 08:14:40 PM PST 24
Peak memory 284976 kb
Host smart-ce1ffeba-9f2b-4fdc-8ebd-6faa1a0c298e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908901151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_dummy_item_extra_dly.1908901151
Directory /workspace/33.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/33.spi_device_extreme_fifo_size.3389222003
Short name T888
Test name
Test status
Simulation time 53752698646 ps
CPU time 124.72 seconds
Started Jan 21 08:10:15 PM PST 24
Finished Jan 21 08:12:26 PM PST 24
Peak memory 236396 kb
Host smart-c88f5049-8dd7-401e-b64f-49897c9c03ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389222003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_extreme_fifo_size.3389222003
Directory /workspace/33.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/33.spi_device_fifo_full.1566561168
Short name T673
Test name
Test status
Simulation time 84874661562 ps
CPU time 760.68 seconds
Started Jan 21 08:10:10 PM PST 24
Finished Jan 21 08:22:54 PM PST 24
Peak memory 261424 kb
Host smart-12cede8a-2ef2-40d7-b5ed-b84b7598b2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566561168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_full.1566561168
Directory /workspace/33.spi_device_fifo_full/latest

Test location /workspace/coverage/default/33.spi_device_fifo_underflow_overflow.2290569714
Short name T60
Test name
Test status
Simulation time 55989855436 ps
CPU time 222.35 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:14:11 PM PST 24
Peak memory 353524 kb
Host smart-f56fecbc-15fb-4013-a319-ee399a1b0f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290569714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_underflow_overf
low.2290569714
Directory /workspace/33.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.868584300
Short name T346
Test name
Test status
Simulation time 61274765973 ps
CPU time 192.99 seconds
Started Jan 21 08:10:33 PM PST 24
Finished Jan 21 08:13:50 PM PST 24
Peak memory 256828 kb
Host smart-d8730fc4-8b26-4189-8d06-e48a73c89da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868584300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.868584300
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2311786850
Short name T1395
Test name
Test status
Simulation time 44973594369 ps
CPU time 287.89 seconds
Started Jan 21 08:10:32 PM PST 24
Finished Jan 21 08:15:24 PM PST 24
Peak memory 283948 kb
Host smart-d520c535-bfa5-492e-9ba2-4c53456b10b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311786850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2311786850
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2155240420
Short name T897
Test name
Test status
Simulation time 27418275506 ps
CPU time 60.72 seconds
Started Jan 21 08:47:25 PM PST 24
Finished Jan 21 08:48:54 PM PST 24
Peak memory 267240 kb
Host smart-1ed6c3ac-c690-41f2-95e1-364f003d51fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155240420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2155240420
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3808606553
Short name T1032
Test name
Test status
Simulation time 340253430 ps
CPU time 3.05 seconds
Started Jan 21 09:14:03 PM PST 24
Finished Jan 21 09:14:24 PM PST 24
Peak memory 234756 kb
Host smart-49f8637d-ac24-422d-8959-214e8e410aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808606553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3808606553
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intr.2690602257
Short name T497
Test name
Test status
Simulation time 10505709138 ps
CPU time 20.79 seconds
Started Jan 21 08:10:15 PM PST 24
Finished Jan 21 08:10:42 PM PST 24
Peak memory 217608 kb
Host smart-f692a51d-0868-4c4d-ae86-99d4ed38ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690602257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intr.2690602257
Directory /workspace/33.spi_device_intr/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3871703023
Short name T1481
Test name
Test status
Simulation time 12442921163 ps
CPU time 13.45 seconds
Started Jan 21 08:10:32 PM PST 24
Finished Jan 21 08:10:49 PM PST 24
Peak memory 223008 kb
Host smart-9843e67c-1cdd-47d4-a4f6-aafb11c735f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871703023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3871703023
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.21692135
Short name T1556
Test name
Test status
Simulation time 1023097119 ps
CPU time 3.63 seconds
Started Jan 21 08:26:44 PM PST 24
Finished Jan 21 08:26:48 PM PST 24
Peak memory 225564 kb
Host smart-55e4ffcb-940b-4f25-8471-c4b705427dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21692135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.21692135
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2331587452
Short name T64
Test name
Test status
Simulation time 78204777 ps
CPU time 3.05 seconds
Started Jan 21 08:10:31 PM PST 24
Finished Jan 21 08:10:38 PM PST 24
Peak memory 234768 kb
Host smart-fcea259a-b9fa-4ffd-97eb-72cd0da36b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331587452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2331587452
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_perf.2611978806
Short name T1321
Test name
Test status
Simulation time 93678202313 ps
CPU time 567.95 seconds
Started Jan 21 08:10:23 PM PST 24
Finished Jan 21 08:19:53 PM PST 24
Peak memory 305900 kb
Host smart-80cdecfb-8c63-450c-b5d1-7505e6814301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611978806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_perf.2611978806
Directory /workspace/33.spi_device_perf/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1476771808
Short name T1455
Test name
Test status
Simulation time 187300856 ps
CPU time 3.86 seconds
Started Jan 21 09:38:33 PM PST 24
Finished Jan 21 09:38:41 PM PST 24
Peak memory 220536 kb
Host smart-32923a25-aad5-4b35-a489-ae7e72510310
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1476771808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1476771808
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_rx_async_fifo_reset.174550232
Short name T702
Test name
Test status
Simulation time 152458652 ps
CPU time 1 seconds
Started Jan 21 08:10:29 PM PST 24
Finished Jan 21 08:10:33 PM PST 24
Peak memory 208792 kb
Host smart-358a4732-71f8-49cb-880c-67119a90cd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174550232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_async_fifo_reset.174550232
Directory /workspace/33.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_rx_timeout.1696437577
Short name T1297
Test name
Test status
Simulation time 472704314 ps
CPU time 5.62 seconds
Started Jan 21 08:10:23 PM PST 24
Finished Jan 21 08:10:31 PM PST 24
Peak memory 217276 kb
Host smart-5170e70d-756b-49f5-91fe-374b05bb7d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696437577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_timeout.1696437577
Directory /workspace/33.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/33.spi_device_smoke.2725112268
Short name T1579
Test name
Test status
Simulation time 24948579 ps
CPU time 0.96 seconds
Started Jan 21 08:10:10 PM PST 24
Finished Jan 21 08:10:15 PM PST 24
Peak memory 208176 kb
Host smart-84dfe826-2524-44e4-bf23-311048cc829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725112268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_smoke.2725112268
Directory /workspace/33.spi_device_smoke/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3738825191
Short name T920
Test name
Test status
Simulation time 118164434612 ps
CPU time 993.61 seconds
Started Jan 21 08:53:25 PM PST 24
Finished Jan 21 09:10:17 PM PST 24
Peak memory 274964 kb
Host smart-d4894f88-076c-43c8-ac8e-fc0dcdb5dffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738825191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3738825191
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2037419071
Short name T1639
Test name
Test status
Simulation time 4279936267 ps
CPU time 36.49 seconds
Started Jan 21 08:10:30 PM PST 24
Finished Jan 21 08:11:09 PM PST 24
Peak memory 217268 kb
Host smart-a019854b-7e7e-4e76-9a14-e030a671fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037419071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2037419071
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1799939563
Short name T1278
Test name
Test status
Simulation time 18109316576 ps
CPU time 5.76 seconds
Started Jan 21 08:10:25 PM PST 24
Finished Jan 21 08:10:33 PM PST 24
Peak memory 217248 kb
Host smart-db991258-490c-49f3-99b3-f5b08f539c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799939563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1799939563
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3652607885
Short name T518
Test name
Test status
Simulation time 69686196 ps
CPU time 1.4 seconds
Started Jan 21 08:29:35 PM PST 24
Finished Jan 21 08:29:37 PM PST 24
Peak memory 217268 kb
Host smart-990a6ff1-d0a4-478a-b64f-cafe9ded67bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652607885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3652607885
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4018981604
Short name T1031
Test name
Test status
Simulation time 185990827 ps
CPU time 0.87 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:30 PM PST 24
Peak memory 207204 kb
Host smart-28fe5003-62ba-4648-87dc-ae5c66f0052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018981604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4018981604
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tx_async_fifo_reset.2794186151
Short name T643
Test name
Test status
Simulation time 17312221 ps
CPU time 0.83 seconds
Started Jan 21 08:10:08 PM PST 24
Finished Jan 21 08:10:13 PM PST 24
Peak memory 207684 kb
Host smart-4c947e73-715f-4b71-acf2-c7590c50e54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794186151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tx_async_fifo_reset.2794186151
Directory /workspace/33.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_txrx.1282786446
Short name T519
Test name
Test status
Simulation time 7807682500 ps
CPU time 114.55 seconds
Started Jan 21 08:10:20 PM PST 24
Finished Jan 21 08:12:19 PM PST 24
Peak memory 268556 kb
Host smart-021a49f4-ae67-4718-9f52-e1863b8cc25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282786446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_txrx.1282786446
Directory /workspace/33.spi_device_txrx/latest

Test location /workspace/coverage/default/33.spi_device_upload.3762218789
Short name T926
Test name
Test status
Simulation time 4659771854 ps
CPU time 17.49 seconds
Started Jan 21 08:42:16 PM PST 24
Finished Jan 21 08:42:34 PM PST 24
Peak memory 234808 kb
Host smart-ab411034-ebc2-4bd5-81c7-e7bfb1cce6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762218789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3762218789
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_abort.2329327498
Short name T685
Test name
Test status
Simulation time 76557474 ps
CPU time 0.73 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:28 PM PST 24
Peak memory 207052 kb
Host smart-efb12a72-b858-419d-ba71-824fe2d1b466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329327498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_abort.2329327498
Directory /workspace/34.spi_device_abort/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.299624592
Short name T101
Test name
Test status
Simulation time 89545210 ps
CPU time 0.73 seconds
Started Jan 21 08:10:33 PM PST 24
Finished Jan 21 08:10:38 PM PST 24
Peak memory 206996 kb
Host smart-37a7c421-df9d-4eb3-898e-22252551e845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299624592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.299624592
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_bit_transfer.261544424
Short name T978
Test name
Test status
Simulation time 1054791858 ps
CPU time 2.75 seconds
Started Jan 21 08:10:28 PM PST 24
Finished Jan 21 08:10:33 PM PST 24
Peak memory 217152 kb
Host smart-f8b021ef-a861-46ee-8713-2dc73044493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261544424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_bit_transfer.261544424
Directory /workspace/34.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/34.spi_device_byte_transfer.2396750839
Short name T1132
Test name
Test status
Simulation time 683779553 ps
CPU time 3.43 seconds
Started Jan 21 08:10:20 PM PST 24
Finished Jan 21 08:10:27 PM PST 24
Peak memory 217264 kb
Host smart-24b4896a-062e-4ad4-a6df-ae3b310e9165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396750839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_byte_transfer.2396750839
Directory /workspace/34.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4138322809
Short name T1382
Test name
Test status
Simulation time 833085991 ps
CPU time 4.79 seconds
Started Jan 21 08:10:28 PM PST 24
Finished Jan 21 08:10:35 PM PST 24
Peak memory 241812 kb
Host smart-ea161810-6ebc-4f67-9413-8f8bb13bf240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138322809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4138322809
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.151925279
Short name T1100
Test name
Test status
Simulation time 133882674 ps
CPU time 0.81 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:29 PM PST 24
Peak memory 208012 kb
Host smart-02ff756f-1c8e-4923-be60-ef92c127caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151925279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.151925279
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_extreme_fifo_size.186004765
Short name T1280
Test name
Test status
Simulation time 38753180736 ps
CPU time 69.15 seconds
Started Jan 21 08:10:11 PM PST 24
Finished Jan 21 08:11:25 PM PST 24
Peak memory 237320 kb
Host smart-b7aeff36-2707-4eb6-8a22-ee7404155456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186004765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_extreme_fifo_size.186004765
Directory /workspace/34.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/34.spi_device_fifo_full.3016958869
Short name T905
Test name
Test status
Simulation time 29261573334 ps
CPU time 457.77 seconds
Started Jan 21 08:10:11 PM PST 24
Finished Jan 21 08:17:53 PM PST 24
Peak memory 274556 kb
Host smart-1c3ba2e9-a9f0-46cb-ab6f-64842b44171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016958869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_full.3016958869
Directory /workspace/34.spi_device_fifo_full/latest

Test location /workspace/coverage/default/34.spi_device_fifo_underflow_overflow.1125235930
Short name T1173
Test name
Test status
Simulation time 74788794737 ps
CPU time 280.52 seconds
Started Jan 21 08:10:10 PM PST 24
Finished Jan 21 08:14:54 PM PST 24
Peak memory 400028 kb
Host smart-43fae35f-f2df-4277-beec-bb5fea5d81d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125235930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_underflow_overf
low.1125235930
Directory /workspace/34.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1556852227
Short name T269
Test name
Test status
Simulation time 5670250582 ps
CPU time 57 seconds
Started Jan 21 08:10:37 PM PST 24
Finished Jan 21 08:11:36 PM PST 24
Peak memory 267804 kb
Host smart-a5be7cb8-916e-459d-82dd-ea63abc81f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556852227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1556852227
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3608045084
Short name T1522
Test name
Test status
Simulation time 806899624587 ps
CPU time 494.51 seconds
Started Jan 21 08:10:32 PM PST 24
Finished Jan 21 08:18:51 PM PST 24
Peak memory 274068 kb
Host smart-7b854695-a88c-452d-aabb-2265fa638c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608045084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3608045084
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2001757153
Short name T350
Test name
Test status
Simulation time 43098248801 ps
CPU time 187.61 seconds
Started Jan 21 08:48:14 PM PST 24
Finished Jan 21 08:51:39 PM PST 24
Peak memory 274856 kb
Host smart-72ef87a9-2f20-4987-bdc9-70e7f18c72cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001757153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2001757153
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2197791891
Short name T1671
Test name
Test status
Simulation time 339213768 ps
CPU time 10.44 seconds
Started Jan 21 08:10:33 PM PST 24
Finished Jan 21 08:10:47 PM PST 24
Peak memory 252520 kb
Host smart-fdc9f01f-83f0-4191-b368-c69771eb32a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197791891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2197791891
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3842209721
Short name T1403
Test name
Test status
Simulation time 1234945714 ps
CPU time 6.99 seconds
Started Jan 21 08:24:13 PM PST 24
Finished Jan 21 08:24:21 PM PST 24
Peak memory 220804 kb
Host smart-f1302cdc-a955-45d4-8ad8-e4178663612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842209721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3842209721
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intr.2670586637
Short name T547
Test name
Test status
Simulation time 89298414909 ps
CPU time 100.31 seconds
Started Jan 21 08:10:20 PM PST 24
Finished Jan 21 08:12:04 PM PST 24
Peak memory 236848 kb
Host smart-9bf8c232-0866-4cf6-84e3-99916ab82f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670586637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intr.2670586637
Directory /workspace/34.spi_device_intr/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.271266714
Short name T258
Test name
Test status
Simulation time 13914236422 ps
CPU time 11.36 seconds
Started Jan 21 08:10:32 PM PST 24
Finished Jan 21 08:10:47 PM PST 24
Peak memory 222904 kb
Host smart-a872d8ab-4252-453b-80d4-93c90e85ba95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271266714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.271266714
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3919026758
Short name T1317
Test name
Test status
Simulation time 14047972432 ps
CPU time 12.81 seconds
Started Jan 21 09:12:23 PM PST 24
Finished Jan 21 09:12:40 PM PST 24
Peak memory 248408 kb
Host smart-ec566195-ec2d-4bcf-a5cc-5626fcfba5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919026758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3919026758
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1169975568
Short name T1411
Test name
Test status
Simulation time 58303870 ps
CPU time 2.97 seconds
Started Jan 21 08:10:28 PM PST 24
Finished Jan 21 08:10:34 PM PST 24
Peak memory 234764 kb
Host smart-fe3acb70-c3bd-4d90-9ab6-616d4fc8db4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169975568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1169975568
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_perf.4152464013
Short name T1663
Test name
Test status
Simulation time 32036798244 ps
CPU time 867.06 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:24:55 PM PST 24
Peak memory 252168 kb
Host smart-16e6e269-2227-44a4-83b1-41e956b32312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152464013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_perf.4152464013
Directory /workspace/34.spi_device_perf/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.740887380
Short name T205
Test name
Test status
Simulation time 81882071 ps
CPU time 3.92 seconds
Started Jan 21 08:46:09 PM PST 24
Finished Jan 21 08:47:00 PM PST 24
Peak memory 234656 kb
Host smart-ae90488f-a873-41dc-825d-63b6ece11062
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=740887380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.740887380
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_rx_async_fifo_reset.3863167835
Short name T148
Test name
Test status
Simulation time 31006436 ps
CPU time 0.9 seconds
Started Jan 21 08:10:24 PM PST 24
Finished Jan 21 08:10:26 PM PST 24
Peak memory 208812 kb
Host smart-aa6b86ec-d1bf-45d7-9792-31c0ea041220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863167835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_async_fifo_reset.3863167835
Directory /workspace/34.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_rx_timeout.1192395983
Short name T974
Test name
Test status
Simulation time 1328140294 ps
CPU time 6.72 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:35 PM PST 24
Peak memory 217236 kb
Host smart-a83f988d-cf3d-4430-9a60-cab519b4b80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192395983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_timeout.1192395983
Directory /workspace/34.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/34.spi_device_smoke.1087412852
Short name T642
Test name
Test status
Simulation time 49460890 ps
CPU time 1.13 seconds
Started Jan 21 08:10:09 PM PST 24
Finished Jan 21 08:10:14 PM PST 24
Peak memory 208748 kb
Host smart-2c6d6283-4f24-4893-be0e-666669cd0b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087412852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_smoke.1087412852
Directory /workspace/34.spi_device_smoke/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1057248705
Short name T1484
Test name
Test status
Simulation time 22360548509 ps
CPU time 61.73 seconds
Started Jan 21 08:10:19 PM PST 24
Finished Jan 21 08:11:25 PM PST 24
Peak memory 217368 kb
Host smart-f468ff87-5283-46ce-9c56-53b39dc6f190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057248705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1057248705
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1208153223
Short name T496
Test name
Test status
Simulation time 3756124920 ps
CPU time 8.79 seconds
Started Jan 21 08:54:01 PM PST 24
Finished Jan 21 08:54:23 PM PST 24
Peak memory 217316 kb
Host smart-c73fe62f-3264-4065-9902-b936e21bd2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208153223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1208153223
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3302205213
Short name T591
Test name
Test status
Simulation time 39578623 ps
CPU time 1.41 seconds
Started Jan 21 08:10:25 PM PST 24
Finished Jan 21 08:10:28 PM PST 24
Peak memory 217296 kb
Host smart-cf70db85-261d-4f4b-b6a5-8f5fda27a3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302205213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3302205213
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3882115043
Short name T1277
Test name
Test status
Simulation time 24480544 ps
CPU time 0.79 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:28 PM PST 24
Peak memory 207204 kb
Host smart-5a61019b-1593-43b8-a4b4-2dd6205b5ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882115043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3882115043
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tx_async_fifo_reset.449009511
Short name T710
Test name
Test status
Simulation time 50304582 ps
CPU time 0.81 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:29 PM PST 24
Peak memory 208808 kb
Host smart-0af68054-11ef-49fd-9132-42315902651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449009511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tx_async_fifo_reset.449009511
Directory /workspace/34.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_txrx.187174344
Short name T886
Test name
Test status
Simulation time 137965203241 ps
CPU time 456.16 seconds
Started Jan 21 08:10:28 PM PST 24
Finished Jan 21 08:18:07 PM PST 24
Peak memory 271876 kb
Host smart-c6688a56-fb61-4c27-8419-b651131a2f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187174344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_txrx.187174344
Directory /workspace/34.spi_device_txrx/latest

Test location /workspace/coverage/default/34.spi_device_upload.716628008
Short name T1345
Test name
Test status
Simulation time 1548207417 ps
CPU time 11.2 seconds
Started Jan 21 08:10:24 PM PST 24
Finished Jan 21 08:10:37 PM PST 24
Peak memory 227408 kb
Host smart-46d96bca-e0dd-404b-a691-283aa68173a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716628008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.716628008
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_abort.2531821778
Short name T674
Test name
Test status
Simulation time 25107744 ps
CPU time 0.73 seconds
Started Jan 21 08:11:02 PM PST 24
Finished Jan 21 08:11:07 PM PST 24
Peak memory 206916 kb
Host smart-7a1de8d8-35bb-46a4-8ced-53bf7aaad2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531821778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_abort.2531821778
Directory /workspace/35.spi_device_abort/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4237080233
Short name T1661
Test name
Test status
Simulation time 22887200 ps
CPU time 0.79 seconds
Started Jan 21 08:11:04 PM PST 24
Finished Jan 21 08:11:08 PM PST 24
Peak memory 206968 kb
Host smart-323423a2-430b-4f56-b431-a7155eed0baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237080233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4237080233
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_bit_transfer.1324014649
Short name T509
Test name
Test status
Simulation time 477327982 ps
CPU time 3.1 seconds
Started Jan 21 08:10:47 PM PST 24
Finished Jan 21 08:10:53 PM PST 24
Peak memory 217208 kb
Host smart-f936eca3-c188-468d-bf68-8cc43dca7392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324014649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_bit_transfer.1324014649
Directory /workspace/35.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/35.spi_device_byte_transfer.4194631643
Short name T1500
Test name
Test status
Simulation time 154748503 ps
CPU time 3.19 seconds
Started Jan 21 08:10:51 PM PST 24
Finished Jan 21 08:10:57 PM PST 24
Peak memory 217228 kb
Host smart-895cbf08-7c8b-468e-bad4-16c6f28b26e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194631643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_byte_transfer.4194631643
Directory /workspace/35.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4283306232
Short name T1378
Test name
Test status
Simulation time 1054888146 ps
CPU time 6.37 seconds
Started Jan 21 08:11:05 PM PST 24
Finished Jan 21 08:11:16 PM PST 24
Peak memory 241876 kb
Host smart-aa692ed0-fe8b-4362-a818-05945da4f715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283306232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4283306232
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.674269273
Short name T1022
Test name
Test status
Simulation time 14433140 ps
CPU time 0.81 seconds
Started Jan 21 08:10:46 PM PST 24
Finished Jan 21 08:10:50 PM PST 24
Peak memory 207020 kb
Host smart-f36c2e37-7308-41d4-8485-a154e73d0908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674269273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.674269273
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_dummy_item_extra_dly.4158787898
Short name T1131
Test name
Test status
Simulation time 84471481884 ps
CPU time 210.55 seconds
Started Jan 21 08:10:45 PM PST 24
Finished Jan 21 08:14:19 PM PST 24
Peak memory 273532 kb
Host smart-e9dba239-2c72-4b24-b3d1-89c38981d250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158787898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_dummy_item_extra_dly.4158787898
Directory /workspace/35.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/35.spi_device_extreme_fifo_size.1090843282
Short name T1010
Test name
Test status
Simulation time 83611431523 ps
CPU time 3807.96 seconds
Started Jan 21 08:10:51 PM PST 24
Finished Jan 21 09:14:22 PM PST 24
Peak memory 221584 kb
Host smart-ea2c31e1-a2d9-47b1-bced-3f01da3ea004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090843282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_extreme_fifo_size.1090843282
Directory /workspace/35.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/35.spi_device_fifo_full.1439236761
Short name T1228
Test name
Test status
Simulation time 158822652739 ps
CPU time 734.07 seconds
Started Jan 21 08:10:46 PM PST 24
Finished Jan 21 08:23:02 PM PST 24
Peak memory 267720 kb
Host smart-c33a3e68-73e1-45f8-a0ea-73bd50208ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439236761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_full.1439236761
Directory /workspace/35.spi_device_fifo_full/latest

Test location /workspace/coverage/default/35.spi_device_fifo_underflow_overflow.2149620405
Short name T910
Test name
Test status
Simulation time 145107513197 ps
CPU time 682.45 seconds
Started Jan 21 08:10:47 PM PST 24
Finished Jan 21 08:22:13 PM PST 24
Peak memory 510132 kb
Host smart-62dfd2ec-38c0-452b-9222-3d39f307e4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149620405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_underflow_overf
low.2149620405
Directory /workspace/35.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2486634101
Short name T250
Test name
Test status
Simulation time 539741018801 ps
CPU time 689.66 seconds
Started Jan 21 08:11:05 PM PST 24
Finished Jan 21 08:22:39 PM PST 24
Peak memory 270472 kb
Host smart-b892565a-997b-4bf7-9c99-64fe70b36988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486634101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2486634101
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1047890175
Short name T119
Test name
Test status
Simulation time 100542381145 ps
CPU time 509.65 seconds
Started Jan 21 08:11:06 PM PST 24
Finished Jan 21 08:19:42 PM PST 24
Peak memory 263896 kb
Host smart-dc8fd7d0-c83d-4b6d-930b-59523194c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047890175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1047890175
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3861518640
Short name T206
Test name
Test status
Simulation time 8544418803 ps
CPU time 11.33 seconds
Started Jan 21 08:11:04 PM PST 24
Finished Jan 21 08:11:19 PM PST 24
Peak memory 249628 kb
Host smart-47d709f1-6a7b-4cc1-ab87-e21310730d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861518640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3861518640
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.774873118
Short name T1239
Test name
Test status
Simulation time 767261384 ps
CPU time 5.74 seconds
Started Jan 21 08:11:10 PM PST 24
Finished Jan 21 08:11:20 PM PST 24
Peak memory 225488 kb
Host smart-2708713f-619d-4dd4-b336-f0e0e79a8e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774873118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.774873118
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intr.1283250466
Short name T876
Test name
Test status
Simulation time 35238630009 ps
CPU time 135.59 seconds
Started Jan 21 08:10:45 PM PST 24
Finished Jan 21 08:13:03 PM PST 24
Peak memory 250012 kb
Host smart-d96ff252-f919-4d62-8931-35f4b6593bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283250466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intr.1283250466
Directory /workspace/35.spi_device_intr/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4068889221
Short name T280
Test name
Test status
Simulation time 9518983852 ps
CPU time 11.15 seconds
Started Jan 21 08:11:02 PM PST 24
Finished Jan 21 08:11:18 PM PST 24
Peak memory 219152 kb
Host smart-42c4f24c-5e83-4a7b-a625-793d6a08ce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068889221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4068889221
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.958919749
Short name T1723
Test name
Test status
Simulation time 4055459208 ps
CPU time 14.99 seconds
Started Jan 21 08:11:02 PM PST 24
Finished Jan 21 08:11:22 PM PST 24
Peak memory 233800 kb
Host smart-c8d9a103-d23d-44ab-ab3c-40893c1f5e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958919749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.958919749
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2257765117
Short name T1148
Test name
Test status
Simulation time 776994881 ps
CPU time 4.24 seconds
Started Jan 21 08:11:02 PM PST 24
Finished Jan 21 08:11:11 PM PST 24
Peak memory 241396 kb
Host smart-98893057-eea8-420e-9334-a331345421f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257765117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2257765117
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_perf.811423786
Short name T1520
Test name
Test status
Simulation time 13505625824 ps
CPU time 405.73 seconds
Started Jan 21 08:10:46 PM PST 24
Finished Jan 21 08:17:34 PM PST 24
Peak memory 315468 kb
Host smart-1cd1aabe-b881-41c1-9efe-006a209bd408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811423786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_perf.811423786
Directory /workspace/35.spi_device_perf/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2104129571
Short name T779
Test name
Test status
Simulation time 871859252 ps
CPU time 6.49 seconds
Started Jan 21 08:11:03 PM PST 24
Finished Jan 21 08:11:14 PM PST 24
Peak memory 234900 kb
Host smart-2f69101c-6964-46be-8b9b-769c3f4bd7b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2104129571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2104129571
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_rx_async_fifo_reset.1413437627
Short name T709
Test name
Test status
Simulation time 240385557 ps
CPU time 0.98 seconds
Started Jan 21 08:10:57 PM PST 24
Finished Jan 21 08:11:04 PM PST 24
Peak memory 208828 kb
Host smart-245045ea-b1f1-4262-96a3-2ec5e47ff21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413437627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_async_fifo_reset.1413437627
Directory /workspace/35.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_rx_timeout.540090475
Short name T657
Test name
Test status
Simulation time 3406077341 ps
CPU time 6.85 seconds
Started Jan 21 08:10:46 PM PST 24
Finished Jan 21 08:10:56 PM PST 24
Peak memory 217264 kb
Host smart-376fb34c-3b76-4cf6-830c-c8345a987580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540090475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_timeout.540090475
Directory /workspace/35.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/35.spi_device_smoke.3503974487
Short name T16
Test name
Test status
Simulation time 115750484 ps
CPU time 1.19 seconds
Started Jan 21 08:10:32 PM PST 24
Finished Jan 21 08:10:37 PM PST 24
Peak memory 216940 kb
Host smart-9ee810a7-742a-45ed-b72f-738b90e26790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503974487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_smoke.3503974487
Directory /workspace/35.spi_device_smoke/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.624810374
Short name T780
Test name
Test status
Simulation time 1397132845 ps
CPU time 3.6 seconds
Started Jan 21 08:10:59 PM PST 24
Finished Jan 21 08:11:10 PM PST 24
Peak memory 217340 kb
Host smart-0fa6af39-cb38-4b01-8a1e-c04e5693db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624810374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.624810374
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1832571992
Short name T958
Test name
Test status
Simulation time 21748326635 ps
CPU time 14.91 seconds
Started Jan 21 08:10:44 PM PST 24
Finished Jan 21 08:11:01 PM PST 24
Peak memory 217352 kb
Host smart-fde74e97-20d4-47e5-bc63-440dfff328bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832571992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1832571992
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2191771585
Short name T1176
Test name
Test status
Simulation time 860007121 ps
CPU time 2.18 seconds
Started Jan 21 08:11:02 PM PST 24
Finished Jan 21 08:11:09 PM PST 24
Peak memory 217320 kb
Host smart-9886725c-8797-44a7-935b-59dafa507808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191771585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2191771585
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2160042440
Short name T768
Test name
Test status
Simulation time 15210970 ps
CPU time 0.75 seconds
Started Jan 21 08:10:57 PM PST 24
Finished Jan 21 08:11:04 PM PST 24
Peak memory 207256 kb
Host smart-893d1c0b-f40c-42a3-9454-671b19a57d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160042440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2160042440
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tx_async_fifo_reset.3391383918
Short name T874
Test name
Test status
Simulation time 32579647 ps
CPU time 0.8 seconds
Started Jan 21 08:10:43 PM PST 24
Finished Jan 21 08:10:45 PM PST 24
Peak memory 208740 kb
Host smart-64116d75-cf06-4e3b-8d3b-db3c88617b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391383918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tx_async_fifo_reset.3391383918
Directory /workspace/35.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_txrx.2896537271
Short name T1632
Test name
Test status
Simulation time 105596685923 ps
CPU time 226.04 seconds
Started Jan 21 08:10:45 PM PST 24
Finished Jan 21 08:14:34 PM PST 24
Peak memory 300652 kb
Host smart-b3aaea3e-3666-4341-bcd7-2217cf89845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896537271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_txrx.2896537271
Directory /workspace/35.spi_device_txrx/latest

Test location /workspace/coverage/default/35.spi_device_upload.3646074535
Short name T675
Test name
Test status
Simulation time 5335756889 ps
CPU time 26.52 seconds
Started Jan 21 08:11:06 PM PST 24
Finished Jan 21 08:11:37 PM PST 24
Peak memory 239292 kb
Host smart-838c096e-ce00-419d-bd66-6a05255214c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646074535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3646074535
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_abort.3674552306
Short name T1662
Test name
Test status
Simulation time 44738498 ps
CPU time 0.76 seconds
Started Jan 21 08:11:31 PM PST 24
Finished Jan 21 08:11:35 PM PST 24
Peak memory 207080 kb
Host smart-8dcc43ab-6324-4e88-8ef8-03fa50090b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674552306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_abort.3674552306
Directory /workspace/36.spi_device_abort/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2412691354
Short name T1437
Test name
Test status
Simulation time 13546997 ps
CPU time 0.77 seconds
Started Jan 21 08:11:25 PM PST 24
Finished Jan 21 08:11:30 PM PST 24
Peak memory 207004 kb
Host smart-96fc0006-60b4-4da9-a559-4bb7afd2e132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412691354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2412691354
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_bit_transfer.3959839496
Short name T1115
Test name
Test status
Simulation time 363858105 ps
CPU time 3.07 seconds
Started Jan 21 08:11:20 PM PST 24
Finished Jan 21 08:11:28 PM PST 24
Peak memory 217212 kb
Host smart-b4faa0eb-ced1-4323-b694-c3e96797c6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959839496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_bit_transfer.3959839496
Directory /workspace/36.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/36.spi_device_byte_transfer.1980638672
Short name T1594
Test name
Test status
Simulation time 147010675 ps
CPU time 3.03 seconds
Started Jan 21 08:11:16 PM PST 24
Finished Jan 21 08:11:28 PM PST 24
Peak memory 217300 kb
Host smart-873f621b-0b8b-4fbf-ba15-81599a34bd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980638672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_byte_transfer.1980638672
Directory /workspace/36.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.61788952
Short name T784
Test name
Test status
Simulation time 1863114421 ps
CPU time 4.85 seconds
Started Jan 21 08:11:29 PM PST 24
Finished Jan 21 08:11:37 PM PST 24
Peak memory 218908 kb
Host smart-9fd146a8-4b7d-40c6-93a9-abd61c1b9959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61788952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.61788952
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3383549909
Short name T959
Test name
Test status
Simulation time 19884270 ps
CPU time 0.85 seconds
Started Jan 21 08:11:16 PM PST 24
Finished Jan 21 08:11:25 PM PST 24
Peak memory 208064 kb
Host smart-0cfba623-7524-4155-8e2c-6c249b56296d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383549909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3383549909
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_dummy_item_extra_dly.3748280270
Short name T1156
Test name
Test status
Simulation time 57825711389 ps
CPU time 518.02 seconds
Started Jan 21 08:11:16 PM PST 24
Finished Jan 21 08:20:03 PM PST 24
Peak memory 254604 kb
Host smart-10b7fd63-f5f3-49ba-9d9f-b71a1acd9931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748280270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_dummy_item_extra_dly.3748280270
Directory /workspace/36.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/36.spi_device_extreme_fifo_size.2360256101
Short name T292
Test name
Test status
Simulation time 4681861974 ps
CPU time 32.67 seconds
Started Jan 21 08:11:19 PM PST 24
Finished Jan 21 08:11:57 PM PST 24
Peak memory 231088 kb
Host smart-6ec93bc2-c694-4240-aef5-9cdb00e7a850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360256101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_extreme_fifo_size.2360256101
Directory /workspace/36.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/36.spi_device_fifo_full.3418424585
Short name T1539
Test name
Test status
Simulation time 23972653446 ps
CPU time 1317.1 seconds
Started Jan 21 08:11:16 PM PST 24
Finished Jan 21 08:33:22 PM PST 24
Peak memory 252340 kb
Host smart-338c6f24-2b6b-4848-a7a0-87e8ec71604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418424585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_full.3418424585
Directory /workspace/36.spi_device_fifo_full/latest

Test location /workspace/coverage/default/36.spi_device_fifo_underflow_overflow.2427130612
Short name T736
Test name
Test status
Simulation time 205197458952 ps
CPU time 1102.18 seconds
Started Jan 21 08:11:19 PM PST 24
Finished Jan 21 08:29:47 PM PST 24
Peak memory 554204 kb
Host smart-657eb745-2178-4839-b8a7-76603e15cf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427130612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_underflow_overf
low.2427130612
Directory /workspace/36.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4070245131
Short name T278
Test name
Test status
Simulation time 26268312462 ps
CPU time 81.21 seconds
Started Jan 21 08:11:31 PM PST 24
Finished Jan 21 08:12:56 PM PST 24
Peak memory 258404 kb
Host smart-b76d0612-19ca-468f-a5dd-8be459433f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070245131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4070245131
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.672332350
Short name T345
Test name
Test status
Simulation time 93670544923 ps
CPU time 531.32 seconds
Started Jan 21 08:33:46 PM PST 24
Finished Jan 21 08:42:42 PM PST 24
Peak memory 267176 kb
Host smart-e2120928-db56-48ed-8397-ad9ba3a433fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672332350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.672332350
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2984444079
Short name T268
Test name
Test status
Simulation time 37041168097 ps
CPU time 92.82 seconds
Started Jan 21 08:11:29 PM PST 24
Finished Jan 21 08:13:04 PM PST 24
Peak memory 267388 kb
Host smart-dd7d7318-20cb-446e-babc-737748d23789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984444079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2984444079
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1552091372
Short name T1372
Test name
Test status
Simulation time 6570715383 ps
CPU time 27.78 seconds
Started Jan 21 08:30:39 PM PST 24
Finished Jan 21 08:31:12 PM PST 24
Peak memory 255144 kb
Host smart-268ee89c-fc0c-411c-938e-c73965d76e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552091372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1552091372
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.524676559
Short name T308
Test name
Test status
Simulation time 780853493 ps
CPU time 4.47 seconds
Started Jan 21 08:11:29 PM PST 24
Finished Jan 21 08:11:37 PM PST 24
Peak memory 239680 kb
Host smart-90362ef9-c96f-43fc-8d46-dc563c3d3e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524676559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.524676559
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intr.691353956
Short name T1576
Test name
Test status
Simulation time 26343285321 ps
CPU time 24.57 seconds
Started Jan 21 08:11:16 PM PST 24
Finished Jan 21 08:11:49 PM PST 24
Peak memory 218396 kb
Host smart-6b145676-3273-4b48-9e25-d975c20c4201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691353956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intr.691353956
Directory /workspace/36.spi_device_intr/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4205324825
Short name T334
Test name
Test status
Simulation time 44411495481 ps
CPU time 34.79 seconds
Started Jan 21 08:11:30 PM PST 24
Finished Jan 21 08:12:08 PM PST 24
Peak memory 235608 kb
Host smart-07a7cce3-a66f-4201-aa52-66a91cd3b970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205324825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4205324825
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.856715349
Short name T803
Test name
Test status
Simulation time 569838626 ps
CPU time 5.42 seconds
Started Jan 21 08:11:29 PM PST 24
Finished Jan 21 08:11:37 PM PST 24
Peak memory 219524 kb
Host smart-ee9186cd-0221-4dba-8941-a5115a7e9d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856715349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.856715349
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1101116731
Short name T624
Test name
Test status
Simulation time 2997617440 ps
CPU time 6.39 seconds
Started Jan 21 08:11:27 PM PST 24
Finished Jan 21 08:11:37 PM PST 24
Peak memory 233936 kb
Host smart-80ec2a9c-0f5d-4ce7-9b18-7489b8a77024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101116731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1101116731
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1616199819
Short name T1545
Test name
Test status
Simulation time 1811625751 ps
CPU time 4.22 seconds
Started Jan 21 08:24:54 PM PST 24
Finished Jan 21 08:25:00 PM PST 24
Peak memory 218992 kb
Host smart-1602c04a-64e3-4f85-bfb4-3e8a97aa3097
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1616199819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1616199819
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_rx_async_fifo_reset.1941524886
Short name T774
Test name
Test status
Simulation time 17835984 ps
CPU time 0.9 seconds
Started Jan 21 08:11:24 PM PST 24
Finished Jan 21 08:11:30 PM PST 24
Peak memory 208796 kb
Host smart-58231f79-f997-4d37-8c83-a8e96caca418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941524886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_async_fifo_reset.1941524886
Directory /workspace/36.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_rx_timeout.875442272
Short name T604
Test name
Test status
Simulation time 2679825966 ps
CPU time 5.8 seconds
Started Jan 21 08:11:15 PM PST 24
Finished Jan 21 08:11:28 PM PST 24
Peak memory 217292 kb
Host smart-b2729d7f-fc7d-410a-b81a-86dda68849dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875442272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_timeout.875442272
Directory /workspace/36.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/36.spi_device_smoke.3562970267
Short name T1318
Test name
Test status
Simulation time 78348595 ps
CPU time 1.31 seconds
Started Jan 21 08:11:06 PM PST 24
Finished Jan 21 08:11:13 PM PST 24
Peak memory 217228 kb
Host smart-58b4d200-5a4d-4685-9d43-427cc4c4e5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562970267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_smoke.3562970267
Directory /workspace/36.spi_device_smoke/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2828260329
Short name T1145
Test name
Test status
Simulation time 165698248075 ps
CPU time 1527.41 seconds
Started Jan 21 08:11:24 PM PST 24
Finished Jan 21 08:36:57 PM PST 24
Peak memory 332532 kb
Host smart-d72c467f-eb52-43c3-a1a8-ed7771716af4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828260329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2828260329
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.555198469
Short name T622
Test name
Test status
Simulation time 400695095 ps
CPU time 7.21 seconds
Started Jan 21 08:11:16 PM PST 24
Finished Jan 21 08:11:32 PM PST 24
Peak memory 217360 kb
Host smart-b6879616-e12b-4111-b7f9-3e0d5d39e056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555198469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.555198469
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1557793317
Short name T495
Test name
Test status
Simulation time 6758328236 ps
CPU time 12.09 seconds
Started Jan 21 08:11:15 PM PST 24
Finished Jan 21 08:11:33 PM PST 24
Peak memory 217316 kb
Host smart-6e495ea7-1846-40a1-af58-bb2ee36092c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557793317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1557793317
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3346269780
Short name T1558
Test name
Test status
Simulation time 13385802 ps
CPU time 0.79 seconds
Started Jan 21 08:11:30 PM PST 24
Finished Jan 21 08:11:33 PM PST 24
Peak memory 207308 kb
Host smart-563263f7-4d0c-45ea-a1ef-3481664a446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346269780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3346269780
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2769370072
Short name T1578
Test name
Test status
Simulation time 81619359 ps
CPU time 1.02 seconds
Started Jan 21 08:11:29 PM PST 24
Finished Jan 21 08:11:33 PM PST 24
Peak memory 208320 kb
Host smart-077910ca-7a6c-4f2d-84b6-910b80d845ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769370072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2769370072
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tx_async_fifo_reset.1896575094
Short name T94
Test name
Test status
Simulation time 44682102 ps
CPU time 0.81 seconds
Started Jan 21 08:11:16 PM PST 24
Finished Jan 21 08:11:25 PM PST 24
Peak memory 208764 kb
Host smart-a5dbf44d-658a-4c9f-a6d8-b38bff552d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896575094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tx_async_fifo_reset.1896575094
Directory /workspace/36.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_txrx.941950573
Short name T1294
Test name
Test status
Simulation time 12879829087 ps
CPU time 196.43 seconds
Started Jan 21 08:11:25 PM PST 24
Finished Jan 21 08:14:46 PM PST 24
Peak memory 271104 kb
Host smart-f6305af7-1ad3-438a-8248-84946ec42f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941950573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_txrx.941950573
Directory /workspace/36.spi_device_txrx/latest

Test location /workspace/coverage/default/36.spi_device_upload.907421797
Short name T1553
Test name
Test status
Simulation time 75280463 ps
CPU time 3.09 seconds
Started Jan 21 08:25:51 PM PST 24
Finished Jan 21 08:25:56 PM PST 24
Peak memory 233744 kb
Host smart-362680f3-aa91-461f-bed9-f148e704ed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907421797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.907421797
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_abort.3333743554
Short name T1361
Test name
Test status
Simulation time 55257269 ps
CPU time 0.78 seconds
Started Jan 21 08:11:36 PM PST 24
Finished Jan 21 08:11:40 PM PST 24
Peak memory 207100 kb
Host smart-bec64e0e-366b-451b-98a2-c7b5ba851a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333743554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_abort.3333743554
Directory /workspace/37.spi_device_abort/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4250273409
Short name T553
Test name
Test status
Simulation time 77663352 ps
CPU time 0.74 seconds
Started Jan 21 08:11:52 PM PST 24
Finished Jan 21 08:11:57 PM PST 24
Peak memory 206980 kb
Host smart-22736a82-8bf4-4daa-9a35-b29d5d8d5e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250273409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4250273409
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_bit_transfer.147030011
Short name T671
Test name
Test status
Simulation time 219822824 ps
CPU time 3.21 seconds
Started Jan 21 08:11:39 PM PST 24
Finished Jan 21 08:11:44 PM PST 24
Peak memory 217192 kb
Host smart-2c72f244-cb77-47f8-9c7c-f796bfa1dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147030011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_bit_transfer.147030011
Directory /workspace/37.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/37.spi_device_byte_transfer.889197573
Short name T1284
Test name
Test status
Simulation time 838917957 ps
CPU time 3.47 seconds
Started Jan 21 08:11:31 PM PST 24
Finished Jan 21 08:11:38 PM PST 24
Peak memory 217252 kb
Host smart-a9d3ac97-7612-4233-b74f-469ac6389fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889197573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_byte_transfer.889197573
Directory /workspace/37.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2190293038
Short name T737
Test name
Test status
Simulation time 96546569 ps
CPU time 3.32 seconds
Started Jan 21 08:11:52 PM PST 24
Finished Jan 21 08:12:00 PM PST 24
Peak memory 239908 kb
Host smart-ef55dc93-41b4-47af-af3f-7f7730adac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190293038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2190293038
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3336061200
Short name T1709
Test name
Test status
Simulation time 19123635 ps
CPU time 0.78 seconds
Started Jan 21 08:11:30 PM PST 24
Finished Jan 21 08:11:33 PM PST 24
Peak memory 206984 kb
Host smart-f6891e3f-b986-47ca-a358-6d8dc7ed1ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336061200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3336061200
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_dummy_item_extra_dly.1376788151
Short name T1023
Test name
Test status
Simulation time 95325760268 ps
CPU time 181.68 seconds
Started Jan 21 08:11:29 PM PST 24
Finished Jan 21 08:14:34 PM PST 24
Peak memory 297780 kb
Host smart-57a4bf8d-b7d1-4a3d-b527-ba80f6de8855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376788151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_dummy_item_extra_dly.1376788151
Directory /workspace/37.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/37.spi_device_extreme_fifo_size.3826836212
Short name T49
Test name
Test status
Simulation time 292927546715 ps
CPU time 2639.75 seconds
Started Jan 21 08:11:30 PM PST 24
Finished Jan 21 08:55:33 PM PST 24
Peak memory 218436 kb
Host smart-5de9419c-8572-4758-9d13-3e442e36c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826836212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_extreme_fifo_size.3826836212
Directory /workspace/37.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/37.spi_device_fifo_full.1348516578
Short name T1172
Test name
Test status
Simulation time 340546053071 ps
CPU time 662.2 seconds
Started Jan 21 08:11:30 PM PST 24
Finished Jan 21 08:22:35 PM PST 24
Peak memory 301672 kb
Host smart-2bf7f375-838a-4809-b3ab-57dc5dec1b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348516578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_full.1348516578
Directory /workspace/37.spi_device_fifo_full/latest

Test location /workspace/coverage/default/37.spi_device_fifo_underflow_overflow.4097764736
Short name T1109
Test name
Test status
Simulation time 40014361356 ps
CPU time 574.64 seconds
Started Jan 21 08:11:30 PM PST 24
Finished Jan 21 08:21:08 PM PST 24
Peak memory 456112 kb
Host smart-2a36fde8-53f3-400f-bcc4-374fa53d19fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097764736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_underflow_overf
low.4097764736
Directory /workspace/37.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1255839576
Short name T235
Test name
Test status
Simulation time 106212680176 ps
CPU time 96.92 seconds
Started Jan 21 08:11:51 PM PST 24
Finished Jan 21 08:13:33 PM PST 24
Peak memory 258428 kb
Host smart-a3d620ef-812e-4484-81cf-1831f9e8b587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255839576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1255839576
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4291980968
Short name T249
Test name
Test status
Simulation time 49063026984 ps
CPU time 433.99 seconds
Started Jan 21 08:11:52 PM PST 24
Finished Jan 21 08:19:11 PM PST 24
Peak memory 258464 kb
Host smart-25b8c617-7664-4fc6-bd9b-0b7378816b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291980968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4291980968
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1864081905
Short name T903
Test name
Test status
Simulation time 5824462116 ps
CPU time 18.06 seconds
Started Jan 21 08:11:55 PM PST 24
Finished Jan 21 08:12:16 PM PST 24
Peak memory 242012 kb
Host smart-0ff48222-ddf7-4513-ad67-d8e3df54c50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864081905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1864081905
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3744031633
Short name T312
Test name
Test status
Simulation time 332533321 ps
CPU time 4.09 seconds
Started Jan 21 08:11:37 PM PST 24
Finished Jan 21 08:11:44 PM PST 24
Peak memory 226596 kb
Host smart-0651d731-30a0-4dfb-9d74-c6a393861494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744031633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3744031633
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intr.146990946
Short name T1565
Test name
Test status
Simulation time 13585477670 ps
CPU time 15.62 seconds
Started Jan 21 08:36:00 PM PST 24
Finished Jan 21 08:36:16 PM PST 24
Peak memory 219452 kb
Host smart-9fac6ed9-f87d-41d6-a833-e1c08dd82d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146990946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intr.146990946
Directory /workspace/37.spi_device_intr/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2330490563
Short name T973
Test name
Test status
Simulation time 36680005084 ps
CPU time 24.57 seconds
Started Jan 21 08:11:53 PM PST 24
Finished Jan 21 08:12:21 PM PST 24
Peak memory 233892 kb
Host smart-a56ef6a8-dd11-4659-8f6d-f144ef49464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330490563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2330490563
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3717676287
Short name T1548
Test name
Test status
Simulation time 7760338767 ps
CPU time 16.13 seconds
Started Jan 21 08:11:37 PM PST 24
Finished Jan 21 08:11:57 PM PST 24
Peak memory 250248 kb
Host smart-6e049ac6-7340-49ec-9d89-a19d6725f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717676287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3717676287
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1597950783
Short name T290
Test name
Test status
Simulation time 66713996590 ps
CPU time 48.59 seconds
Started Jan 21 08:11:39 PM PST 24
Finished Jan 21 08:12:33 PM PST 24
Peak memory 248960 kb
Host smart-cb771a16-f21d-4359-b0af-986da732e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597950783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1597950783
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_perf.3584141805
Short name T1456
Test name
Test status
Simulation time 17705978489 ps
CPU time 106.15 seconds
Started Jan 21 09:47:08 PM PST 24
Finished Jan 21 09:48:55 PM PST 24
Peak memory 251360 kb
Host smart-79cadc95-bc8e-45b2-841f-629f71565ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584141805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_perf.3584141805
Directory /workspace/37.spi_device_perf/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3366162872
Short name T130
Test name
Test status
Simulation time 250260134 ps
CPU time 4.08 seconds
Started Jan 21 08:11:50 PM PST 24
Finished Jan 21 08:11:59 PM PST 24
Peak memory 220772 kb
Host smart-c46c6e80-b9f1-493f-b9d5-5ae247abf04a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3366162872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3366162872
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_rx_async_fifo_reset.1557613077
Short name T1485
Test name
Test status
Simulation time 92070233 ps
CPU time 0.95 seconds
Started Jan 21 08:11:38 PM PST 24
Finished Jan 21 08:11:42 PM PST 24
Peak memory 208812 kb
Host smart-e2873f56-659b-421c-b41d-6d6c6e6b0387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557613077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_async_fifo_reset.1557613077
Directory /workspace/37.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_rx_timeout.352258253
Short name T1190
Test name
Test status
Simulation time 935861837 ps
CPU time 5.25 seconds
Started Jan 21 08:36:18 PM PST 24
Finished Jan 21 08:36:26 PM PST 24
Peak memory 217364 kb
Host smart-f3f13902-1a5c-42d4-aa16-f5a0a32e678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352258253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_timeout.352258253
Directory /workspace/37.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/37.spi_device_smoke.1815075499
Short name T763
Test name
Test status
Simulation time 262565161 ps
CPU time 1.33 seconds
Started Jan 21 08:11:29 PM PST 24
Finished Jan 21 08:11:34 PM PST 24
Peak memory 217264 kb
Host smart-4b16e997-524a-40e9-8985-2bdd422435cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815075499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_smoke.1815075499
Directory /workspace/37.spi_device_smoke/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3510318754
Short name T1642
Test name
Test status
Simulation time 10916401994 ps
CPU time 53.85 seconds
Started Jan 21 08:11:37 PM PST 24
Finished Jan 21 08:12:33 PM PST 24
Peak memory 222288 kb
Host smart-386413ba-3d12-4604-bcaf-243ea5e23aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510318754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3510318754
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4129885573
Short name T739
Test name
Test status
Simulation time 6379540047 ps
CPU time 6.91 seconds
Started Jan 21 08:42:09 PM PST 24
Finished Jan 21 08:42:17 PM PST 24
Peak memory 217464 kb
Host smart-17d4f4ff-cc4c-4f2f-b8ff-cb3a67f5e593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129885573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4129885573
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.584721114
Short name T1488
Test name
Test status
Simulation time 204843390 ps
CPU time 5.11 seconds
Started Jan 21 08:11:37 PM PST 24
Finished Jan 21 08:11:44 PM PST 24
Peak memory 217304 kb
Host smart-a63077c8-1a19-4f4a-bf62-919e3b8cd60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584721114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.584721114
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4200468271
Short name T1704
Test name
Test status
Simulation time 27696070 ps
CPU time 0.78 seconds
Started Jan 21 08:11:37 PM PST 24
Finished Jan 21 08:11:41 PM PST 24
Peak memory 207232 kb
Host smart-f5cf56e7-8db4-473b-b388-6874bf2e48cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200468271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4200468271
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tx_async_fifo_reset.1758385451
Short name T856
Test name
Test status
Simulation time 16907971 ps
CPU time 0.81 seconds
Started Jan 21 08:11:38 PM PST 24
Finished Jan 21 08:11:41 PM PST 24
Peak memory 208812 kb
Host smart-6868d066-9c48-490e-bcad-d61157d7f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758385451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tx_async_fifo_reset.1758385451
Directory /workspace/37.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_txrx.4010023974
Short name T527
Test name
Test status
Simulation time 6610226937 ps
CPU time 127.05 seconds
Started Jan 21 08:22:41 PM PST 24
Finished Jan 21 08:24:49 PM PST 24
Peak memory 250908 kb
Host smart-8b035cde-041c-4e90-84cc-c2ca608868a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010023974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_txrx.4010023974
Directory /workspace/37.spi_device_txrx/latest

Test location /workspace/coverage/default/37.spi_device_upload.2032069549
Short name T1688
Test name
Test status
Simulation time 4015877527 ps
CPU time 7.23 seconds
Started Jan 21 08:11:52 PM PST 24
Finished Jan 21 08:12:04 PM PST 24
Peak memory 241924 kb
Host smart-ba898d52-f973-4c8c-8e6f-75b3085e78e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032069549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2032069549
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_abort.822244057
Short name T1237
Test name
Test status
Simulation time 40985032 ps
CPU time 0.78 seconds
Started Jan 21 08:12:10 PM PST 24
Finished Jan 21 08:12:13 PM PST 24
Peak memory 207076 kb
Host smart-cb83c562-8304-4a40-a28b-2e75149af8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822244057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_abort.822244057
Directory /workspace/38.spi_device_abort/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3552763401
Short name T1554
Test name
Test status
Simulation time 21756844 ps
CPU time 0.74 seconds
Started Jan 21 08:12:17 PM PST 24
Finished Jan 21 08:12:23 PM PST 24
Peak memory 206980 kb
Host smart-209c8dee-3c95-445d-913a-10c04a43f464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552763401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3552763401
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_bit_transfer.2507581714
Short name T1232
Test name
Test status
Simulation time 464674669 ps
CPU time 2.44 seconds
Started Jan 21 08:12:11 PM PST 24
Finished Jan 21 08:12:16 PM PST 24
Peak memory 217372 kb
Host smart-e5b44a3a-4c24-46db-9da7-d88fd0de08f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507581714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_bit_transfer.2507581714
Directory /workspace/38.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/38.spi_device_byte_transfer.2442030365
Short name T1538
Test name
Test status
Simulation time 693345288 ps
CPU time 3.49 seconds
Started Jan 21 08:12:03 PM PST 24
Finished Jan 21 08:12:08 PM PST 24
Peak memory 217236 kb
Host smart-9b7b1821-ea3a-48c5-8c9a-12b7ba831b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442030365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_byte_transfer.2442030365
Directory /workspace/38.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1929661576
Short name T331
Test name
Test status
Simulation time 4585300441 ps
CPU time 5.99 seconds
Started Jan 21 08:12:14 PM PST 24
Finished Jan 21 08:12:23 PM PST 24
Peak memory 221812 kb
Host smart-c7921f52-e121-4c3f-bef4-4e8a39a3f023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929661576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1929661576
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3246994584
Short name T1188
Test name
Test status
Simulation time 40680231 ps
CPU time 0.84 seconds
Started Jan 21 08:12:03 PM PST 24
Finished Jan 21 08:12:06 PM PST 24
Peak memory 208032 kb
Host smart-aef68519-719b-4939-b768-3df034a9ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246994584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3246994584
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_dummy_item_extra_dly.3511214132
Short name T1641
Test name
Test status
Simulation time 38256256083 ps
CPU time 1034.03 seconds
Started Jan 21 08:12:01 PM PST 24
Finished Jan 21 08:29:16 PM PST 24
Peak memory 232072 kb
Host smart-28b90bae-6271-4776-a03d-48ae81691f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511214132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_dummy_item_extra_dly.3511214132
Directory /workspace/38.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/38.spi_device_extreme_fifo_size.3149178002
Short name T1075
Test name
Test status
Simulation time 72178234644 ps
CPU time 1029.23 seconds
Started Jan 21 08:12:10 PM PST 24
Finished Jan 21 08:29:22 PM PST 24
Peak memory 221460 kb
Host smart-7096d545-3ba6-421f-ac39-cbaf9a2e5a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149178002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_extreme_fifo_size.3149178002
Directory /workspace/38.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/38.spi_device_fifo_full.1340733027
Short name T887
Test name
Test status
Simulation time 178333916240 ps
CPU time 1061.2 seconds
Started Jan 21 08:12:01 PM PST 24
Finished Jan 21 08:29:44 PM PST 24
Peak memory 307208 kb
Host smart-1b76b8eb-52ff-4de2-a820-108d05c5c929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340733027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_full.1340733027
Directory /workspace/38.spi_device_fifo_full/latest

Test location /workspace/coverage/default/38.spi_device_fifo_underflow_overflow.156740046
Short name T890
Test name
Test status
Simulation time 19333545474 ps
CPU time 299.42 seconds
Started Jan 21 08:12:09 PM PST 24
Finished Jan 21 08:17:11 PM PST 24
Peak memory 341156 kb
Host smart-6043bba1-6052-4a26-a725-48de8e870a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156740046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_underflow_overfl
ow.156740046
Directory /workspace/38.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1459128124
Short name T621
Test name
Test status
Simulation time 24541046645 ps
CPU time 122.67 seconds
Started Jan 21 08:12:15 PM PST 24
Finished Jan 21 08:14:22 PM PST 24
Peak memory 255828 kb
Host smart-49bbcb37-6942-4ef6-8fc8-3e7605907526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459128124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1459128124
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1451018888
Short name T1307
Test name
Test status
Simulation time 15588722531 ps
CPU time 81.67 seconds
Started Jan 21 08:32:47 PM PST 24
Finished Jan 21 08:34:11 PM PST 24
Peak memory 256632 kb
Host smart-53fc8991-d661-46ea-a42a-bc49cdc5f0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451018888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1451018888
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1095686525
Short name T885
Test name
Test status
Simulation time 3843197174 ps
CPU time 13.92 seconds
Started Jan 21 09:20:20 PM PST 24
Finished Jan 21 09:20:38 PM PST 24
Peak memory 270320 kb
Host smart-892bf01d-3270-42ab-bec4-f6b66728a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095686525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1095686525
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2445617426
Short name T24
Test name
Test status
Simulation time 234755228 ps
CPU time 4.09 seconds
Started Jan 21 08:12:11 PM PST 24
Finished Jan 21 08:12:17 PM PST 24
Peak memory 225480 kb
Host smart-6117c554-180d-4ce5-9e5b-82210d25f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445617426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2445617426
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intr.3938500475
Short name T999
Test name
Test status
Simulation time 15343810539 ps
CPU time 42.07 seconds
Started Jan 21 08:12:00 PM PST 24
Finished Jan 21 08:12:44 PM PST 24
Peak memory 223500 kb
Host smart-addd7bf3-c8a7-4737-ab7b-c0042b608655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938500475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intr.3938500475
Directory /workspace/38.spi_device_intr/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3981621399
Short name T254
Test name
Test status
Simulation time 2956887242 ps
CPU time 12.61 seconds
Started Jan 21 08:12:11 PM PST 24
Finished Jan 21 08:12:26 PM PST 24
Peak memory 220368 kb
Host smart-30890a67-c182-40dc-8ae1-59f6c6139df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981621399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3981621399
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3697232852
Short name T1433
Test name
Test status
Simulation time 12024108046 ps
CPU time 9.79 seconds
Started Jan 21 08:12:09 PM PST 24
Finished Jan 21 08:12:22 PM PST 24
Peak memory 220036 kb
Host smart-5e83d124-1110-4e0f-8ff5-e9859dca3d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697232852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3697232852
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1926921116
Short name T1381
Test name
Test status
Simulation time 16950677180 ps
CPU time 48.17 seconds
Started Jan 21 08:12:12 PM PST 24
Finished Jan 21 08:13:03 PM PST 24
Peak memory 252264 kb
Host smart-bc0fb989-0111-4c47-90a8-ee1830a6dabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926921116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1926921116
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_perf.913156270
Short name T884
Test name
Test status
Simulation time 19954538279 ps
CPU time 564.5 seconds
Started Jan 21 08:12:10 PM PST 24
Finished Jan 21 08:21:37 PM PST 24
Peak memory 254424 kb
Host smart-b9db6861-9a0d-41ce-b4ea-0a323083f262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913156270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_perf.913156270
Directory /workspace/38.spi_device_perf/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.320326403
Short name T1717
Test name
Test status
Simulation time 941253627 ps
CPU time 5.97 seconds
Started Jan 21 08:12:14 PM PST 24
Finished Jan 21 08:12:23 PM PST 24
Peak memory 234896 kb
Host smart-4b58c15f-15ea-41f5-861b-0da5193ed84b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=320326403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.320326403
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_rx_async_fifo_reset.3514528991
Short name T929
Test name
Test status
Simulation time 28437910 ps
CPU time 0.88 seconds
Started Jan 21 08:12:10 PM PST 24
Finished Jan 21 08:12:13 PM PST 24
Peak memory 208824 kb
Host smart-04259671-f95a-410d-b051-b95def74b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514528991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_async_fifo_reset.3514528991
Directory /workspace/38.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_rx_timeout.2881787531
Short name T1380
Test name
Test status
Simulation time 471236614 ps
CPU time 6.15 seconds
Started Jan 21 08:12:09 PM PST 24
Finished Jan 21 08:12:17 PM PST 24
Peak memory 217200 kb
Host smart-27fe0591-1c70-4d99-bc59-1a14b5c2912f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881787531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_timeout.2881787531
Directory /workspace/38.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/38.spi_device_smoke.1404465354
Short name T1247
Test name
Test status
Simulation time 30973768 ps
CPU time 0.88 seconds
Started Jan 21 08:11:51 PM PST 24
Finished Jan 21 08:11:57 PM PST 24
Peak memory 208228 kb
Host smart-a881385d-0485-40f0-b6ec-98e574bf397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404465354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_smoke.1404465354
Directory /workspace/38.spi_device_smoke/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1698917436
Short name T1151
Test name
Test status
Simulation time 1473207015 ps
CPU time 9.66 seconds
Started Jan 21 08:12:03 PM PST 24
Finished Jan 21 08:12:15 PM PST 24
Peak memory 217328 kb
Host smart-7ff04d5d-1682-4fd8-aaa3-ef8e47fd08a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698917436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1698917436
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1462215869
Short name T123
Test name
Test status
Simulation time 18805172348 ps
CPU time 22.85 seconds
Started Jan 21 08:12:10 PM PST 24
Finished Jan 21 08:12:35 PM PST 24
Peak memory 217376 kb
Host smart-57f7531a-a1d4-4e0f-97cc-ea7627d42c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462215869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1462215869
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.863529724
Short name T376
Test name
Test status
Simulation time 103745410 ps
CPU time 1.05 seconds
Started Jan 21 08:12:14 PM PST 24
Finished Jan 21 08:12:19 PM PST 24
Peak memory 208348 kb
Host smart-7da4220a-f4a5-4783-aa11-90a994191b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863529724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.863529724
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1457224141
Short name T801
Test name
Test status
Simulation time 64476617 ps
CPU time 0.81 seconds
Started Jan 21 08:12:11 PM PST 24
Finished Jan 21 08:12:15 PM PST 24
Peak memory 207236 kb
Host smart-96abfe60-4d15-4ce0-bd6e-a3bb60464109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457224141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1457224141
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tx_async_fifo_reset.1907038848
Short name T1397
Test name
Test status
Simulation time 32674580 ps
CPU time 0.79 seconds
Started Jan 21 08:12:12 PM PST 24
Finished Jan 21 08:12:16 PM PST 24
Peak memory 208816 kb
Host smart-c609929c-1adb-4a5c-a30a-110651effddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907038848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tx_async_fifo_reset.1907038848
Directory /workspace/38.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_txrx.3915170276
Short name T1412
Test name
Test status
Simulation time 34321160496 ps
CPU time 231.96 seconds
Started Jan 21 08:12:02 PM PST 24
Finished Jan 21 08:15:55 PM PST 24
Peak memory 282928 kb
Host smart-24795889-d235-4812-b1da-73b41d00bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915170276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_txrx.3915170276
Directory /workspace/38.spi_device_txrx/latest

Test location /workspace/coverage/default/38.spi_device_upload.1776656536
Short name T217
Test name
Test status
Simulation time 1424843359 ps
CPU time 11.38 seconds
Started Jan 21 08:12:14 PM PST 24
Finished Jan 21 08:12:29 PM PST 24
Peak memory 241896 kb
Host smart-4372bb2c-3b71-46d3-af48-6a7792a44816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776656536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1776656536
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_abort.2384107616
Short name T1331
Test name
Test status
Simulation time 28734177 ps
CPU time 0.79 seconds
Started Jan 21 08:24:20 PM PST 24
Finished Jan 21 08:24:22 PM PST 24
Peak memory 207076 kb
Host smart-df3a7138-dff8-4fd8-8b17-91b527acee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384107616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_abort.2384107616
Directory /workspace/39.spi_device_abort/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.661360120
Short name T1682
Test name
Test status
Simulation time 65362944 ps
CPU time 0.73 seconds
Started Jan 21 08:12:43 PM PST 24
Finished Jan 21 08:12:45 PM PST 24
Peak memory 206908 kb
Host smart-401ba9bf-673f-408b-bed6-ce664250bfa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661360120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.661360120
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_bit_transfer.2892912551
Short name T1407
Test name
Test status
Simulation time 145683089 ps
CPU time 2.7 seconds
Started Jan 21 08:42:39 PM PST 24
Finished Jan 21 08:42:43 PM PST 24
Peak memory 217224 kb
Host smart-922d638c-408a-48bd-9ad8-7c57498e9dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892912551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_bit_transfer.2892912551
Directory /workspace/39.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/39.spi_device_byte_transfer.1093007389
Short name T745
Test name
Test status
Simulation time 236712679 ps
CPU time 3.1 seconds
Started Jan 21 08:47:41 PM PST 24
Finished Jan 21 08:48:09 PM PST 24
Peak memory 217228 kb
Host smart-7036c7f3-aee4-49fa-89e8-4e58d2dd1ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093007389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_byte_transfer.1093007389
Directory /workspace/39.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.352548203
Short name T798
Test name
Test status
Simulation time 1064534152 ps
CPU time 5.23 seconds
Started Jan 21 08:12:28 PM PST 24
Finished Jan 21 08:12:36 PM PST 24
Peak memory 225496 kb
Host smart-f79f872c-c8bd-4b93-962a-f4da544b1260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352548203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.352548203
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1171486107
Short name T941
Test name
Test status
Simulation time 14433160 ps
CPU time 0.8 seconds
Started Jan 21 08:12:26 PM PST 24
Finished Jan 21 08:12:28 PM PST 24
Peak memory 206988 kb
Host smart-f6e547cb-a484-45d7-85f7-8f2820ff7a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171486107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1171486107
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_dummy_item_extra_dly.3297830951
Short name T577
Test name
Test status
Simulation time 50810680176 ps
CPU time 250.05 seconds
Started Jan 21 08:12:26 PM PST 24
Finished Jan 21 08:16:38 PM PST 24
Peak memory 261672 kb
Host smart-ebddf7c3-fce1-432c-ab4c-3a0a708c4824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297830951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_dummy_item_extra_dly.3297830951
Directory /workspace/39.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/39.spi_device_extreme_fifo_size.1035924908
Short name T1325
Test name
Test status
Simulation time 13137107971 ps
CPU time 66.29 seconds
Started Jan 21 08:12:23 PM PST 24
Finished Jan 21 08:13:32 PM PST 24
Peak memory 225476 kb
Host smart-a4daacd6-67d0-46da-82e2-185f909eb201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035924908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_extreme_fifo_size.1035924908
Directory /workspace/39.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/39.spi_device_fifo_full.1773831518
Short name T247
Test name
Test status
Simulation time 60021454399 ps
CPU time 629.49 seconds
Started Jan 21 08:44:48 PM PST 24
Finished Jan 21 08:55:18 PM PST 24
Peak memory 266636 kb
Host smart-b538632b-ce04-4544-88ad-c12005f44272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773831518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_full.1773831518
Directory /workspace/39.spi_device_fifo_full/latest

Test location /workspace/coverage/default/39.spi_device_fifo_underflow_overflow.692413776
Short name T953
Test name
Test status
Simulation time 1193605254166 ps
CPU time 626.88 seconds
Started Jan 21 08:12:22 PM PST 24
Finished Jan 21 08:22:52 PM PST 24
Peak memory 440668 kb
Host smart-e0295184-e01d-4fd7-9e0c-ae7a99816b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692413776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_underflow_overfl
ow.692413776
Directory /workspace/39.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.834370173
Short name T320
Test name
Test status
Simulation time 58435507521 ps
CPU time 313.75 seconds
Started Jan 21 08:12:44 PM PST 24
Finished Jan 21 08:17:59 PM PST 24
Peak memory 267744 kb
Host smart-4a91d08b-e6cd-4acc-86ad-08321ffe2307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834370173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.834370173
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.475251040
Short name T5
Test name
Test status
Simulation time 14922674091 ps
CPU time 69.55 seconds
Started Jan 21 08:12:47 PM PST 24
Finished Jan 21 08:13:59 PM PST 24
Peak memory 225672 kb
Host smart-ba33c3e8-baf7-4eb5-bf12-c31013a65b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475251040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.475251040
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.479645234
Short name T608
Test name
Test status
Simulation time 2576448595 ps
CPU time 9.86 seconds
Started Jan 21 08:12:30 PM PST 24
Finished Jan 21 08:12:42 PM PST 24
Peak memory 258016 kb
Host smart-39c603be-b9b2-4f68-9812-80ebba41422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479645234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.479645234
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3567656412
Short name T1238
Test name
Test status
Simulation time 8214464112 ps
CPU time 6.58 seconds
Started Jan 21 08:12:29 PM PST 24
Finished Jan 21 08:12:38 PM PST 24
Peak memory 233948 kb
Host smart-6eac4338-3978-4040-9f06-8e82d125e859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567656412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3567656412
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intr.2932463075
Short name T872
Test name
Test status
Simulation time 34278055489 ps
CPU time 35.34 seconds
Started Jan 21 08:26:41 PM PST 24
Finished Jan 21 08:27:17 PM PST 24
Peak memory 241080 kb
Host smart-4f423df1-84c9-4929-abbd-50b285bc2072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932463075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intr.2932463075
Directory /workspace/39.spi_device_intr/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1543003766
Short name T1584
Test name
Test status
Simulation time 25882474842 ps
CPU time 33.18 seconds
Started Jan 21 08:12:29 PM PST 24
Finished Jan 21 08:13:04 PM PST 24
Peak memory 231912 kb
Host smart-e045ad29-78e4-4969-bef4-b8913d98e28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543003766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1543003766
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1948039244
Short name T1338
Test name
Test status
Simulation time 154309868 ps
CPU time 3.82 seconds
Started Jan 21 08:12:29 PM PST 24
Finished Jan 21 08:12:35 PM PST 24
Peak memory 239592 kb
Host smart-def67260-e1ac-40f7-9fea-c427c06ecd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948039244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1948039244
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2334507536
Short name T74
Test name
Test status
Simulation time 61159087738 ps
CPU time 18.57 seconds
Started Jan 21 08:12:34 PM PST 24
Finished Jan 21 08:12:55 PM PST 24
Peak memory 229636 kb
Host smart-861c1238-29cf-41ee-8bf3-2dbebf263aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334507536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2334507536
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_perf.1012409825
Short name T1233
Test name
Test status
Simulation time 11967911958 ps
CPU time 819.85 seconds
Started Jan 21 08:41:58 PM PST 24
Finished Jan 21 08:55:39 PM PST 24
Peak memory 298584 kb
Host smart-950c2440-7425-433f-a713-29331675c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012409825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_perf.1012409825
Directory /workspace/39.spi_device_perf/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2151099963
Short name T1258
Test name
Test status
Simulation time 5916932357 ps
CPU time 7.12 seconds
Started Jan 21 09:54:24 PM PST 24
Finished Jan 21 09:54:44 PM PST 24
Peak memory 221388 kb
Host smart-a94318be-fda1-4ced-8ea7-ab4dd410b476
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2151099963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2151099963
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_rx_async_fifo_reset.3920771294
Short name T996
Test name
Test status
Simulation time 36052925 ps
CPU time 0.91 seconds
Started Jan 21 08:12:34 PM PST 24
Finished Jan 21 08:12:37 PM PST 24
Peak memory 208780 kb
Host smart-263c5151-b40a-4cb9-a1fd-987d68669465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920771294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_async_fifo_reset.3920771294
Directory /workspace/39.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_rx_timeout.3309592664
Short name T640
Test name
Test status
Simulation time 1637171403 ps
CPU time 5.49 seconds
Started Jan 21 08:12:27 PM PST 24
Finished Jan 21 08:12:35 PM PST 24
Peak memory 217196 kb
Host smart-727947f8-097e-418b-8f7e-a1b44aced6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309592664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_timeout.3309592664
Directory /workspace/39.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/39.spi_device_smoke.1354540032
Short name T1008
Test name
Test status
Simulation time 43176682 ps
CPU time 1.16 seconds
Started Jan 21 08:12:16 PM PST 24
Finished Jan 21 08:12:23 PM PST 24
Peak memory 208720 kb
Host smart-5fd772aa-ad0a-4472-92c0-ceb663b9d46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354540032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_smoke.1354540032
Directory /workspace/39.spi_device_smoke/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.129991882
Short name T52
Test name
Test status
Simulation time 37913617556 ps
CPU time 58.04 seconds
Started Jan 21 09:25:16 PM PST 24
Finished Jan 21 09:26:20 PM PST 24
Peak memory 217700 kb
Host smart-a3d792ca-ae2f-4316-882a-7efedc4bb78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129991882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.129991882
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.937537232
Short name T1179
Test name
Test status
Simulation time 9538846226 ps
CPU time 15.27 seconds
Started Jan 21 08:12:29 PM PST 24
Finished Jan 21 08:12:48 PM PST 24
Peak memory 217376 kb
Host smart-f88610f3-eb78-4d9c-a73d-39fb42151414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937537232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.937537232
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3337880061
Short name T773
Test name
Test status
Simulation time 170387144 ps
CPU time 2.02 seconds
Started Jan 21 08:12:29 PM PST 24
Finished Jan 21 08:12:33 PM PST 24
Peak memory 217248 kb
Host smart-ba9d58c6-91a9-4a4f-a764-6562e151b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337880061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3337880061
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3153671679
Short name T1727
Test name
Test status
Simulation time 204345889 ps
CPU time 1 seconds
Started Jan 21 08:12:29 PM PST 24
Finished Jan 21 08:12:33 PM PST 24
Peak memory 207412 kb
Host smart-e11268f4-e7ab-4dee-8449-6259fdf08312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153671679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3153671679
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tx_async_fifo_reset.3288898402
Short name T76
Test name
Test status
Simulation time 31509861 ps
CPU time 0.78 seconds
Started Jan 21 08:12:28 PM PST 24
Finished Jan 21 08:12:30 PM PST 24
Peak memory 208716 kb
Host smart-7947cfd6-e3be-4c92-bed3-17d4a116e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288898402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tx_async_fifo_reset.3288898402
Directory /workspace/39.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_txrx.518825735
Short name T678
Test name
Test status
Simulation time 51458189787 ps
CPU time 132.76 seconds
Started Jan 21 08:12:26 PM PST 24
Finished Jan 21 08:14:40 PM PST 24
Peak memory 233792 kb
Host smart-f7c41a4c-5b8d-4187-9713-911be6f83a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518825735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_txrx.518825735
Directory /workspace/39.spi_device_txrx/latest

Test location /workspace/coverage/default/39.spi_device_upload.3663495586
Short name T1441
Test name
Test status
Simulation time 533298261 ps
CPU time 8.27 seconds
Started Jan 21 08:20:22 PM PST 24
Finished Jan 21 08:20:33 PM PST 24
Peak memory 225468 kb
Host smart-365f62f7-41a9-427d-88a0-69b5ccce9f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663495586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3663495586
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_abort.3459199928
Short name T610
Test name
Test status
Simulation time 45904028 ps
CPU time 0.8 seconds
Started Jan 21 07:53:58 PM PST 24
Finished Jan 21 07:54:04 PM PST 24
Peak memory 207108 kb
Host smart-20fb1771-f45a-43b7-9fb1-0aa36835f389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459199928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_abort.3459199928
Directory /workspace/4.spi_device_abort/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2208664920
Short name T868
Test name
Test status
Simulation time 33508646 ps
CPU time 0.73 seconds
Started Jan 21 07:54:06 PM PST 24
Finished Jan 21 07:54:11 PM PST 24
Peak memory 206968 kb
Host smart-8a0909d3-b0fa-4c37-a14a-57c1190f9d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208664920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
208664920
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_bit_transfer.4088004429
Short name T677
Test name
Test status
Simulation time 195593200 ps
CPU time 2.48 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:54:05 PM PST 24
Peak memory 217244 kb
Host smart-c234a620-042f-48b8-8fdf-d615facecdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088004429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_bit_transfer.4088004429
Directory /workspace/4.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/4.spi_device_byte_transfer.4175623300
Short name T1631
Test name
Test status
Simulation time 213955889 ps
CPU time 3.08 seconds
Started Jan 21 07:53:56 PM PST 24
Finished Jan 21 07:54:06 PM PST 24
Peak memory 217140 kb
Host smart-34bc266e-c17f-4292-a407-62844c356807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175623300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_byte_transfer.4175623300
Directory /workspace/4.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3684559221
Short name T559
Test name
Test status
Simulation time 5973450198 ps
CPU time 4.97 seconds
Started Jan 21 08:33:42 PM PST 24
Finished Jan 21 08:33:50 PM PST 24
Peak memory 221868 kb
Host smart-def0448d-6ad4-4278-8ca7-161036bb8415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684559221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3684559221
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.481912743
Short name T889
Test name
Test status
Simulation time 30917974 ps
CPU time 0.79 seconds
Started Jan 21 07:53:47 PM PST 24
Finished Jan 21 07:53:51 PM PST 24
Peak memory 207020 kb
Host smart-65da8f85-5c13-4329-888c-58321310daaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481912743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.481912743
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_dummy_item_extra_dly.694587294
Short name T549
Test name
Test status
Simulation time 82799400751 ps
CPU time 227.58 seconds
Started Jan 21 07:53:46 PM PST 24
Finished Jan 21 07:57:37 PM PST 24
Peak memory 299340 kb
Host smart-82259109-bd35-4e62-aaa5-ab823759c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694587294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_dummy_item_extra_dly.694587294
Directory /workspace/4.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/4.spi_device_extreme_fifo_size.2927373543
Short name T1069
Test name
Test status
Simulation time 11030331749 ps
CPU time 28.53 seconds
Started Jan 21 07:53:47 PM PST 24
Finished Jan 21 07:54:19 PM PST 24
Peak memory 235136 kb
Host smart-a944aa9f-0a34-4dff-b54f-6169db885bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927373543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_extreme_fifo_size.2927373543
Directory /workspace/4.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/4.spi_device_fifo_full.961484599
Short name T609
Test name
Test status
Simulation time 21048764012 ps
CPU time 382.41 seconds
Started Jan 21 07:53:43 PM PST 24
Finished Jan 21 08:00:09 PM PST 24
Peak memory 322476 kb
Host smart-b30fe394-f4f5-4115-b11f-aefde21cf9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961484599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_full.961484599
Directory /workspace/4.spi_device_fifo_full/latest

Test location /workspace/coverage/default/4.spi_device_fifo_underflow_overflow.1275314751
Short name T1080
Test name
Test status
Simulation time 12719332995 ps
CPU time 157.78 seconds
Started Jan 21 07:53:49 PM PST 24
Finished Jan 21 07:56:30 PM PST 24
Peak memory 311512 kb
Host smart-e9563be4-17c2-4b1f-8573-a9132067ba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275314751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_underflow_overfl
ow.1275314751
Directory /workspace/4.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2522614974
Short name T724
Test name
Test status
Simulation time 559325617238 ps
CPU time 207.55 seconds
Started Jan 21 08:15:39 PM PST 24
Finished Jan 21 08:19:09 PM PST 24
Peak memory 250656 kb
Host smart-fc590578-83bf-4324-a4cc-828b71f0fa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522614974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2522614974
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2713434151
Short name T365
Test name
Test status
Simulation time 31375758255 ps
CPU time 144.08 seconds
Started Jan 21 07:54:00 PM PST 24
Finished Jan 21 07:56:31 PM PST 24
Peak memory 253808 kb
Host smart-d07fec5e-8a7e-4c85-9a56-9d2b3284f7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713434151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2713434151
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2039883879
Short name T277
Test name
Test status
Simulation time 18873903695 ps
CPU time 184.28 seconds
Started Jan 21 08:56:01 PM PST 24
Finished Jan 21 08:59:38 PM PST 24
Peak memory 258348 kb
Host smart-9e19db2f-3656-456e-9a68-92368eed4e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039883879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2039883879
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1791080617
Short name T370
Test name
Test status
Simulation time 11366756964 ps
CPU time 26.88 seconds
Started Jan 21 08:28:18 PM PST 24
Finished Jan 21 08:28:46 PM PST 24
Peak memory 234896 kb
Host smart-cb794c1d-8afb-4077-a274-a8c644e1e5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791080617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1791080617
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4198377066
Short name T315
Test name
Test status
Simulation time 1290392503 ps
CPU time 5.85 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:54:09 PM PST 24
Peak memory 239168 kb
Host smart-389cb0f5-e0f1-4d59-ac66-f6c69730e212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198377066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4198377066
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intr.2641860582
Short name T1113
Test name
Test status
Simulation time 5203475132 ps
CPU time 32.85 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:54:36 PM PST 24
Peak memory 240908 kb
Host smart-fc846c0e-1b1d-48da-8451-ce3f7b7a1f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641860582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intr.2641860582
Directory /workspace/4.spi_device_intr/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3740158694
Short name T707
Test name
Test status
Simulation time 143217622635 ps
CPU time 36.41 seconds
Started Jan 21 07:54:06 PM PST 24
Finished Jan 21 07:54:47 PM PST 24
Peak memory 233888 kb
Host smart-ba0ec5ed-4507-4d05-b4cc-20615a683db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740158694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3740158694
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1156684739
Short name T810
Test name
Test status
Simulation time 30577525 ps
CPU time 1.12 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:54:04 PM PST 24
Peak memory 219316 kb
Host smart-70752e75-fcaa-4e54-a2d6-cd7b38703c73
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156684739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1156684739
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3958003337
Short name T325
Test name
Test status
Simulation time 5350508132 ps
CPU time 19.88 seconds
Started Jan 21 07:53:58 PM PST 24
Finished Jan 21 07:54:23 PM PST 24
Peak memory 246804 kb
Host smart-13416328-365c-4367-ae67-20a7a81da581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958003337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3958003337
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3926882329
Short name T1454
Test name
Test status
Simulation time 201327172 ps
CPU time 4.25 seconds
Started Jan 21 07:53:59 PM PST 24
Finished Jan 21 07:54:08 PM PST 24
Peak memory 225568 kb
Host smart-86ae5910-cd21-4c11-9061-0aeda305e5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926882329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3926882329
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_perf.1976648164
Short name T491
Test name
Test status
Simulation time 351130490408 ps
CPU time 743.85 seconds
Started Jan 21 07:53:50 PM PST 24
Finished Jan 21 08:06:17 PM PST 24
Peak memory 274204 kb
Host smart-2f6ef235-fed6-4454-b345-dba6b2ba3e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976648164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_perf.1976648164
Directory /workspace/4.spi_device_perf/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.678983991
Short name T964
Test name
Test status
Simulation time 28732217 ps
CPU time 0.74 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:54:03 PM PST 24
Peak memory 217104 kb
Host smart-b28c97c6-5cc6-4b7c-a737-62291ad5d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678983991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.678983991
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4049311587
Short name T661
Test name
Test status
Simulation time 4582445133 ps
CPU time 6.58 seconds
Started Jan 21 08:18:29 PM PST 24
Finished Jan 21 08:18:37 PM PST 24
Peak memory 235004 kb
Host smart-53853a2d-1b04-4b07-89f4-bd4fadbe4341
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049311587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4049311587
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_rx_async_fifo_reset.3224713776
Short name T948
Test name
Test status
Simulation time 62694945 ps
CPU time 0.86 seconds
Started Jan 21 08:22:19 PM PST 24
Finished Jan 21 08:22:22 PM PST 24
Peak memory 208848 kb
Host smart-0f6546e9-bd60-488f-9ce0-b1be4a18c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224713776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_async_fifo_reset.3224713776
Directory /workspace/4.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_rx_timeout.199353160
Short name T704
Test name
Test status
Simulation time 790427074 ps
CPU time 5.64 seconds
Started Jan 21 07:53:58 PM PST 24
Finished Jan 21 07:54:09 PM PST 24
Peak memory 217220 kb
Host smart-bee4e1cb-6f6f-4c53-96dd-aa610a9dfac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199353160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_timeout.199353160
Directory /workspace/4.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1009717258
Short name T110
Test name
Test status
Simulation time 377915300 ps
CPU time 1.24 seconds
Started Jan 21 08:50:51 PM PST 24
Finished Jan 21 08:51:21 PM PST 24
Peak memory 238568 kb
Host smart-17a12f63-de82-489e-93dd-d4cb96f2c522
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009717258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1009717258
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_smoke.2918571208
Short name T1430
Test name
Test status
Simulation time 46580854 ps
CPU time 1.17 seconds
Started Jan 21 07:53:49 PM PST 24
Finished Jan 21 07:53:53 PM PST 24
Peak memory 216920 kb
Host smart-24bcb840-6b2d-4cec-93df-747a393d4e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918571208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_smoke.2918571208
Directory /workspace/4.spi_device_smoke/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1026769658
Short name T1669
Test name
Test status
Simulation time 190900728886 ps
CPU time 1469.01 seconds
Started Jan 21 07:54:00 PM PST 24
Finished Jan 21 08:18:36 PM PST 24
Peak memory 430676 kb
Host smart-2cf77376-7fc2-49fd-9f76-bac7926703d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026769658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1026769658
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.855274433
Short name T375
Test name
Test status
Simulation time 18110922099 ps
CPU time 36.06 seconds
Started Jan 21 07:53:53 PM PST 24
Finished Jan 21 07:54:36 PM PST 24
Peak memory 217348 kb
Host smart-3a5dcb7a-07f4-44aa-b0f5-9281c94b9320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855274433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.855274433
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2461437862
Short name T873
Test name
Test status
Simulation time 1775277205 ps
CPU time 8.86 seconds
Started Jan 21 07:53:55 PM PST 24
Finished Jan 21 07:54:12 PM PST 24
Peak memory 217184 kb
Host smart-c07b08af-1950-4599-9036-62f500892420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461437862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2461437862
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.407359788
Short name T75
Test name
Test status
Simulation time 28938863 ps
CPU time 1.72 seconds
Started Jan 21 07:53:54 PM PST 24
Finished Jan 21 07:54:03 PM PST 24
Peak memory 217224 kb
Host smart-8dbab418-1caf-42f9-a00a-dfcbabc24519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407359788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.407359788
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2327179931
Short name T1528
Test name
Test status
Simulation time 68030476 ps
CPU time 1.01 seconds
Started Jan 21 07:53:56 PM PST 24
Finished Jan 21 07:54:04 PM PST 24
Peak memory 208796 kb
Host smart-9bb6f9be-3664-472a-8b26-76ea59e50f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327179931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2327179931
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tx_async_fifo_reset.470363713
Short name T759
Test name
Test status
Simulation time 28388307 ps
CPU time 0.83 seconds
Started Jan 21 07:53:56 PM PST 24
Finished Jan 21 07:54:04 PM PST 24
Peak memory 208732 kb
Host smart-9a554d7e-3647-4379-8f28-93d67a3aa60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470363713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tx_async_fifo_reset.470363713
Directory /workspace/4.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_txrx.3850193149
Short name T569
Test name
Test status
Simulation time 42849917434 ps
CPU time 127.86 seconds
Started Jan 21 07:53:46 PM PST 24
Finished Jan 21 07:55:57 PM PST 24
Peak memory 240332 kb
Host smart-7ddf133f-e71f-4359-9363-b94cedb16532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850193149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_txrx.3850193149
Directory /workspace/4.spi_device_txrx/latest

Test location /workspace/coverage/default/4.spi_device_upload.3686905097
Short name T951
Test name
Test status
Simulation time 32362175535 ps
CPU time 10.92 seconds
Started Jan 21 07:54:02 PM PST 24
Finished Jan 21 07:54:19 PM PST 24
Peak memory 238088 kb
Host smart-0e18b1fd-984f-434d-9f1c-761f1aa03ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686905097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3686905097
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_abort.1552326024
Short name T782
Test name
Test status
Simulation time 81581166 ps
CPU time 0.74 seconds
Started Jan 21 09:00:40 PM PST 24
Finished Jan 21 09:01:08 PM PST 24
Peak memory 207088 kb
Host smart-9d2442fd-ef01-4680-bf68-dc74e9944439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552326024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_abort.1552326024
Directory /workspace/40.spi_device_abort/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1969143138
Short name T808
Test name
Test status
Simulation time 18817303 ps
CPU time 0.76 seconds
Started Jan 21 08:35:59 PM PST 24
Finished Jan 21 08:36:01 PM PST 24
Peak memory 206940 kb
Host smart-2c9e30e3-1217-452d-81a7-a24c03ce729d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969143138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1969143138
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_bit_transfer.3501818757
Short name T1242
Test name
Test status
Simulation time 204413242 ps
CPU time 3.04 seconds
Started Jan 21 08:12:49 PM PST 24
Finished Jan 21 08:12:54 PM PST 24
Peak memory 217192 kb
Host smart-c4cc67c9-0a02-4de3-862a-911de06a3e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501818757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_bit_transfer.3501818757
Directory /workspace/40.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/40.spi_device_byte_transfer.1068868025
Short name T1702
Test name
Test status
Simulation time 135905972 ps
CPU time 2.75 seconds
Started Jan 21 08:12:51 PM PST 24
Finished Jan 21 08:12:56 PM PST 24
Peak memory 217244 kb
Host smart-7d5e59bd-3a90-4efa-8720-d3c4c5448931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068868025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_byte_transfer.1068868025
Directory /workspace/40.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1962236938
Short name T766
Test name
Test status
Simulation time 1252397654 ps
CPU time 4.85 seconds
Started Jan 21 08:12:59 PM PST 24
Finished Jan 21 08:13:05 PM PST 24
Peak memory 241756 kb
Host smart-ccdafbd3-5e09-4de5-b24b-a7830b7a4faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962236938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1962236938
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3111372236
Short name T1225
Test name
Test status
Simulation time 19948151 ps
CPU time 0.81 seconds
Started Jan 21 08:12:48 PM PST 24
Finished Jan 21 08:12:50 PM PST 24
Peak memory 207000 kb
Host smart-953f1c56-31d3-4bcc-a734-6dca8b274e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111372236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3111372236
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_dummy_item_extra_dly.3084356766
Short name T896
Test name
Test status
Simulation time 60791863039 ps
CPU time 236.18 seconds
Started Jan 21 08:12:47 PM PST 24
Finished Jan 21 08:16:45 PM PST 24
Peak memory 246396 kb
Host smart-d88540b4-50d9-4169-ac13-3fb7b00b17ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084356766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_dummy_item_extra_dly.3084356766
Directory /workspace/40.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/40.spi_device_extreme_fifo_size.1837654263
Short name T1251
Test name
Test status
Simulation time 39074703156 ps
CPU time 217.26 seconds
Started Jan 21 08:12:48 PM PST 24
Finished Jan 21 08:16:26 PM PST 24
Peak memory 225572 kb
Host smart-f2cda04a-2347-4559-a8c2-13d210db742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837654263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_extreme_fifo_size.1837654263
Directory /workspace/40.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/40.spi_device_fifo_full.989000952
Short name T846
Test name
Test status
Simulation time 17349481822 ps
CPU time 370.47 seconds
Started Jan 21 08:12:45 PM PST 24
Finished Jan 21 08:18:56 PM PST 24
Peak memory 296336 kb
Host smart-22fe7992-daac-4d00-8a44-09d21a16da96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989000952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_full.989000952
Directory /workspace/40.spi_device_fifo_full/latest

Test location /workspace/coverage/default/40.spi_device_fifo_underflow_overflow.702891511
Short name T223
Test name
Test status
Simulation time 5805191197 ps
CPU time 58.05 seconds
Started Jan 21 08:12:42 PM PST 24
Finished Jan 21 08:13:41 PM PST 24
Peak memory 258324 kb
Host smart-ce7bed83-789e-4b34-a0ee-f21720b46493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702891511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_underflow_overfl
ow.702891511
Directory /workspace/40.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.459999021
Short name T234
Test name
Test status
Simulation time 15363279476 ps
CPU time 76.67 seconds
Started Jan 21 08:13:10 PM PST 24
Finished Jan 21 08:14:28 PM PST 24
Peak memory 240420 kb
Host smart-216dbe5d-a54e-4b6f-b92b-fd62f574364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459999021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.459999021
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3940891290
Short name T1657
Test name
Test status
Simulation time 1708973384 ps
CPU time 42.59 seconds
Started Jan 21 08:13:09 PM PST 24
Finished Jan 21 08:13:53 PM PST 24
Peak memory 250220 kb
Host smart-4bea0176-73d5-4465-9403-9eabc7946e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940891290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3940891290
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3524562951
Short name T822
Test name
Test status
Simulation time 27860639227 ps
CPU time 99.57 seconds
Started Jan 21 08:18:59 PM PST 24
Finished Jan 21 08:20:40 PM PST 24
Peak memory 266556 kb
Host smart-35d96de7-9f9a-4fa6-953d-0dec04bba171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524562951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3524562951
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.399040842
Short name T722
Test name
Test status
Simulation time 4245893926 ps
CPU time 27.25 seconds
Started Jan 21 08:12:58 PM PST 24
Finished Jan 21 08:13:26 PM PST 24
Peak memory 246144 kb
Host smart-ba7700e7-210b-4596-b92f-dfd22abc8d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399040842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.399040842
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1593036608
Short name T1534
Test name
Test status
Simulation time 838742586 ps
CPU time 5.46 seconds
Started Jan 21 08:13:01 PM PST 24
Finished Jan 21 08:13:08 PM PST 24
Peak memory 241892 kb
Host smart-2f33156d-4a0f-42b0-b426-3c5f381e20dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593036608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1593036608
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intr.3317559434
Short name T1114
Test name
Test status
Simulation time 23137607958 ps
CPU time 101.88 seconds
Started Jan 21 08:12:44 PM PST 24
Finished Jan 21 08:14:27 PM PST 24
Peak memory 240344 kb
Host smart-f43eddf4-ca71-4f56-a7fb-f3b651e4f3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317559434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intr.3317559434
Directory /workspace/40.spi_device_intr/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2912441375
Short name T326
Test name
Test status
Simulation time 645560324 ps
CPU time 7.37 seconds
Started Jan 21 08:12:58 PM PST 24
Finished Jan 21 08:13:06 PM PST 24
Peak memory 241348 kb
Host smart-837f87d1-e5c0-417b-8b0c-1e0ee9e4df2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912441375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2912441375
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1725653069
Short name T158
Test name
Test status
Simulation time 9494542108 ps
CPU time 11.84 seconds
Started Jan 21 08:13:00 PM PST 24
Finished Jan 21 08:13:14 PM PST 24
Peak memory 247460 kb
Host smart-b45d776a-0a75-457d-b848-dfcef2d8d8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725653069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1725653069
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2803657219
Short name T304
Test name
Test status
Simulation time 14402114943 ps
CPU time 28.5 seconds
Started Jan 21 08:13:00 PM PST 24
Finished Jan 21 08:13:30 PM PST 24
Peak memory 241996 kb
Host smart-c5914d8f-83c6-422f-8a09-4dc9a108c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803657219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2803657219
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_perf.978624512
Short name T551
Test name
Test status
Simulation time 18289874379 ps
CPU time 725.09 seconds
Started Jan 21 08:12:44 PM PST 24
Finished Jan 21 08:24:50 PM PST 24
Peak memory 269596 kb
Host smart-4ec216c3-21a7-4b62-81a1-fec261c1e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978624512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_perf.978624512
Directory /workspace/40.spi_device_perf/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2708633428
Short name T836
Test name
Test status
Simulation time 2714558806 ps
CPU time 6.03 seconds
Started Jan 21 08:13:14 PM PST 24
Finished Jan 21 08:13:20 PM PST 24
Peak memory 235016 kb
Host smart-d4d4fa7f-ee29-4a50-85a5-a2cf3a05e0ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2708633428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2708633428
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_rx_async_fifo_reset.91634190
Short name T1360
Test name
Test status
Simulation time 30204611 ps
CPU time 0.86 seconds
Started Jan 21 08:12:54 PM PST 24
Finished Jan 21 08:12:57 PM PST 24
Peak memory 208836 kb
Host smart-8459fab0-d006-4d81-9a2f-8d6548f2b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91634190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_async_fifo_reset.91634190
Directory /workspace/40.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_rx_timeout.3183364120
Short name T584
Test name
Test status
Simulation time 11893918763 ps
CPU time 5.45 seconds
Started Jan 21 08:12:55 PM PST 24
Finished Jan 21 08:13:02 PM PST 24
Peak memory 217376 kb
Host smart-657d6fe9-c33e-47bb-9c7c-2c690bcf4bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183364120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_timeout.3183364120
Directory /workspace/40.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/40.spi_device_smoke.2800673235
Short name T35
Test name
Test status
Simulation time 33294321 ps
CPU time 1.12 seconds
Started Jan 21 08:12:44 PM PST 24
Finished Jan 21 08:12:46 PM PST 24
Peak memory 208736 kb
Host smart-7cd5316f-b997-4d3d-b1d6-e99c8ef100c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800673235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_smoke.2800673235
Directory /workspace/40.spi_device_smoke/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1908989962
Short name T1625
Test name
Test status
Simulation time 130481954375 ps
CPU time 526.25 seconds
Started Jan 21 08:13:11 PM PST 24
Finished Jan 21 08:21:58 PM PST 24
Peak memory 357836 kb
Host smart-3a411a3c-c14e-41be-8b3b-eb4dd569cb63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908989962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1908989962
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3914315848
Short name T1147
Test name
Test status
Simulation time 1127443244 ps
CPU time 7.34 seconds
Started Jan 21 08:12:53 PM PST 24
Finished Jan 21 08:13:02 PM PST 24
Peak memory 217444 kb
Host smart-4c5ff184-628f-4255-972a-06d294ea3e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914315848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3914315848
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.869064533
Short name T1438
Test name
Test status
Simulation time 721546696 ps
CPU time 3.76 seconds
Started Jan 21 08:12:54 PM PST 24
Finished Jan 21 08:12:59 PM PST 24
Peak memory 217192 kb
Host smart-608a5de3-ab66-4e53-ae16-aff2b345abaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869064533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.869064533
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.87984641
Short name T588
Test name
Test status
Simulation time 294675195 ps
CPU time 3.64 seconds
Started Jan 21 08:12:59 PM PST 24
Finished Jan 21 08:13:04 PM PST 24
Peak memory 217304 kb
Host smart-f75e57cd-a569-4013-9dbf-6aed3c65cb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87984641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.87984641
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1225496490
Short name T1462
Test name
Test status
Simulation time 83509456 ps
CPU time 0.78 seconds
Started Jan 21 08:12:59 PM PST 24
Finished Jan 21 08:13:02 PM PST 24
Peak memory 207200 kb
Host smart-150119ea-df43-4e5d-a4f4-0adddb1c0f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225496490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1225496490
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tx_async_fifo_reset.1879372114
Short name T1636
Test name
Test status
Simulation time 35687296 ps
CPU time 0.79 seconds
Started Jan 21 08:12:51 PM PST 24
Finished Jan 21 08:12:54 PM PST 24
Peak memory 207688 kb
Host smart-ed7dd3f7-699c-4fed-a3ef-10bd0489fbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879372114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tx_async_fifo_reset.1879372114
Directory /workspace/40.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_txrx.481663900
Short name T53
Test name
Test status
Simulation time 36090206150 ps
CPU time 220.6 seconds
Started Jan 21 08:12:45 PM PST 24
Finished Jan 21 08:16:26 PM PST 24
Peak memory 282816 kb
Host smart-0773d42a-b5b9-4af6-a8d7-152e6f56d5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481663900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_txrx.481663900
Directory /workspace/40.spi_device_txrx/latest

Test location /workspace/coverage/default/40.spi_device_upload.3325843779
Short name T1095
Test name
Test status
Simulation time 7697682447 ps
CPU time 32.17 seconds
Started Jan 21 08:13:00 PM PST 24
Finished Jan 21 08:13:34 PM PST 24
Peak memory 236764 kb
Host smart-1a5c2910-1ea9-421a-b080-63ed5f9a5a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325843779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3325843779
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_abort.3142901858
Short name T1652
Test name
Test status
Simulation time 64854672 ps
CPU time 0.78 seconds
Started Jan 21 08:13:18 PM PST 24
Finished Jan 21 08:13:20 PM PST 24
Peak memory 207100 kb
Host smart-1d2aadee-185e-4d9b-8c29-09ee6001a897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142901858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_abort.3142901858
Directory /workspace/41.spi_device_abort/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4237239731
Short name T1627
Test name
Test status
Simulation time 14883298 ps
CPU time 0.72 seconds
Started Jan 21 08:13:32 PM PST 24
Finished Jan 21 08:13:34 PM PST 24
Peak memory 206968 kb
Host smart-24900968-5924-4ed3-877e-862df7c57369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237239731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4237239731
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_bit_transfer.2545452201
Short name T728
Test name
Test status
Simulation time 1092209801 ps
CPU time 2.11 seconds
Started Jan 21 08:13:14 PM PST 24
Finished Jan 21 08:13:18 PM PST 24
Peak memory 217172 kb
Host smart-4abd8b7a-32c7-4171-ae16-70c7c17b613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545452201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_bit_transfer.2545452201
Directory /workspace/41.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/41.spi_device_byte_transfer.3414025653
Short name T659
Test name
Test status
Simulation time 133240390 ps
CPU time 2.8 seconds
Started Jan 21 08:13:12 PM PST 24
Finished Jan 21 08:13:15 PM PST 24
Peak memory 217224 kb
Host smart-e05e1fd3-33ef-4dd1-87ac-892c765c1049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414025653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_byte_transfer.3414025653
Directory /workspace/41.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2446028872
Short name T1446
Test name
Test status
Simulation time 728385655 ps
CPU time 2.86 seconds
Started Jan 21 08:29:15 PM PST 24
Finished Jan 21 08:29:19 PM PST 24
Peak memory 240020 kb
Host smart-75f43e92-35db-4d67-b8ef-1a615370b58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446028872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2446028872
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.207391343
Short name T1568
Test name
Test status
Simulation time 49701327 ps
CPU time 0.78 seconds
Started Jan 21 09:24:37 PM PST 24
Finished Jan 21 09:24:45 PM PST 24
Peak memory 207028 kb
Host smart-e31eb3fc-9122-4460-9239-59b3c3a4ad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207391343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.207391343
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_dummy_item_extra_dly.1048156461
Short name T1120
Test name
Test status
Simulation time 21933789845 ps
CPU time 190.15 seconds
Started Jan 21 08:58:36 PM PST 24
Finished Jan 21 09:02:16 PM PST 24
Peak memory 253748 kb
Host smart-08b2fa49-429c-4efd-b64e-d9ae243bb281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048156461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_dummy_item_extra_dly.1048156461
Directory /workspace/41.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/41.spi_device_extreme_fifo_size.715168161
Short name T904
Test name
Test status
Simulation time 62519440579 ps
CPU time 2414.04 seconds
Started Jan 21 08:13:11 PM PST 24
Finished Jan 21 08:53:26 PM PST 24
Peak memory 217372 kb
Host smart-9ff5894c-3de6-47d5-acf7-57a42fca7f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715168161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_extreme_fifo_size.715168161
Directory /workspace/41.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/41.spi_device_fifo_full.1116129603
Short name T849
Test name
Test status
Simulation time 40582438562 ps
CPU time 671.91 seconds
Started Jan 21 08:13:14 PM PST 24
Finished Jan 21 08:24:27 PM PST 24
Peak memory 303160 kb
Host smart-0aca9d2d-51a0-4d1b-a136-9650d1115dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116129603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_full.1116129603
Directory /workspace/41.spi_device_fifo_full/latest

Test location /workspace/coverage/default/41.spi_device_fifo_underflow_overflow.1021780738
Short name T1535
Test name
Test status
Simulation time 208370139846 ps
CPU time 484.29 seconds
Started Jan 21 08:13:09 PM PST 24
Finished Jan 21 08:21:14 PM PST 24
Peak memory 393820 kb
Host smart-322963ae-5765-4ac9-a213-00f7891272c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021780738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_underflow_overf
low.1021780738
Directory /workspace/41.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4173759006
Short name T1257
Test name
Test status
Simulation time 8779922181 ps
CPU time 69.46 seconds
Started Jan 21 08:13:17 PM PST 24
Finished Jan 21 08:14:28 PM PST 24
Peak memory 255536 kb
Host smart-6e6318fa-6598-4a07-b843-9c3265ac2001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173759006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4173759006
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.524015248
Short name T344
Test name
Test status
Simulation time 79115071533 ps
CPU time 661.28 seconds
Started Jan 21 08:13:17 PM PST 24
Finished Jan 21 08:24:19 PM PST 24
Peak memory 266636 kb
Host smart-91b87bb6-ab68-401d-a5ba-c9e79a17c28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524015248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.524015248
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1387080702
Short name T1033
Test name
Test status
Simulation time 16461890770 ps
CPU time 22.52 seconds
Started Jan 21 08:13:18 PM PST 24
Finished Jan 21 08:13:42 PM PST 24
Peak memory 241908 kb
Host smart-ec491121-cc0e-476b-a39d-79f3697b9c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387080702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1387080702
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1276839747
Short name T785
Test name
Test status
Simulation time 1903499929 ps
CPU time 5.16 seconds
Started Jan 21 08:56:25 PM PST 24
Finished Jan 21 08:57:11 PM PST 24
Peak memory 220756 kb
Host smart-37186657-951f-4ad0-b3b1-ac60b1e477f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276839747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1276839747
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intr.1690389614
Short name T224
Test name
Test status
Simulation time 6096633038 ps
CPU time 50.86 seconds
Started Jan 21 08:47:57 PM PST 24
Finished Jan 21 08:49:08 PM PST 24
Peak memory 241096 kb
Host smart-27a44829-fa91-45c2-9f23-b7da0e06145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690389614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intr.1690389614
Directory /workspace/41.spi_device_intr/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3337555502
Short name T1741
Test name
Test status
Simulation time 2618180000 ps
CPU time 10.15 seconds
Started Jan 21 09:11:15 PM PST 24
Finished Jan 21 09:11:34 PM PST 24
Peak memory 225256 kb
Host smart-40662639-71e0-4939-b08d-14ff725537a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337555502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3337555502
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1045503446
Short name T804
Test name
Test status
Simulation time 300304325 ps
CPU time 7.25 seconds
Started Jan 21 08:13:19 PM PST 24
Finished Jan 21 08:13:27 PM PST 24
Peak memory 247748 kb
Host smart-924c8759-1ff7-4873-9014-884b07f6e0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045503446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1045503446
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.45997248
Short name T255
Test name
Test status
Simulation time 3153507136 ps
CPU time 4.06 seconds
Started Jan 21 08:13:19 PM PST 24
Finished Jan 21 08:13:24 PM PST 24
Peak memory 219692 kb
Host smart-cc959c81-8fb2-4e66-9eb1-68dd981a60e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45997248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.45997248
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_perf.734168337
Short name T1431
Test name
Test status
Simulation time 94610326200 ps
CPU time 3063.53 seconds
Started Jan 21 08:13:15 PM PST 24
Finished Jan 21 09:04:20 PM PST 24
Peak memory 290716 kb
Host smart-2ca94d8e-04ec-42be-8303-63ab1f57705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734168337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_perf.734168337
Directory /workspace/41.spi_device_perf/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2609880075
Short name T753
Test name
Test status
Simulation time 4065767928 ps
CPU time 5.4 seconds
Started Jan 21 08:13:17 PM PST 24
Finished Jan 21 08:13:24 PM PST 24
Peak memory 219196 kb
Host smart-ebeaf628-d024-49ee-b96f-fa3cb99fe09c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2609880075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2609880075
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_rx_async_fifo_reset.2877047093
Short name T686
Test name
Test status
Simulation time 18968369 ps
CPU time 0.92 seconds
Started Jan 21 08:35:03 PM PST 24
Finished Jan 21 08:35:05 PM PST 24
Peak memory 208776 kb
Host smart-bf0ae4c2-f7a0-455d-9451-f54ae05f240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877047093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_async_fifo_reset.2877047093
Directory /workspace/41.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_rx_timeout.2379963771
Short name T506
Test name
Test status
Simulation time 3050315392 ps
CPU time 5.71 seconds
Started Jan 21 08:13:14 PM PST 24
Finished Jan 21 08:13:20 PM PST 24
Peak memory 217212 kb
Host smart-6f3e4dff-8a6b-4e95-91cf-071202500282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379963771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_timeout.2379963771
Directory /workspace/41.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/41.spi_device_smoke.4195680476
Short name T561
Test name
Test status
Simulation time 163745816 ps
CPU time 0.99 seconds
Started Jan 21 08:13:12 PM PST 24
Finished Jan 21 08:13:14 PM PST 24
Peak memory 208244 kb
Host smart-ba606977-6102-4eaa-b82a-3699bd3dd7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195680476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_smoke.4195680476
Directory /workspace/41.spi_device_smoke/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3419891793
Short name T341
Test name
Test status
Simulation time 221522533330 ps
CPU time 1529.79 seconds
Started Jan 21 08:36:06 PM PST 24
Finished Jan 21 09:01:37 PM PST 24
Peak memory 347356 kb
Host smart-a3e58e24-b6e3-47aa-8470-1d45642908f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419891793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3419891793
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.76576600
Short name T1370
Test name
Test status
Simulation time 4651354996 ps
CPU time 21.72 seconds
Started Jan 21 08:13:11 PM PST 24
Finished Jan 21 08:13:34 PM PST 24
Peak memory 217400 kb
Host smart-beb87fda-344f-493a-946c-aba714c3f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76576600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.76576600
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2254431651
Short name T762
Test name
Test status
Simulation time 4136443401 ps
CPU time 10.16 seconds
Started Jan 21 08:13:16 PM PST 24
Finished Jan 21 08:13:27 PM PST 24
Peak memory 217296 kb
Host smart-7a650bce-8336-41dc-a2eb-81c9d72802db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254431651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2254431651
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3664595864
Short name T585
Test name
Test status
Simulation time 1306938024 ps
CPU time 5.91 seconds
Started Jan 21 08:13:18 PM PST 24
Finished Jan 21 08:13:25 PM PST 24
Peak memory 217268 kb
Host smart-83bc40e3-5086-4d29-8024-0cffc1df41f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664595864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3664595864
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4244809024
Short name T1249
Test name
Test status
Simulation time 160873810 ps
CPU time 1.24 seconds
Started Jan 21 08:13:16 PM PST 24
Finished Jan 21 08:13:18 PM PST 24
Peak memory 208408 kb
Host smart-a26388a9-2c54-49f0-9f30-e5a19ac341af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244809024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4244809024
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tx_async_fifo_reset.1536926899
Short name T1364
Test name
Test status
Simulation time 16211986 ps
CPU time 0.79 seconds
Started Jan 21 08:13:18 PM PST 24
Finished Jan 21 08:13:20 PM PST 24
Peak memory 208792 kb
Host smart-467a639f-f9c3-4d98-b0f3-75dd8ff40337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536926899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tx_async_fifo_reset.1536926899
Directory /workspace/41.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_txrx.4131143949
Short name T298
Test name
Test status
Simulation time 43116810603 ps
CPU time 255.14 seconds
Started Jan 21 08:13:14 PM PST 24
Finished Jan 21 08:17:30 PM PST 24
Peak memory 273376 kb
Host smart-35c725f6-d97b-47ab-8667-0784e057af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131143949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_txrx.4131143949
Directory /workspace/41.spi_device_txrx/latest

Test location /workspace/coverage/default/41.spi_device_upload.3684445757
Short name T71
Test name
Test status
Simulation time 807993607 ps
CPU time 6.58 seconds
Started Jan 21 08:34:18 PM PST 24
Finished Jan 21 08:34:26 PM PST 24
Peak memory 241960 kb
Host smart-199ed643-0cfe-4769-a289-146ade536d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684445757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3684445757
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_abort.2703531937
Short name T1162
Test name
Test status
Simulation time 59742569 ps
CPU time 0.8 seconds
Started Jan 21 08:13:35 PM PST 24
Finished Jan 21 08:13:37 PM PST 24
Peak memory 207068 kb
Host smart-e3c3381b-b504-4a0d-a18f-4f26fd9df356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703531937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_abort.2703531937
Directory /workspace/42.spi_device_abort/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1349366267
Short name T895
Test name
Test status
Simulation time 22152129 ps
CPU time 0.74 seconds
Started Jan 21 08:13:55 PM PST 24
Finished Jan 21 08:13:57 PM PST 24
Peak memory 206972 kb
Host smart-253fefb4-108f-47de-b53d-68a4f7617579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349366267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1349366267
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_bit_transfer.3289994282
Short name T1342
Test name
Test status
Simulation time 366547352 ps
CPU time 3.14 seconds
Started Jan 21 09:11:03 PM PST 24
Finished Jan 21 09:11:19 PM PST 24
Peak memory 217196 kb
Host smart-6529b9ed-97b6-4287-8ae2-32b2ffafe282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289994282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_bit_transfer.3289994282
Directory /workspace/42.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/42.spi_device_byte_transfer.353727627
Short name T1385
Test name
Test status
Simulation time 547276077 ps
CPU time 2.53 seconds
Started Jan 21 08:58:03 PM PST 24
Finished Jan 21 08:58:28 PM PST 24
Peak memory 217204 kb
Host smart-b8853e20-4e47-435d-9856-cc09e94bb093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353727627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_byte_transfer.353727627
Directory /workspace/42.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1395486650
Short name T307
Test name
Test status
Simulation time 210745064 ps
CPU time 4.11 seconds
Started Jan 21 08:13:45 PM PST 24
Finished Jan 21 08:13:50 PM PST 24
Peak memory 240556 kb
Host smart-d599a843-5d55-4f5e-a6f4-626d2516ae92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395486650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1395486650
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4288380921
Short name T749
Test name
Test status
Simulation time 37357206 ps
CPU time 0.82 seconds
Started Jan 21 08:13:35 PM PST 24
Finished Jan 21 08:13:37 PM PST 24
Peak memory 208036 kb
Host smart-0795519e-0e07-4774-98fd-59046759a8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288380921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4288380921
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_dummy_item_extra_dly.698383438
Short name T971
Test name
Test status
Simulation time 171106039359 ps
CPU time 481.81 seconds
Started Jan 21 09:11:32 PM PST 24
Finished Jan 21 09:19:38 PM PST 24
Peak memory 305128 kb
Host smart-8cf1e4f1-c636-4efc-a585-8518427c6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698383438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_dummy_item_extra_dly.698383438
Directory /workspace/42.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/42.spi_device_extreme_fifo_size.461137407
Short name T295
Test name
Test status
Simulation time 59570554732 ps
CPU time 801.63 seconds
Started Jan 21 08:13:27 PM PST 24
Finished Jan 21 08:26:50 PM PST 24
Peak memory 219496 kb
Host smart-410be84d-5d1f-4e6f-bdf1-6de569063fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461137407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_extreme_fifo_size.461137407
Directory /workspace/42.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/42.spi_device_fifo_full.2699860374
Short name T1772
Test name
Test status
Simulation time 76407142625 ps
CPU time 1255.18 seconds
Started Jan 21 08:13:29 PM PST 24
Finished Jan 21 08:34:26 PM PST 24
Peak memory 301484 kb
Host smart-146a7f7c-1e2f-4034-9fcd-26750a122cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699860374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_full.2699860374
Directory /workspace/42.spi_device_fifo_full/latest

Test location /workspace/coverage/default/42.spi_device_fifo_underflow_overflow.3775266561
Short name T816
Test name
Test status
Simulation time 205596021056 ps
CPU time 456.37 seconds
Started Jan 21 08:13:30 PM PST 24
Finished Jan 21 08:21:07 PM PST 24
Peak memory 417984 kb
Host smart-9597f124-acdd-49b4-a0df-0e10962df18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775266561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_underflow_overf
low.3775266561
Directory /workspace/42.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1591331038
Short name T360
Test name
Test status
Simulation time 121584590573 ps
CPU time 307.6 seconds
Started Jan 21 08:13:44 PM PST 24
Finished Jan 21 08:18:52 PM PST 24
Peak memory 258416 kb
Host smart-7bd7455c-45a4-4f32-bd77-514d595f133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591331038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1591331038
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1798676972
Short name T1655
Test name
Test status
Simulation time 4087584186 ps
CPU time 61.52 seconds
Started Jan 21 08:13:53 PM PST 24
Finished Jan 21 08:14:56 PM PST 24
Peak memory 241716 kb
Host smart-2a51db1e-3c73-46ea-9ec9-8f58100c39af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798676972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1798676972
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2496099038
Short name T1514
Test name
Test status
Simulation time 86346130252 ps
CPU time 725.93 seconds
Started Jan 21 08:13:53 PM PST 24
Finished Jan 21 08:26:00 PM PST 24
Peak memory 266720 kb
Host smart-f71a17c7-dcb9-401a-9466-e9e2893d01f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496099038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2496099038
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.601465278
Short name T199
Test name
Test status
Simulation time 136494648 ps
CPU time 5.73 seconds
Started Jan 21 08:13:49 PM PST 24
Finished Jan 21 08:13:56 PM PST 24
Peak memory 233908 kb
Host smart-8e19fd77-34da-462a-a8db-3ba64981e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601465278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.601465278
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2467941837
Short name T1416
Test name
Test status
Simulation time 1470215668 ps
CPU time 3.23 seconds
Started Jan 21 08:13:46 PM PST 24
Finished Jan 21 08:13:51 PM PST 24
Peak memory 234760 kb
Host smart-53008105-68d2-4611-8d1b-341ee564cb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467941837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2467941837
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intr.702430088
Short name T1160
Test name
Test status
Simulation time 6570310977 ps
CPU time 43.02 seconds
Started Jan 21 08:13:32 PM PST 24
Finished Jan 21 08:14:17 PM PST 24
Peak memory 235904 kb
Host smart-aaa46e2a-c72b-45f5-a623-d1f74725bcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702430088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intr.702430088
Directory /workspace/42.spi_device_intr/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1104638029
Short name T260
Test name
Test status
Simulation time 1449742580 ps
CPU time 12.01 seconds
Started Jan 21 08:13:51 PM PST 24
Finished Jan 21 08:14:04 PM PST 24
Peak memory 248224 kb
Host smart-d80fbe59-dc1c-4f2d-9b6b-3520f863dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104638029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1104638029
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2308314194
Short name T701
Test name
Test status
Simulation time 14336354951 ps
CPU time 35.51 seconds
Started Jan 21 08:13:32 PM PST 24
Finished Jan 21 08:14:10 PM PST 24
Peak memory 220276 kb
Host smart-018f9d6a-f9d6-4fa0-a386-4ed7d05fc4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308314194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2308314194
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.558952735
Short name T831
Test name
Test status
Simulation time 448273252 ps
CPU time 4.75 seconds
Started Jan 21 08:13:35 PM PST 24
Finished Jan 21 08:13:41 PM PST 24
Peak memory 219712 kb
Host smart-4e948925-0a44-4993-9ac4-873af6683b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558952735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.558952735
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_perf.3382166661
Short name T1313
Test name
Test status
Simulation time 391092807743 ps
CPU time 838.3 seconds
Started Jan 21 08:13:36 PM PST 24
Finished Jan 21 08:27:35 PM PST 24
Peak memory 235784 kb
Host smart-9c5419be-fa63-4a07-9573-05cb931b33df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382166661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_perf.3382166661
Directory /workspace/42.spi_device_perf/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4092213944
Short name T201
Test name
Test status
Simulation time 1022375523 ps
CPU time 4.53 seconds
Started Jan 21 08:13:49 PM PST 24
Finished Jan 21 08:13:55 PM PST 24
Peak memory 220404 kb
Host smart-e7d8ca82-3237-4abc-96ab-2f23f8db5163
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4092213944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4092213944
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_rx_async_fifo_reset.942108695
Short name T1543
Test name
Test status
Simulation time 156793589 ps
CPU time 0.91 seconds
Started Jan 21 08:13:35 PM PST 24
Finished Jan 21 08:13:37 PM PST 24
Peak memory 208840 kb
Host smart-b4dcc7e5-70e1-4a66-869b-58ab2865a995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942108695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_async_fifo_reset.942108695
Directory /workspace/42.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_rx_timeout.521134548
Short name T1720
Test name
Test status
Simulation time 625025332 ps
CPU time 6.47 seconds
Started Jan 21 08:13:27 PM PST 24
Finished Jan 21 08:13:35 PM PST 24
Peak memory 217176 kb
Host smart-6e68b200-1deb-40ea-af7b-c59182d6bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521134548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_timeout.521134548
Directory /workspace/42.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/42.spi_device_smoke.2117819361
Short name T1256
Test name
Test status
Simulation time 166855166 ps
CPU time 1.11 seconds
Started Jan 21 08:13:32 PM PST 24
Finished Jan 21 08:13:34 PM PST 24
Peak memory 208400 kb
Host smart-a6be9d63-b4e7-455c-b1da-272ffef91aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117819361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_smoke.2117819361
Directory /workspace/42.spi_device_smoke/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2149704936
Short name T1164
Test name
Test status
Simulation time 99431439427 ps
CPU time 261.84 seconds
Started Jan 21 08:13:53 PM PST 24
Finished Jan 21 08:18:16 PM PST 24
Peak memory 258428 kb
Host smart-e14dc85b-ecb2-4d11-b0b1-769c94cad425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149704936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2149704936
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4126323347
Short name T1474
Test name
Test status
Simulation time 16232484946 ps
CPU time 73.02 seconds
Started Jan 21 08:13:35 PM PST 24
Finished Jan 21 08:14:49 PM PST 24
Peak memory 221428 kb
Host smart-9f470667-bbb1-434d-91cc-a4005c9430c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126323347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4126323347
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2420966446
Short name T1391
Test name
Test status
Simulation time 297715543 ps
CPU time 1.27 seconds
Started Jan 21 08:31:54 PM PST 24
Finished Jan 21 08:31:57 PM PST 24
Peak memory 208324 kb
Host smart-1a459a42-2d57-48d8-81ec-405763257e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420966446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2420966446
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1223641509
Short name T1292
Test name
Test status
Simulation time 71501956 ps
CPU time 1.54 seconds
Started Jan 21 08:13:37 PM PST 24
Finished Jan 21 08:13:39 PM PST 24
Peak memory 217304 kb
Host smart-5d1ffd53-cf91-4b10-89ed-de1521a78117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223641509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1223641509
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1621139406
Short name T1041
Test name
Test status
Simulation time 31885438 ps
CPU time 0.8 seconds
Started Jan 21 10:32:03 PM PST 24
Finished Jan 21 10:32:12 PM PST 24
Peak memory 207256 kb
Host smart-a02d5ff1-41af-4b19-b8e9-33064aa82b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621139406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1621139406
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tx_async_fifo_reset.4107241050
Short name T1219
Test name
Test status
Simulation time 17666917 ps
CPU time 0.84 seconds
Started Jan 21 08:13:37 PM PST 24
Finished Jan 21 08:13:39 PM PST 24
Peak memory 207716 kb
Host smart-abeacb49-7bc5-480c-9f6d-0fb774cdf0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107241050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tx_async_fifo_reset.4107241050
Directory /workspace/42.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_txrx.512706264
Short name T594
Test name
Test status
Simulation time 7721231901 ps
CPU time 152.32 seconds
Started Jan 21 08:13:32 PM PST 24
Finished Jan 21 08:16:06 PM PST 24
Peak memory 268076 kb
Host smart-28121697-232f-4189-90f0-6276bed0ba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512706264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_txrx.512706264
Directory /workspace/42.spi_device_txrx/latest

Test location /workspace/coverage/default/42.spi_device_upload.3000873711
Short name T852
Test name
Test status
Simulation time 812678205 ps
CPU time 11.97 seconds
Started Jan 21 08:13:44 PM PST 24
Finished Jan 21 08:13:57 PM PST 24
Peak memory 252632 kb
Host smart-48038e29-f5c7-4406-abc4-1c56a9b9c2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000873711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3000873711
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_abort.750518379
Short name T592
Test name
Test status
Simulation time 46730423 ps
CPU time 0.82 seconds
Started Jan 21 08:14:03 PM PST 24
Finished Jan 21 08:14:05 PM PST 24
Peak memory 207080 kb
Host smart-277d2bf0-d1d6-4ed4-9e50-9e10fe3d3432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750518379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_abort.750518379
Directory /workspace/43.spi_device_abort/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1236937466
Short name T865
Test name
Test status
Simulation time 47062707 ps
CPU time 0.74 seconds
Started Jan 21 08:32:16 PM PST 24
Finished Jan 21 08:32:17 PM PST 24
Peak memory 207000 kb
Host smart-e813c167-f267-4453-b479-00c4e648fef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236937466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1236937466
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_bit_transfer.3248402944
Short name T586
Test name
Test status
Simulation time 433064229 ps
CPU time 2.62 seconds
Started Jan 21 08:14:02 PM PST 24
Finished Jan 21 08:14:06 PM PST 24
Peak memory 217208 kb
Host smart-ce515a32-ef5c-4588-9b5c-72958ed43716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248402944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_bit_transfer.3248402944
Directory /workspace/43.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/43.spi_device_byte_transfer.3570072004
Short name T934
Test name
Test status
Simulation time 2231502938 ps
CPU time 2.95 seconds
Started Jan 21 08:13:55 PM PST 24
Finished Jan 21 08:13:59 PM PST 24
Peak memory 217300 kb
Host smart-37d1da6f-22f1-4af9-9bbc-4780e53eb178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570072004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_byte_transfer.3570072004
Directory /workspace/43.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2955615466
Short name T1546
Test name
Test status
Simulation time 293947915 ps
CPU time 4.2 seconds
Started Jan 21 08:14:16 PM PST 24
Finished Jan 21 08:14:21 PM PST 24
Peak memory 241188 kb
Host smart-ca0b8588-f908-4b4b-a879-a1c40119f5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955615466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2955615466
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2813796723
Short name T565
Test name
Test status
Simulation time 27895679 ps
CPU time 0.76 seconds
Started Jan 21 08:13:52 PM PST 24
Finished Jan 21 08:13:53 PM PST 24
Peak memory 207020 kb
Host smart-76c6da28-4e16-4322-82bd-c77e912e699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813796723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2813796723
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_dummy_item_extra_dly.771321968
Short name T1117
Test name
Test status
Simulation time 65763740389 ps
CPU time 340.14 seconds
Started Jan 21 08:13:52 PM PST 24
Finished Jan 21 08:19:33 PM PST 24
Peak memory 287588 kb
Host smart-286c2710-f7ba-4cee-94d9-d714edbb92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771321968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_dummy_item_extra_dly.771321968
Directory /workspace/43.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/43.spi_device_extreme_fifo_size.549773509
Short name T296
Test name
Test status
Simulation time 12237326831 ps
CPU time 91.22 seconds
Started Jan 21 08:13:55 PM PST 24
Finished Jan 21 08:15:28 PM PST 24
Peak memory 237384 kb
Host smart-c4acf90f-691e-445d-874b-9a3be2c4589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549773509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_extreme_fifo_size.549773509
Directory /workspace/43.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/43.spi_device_fifo_full.3808324097
Short name T1291
Test name
Test status
Simulation time 54375957741 ps
CPU time 715.59 seconds
Started Jan 21 08:13:52 PM PST 24
Finished Jan 21 08:25:49 PM PST 24
Peak memory 281324 kb
Host smart-a90d7f48-27cf-45ad-92f3-d67d81dda961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808324097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_full.3808324097
Directory /workspace/43.spi_device_fifo_full/latest

Test location /workspace/coverage/default/43.spi_device_fifo_underflow_overflow.3805010770
Short name T995
Test name
Test status
Simulation time 408617753492 ps
CPU time 2069.84 seconds
Started Jan 21 08:13:52 PM PST 24
Finished Jan 21 08:48:23 PM PST 24
Peak memory 644024 kb
Host smart-0b4b0fb1-9a62-47a0-a54a-26aaee8d0617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805010770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_underflow_overf
low.3805010770
Directory /workspace/43.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1776438701
Short name T837
Test name
Test status
Simulation time 788286845 ps
CPU time 8.42 seconds
Started Jan 21 08:30:41 PM PST 24
Finished Jan 21 08:30:52 PM PST 24
Peak memory 241888 kb
Host smart-af1e1237-5203-4c13-96a7-8a4ccc023a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776438701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1776438701
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.616973845
Short name T262
Test name
Test status
Simulation time 52017277029 ps
CPU time 312.66 seconds
Started Jan 21 08:14:14 PM PST 24
Finished Jan 21 08:19:28 PM PST 24
Peak memory 274796 kb
Host smart-4d0867fd-5bc4-421f-beba-21aab7a2ee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616973845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.616973845
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.124891903
Short name T22
Test name
Test status
Simulation time 28943517807 ps
CPU time 127.21 seconds
Started Jan 21 08:14:13 PM PST 24
Finished Jan 21 08:16:21 PM PST 24
Peak memory 240376 kb
Host smart-884508e9-f246-441c-9626-750261508af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124891903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.124891903
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2780622077
Short name T1770
Test name
Test status
Simulation time 1653533987 ps
CPU time 26.36 seconds
Started Jan 21 08:18:54 PM PST 24
Finished Jan 21 08:19:23 PM PST 24
Peak memory 237036 kb
Host smart-93ef0958-e2a4-4993-8346-eb99dd804187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780622077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2780622077
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3120192493
Short name T1261
Test name
Test status
Simulation time 7424161110 ps
CPU time 7.94 seconds
Started Jan 21 08:14:15 PM PST 24
Finished Jan 21 08:14:24 PM PST 24
Peak memory 242000 kb
Host smart-3555c7a5-4132-4b68-b92e-91465cc0fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120192493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3120192493
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.590538904
Short name T635
Test name
Test status
Simulation time 87891640101 ps
CPU time 37.51 seconds
Started Jan 21 08:14:13 PM PST 24
Finished Jan 21 08:14:51 PM PST 24
Peak memory 241984 kb
Host smart-482b8f87-eff6-4e23-81d5-5e9ad310aede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590538904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.590538904
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.381666445
Short name T1443
Test name
Test status
Simulation time 7236244153 ps
CPU time 12.16 seconds
Started Jan 21 08:14:17 PM PST 24
Finished Jan 21 08:14:30 PM PST 24
Peak memory 240828 kb
Host smart-7bc18c78-64d9-4d06-afd6-52af59991e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381666445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.381666445
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3929973457
Short name T757
Test name
Test status
Simulation time 4791235337 ps
CPU time 18 seconds
Started Jan 21 08:14:14 PM PST 24
Finished Jan 21 08:14:33 PM PST 24
Peak memory 249280 kb
Host smart-d38e6eb2-f5c7-40a3-8ead-a62e947e4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929973457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3929973457
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_perf.1172296821
Short name T1588
Test name
Test status
Simulation time 152876195347 ps
CPU time 429.08 seconds
Started Jan 21 08:13:54 PM PST 24
Finished Jan 21 08:21:04 PM PST 24
Peak memory 273916 kb
Host smart-3ab52143-2d6a-459f-adc8-df8142f41543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172296821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_perf.1172296821
Directory /workspace/43.spi_device_perf/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3807489108
Short name T43
Test name
Test status
Simulation time 388169292 ps
CPU time 4.79 seconds
Started Jan 21 08:14:13 PM PST 24
Finished Jan 21 08:14:19 PM PST 24
Peak memory 221488 kb
Host smart-51541d25-3f90-4df6-b218-a34d5060e6ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3807489108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3807489108
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_rx_async_fifo_reset.1224251620
Short name T1750
Test name
Test status
Simulation time 40964364 ps
CPU time 0.89 seconds
Started Jan 21 08:14:00 PM PST 24
Finished Jan 21 08:14:01 PM PST 24
Peak memory 208716 kb
Host smart-a37073ab-8d62-4569-aad6-75e48410e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224251620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_async_fifo_reset.1224251620
Directory /workspace/43.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_smoke.4015786058
Short name T1185
Test name
Test status
Simulation time 79007354 ps
CPU time 1.11 seconds
Started Jan 21 08:13:55 PM PST 24
Finished Jan 21 08:13:57 PM PST 24
Peak memory 208808 kb
Host smart-9f4033a9-62c7-4d7b-bd2c-4b283828a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015786058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_smoke.4015786058
Directory /workspace/43.spi_device_smoke/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2127262020
Short name T343
Test name
Test status
Simulation time 260221361711 ps
CPU time 591.77 seconds
Started Jan 21 08:14:13 PM PST 24
Finished Jan 21 08:24:06 PM PST 24
Peak memory 357012 kb
Host smart-f5f2009d-60d3-490a-bf6b-029bb47abeda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127262020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2127262020
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1008403874
Short name T120
Test name
Test status
Simulation time 8512777082 ps
CPU time 40.92 seconds
Started Jan 21 08:14:00 PM PST 24
Finished Jan 21 08:14:42 PM PST 24
Peak memory 222620 kb
Host smart-e7f0289b-da37-478f-a786-df7509d20d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008403874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1008403874
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3801900491
Short name T1138
Test name
Test status
Simulation time 809022922 ps
CPU time 3.13 seconds
Started Jan 21 08:14:00 PM PST 24
Finished Jan 21 08:14:05 PM PST 24
Peak memory 208772 kb
Host smart-4efb6053-e63a-4c8f-b703-c4dfa32994b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801900491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3801900491
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.375934375
Short name T531
Test name
Test status
Simulation time 46827058 ps
CPU time 2.48 seconds
Started Jan 21 08:14:02 PM PST 24
Finished Jan 21 08:14:05 PM PST 24
Peak memory 217196 kb
Host smart-2c17a4d1-2ff6-4eaa-8a02-19b190509261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375934375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.375934375
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4265687687
Short name T807
Test name
Test status
Simulation time 47928002 ps
CPU time 0.85 seconds
Started Jan 21 08:14:01 PM PST 24
Finished Jan 21 08:14:03 PM PST 24
Peak memory 207236 kb
Host smart-93470980-cdfb-4719-a45b-9b01c4d0e0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265687687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4265687687
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tx_async_fifo_reset.3287407528
Short name T1363
Test name
Test status
Simulation time 14274378 ps
CPU time 0.8 seconds
Started Jan 21 08:14:01 PM PST 24
Finished Jan 21 08:14:03 PM PST 24
Peak memory 208696 kb
Host smart-ad5d1e2c-f2e1-4fd3-8ee3-d78fe6b1a739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287407528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tx_async_fifo_reset.3287407528
Directory /workspace/43.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_txrx.3283529130
Short name T1302
Test name
Test status
Simulation time 163816745647 ps
CPU time 292.82 seconds
Started Jan 21 08:13:55 PM PST 24
Finished Jan 21 08:18:49 PM PST 24
Peak memory 289048 kb
Host smart-ff9153c6-b5df-41ec-bf3a-9453053701fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283529130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_txrx.3283529130
Directory /workspace/43.spi_device_txrx/latest

Test location /workspace/coverage/default/43.spi_device_upload.3892336216
Short name T279
Test name
Test status
Simulation time 3820808427 ps
CPU time 6.99 seconds
Started Jan 21 08:14:14 PM PST 24
Finished Jan 21 08:14:22 PM PST 24
Peak memory 235808 kb
Host smart-461bbec3-3045-4e87-ba0c-9569ab8e030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892336216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3892336216
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_abort.742955694
Short name T1608
Test name
Test status
Simulation time 14242586 ps
CPU time 0.77 seconds
Started Jan 21 08:14:41 PM PST 24
Finished Jan 21 08:14:46 PM PST 24
Peak memory 207072 kb
Host smart-6dfea427-3189-4881-853b-996b79cab2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742955694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_abort.742955694
Directory /workspace/44.spi_device_abort/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3566483799
Short name T1146
Test name
Test status
Simulation time 16206285 ps
CPU time 0.75 seconds
Started Jan 21 08:14:51 PM PST 24
Finished Jan 21 08:14:54 PM PST 24
Peak memory 206948 kb
Host smart-0699859f-22b4-43a2-91ef-38b432dac3ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566483799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3566483799
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_bit_transfer.2651571464
Short name T567
Test name
Test status
Simulation time 462026353 ps
CPU time 2.42 seconds
Started Jan 21 08:14:41 PM PST 24
Finished Jan 21 08:14:47 PM PST 24
Peak memory 217228 kb
Host smart-bf62b92f-b3e0-4f6a-855f-b9152defcc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651571464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_bit_transfer.2651571464
Directory /workspace/44.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/44.spi_device_byte_transfer.380286040
Short name T670
Test name
Test status
Simulation time 226017372 ps
CPU time 2.75 seconds
Started Jan 21 08:14:48 PM PST 24
Finished Jan 21 08:14:52 PM PST 24
Peak memory 217280 kb
Host smart-fabe0dd8-aabe-4c1d-b208-c46e784b68e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380286040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_byte_transfer.380286040
Directory /workspace/44.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.249280737
Short name T540
Test name
Test status
Simulation time 2744466601 ps
CPU time 10.32 seconds
Started Jan 21 08:14:51 PM PST 24
Finished Jan 21 08:15:03 PM PST 24
Peak memory 225572 kb
Host smart-ac5cb5f2-3889-4c34-9af4-5a1ea069c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249280737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.249280737
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3443580462
Short name T815
Test name
Test status
Simulation time 53002104 ps
CPU time 0.76 seconds
Started Jan 21 08:14:40 PM PST 24
Finished Jan 21 08:14:45 PM PST 24
Peak memory 206984 kb
Host smart-e18bc70a-3ced-426e-88ef-aae7e9a17d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443580462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3443580462
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_dummy_item_extra_dly.2876337740
Short name T552
Test name
Test status
Simulation time 77107860251 ps
CPU time 170.74 seconds
Started Jan 21 08:14:42 PM PST 24
Finished Jan 21 08:17:36 PM PST 24
Peak memory 267732 kb
Host smart-d621cc32-331e-4864-87b5-49bf9f5f5b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876337740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_dummy_item_extra_dly.2876337740
Directory /workspace/44.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/44.spi_device_extreme_fifo_size.701760636
Short name T1424
Test name
Test status
Simulation time 32369912467 ps
CPU time 324.99 seconds
Started Jan 21 08:14:41 PM PST 24
Finished Jan 21 08:20:10 PM PST 24
Peak memory 219568 kb
Host smart-e6af6af5-955e-4d39-a8dd-a751d3982ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701760636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_extreme_fifo_size.701760636
Directory /workspace/44.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/44.spi_device_fifo_full.2309876378
Short name T1697
Test name
Test status
Simulation time 471400958027 ps
CPU time 522.43 seconds
Started Jan 21 08:14:59 PM PST 24
Finished Jan 21 08:23:48 PM PST 24
Peak memory 303556 kb
Host smart-b5f486f5-2aeb-490b-8cf8-3c4bbc37efc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309876378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_full.2309876378
Directory /workspace/44.spi_device_fifo_full/latest

Test location /workspace/coverage/default/44.spi_device_fifo_underflow_overflow.2476530492
Short name T1552
Test name
Test status
Simulation time 16368277705 ps
CPU time 164.19 seconds
Started Jan 21 08:14:41 PM PST 24
Finished Jan 21 08:17:30 PM PST 24
Peak memory 339528 kb
Host smart-6ec7df79-6650-4d60-9ac2-b736d6a3e30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476530492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_underflow_overf
low.2476530492
Directory /workspace/44.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2682422419
Short name T1606
Test name
Test status
Simulation time 35966472685 ps
CPU time 189.11 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:18:10 PM PST 24
Peak memory 257280 kb
Host smart-4ef9ef1a-87fd-4684-bd69-e06be2358187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682422419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2682422419
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2075868065
Short name T1002
Test name
Test status
Simulation time 56686321032 ps
CPU time 330.86 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:20:30 PM PST 24
Peak memory 263924 kb
Host smart-7e54b248-e18e-4c9e-af4c-ceb82fe07b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075868065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2075868065
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2803788117
Short name T29
Test name
Test status
Simulation time 6502210693 ps
CPU time 83.83 seconds
Started Jan 21 08:14:51 PM PST 24
Finished Jan 21 08:16:17 PM PST 24
Peak memory 250352 kb
Host smart-8b133401-94b2-44c6-b286-7efdfbd7b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803788117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2803788117
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3901736411
Short name T281
Test name
Test status
Simulation time 280108295 ps
CPU time 4.77 seconds
Started Jan 21 08:14:42 PM PST 24
Finished Jan 21 08:14:50 PM PST 24
Peak memory 241948 kb
Host smart-3946a7f6-22b2-40a1-b562-28842e16061e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901736411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3901736411
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intr.3949465168
Short name T162
Test name
Test status
Simulation time 40583747583 ps
CPU time 65.52 seconds
Started Jan 21 08:14:42 PM PST 24
Finished Jan 21 08:15:51 PM PST 24
Peak memory 241628 kb
Host smart-8bb03fa6-2b11-47ae-8dcd-1bb48dcb93e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949465168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intr.3949465168
Directory /workspace/44.spi_device_intr/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1471289073
Short name T1086
Test name
Test status
Simulation time 18426086807 ps
CPU time 13.63 seconds
Started Jan 21 08:14:50 PM PST 24
Finished Jan 21 08:15:06 PM PST 24
Peak memory 240840 kb
Host smart-8a61170f-eedf-4d8f-abec-f5faa48f1788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471289073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1471289073
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3723078509
Short name T11
Test name
Test status
Simulation time 589851018 ps
CPU time 8.95 seconds
Started Jan 21 08:14:41 PM PST 24
Finished Jan 21 08:14:54 PM PST 24
Peak memory 238920 kb
Host smart-02389954-fabe-411d-a81c-0f7725c6a10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723078509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3723078509
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2850446132
Short name T991
Test name
Test status
Simulation time 1307363387 ps
CPU time 9.38 seconds
Started Jan 21 08:14:40 PM PST 24
Finished Jan 21 08:14:54 PM PST 24
Peak memory 237264 kb
Host smart-dda64b36-457e-4bcf-81bd-fcc5db00b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850446132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2850446132
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_perf.1205098365
Short name T1081
Test name
Test status
Simulation time 7938838952 ps
CPU time 230.78 seconds
Started Jan 21 08:14:44 PM PST 24
Finished Jan 21 08:18:37 PM PST 24
Peak memory 252212 kb
Host smart-5215069a-13bc-4ba0-960e-275a0e9b4ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205098365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_perf.1205098365
Directory /workspace/44.spi_device_perf/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1305936694
Short name T1248
Test name
Test status
Simulation time 1232386013 ps
CPU time 4.31 seconds
Started Jan 21 08:14:51 PM PST 24
Finished Jan 21 08:14:57 PM PST 24
Peak memory 235816 kb
Host smart-ce67011f-3511-49f3-8cd1-fefb20130ffd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1305936694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1305936694
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_rx_async_fifo_reset.1861620471
Short name T975
Test name
Test status
Simulation time 97845181 ps
CPU time 1 seconds
Started Jan 21 08:14:42 PM PST 24
Finished Jan 21 08:14:47 PM PST 24
Peak memory 208992 kb
Host smart-9ddf0eb8-cb89-4868-8345-fddf543d7023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861620471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_async_fifo_reset.1861620471
Directory /workspace/44.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_rx_timeout.3580456975
Short name T917
Test name
Test status
Simulation time 598478277 ps
CPU time 6.28 seconds
Started Jan 21 08:14:40 PM PST 24
Finished Jan 21 08:14:51 PM PST 24
Peak memory 217264 kb
Host smart-40a15492-5d5e-4901-90a6-d964d4e34cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580456975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_timeout.3580456975
Directory /workspace/44.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/44.spi_device_smoke.1678621445
Short name T502
Test name
Test status
Simulation time 39856360 ps
CPU time 1.07 seconds
Started Jan 21 08:46:20 PM PST 24
Finished Jan 21 08:47:10 PM PST 24
Peak memory 208752 kb
Host smart-91d431be-3790-4e2a-824f-a05decdcc14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678621445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_smoke.1678621445
Directory /workspace/44.spi_device_smoke/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4116217052
Short name T131
Test name
Test status
Simulation time 1430625969 ps
CPU time 16.93 seconds
Started Jan 21 08:14:40 PM PST 24
Finished Jan 21 08:15:01 PM PST 24
Peak memory 220820 kb
Host smart-68ea68f3-0019-49eb-895f-e1dea073611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116217052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4116217052
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.82213966
Short name T1208
Test name
Test status
Simulation time 21530354244 ps
CPU time 33.43 seconds
Started Jan 21 08:14:42 PM PST 24
Finished Jan 21 08:15:19 PM PST 24
Peak memory 217380 kb
Host smart-0f3f9dc5-aa6b-4a83-ad11-02bd4e5f54f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82213966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.82213966
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3404141600
Short name T1601
Test name
Test status
Simulation time 611391382 ps
CPU time 11.49 seconds
Started Jan 21 08:14:42 PM PST 24
Finished Jan 21 08:14:57 PM PST 24
Peak memory 217272 kb
Host smart-ccaa7985-dd25-473d-9887-f8378be9a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404141600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3404141600
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3749373592
Short name T855
Test name
Test status
Simulation time 206366972 ps
CPU time 1.08 seconds
Started Jan 21 08:14:42 PM PST 24
Finished Jan 21 08:14:47 PM PST 24
Peak memory 207272 kb
Host smart-e6d08652-ec67-40df-a616-ae3b7730bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749373592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3749373592
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tx_async_fifo_reset.1105092402
Short name T1628
Test name
Test status
Simulation time 77018981 ps
CPU time 0.8 seconds
Started Jan 21 08:14:43 PM PST 24
Finished Jan 21 08:14:47 PM PST 24
Peak memory 208800 kb
Host smart-8f3c62af-49ea-414a-9bd3-0612aebf460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105092402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tx_async_fifo_reset.1105092402
Directory /workspace/44.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_txrx.1482815805
Short name T1618
Test name
Test status
Simulation time 90675069381 ps
CPU time 1566.8 seconds
Started Jan 21 08:14:40 PM PST 24
Finished Jan 21 08:40:51 PM PST 24
Peak memory 257340 kb
Host smart-cd64252e-5f94-4ade-8c62-61ab3c2b37a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482815805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_txrx.1482815805
Directory /workspace/44.spi_device_txrx/latest

Test location /workspace/coverage/default/44.spi_device_upload.1754713914
Short name T19
Test name
Test status
Simulation time 3215615508 ps
CPU time 8.51 seconds
Started Jan 21 08:14:52 PM PST 24
Finished Jan 21 08:15:06 PM PST 24
Peak memory 219968 kb
Host smart-c5829e28-bb89-437b-b148-2ae4a5467815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754713914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1754713914
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_abort.2115837743
Short name T758
Test name
Test status
Simulation time 46029007 ps
CPU time 0.77 seconds
Started Jan 21 08:14:58 PM PST 24
Finished Jan 21 08:15:02 PM PST 24
Peak memory 207064 kb
Host smart-f09f4a68-ad46-4e16-908a-618698f0d95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115837743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_abort.2115837743
Directory /workspace/45.spi_device_abort/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.255640666
Short name T1035
Test name
Test status
Simulation time 44356444 ps
CPU time 0.76 seconds
Started Jan 21 08:15:09 PM PST 24
Finished Jan 21 08:15:13 PM PST 24
Peak memory 206984 kb
Host smart-e86ffe54-8a3c-4d86-9373-82297246754a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255640666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.255640666
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_bit_transfer.1742133038
Short name T636
Test name
Test status
Simulation time 685902492 ps
CPU time 2.68 seconds
Started Jan 21 08:14:55 PM PST 24
Finished Jan 21 08:15:03 PM PST 24
Peak memory 217196 kb
Host smart-d323111f-cde0-4daf-a9e5-09c5b9cb2dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742133038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_bit_transfer.1742133038
Directory /workspace/45.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/45.spi_device_byte_transfer.2819104117
Short name T1334
Test name
Test status
Simulation time 138016106 ps
CPU time 3.18 seconds
Started Jan 21 08:14:54 PM PST 24
Finished Jan 21 08:15:04 PM PST 24
Peak memory 217240 kb
Host smart-bf7bdfc5-a261-4710-838b-79087e67e638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819104117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_byte_transfer.2819104117
Directory /workspace/45.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1669504537
Short name T1615
Test name
Test status
Simulation time 2418137172 ps
CPU time 4.82 seconds
Started Jan 21 08:14:56 PM PST 24
Finished Jan 21 08:15:06 PM PST 24
Peak memory 221056 kb
Host smart-96ea39d8-b98b-47a6-b069-5970ff4e90bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669504537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1669504537
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2007394338
Short name T1234
Test name
Test status
Simulation time 40955303 ps
CPU time 0.8 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:15:02 PM PST 24
Peak memory 207020 kb
Host smart-913ee970-3967-431a-bfd7-c805abce954b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007394338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2007394338
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_dummy_item_extra_dly.684750616
Short name T1129
Test name
Test status
Simulation time 50536778971 ps
CPU time 770.25 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:27:50 PM PST 24
Peak memory 295712 kb
Host smart-febfd3b2-d20a-494d-8321-3a58bf495567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684750616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_dummy_item_extra_dly.684750616
Directory /workspace/45.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/45.spi_device_extreme_fifo_size.2734151626
Short name T1189
Test name
Test status
Simulation time 65191214177 ps
CPU time 1217.04 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:35:18 PM PST 24
Peak memory 221460 kb
Host smart-1c9184bc-7ecb-4e66-889b-13f0b5bd5337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734151626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_extreme_fifo_size.2734151626
Directory /workspace/45.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/45.spi_device_fifo_full.2260819671
Short name T1503
Test name
Test status
Simulation time 38499463227 ps
CPU time 2287.44 seconds
Started Jan 21 08:14:50 PM PST 24
Finished Jan 21 08:53:00 PM PST 24
Peak memory 293296 kb
Host smart-37852700-cb16-481c-8ffa-623f2bda80b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260819671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_full.2260819671
Directory /workspace/45.spi_device_fifo_full/latest

Test location /workspace/coverage/default/45.spi_device_fifo_underflow_overflow.3991526765
Short name T1622
Test name
Test status
Simulation time 68383274529 ps
CPU time 99.17 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:16:40 PM PST 24
Peak memory 267496 kb
Host smart-f98ecb9c-75c5-4f5f-ada9-cc0ee07f9dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991526765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_underflow_overf
low.3991526765
Directory /workspace/45.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2623047148
Short name T682
Test name
Test status
Simulation time 1044350770 ps
CPU time 11.35 seconds
Started Jan 21 08:15:11 PM PST 24
Finished Jan 21 08:15:26 PM PST 24
Peak memory 239436 kb
Host smart-f194fb64-c90a-4a53-969f-c0c20e78b127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623047148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2623047148
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1896597290
Short name T696
Test name
Test status
Simulation time 7838990220 ps
CPU time 47.37 seconds
Started Jan 21 08:15:10 PM PST 24
Finished Jan 21 08:16:02 PM PST 24
Peak memory 234956 kb
Host smart-4490436c-70c2-4715-b01b-e8d7d72bcf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896597290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1896597290
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3455884726
Short name T1319
Test name
Test status
Simulation time 21898874437 ps
CPU time 205.68 seconds
Started Jan 21 08:15:11 PM PST 24
Finished Jan 21 08:18:41 PM PST 24
Peak memory 251340 kb
Host smart-825ff25d-cdb1-4af2-bba5-7d5f66fde9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455884726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3455884726
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1113986971
Short name T265
Test name
Test status
Simulation time 1232029590 ps
CPU time 8.66 seconds
Started Jan 21 08:14:59 PM PST 24
Finished Jan 21 08:15:13 PM PST 24
Peak memory 238620 kb
Host smart-b8935bf9-f6ee-4fa3-9f7c-df5d4c0eb768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113986971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1113986971
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.596963036
Short name T276
Test name
Test status
Simulation time 1705084953 ps
CPU time 5.98 seconds
Started Jan 21 08:14:59 PM PST 24
Finished Jan 21 08:15:11 PM PST 24
Peak memory 225576 kb
Host smart-32afaa86-f5ff-49fa-a19a-b2859e9f5845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596963036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.596963036
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intr.2426245460
Short name T126
Test name
Test status
Simulation time 30276473128 ps
CPU time 131.78 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:17:13 PM PST 24
Peak memory 251384 kb
Host smart-203e78a7-5e2c-41e6-b66f-63203716d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426245460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intr.2426245460
Directory /workspace/45.spi_device_intr/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3817560621
Short name T1077
Test name
Test status
Simulation time 7375585956 ps
CPU time 19.87 seconds
Started Jan 21 08:14:54 PM PST 24
Finished Jan 21 08:15:21 PM PST 24
Peak memory 249420 kb
Host smart-b69ce0a1-f211-4817-826a-646fca060d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817560621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3817560621
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1033102835
Short name T1742
Test name
Test status
Simulation time 1554977936 ps
CPU time 7.99 seconds
Started Jan 21 08:14:59 PM PST 24
Finished Jan 21 08:15:13 PM PST 24
Peak memory 250160 kb
Host smart-ccbbff03-bb4a-4455-8ebb-bb091922aba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033102835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1033102835
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.785104736
Short name T746
Test name
Test status
Simulation time 986446484 ps
CPU time 4.41 seconds
Started Jan 21 08:14:57 PM PST 24
Finished Jan 21 08:15:06 PM PST 24
Peak memory 218560 kb
Host smart-e9987b47-9019-4a04-ab19-95e53f7f1376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785104736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.785104736
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_perf.601217928
Short name T1136
Test name
Test status
Simulation time 72928494258 ps
CPU time 1086.01 seconds
Started Jan 21 08:14:54 PM PST 24
Finished Jan 21 08:33:07 PM PST 24
Peak memory 241780 kb
Host smart-41dcb7cf-bb85-408c-8e5b-2fd0e84cb89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601217928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_perf.601217928
Directory /workspace/45.spi_device_perf/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2829827306
Short name T989
Test name
Test status
Simulation time 624604272 ps
CPU time 4.47 seconds
Started Jan 21 08:35:03 PM PST 24
Finished Jan 21 08:35:08 PM PST 24
Peak memory 221708 kb
Host smart-68a68c33-cd5b-4647-b7c3-b306e0ff1171
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2829827306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2829827306
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_rx_async_fifo_reset.3299472122
Short name T834
Test name
Test status
Simulation time 84302151 ps
CPU time 0.98 seconds
Started Jan 21 08:14:54 PM PST 24
Finished Jan 21 08:15:02 PM PST 24
Peak memory 208796 kb
Host smart-7d24903f-6278-4f4f-a105-d318452087d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299472122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_async_fifo_reset.3299472122
Directory /workspace/45.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_rx_timeout.3849824691
Short name T1421
Test name
Test status
Simulation time 1461444951 ps
CPU time 5.29 seconds
Started Jan 21 08:14:55 PM PST 24
Finished Jan 21 08:15:06 PM PST 24
Peak memory 216964 kb
Host smart-f9190c09-8f1c-4041-8e25-2db0eb9b5ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849824691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_timeout.3849824691
Directory /workspace/45.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/45.spi_device_smoke.2756472998
Short name T647
Test name
Test status
Simulation time 48467509 ps
CPU time 1.05 seconds
Started Jan 21 08:14:50 PM PST 24
Finished Jan 21 08:14:53 PM PST 24
Peak memory 208328 kb
Host smart-016bf64a-d4a8-4ff6-9ce2-e41a876e394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756472998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_smoke.2756472998
Directory /workspace/45.spi_device_smoke/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2062396656
Short name T1654
Test name
Test status
Simulation time 26147163268 ps
CPU time 259.17 seconds
Started Jan 21 08:15:07 PM PST 24
Finished Jan 21 08:19:28 PM PST 24
Peak memory 348384 kb
Host smart-f2ee6c62-eed5-4e3e-af7d-e8344cbd546f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062396656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2062396656
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3853545304
Short name T1624
Test name
Test status
Simulation time 153359499458 ps
CPU time 203.92 seconds
Started Jan 21 08:14:54 PM PST 24
Finished Jan 21 08:18:25 PM PST 24
Peak memory 217396 kb
Host smart-eb10227a-95eb-404e-a0bd-cff79ebf98a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853545304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3853545304
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1950199598
Short name T1530
Test name
Test status
Simulation time 17766049825 ps
CPU time 13.86 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:15:15 PM PST 24
Peak memory 217284 kb
Host smart-22db506d-1e9f-4272-ac21-00357c77296b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950199598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1950199598
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2572591226
Short name T1279
Test name
Test status
Simulation time 77721672 ps
CPU time 2.03 seconds
Started Jan 21 08:14:57 PM PST 24
Finished Jan 21 08:15:03 PM PST 24
Peak memory 217236 kb
Host smart-e55eef80-dcdd-414f-ae5a-24877eff8815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572591226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2572591226
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2976000275
Short name T1428
Test name
Test status
Simulation time 153020594 ps
CPU time 0.83 seconds
Started Jan 21 08:14:59 PM PST 24
Finished Jan 21 08:15:06 PM PST 24
Peak memory 207256 kb
Host smart-7e682561-90f1-4b4f-b121-39004c161ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976000275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2976000275
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tx_async_fifo_reset.2862229985
Short name T570
Test name
Test status
Simulation time 14552596 ps
CPU time 0.79 seconds
Started Jan 21 08:14:53 PM PST 24
Finished Jan 21 08:15:01 PM PST 24
Peak memory 207684 kb
Host smart-e32446a5-0111-4964-b449-f6ea8cf800f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862229985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tx_async_fifo_reset.2862229985
Directory /workspace/45.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_txrx.2656573756
Short name T1693
Test name
Test status
Simulation time 12118336723 ps
CPU time 148.24 seconds
Started Jan 21 08:14:52 PM PST 24
Finished Jan 21 08:17:27 PM PST 24
Peak memory 273028 kb
Host smart-c5c5e7d8-36d5-4b8e-a9e8-1bb1cfa41377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656573756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_txrx.2656573756
Directory /workspace/45.spi_device_txrx/latest

Test location /workspace/coverage/default/45.spi_device_upload.1156753659
Short name T267
Test name
Test status
Simulation time 1035771115 ps
CPU time 3.36 seconds
Started Jan 21 08:35:16 PM PST 24
Finished Jan 21 08:35:20 PM PST 24
Peak memory 234724 kb
Host smart-74667407-6558-4609-9cce-25552d61c18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156753659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1156753659
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_abort.1767011602
Short name T687
Test name
Test status
Simulation time 47874030 ps
CPU time 0.75 seconds
Started Jan 21 08:15:33 PM PST 24
Finished Jan 21 08:15:36 PM PST 24
Peak memory 207124 kb
Host smart-2286d327-10fa-4f47-8585-fd9474c22583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767011602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_abort.1767011602
Directory /workspace/46.spi_device_abort/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.327596638
Short name T627
Test name
Test status
Simulation time 47395584 ps
CPU time 0.78 seconds
Started Jan 21 08:15:40 PM PST 24
Finished Jan 21 08:15:43 PM PST 24
Peak memory 206984 kb
Host smart-ed425da5-bca4-4e76-aa57-b978778c45d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327596638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.327596638
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_bit_transfer.1716315533
Short name T1732
Test name
Test status
Simulation time 1062915867 ps
CPU time 2.45 seconds
Started Jan 21 08:15:27 PM PST 24
Finished Jan 21 08:15:32 PM PST 24
Peak memory 217212 kb
Host smart-3c7f37ec-3adb-45e9-a619-59b98cb5602d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716315533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_bit_transfer.1716315533
Directory /workspace/46.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/46.spi_device_byte_transfer.1848685806
Short name T1112
Test name
Test status
Simulation time 332296919 ps
CPU time 3.22 seconds
Started Jan 21 08:15:16 PM PST 24
Finished Jan 21 08:15:27 PM PST 24
Peak memory 217232 kb
Host smart-45032bbb-26de-49be-9879-8711ffaf9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848685806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_byte_transfer.1848685806
Directory /workspace/46.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.168233470
Short name T1272
Test name
Test status
Simulation time 462657578 ps
CPU time 3.71 seconds
Started Jan 21 08:15:38 PM PST 24
Finished Jan 21 08:15:45 PM PST 24
Peak memory 238908 kb
Host smart-71196997-8662-462d-af75-0d176c58cab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168233470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.168233470
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4261102721
Short name T483
Test name
Test status
Simulation time 41085338 ps
CPU time 0.75 seconds
Started Jan 21 08:15:16 PM PST 24
Finished Jan 21 08:15:24 PM PST 24
Peak memory 207004 kb
Host smart-1bc57699-3068-496f-8dec-e92e8dfd8a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261102721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4261102721
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_dummy_item_extra_dly.359470158
Short name T620
Test name
Test status
Simulation time 22309163190 ps
CPU time 337.12 seconds
Started Jan 21 08:15:15 PM PST 24
Finished Jan 21 08:20:59 PM PST 24
Peak memory 265776 kb
Host smart-683562ef-d457-4e66-ade1-9085eb6b2cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359470158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_dummy_item_extra_dly.359470158
Directory /workspace/46.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/46.spi_device_extreme_fifo_size.3225960776
Short name T58
Test name
Test status
Simulation time 30444802912 ps
CPU time 526.01 seconds
Started Jan 21 08:15:15 PM PST 24
Finished Jan 21 08:24:08 PM PST 24
Peak memory 217352 kb
Host smart-949aaaf1-75c0-435c-b802-5277f588b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225960776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_extreme_fifo_size.3225960776
Directory /workspace/46.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/46.spi_device_fifo_full.3438863670
Short name T1665
Test name
Test status
Simulation time 33395337204 ps
CPU time 1750.1 seconds
Started Jan 21 08:46:22 PM PST 24
Finished Jan 21 09:16:21 PM PST 24
Peak memory 282768 kb
Host smart-212d4d8e-318e-426f-9252-a5df00f10f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438863670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_full.3438863670
Directory /workspace/46.spi_device_fifo_full/latest

Test location /workspace/coverage/default/46.spi_device_fifo_underflow_overflow.3655482845
Short name T729
Test name
Test status
Simulation time 355628168696 ps
CPU time 239.65 seconds
Started Jan 21 08:15:15 PM PST 24
Finished Jan 21 08:19:22 PM PST 24
Peak memory 307400 kb
Host smart-8d885909-f4de-4099-87fd-3322e666c713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655482845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_underflow_overf
low.3655482845
Directory /workspace/46.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.628589680
Short name T1574
Test name
Test status
Simulation time 9230749396 ps
CPU time 44.15 seconds
Started Jan 21 08:15:37 PM PST 24
Finished Jan 21 08:16:24 PM PST 24
Peak memory 258292 kb
Host smart-8d0937ec-80a0-4be8-8b03-9a411544e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628589680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.628589680
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3354612246
Short name T1658
Test name
Test status
Simulation time 79406915122 ps
CPU time 173.27 seconds
Started Jan 21 08:15:35 PM PST 24
Finished Jan 21 08:18:30 PM PST 24
Peak memory 254208 kb
Host smart-c2fd0e0a-580b-4de8-b5c1-75fa7a350d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354612246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3354612246
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.568880068
Short name T1763
Test name
Test status
Simulation time 10233047952 ps
CPU time 161.53 seconds
Started Jan 21 08:15:35 PM PST 24
Finished Jan 21 08:18:18 PM PST 24
Peak memory 271628 kb
Host smart-4ef3c8d4-f377-4816-80ae-2a76c67f365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568880068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.568880068
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.340181644
Short name T1643
Test name
Test status
Simulation time 17977348317 ps
CPU time 19.45 seconds
Started Jan 21 08:15:36 PM PST 24
Finished Jan 21 08:15:58 PM PST 24
Peak memory 235328 kb
Host smart-608a5e35-c4bf-4cb3-bbc7-d4014b823905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340181644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.340181644
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.50124698
Short name T1383
Test name
Test status
Simulation time 1548219167 ps
CPU time 6.13 seconds
Started Jan 21 08:15:36 PM PST 24
Finished Jan 21 08:15:44 PM PST 24
Peak memory 241900 kb
Host smart-cd55c9da-7356-4e77-b5c7-15982efb0e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50124698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.50124698
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intr.1960173735
Short name T1379
Test name
Test status
Simulation time 51037978551 ps
CPU time 26.08 seconds
Started Jan 21 09:40:10 PM PST 24
Finished Jan 21 09:40:43 PM PST 24
Peak memory 219000 kb
Host smart-5109301d-7cab-4113-8bed-20e2b5be14bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960173735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intr.1960173735
Directory /workspace/46.spi_device_intr/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3109461783
Short name T1230
Test name
Test status
Simulation time 2848060314 ps
CPU time 20.93 seconds
Started Jan 21 08:15:33 PM PST 24
Finished Jan 21 08:15:55 PM PST 24
Peak memory 235704 kb
Host smart-5659e0d2-797e-4017-b86c-5468fd2a22e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109461783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3109461783
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2641841441
Short name T1434
Test name
Test status
Simulation time 146594440 ps
CPU time 3.17 seconds
Started Jan 21 08:15:34 PM PST 24
Finished Jan 21 08:15:39 PM PST 24
Peak memory 238436 kb
Host smart-f03cc2c9-35b3-45ee-b17c-da96e805f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641841441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2641841441
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2547178252
Short name T1452
Test name
Test status
Simulation time 2196507721 ps
CPU time 11.19 seconds
Started Jan 21 08:15:36 PM PST 24
Finished Jan 21 08:15:49 PM PST 24
Peak memory 221144 kb
Host smart-aca05d62-670e-43ce-b9e8-4834bc5cca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547178252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2547178252
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_perf.3400042500
Short name T718
Test name
Test status
Simulation time 96984987818 ps
CPU time 1833.57 seconds
Started Jan 21 08:15:16 PM PST 24
Finished Jan 21 08:45:57 PM PST 24
Peak memory 282580 kb
Host smart-68de8511-bec1-49b5-a56a-94cfe70d7fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400042500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_perf.3400042500
Directory /workspace/46.spi_device_perf/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.320417629
Short name T1067
Test name
Test status
Simulation time 1656697496 ps
CPU time 4.08 seconds
Started Jan 21 08:15:39 PM PST 24
Finished Jan 21 08:15:46 PM PST 24
Peak memory 218988 kb
Host smart-75e0931f-758f-4266-a554-3b4dda944cd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=320417629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.320417629
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_rx_async_fifo_reset.4167260539
Short name T1749
Test name
Test status
Simulation time 144770491 ps
CPU time 1.02 seconds
Started Jan 21 08:15:27 PM PST 24
Finished Jan 21 08:15:31 PM PST 24
Peak memory 208780 kb
Host smart-81b53084-14c8-40c3-ba8b-1c20717653ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167260539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_async_fifo_reset.4167260539
Directory /workspace/46.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_rx_timeout.1630033046
Short name T1149
Test name
Test status
Simulation time 1781860088 ps
CPU time 7.13 seconds
Started Jan 21 08:15:17 PM PST 24
Finished Jan 21 08:15:32 PM PST 24
Peak memory 217264 kb
Host smart-b16e4620-cf94-41a9-8cb1-52101b9a0380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630033046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_timeout.1630033046
Directory /workspace/46.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/46.spi_device_smoke.2658818845
Short name T582
Test name
Test status
Simulation time 28359133 ps
CPU time 1 seconds
Started Jan 21 08:15:08 PM PST 24
Finished Jan 21 08:15:10 PM PST 24
Peak memory 208944 kb
Host smart-7533df9f-b0ec-41c6-b51a-2f00c189bcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658818845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_smoke.2658818845
Directory /workspace/46.spi_device_smoke/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.930225573
Short name T1515
Test name
Test status
Simulation time 10402852847 ps
CPU time 24.03 seconds
Started Jan 21 08:15:27 PM PST 24
Finished Jan 21 08:15:54 PM PST 24
Peak memory 217676 kb
Host smart-407e8629-4059-4041-ba47-3ed939d00d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930225573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.930225573
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.515944058
Short name T557
Test name
Test status
Simulation time 65528510583 ps
CPU time 27.76 seconds
Started Jan 21 08:15:26 PM PST 24
Finished Jan 21 08:15:57 PM PST 24
Peak memory 217304 kb
Host smart-0795b343-090e-43ba-99f4-4248e96a0367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515944058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.515944058
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2315699070
Short name T1406
Test name
Test status
Simulation time 1550980856 ps
CPU time 5.03 seconds
Started Jan 21 08:15:33 PM PST 24
Finished Jan 21 08:15:40 PM PST 24
Peak memory 217236 kb
Host smart-abb18d33-186f-4f94-b00e-746f74a61a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315699070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2315699070
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3700052874
Short name T1047
Test name
Test status
Simulation time 630238957 ps
CPU time 1.23 seconds
Started Jan 21 08:15:33 PM PST 24
Finished Jan 21 08:15:36 PM PST 24
Peak memory 208384 kb
Host smart-eb8b5d63-1918-4ea3-bebe-a91593dc9d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700052874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3700052874
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tx_async_fifo_reset.3323160583
Short name T1276
Test name
Test status
Simulation time 14599201 ps
CPU time 0.78 seconds
Started Jan 21 08:15:25 PM PST 24
Finished Jan 21 08:15:30 PM PST 24
Peak memory 208768 kb
Host smart-d1194483-83a2-4d48-9160-f29594ee8fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323160583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tx_async_fifo_reset.3323160583
Directory /workspace/46.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_txrx.809276767
Short name T501
Test name
Test status
Simulation time 12119659030 ps
CPU time 123.44 seconds
Started Jan 21 08:15:16 PM PST 24
Finished Jan 21 08:17:27 PM PST 24
Peak memory 253392 kb
Host smart-5b834978-92bb-4354-9bdc-87958ce64d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809276767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_txrx.809276767
Directory /workspace/46.spi_device_txrx/latest

Test location /workspace/coverage/default/46.spi_device_upload.1143304324
Short name T892
Test name
Test status
Simulation time 239183038 ps
CPU time 3.52 seconds
Started Jan 21 08:15:37 PM PST 24
Finished Jan 21 08:15:43 PM PST 24
Peak memory 233876 kb
Host smart-2275ffec-94eb-4b9e-b99f-6c790570830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143304324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1143304324
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_abort.2264879192
Short name T962
Test name
Test status
Simulation time 52945146 ps
CPU time 0.78 seconds
Started Jan 21 08:15:55 PM PST 24
Finished Jan 21 08:15:58 PM PST 24
Peak memory 207076 kb
Host smart-9b8036d4-8fc0-4ce0-a778-4c31ccfabff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264879192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_abort.2264879192
Directory /workspace/47.spi_device_abort/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1766501053
Short name T1123
Test name
Test status
Simulation time 114999330 ps
CPU time 0.72 seconds
Started Jan 21 08:16:04 PM PST 24
Finished Jan 21 08:16:07 PM PST 24
Peak memory 206972 kb
Host smart-ea6f2aae-a25d-4c2a-ade4-c852361ca3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766501053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1766501053
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_bit_transfer.58429006
Short name T537
Test name
Test status
Simulation time 2224015742 ps
CPU time 2.77 seconds
Started Jan 21 08:15:55 PM PST 24
Finished Jan 21 08:16:00 PM PST 24
Peak memory 217244 kb
Host smart-0da43283-5315-41d3-a814-3bd848deb48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58429006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_bit_transfer.58429006
Directory /workspace/47.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/47.spi_device_byte_transfer.2790598098
Short name T1511
Test name
Test status
Simulation time 276743685 ps
CPU time 3.63 seconds
Started Jan 21 08:15:46 PM PST 24
Finished Jan 21 08:15:52 PM PST 24
Peak memory 217192 kb
Host smart-84903a09-eca8-459a-a12e-d4315f9a0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790598098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_byte_transfer.2790598098
Directory /workspace/47.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1169130618
Short name T764
Test name
Test status
Simulation time 804083657 ps
CPU time 4.69 seconds
Started Jan 21 08:59:05 PM PST 24
Finished Jan 21 08:59:35 PM PST 24
Peak memory 236996 kb
Host smart-0cc60c01-67d2-4b54-bf4d-3e69819a0a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169130618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1169130618
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1797721451
Short name T541
Test name
Test status
Simulation time 74538291 ps
CPU time 0.8 seconds
Started Jan 21 08:15:50 PM PST 24
Finished Jan 21 08:15:54 PM PST 24
Peak memory 208048 kb
Host smart-a49af18a-537f-47f4-9e53-4976feb8e0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797721451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1797721451
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_dummy_item_extra_dly.64324384
Short name T854
Test name
Test status
Simulation time 41045756731 ps
CPU time 300.39 seconds
Started Jan 21 08:15:44 PM PST 24
Finished Jan 21 08:20:46 PM PST 24
Peak memory 268236 kb
Host smart-488c872f-d98a-4854-b027-8b7b320c665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64324384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_dummy_item_extra_dly.64324384
Directory /workspace/47.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/47.spi_device_extreme_fifo_size.3501061651
Short name T1714
Test name
Test status
Simulation time 56059667009 ps
CPU time 668.84 seconds
Started Jan 21 08:15:36 PM PST 24
Finished Jan 21 08:26:46 PM PST 24
Peak memory 219436 kb
Host smart-2caba7be-5df5-47bb-8c9d-0df62ebcd31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501061651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_extreme_fifo_size.3501061651
Directory /workspace/47.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/47.spi_device_fifo_full.59146776
Short name T638
Test name
Test status
Simulation time 87110980294 ps
CPU time 1337.6 seconds
Started Jan 21 08:37:03 PM PST 24
Finished Jan 21 08:59:24 PM PST 24
Peak memory 303640 kb
Host smart-7b8fe7cf-19a9-4ae6-b7e7-35d834f4a277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59146776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_full.59146776
Directory /workspace/47.spi_device_fifo_full/latest

Test location /workspace/coverage/default/47.spi_device_fifo_underflow_overflow.2768836586
Short name T1141
Test name
Test status
Simulation time 216051289827 ps
CPU time 257.93 seconds
Started Jan 21 08:15:38 PM PST 24
Finished Jan 21 08:19:58 PM PST 24
Peak memory 322948 kb
Host smart-8e84f3d9-1121-4d5e-ad99-b36b1fffe329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768836586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_underflow_overf
low.2768836586
Directory /workspace/47.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1508443427
Short name T335
Test name
Test status
Simulation time 31343037768 ps
CPU time 124.87 seconds
Started Jan 21 08:15:53 PM PST 24
Finished Jan 21 08:18:02 PM PST 24
Peak memory 258396 kb
Host smart-b1114b07-ed37-4895-b459-49f5f71b0e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508443427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1508443427
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4246878865
Short name T1341
Test name
Test status
Simulation time 322776883189 ps
CPU time 181.86 seconds
Started Jan 21 08:15:54 PM PST 24
Finished Jan 21 08:18:59 PM PST 24
Peak memory 254992 kb
Host smart-0591801b-9ffe-47e3-b30c-7f37775cdbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246878865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4246878865
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3622919953
Short name T367
Test name
Test status
Simulation time 55693305569 ps
CPU time 314.55 seconds
Started Jan 21 08:16:04 PM PST 24
Finished Jan 21 08:21:21 PM PST 24
Peak memory 266676 kb
Host smart-09d7d230-e0e2-436b-939d-2a781c9b6b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622919953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3622919953
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.446831377
Short name T1495
Test name
Test status
Simulation time 1270678470 ps
CPU time 22.88 seconds
Started Jan 21 08:15:57 PM PST 24
Finished Jan 21 08:16:23 PM PST 24
Peak memory 249556 kb
Host smart-cb0b0ff7-0476-49de-a4ab-6c2512e9f549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446831377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.446831377
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.192968223
Short name T274
Test name
Test status
Simulation time 583743665 ps
CPU time 4.49 seconds
Started Jan 21 08:15:56 PM PST 24
Finished Jan 21 08:16:03 PM PST 24
Peak memory 219580 kb
Host smart-3c8ec281-ff2f-4514-92df-679fbd363093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192968223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.192968223
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intr.4233452338
Short name T544
Test name
Test status
Simulation time 2944007367 ps
CPU time 13.39 seconds
Started Jan 21 08:15:51 PM PST 24
Finished Jan 21 08:16:07 PM PST 24
Peak memory 218252 kb
Host smart-f8bfc171-3827-4482-a14f-8b00a343e9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233452338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intr.4233452338
Directory /workspace/47.spi_device_intr/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3258795424
Short name T1029
Test name
Test status
Simulation time 13305253827 ps
CPU time 9.64 seconds
Started Jan 21 08:15:51 PM PST 24
Finished Jan 21 08:16:05 PM PST 24
Peak memory 241600 kb
Host smart-d2782f35-ce00-42d7-b3f3-4c6cce78a33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258795424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3258795424
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.732466372
Short name T1496
Test name
Test status
Simulation time 4777747631 ps
CPU time 11.42 seconds
Started Jan 21 08:15:53 PM PST 24
Finished Jan 21 08:16:08 PM PST 24
Peak memory 250188 kb
Host smart-5149ea3b-86b0-4647-b92f-7f9b17d84da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732466372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.732466372
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2479791166
Short name T1405
Test name
Test status
Simulation time 185444431 ps
CPU time 5 seconds
Started Jan 21 08:15:53 PM PST 24
Finished Jan 21 08:16:02 PM PST 24
Peak memory 238924 kb
Host smart-b326d3ef-375c-4e61-a6f7-3fdf9d46ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479791166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2479791166
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_perf.1542286273
Short name T1193
Test name
Test status
Simulation time 79297172879 ps
CPU time 634.96 seconds
Started Jan 21 08:15:45 PM PST 24
Finished Jan 21 08:26:22 PM PST 24
Peak memory 288344 kb
Host smart-3a6369b1-db40-4f52-b8cf-8758c1e5064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542286273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_perf.1542286273
Directory /workspace/47.spi_device_perf/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1577804291
Short name T1090
Test name
Test status
Simulation time 761825336 ps
CPU time 4.11 seconds
Started Jan 21 08:15:54 PM PST 24
Finished Jan 21 08:16:01 PM PST 24
Peak memory 234584 kb
Host smart-7b2e4820-456f-4b40-9f74-4be894a38a85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577804291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1577804291
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_rx_async_fifo_reset.3071779521
Short name T1649
Test name
Test status
Simulation time 42949257 ps
CPU time 1.01 seconds
Started Jan 21 08:15:57 PM PST 24
Finished Jan 21 08:16:01 PM PST 24
Peak memory 208836 kb
Host smart-9a8b54d4-9ed8-4273-98dd-e8cca7d614cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071779521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_async_fifo_reset.3071779521
Directory /workspace/47.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_smoke.998049284
Short name T911
Test name
Test status
Simulation time 296203054 ps
CPU time 1.14 seconds
Started Jan 21 08:15:37 PM PST 24
Finished Jan 21 08:15:40 PM PST 24
Peak memory 208784 kb
Host smart-cfb97813-7eb2-4808-af0c-151ba99df2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998049284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_smoke.998049284
Directory /workspace/47.spi_device_smoke/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4099472163
Short name T1550
Test name
Test status
Simulation time 148870850234 ps
CPU time 3781.19 seconds
Started Jan 21 08:16:01 PM PST 24
Finished Jan 21 09:19:05 PM PST 24
Peak memory 337868 kb
Host smart-401dacd9-f46d-4c04-830f-96405f0f5f63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099472163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4099472163
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1654491185
Short name T634
Test name
Test status
Simulation time 2497699257 ps
CPU time 20.09 seconds
Started Jan 21 08:15:55 PM PST 24
Finished Jan 21 08:16:17 PM PST 24
Peak memory 217368 kb
Host smart-9cb7e68c-6fcd-4304-a572-7c54f20aff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654491185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1654491185
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3227518247
Short name T1043
Test name
Test status
Simulation time 1622215482 ps
CPU time 10.59 seconds
Started Jan 21 08:15:45 PM PST 24
Finished Jan 21 08:15:58 PM PST 24
Peak memory 217416 kb
Host smart-5efae37f-8fa7-4a8b-8c4b-41b18547eead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227518247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3227518247
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1456678248
Short name T1572
Test name
Test status
Simulation time 115849638 ps
CPU time 1.58 seconds
Started Jan 21 08:15:54 PM PST 24
Finished Jan 21 08:15:59 PM PST 24
Peak memory 217260 kb
Host smart-9099b44f-9e45-419e-9936-e88becc6071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456678248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1456678248
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3396442256
Short name T1777
Test name
Test status
Simulation time 63347922 ps
CPU time 0.8 seconds
Started Jan 21 08:15:53 PM PST 24
Finished Jan 21 08:15:58 PM PST 24
Peak memory 207252 kb
Host smart-9a5fe259-0beb-4094-9114-ec9d28c222a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396442256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3396442256
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tx_async_fifo_reset.3064907896
Short name T956
Test name
Test status
Simulation time 15799229 ps
CPU time 0.83 seconds
Started Jan 21 08:15:57 PM PST 24
Finished Jan 21 08:16:01 PM PST 24
Peak memory 208812 kb
Host smart-b1364a6a-ab18-4c6a-a7f9-fc60ccac02ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064907896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tx_async_fifo_reset.3064907896
Directory /workspace/47.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_txrx.2582882826
Short name T1666
Test name
Test status
Simulation time 18626353357 ps
CPU time 172.6 seconds
Started Jan 21 08:15:38 PM PST 24
Finished Jan 21 08:18:34 PM PST 24
Peak memory 279016 kb
Host smart-bdabb2cc-2996-401f-b902-3d134acd19d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582882826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_txrx.2582882826
Directory /workspace/47.spi_device_txrx/latest

Test location /workspace/coverage/default/47.spi_device_upload.739975298
Short name T857
Test name
Test status
Simulation time 19361093012 ps
CPU time 19.77 seconds
Started Jan 21 08:15:59 PM PST 24
Finished Jan 21 08:16:22 PM PST 24
Peak memory 233812 kb
Host smart-da4470d9-6662-43ff-8c91-ec7b29999e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739975298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.739975298
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_abort.2577448064
Short name T1152
Test name
Test status
Simulation time 25546495 ps
CPU time 0.76 seconds
Started Jan 21 08:16:19 PM PST 24
Finished Jan 21 08:16:22 PM PST 24
Peak memory 207068 kb
Host smart-4312f4bd-90b3-43c8-9646-ad0aa29063f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577448064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_abort.2577448064
Directory /workspace/48.spi_device_abort/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1733869402
Short name T1037
Test name
Test status
Simulation time 26896848 ps
CPU time 0.72 seconds
Started Jan 21 08:16:30 PM PST 24
Finished Jan 21 08:16:33 PM PST 24
Peak memory 206984 kb
Host smart-b0969b87-908f-43cb-b192-7f5f60552fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733869402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1733869402
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_bit_transfer.3431762649
Short name T1366
Test name
Test status
Simulation time 305418426 ps
CPU time 2.15 seconds
Started Jan 21 08:16:18 PM PST 24
Finished Jan 21 08:16:22 PM PST 24
Peak memory 217244 kb
Host smart-785a6298-88aa-42ab-a160-d1ff3f21482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431762649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_bit_transfer.3431762649
Directory /workspace/48.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/48.spi_device_byte_transfer.3385075868
Short name T841
Test name
Test status
Simulation time 646182364 ps
CPU time 3.14 seconds
Started Jan 21 08:16:13 PM PST 24
Finished Jan 21 08:16:17 PM PST 24
Peak memory 217248 kb
Host smart-5d2cfaed-fdea-4646-a8c8-e7fef820b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385075868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_byte_transfer.3385075868
Directory /workspace/48.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3501562353
Short name T15
Test name
Test status
Simulation time 247416025 ps
CPU time 3.29 seconds
Started Jan 21 08:16:30 PM PST 24
Finished Jan 21 08:16:35 PM PST 24
Peak memory 220724 kb
Host smart-d0e55331-be5a-4439-8dbc-eb6c263de9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501562353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3501562353
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1407646174
Short name T1761
Test name
Test status
Simulation time 20210143 ps
CPU time 0.81 seconds
Started Jan 21 08:16:12 PM PST 24
Finished Jan 21 08:16:14 PM PST 24
Peak memory 208028 kb
Host smart-b19032cd-adb1-40ff-9c62-9e50782654f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407646174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1407646174
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_dummy_item_extra_dly.172987237
Short name T116
Test name
Test status
Simulation time 39048915914 ps
CPU time 719.98 seconds
Started Jan 21 08:15:59 PM PST 24
Finished Jan 21 08:28:02 PM PST 24
Peak memory 266540 kb
Host smart-aa82d29e-2687-4e61-a549-f9cece95b8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172987237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_dummy_item_extra_dly.172987237
Directory /workspace/48.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/48.spi_device_extreme_fifo_size.532778745
Short name T293
Test name
Test status
Simulation time 13410107867 ps
CPU time 52.59 seconds
Started Jan 21 08:16:03 PM PST 24
Finished Jan 21 08:16:56 PM PST 24
Peak memory 235552 kb
Host smart-373740c6-a2ef-4901-83df-df16bb8d4ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532778745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_extreme_fifo_size.532778745
Directory /workspace/48.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/48.spi_device_fifo_full.3726909550
Short name T1214
Test name
Test status
Simulation time 18194912204 ps
CPU time 373.36 seconds
Started Jan 21 08:15:59 PM PST 24
Finished Jan 21 08:22:14 PM PST 24
Peak memory 287940 kb
Host smart-77716685-e47b-4547-a364-5b8716ffd8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726909550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_full.3726909550
Directory /workspace/48.spi_device_fifo_full/latest

Test location /workspace/coverage/default/48.spi_device_fifo_underflow_overflow.3659282195
Short name T1684
Test name
Test status
Simulation time 79851641189 ps
CPU time 406.4 seconds
Started Jan 21 08:16:01 PM PST 24
Finished Jan 21 08:22:50 PM PST 24
Peak memory 376436 kb
Host smart-b9bc46a3-3957-455e-b3f6-f2e58f73de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659282195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_underflow_overf
low.3659282195
Directory /workspace/48.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.930233815
Short name T1752
Test name
Test status
Simulation time 32981697327 ps
CPU time 175.82 seconds
Started Jan 21 08:16:32 PM PST 24
Finished Jan 21 08:19:30 PM PST 24
Peak memory 271028 kb
Host smart-628bb9a8-902e-4995-9ebe-15e1c5d3d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930233815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.930233815
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3928213787
Short name T1335
Test name
Test status
Simulation time 158066097801 ps
CPU time 136.22 seconds
Started Jan 21 08:16:31 PM PST 24
Finished Jan 21 08:18:49 PM PST 24
Peak memory 250260 kb
Host smart-e5fb241c-54ba-4871-919d-c6a57cdadfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928213787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3928213787
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.276155946
Short name T161
Test name
Test status
Simulation time 31413287604 ps
CPU time 105.16 seconds
Started Jan 21 08:16:28 PM PST 24
Finished Jan 21 08:18:15 PM PST 24
Peak memory 257608 kb
Host smart-082f0175-5dc9-4311-9aee-6f9b1629e347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276155946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.276155946
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3979901389
Short name T1222
Test name
Test status
Simulation time 1612426658 ps
CPU time 6.31 seconds
Started Jan 21 08:16:21 PM PST 24
Finished Jan 21 08:16:29 PM PST 24
Peak memory 225560 kb
Host smart-f7a7f0c7-65cb-43e1-9037-2acce2b2be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979901389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3979901389
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intr.1265064271
Short name T935
Test name
Test status
Simulation time 5753980041 ps
CPU time 26.22 seconds
Started Jan 21 08:16:09 PM PST 24
Finished Jan 21 08:16:36 PM PST 24
Peak memory 221996 kb
Host smart-44fa9610-0554-4a9f-9818-d52618fd0535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265064271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intr.1265064271
Directory /workspace/48.spi_device_intr/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3890469212
Short name T1191
Test name
Test status
Simulation time 216377122 ps
CPU time 3.05 seconds
Started Jan 21 08:16:21 PM PST 24
Finished Jan 21 08:16:26 PM PST 24
Peak memory 219036 kb
Host smart-20b6bb5e-34c1-47e9-9d49-d1f440adf54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890469212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3890469212
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1984932769
Short name T750
Test name
Test status
Simulation time 118104679 ps
CPU time 4.48 seconds
Started Jan 21 08:16:23 PM PST 24
Finished Jan 21 08:16:29 PM PST 24
Peak memory 238560 kb
Host smart-67e2a8db-1efc-424e-9a68-920a02fca95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984932769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1984932769
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1273121786
Short name T922
Test name
Test status
Simulation time 2438667459 ps
CPU time 9.46 seconds
Started Jan 21 08:16:25 PM PST 24
Finished Jan 21 08:16:36 PM PST 24
Peak memory 249284 kb
Host smart-3ba8c4d7-d2ed-484a-a1f1-4ee8bdfeedac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273121786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1273121786
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_perf.3302278773
Short name T1458
Test name
Test status
Simulation time 9242997993 ps
CPU time 263.66 seconds
Started Jan 21 08:16:09 PM PST 24
Finished Jan 21 08:20:34 PM PST 24
Peak memory 287904 kb
Host smart-5b9c9b4d-dc60-4dc4-8002-40b6d22a2a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302278773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_perf.3302278773
Directory /workspace/48.spi_device_perf/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1703236061
Short name T1103
Test name
Test status
Simulation time 238675405 ps
CPU time 3.99 seconds
Started Jan 21 08:16:30 PM PST 24
Finished Jan 21 08:16:36 PM PST 24
Peak memory 221240 kb
Host smart-f34a4284-f2db-43e8-8692-66b78afed249
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1703236061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1703236061
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_rx_async_fifo_reset.205104285
Short name T151
Test name
Test status
Simulation time 46131338 ps
CPU time 0.95 seconds
Started Jan 21 08:16:18 PM PST 24
Finished Jan 21 08:16:20 PM PST 24
Peak memory 208812 kb
Host smart-d3163aa5-a978-41be-a9e9-e6c090c3fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205104285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_async_fifo_reset.205104285
Directory /workspace/48.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_rx_timeout.3070524291
Short name T1439
Test name
Test status
Simulation time 2973508391 ps
CPU time 6.03 seconds
Started Jan 21 08:16:17 PM PST 24
Finished Jan 21 08:16:25 PM PST 24
Peak memory 217212 kb
Host smart-b775af21-035e-44be-89fa-0826c9ae84b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070524291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_timeout.3070524291
Directory /workspace/48.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/48.spi_device_smoke.243436220
Short name T1016
Test name
Test status
Simulation time 104557407 ps
CPU time 1.25 seconds
Started Jan 21 08:16:02 PM PST 24
Finished Jan 21 08:16:05 PM PST 24
Peak memory 217160 kb
Host smart-a62cbf7f-ce6c-41cb-8753-0b57ea97ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243436220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_smoke.243436220
Directory /workspace/48.spi_device_smoke/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.583859185
Short name T1298
Test name
Test status
Simulation time 40299750668 ps
CPU time 442.38 seconds
Started Jan 21 08:16:31 PM PST 24
Finished Jan 21 08:23:56 PM PST 24
Peak memory 283428 kb
Host smart-d7a5bc36-740e-4873-931d-ece8b2497d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583859185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.583859185
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4182299084
Short name T127
Test name
Test status
Simulation time 20046357130 ps
CPU time 85.02 seconds
Started Jan 21 08:16:20 PM PST 24
Finished Jan 21 08:17:46 PM PST 24
Peak memory 217392 kb
Host smart-24876e16-1b78-4620-8d9e-1dd5abbb157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182299084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4182299084
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1127474586
Short name T1677
Test name
Test status
Simulation time 1438145872 ps
CPU time 6.48 seconds
Started Jan 21 08:16:24 PM PST 24
Finished Jan 21 08:16:32 PM PST 24
Peak memory 217164 kb
Host smart-7ccd3625-0246-49ae-9ab3-f268b3bb9b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127474586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1127474586
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.727628455
Short name T1071
Test name
Test status
Simulation time 41777796 ps
CPU time 2.67 seconds
Started Jan 21 08:16:19 PM PST 24
Finished Jan 21 08:16:24 PM PST 24
Peak memory 217228 kb
Host smart-ef653503-a5d6-4726-a7da-c328ef11c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727628455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.727628455
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2135554783
Short name T575
Test name
Test status
Simulation time 21763788 ps
CPU time 0.79 seconds
Started Jan 21 08:16:19 PM PST 24
Finished Jan 21 08:16:21 PM PST 24
Peak memory 207232 kb
Host smart-0419995f-e07c-471a-ade3-71f904215ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135554783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2135554783
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tx_async_fifo_reset.3823283800
Short name T166
Test name
Test status
Simulation time 20000086 ps
CPU time 0.81 seconds
Started Jan 21 08:16:15 PM PST 24
Finished Jan 21 08:16:17 PM PST 24
Peak memory 208732 kb
Host smart-a7e4ecc2-b598-4d62-8b46-72cba79fbde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823283800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tx_async_fifo_reset.3823283800
Directory /workspace/48.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_txrx.1326567387
Short name T1489
Test name
Test status
Simulation time 148650111628 ps
CPU time 355.96 seconds
Started Jan 21 08:16:00 PM PST 24
Finished Jan 21 08:21:58 PM PST 24
Peak memory 294724 kb
Host smart-99a6ccf0-ac1b-4e09-9ead-ea0a0fee4404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326567387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_txrx.1326567387
Directory /workspace/48.spi_device_txrx/latest

Test location /workspace/coverage/default/48.spi_device_upload.3455297768
Short name T285
Test name
Test status
Simulation time 5860723265 ps
CPU time 8.81 seconds
Started Jan 21 08:16:31 PM PST 24
Finished Jan 21 08:16:42 PM PST 24
Peak memory 221788 kb
Host smart-9d45ccc5-1599-436f-9fd2-2d19e2815f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455297768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3455297768
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_abort.961551228
Short name T1417
Test name
Test status
Simulation time 24269320 ps
CPU time 0.75 seconds
Started Jan 21 08:16:50 PM PST 24
Finished Jan 21 08:16:53 PM PST 24
Peak memory 207120 kb
Host smart-abaf6a0e-db30-426d-8ee1-ccb50a609a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961551228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_abort.961551228
Directory /workspace/49.spi_device_abort/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.105831116
Short name T534
Test name
Test status
Simulation time 40293346 ps
CPU time 0.73 seconds
Started Jan 21 08:16:57 PM PST 24
Finished Jan 21 08:17:00 PM PST 24
Peak memory 206936 kb
Host smart-7b3bdda4-200d-46f5-95b5-17f47f5004cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105831116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.105831116
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_bit_transfer.3112035574
Short name T1519
Test name
Test status
Simulation time 478426821 ps
CPU time 2.43 seconds
Started Jan 21 08:16:45 PM PST 24
Finished Jan 21 08:16:50 PM PST 24
Peak memory 217228 kb
Host smart-be328ae3-941b-4fc0-bd68-1648bbbf23bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112035574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_bit_transfer.3112035574
Directory /workspace/49.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/49.spi_device_byte_transfer.1163338540
Short name T1466
Test name
Test status
Simulation time 317903914 ps
CPU time 3.22 seconds
Started Jan 21 08:16:49 PM PST 24
Finished Jan 21 08:16:54 PM PST 24
Peak memory 217240 kb
Host smart-85c7fb33-4ccd-4665-9712-c2a810af4347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163338540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_byte_transfer.1163338540
Directory /workspace/49.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3718627341
Short name T1085
Test name
Test status
Simulation time 3130400705 ps
CPU time 13.75 seconds
Started Jan 21 08:16:49 PM PST 24
Finished Jan 21 08:17:05 PM PST 24
Peak memory 241952 kb
Host smart-588a6a27-6452-43bc-b650-7b450f9a016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718627341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3718627341
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2494491988
Short name T1356
Test name
Test status
Simulation time 43632133 ps
CPU time 0.76 seconds
Started Jan 21 08:16:44 PM PST 24
Finished Jan 21 08:16:46 PM PST 24
Peak memory 206988 kb
Host smart-3b90ceea-838d-4287-9a21-c0db6be79d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494491988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2494491988
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_dummy_item_extra_dly.1174653816
Short name T720
Test name
Test status
Simulation time 93574701611 ps
CPU time 274.91 seconds
Started Jan 21 08:16:37 PM PST 24
Finished Jan 21 08:21:14 PM PST 24
Peak memory 319928 kb
Host smart-e1b25e6e-0c52-46d8-a97a-b438781cf5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174653816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_dummy_item_extra_dly.1174653816
Directory /workspace/49.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/49.spi_device_extreme_fifo_size.1150674089
Short name T291
Test name
Test status
Simulation time 6758218414 ps
CPU time 46.95 seconds
Started Jan 21 08:16:35 PM PST 24
Finished Jan 21 08:17:25 PM PST 24
Peak memory 233324 kb
Host smart-7f28452b-68bd-4ce1-95b7-358557ebfe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150674089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_extreme_fifo_size.1150674089
Directory /workspace/49.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/49.spi_device_fifo_full.4281411128
Short name T494
Test name
Test status
Simulation time 143497062159 ps
CPU time 860.54 seconds
Started Jan 21 08:16:36 PM PST 24
Finished Jan 21 08:30:59 PM PST 24
Peak memory 254628 kb
Host smart-b92d3901-e24d-411f-8e33-f87728ec3d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281411128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_full.4281411128
Directory /workspace/49.spi_device_fifo_full/latest

Test location /workspace/coverage/default/49.spi_device_fifo_underflow_overflow.1797477249
Short name T1603
Test name
Test status
Simulation time 9644545745 ps
CPU time 123.46 seconds
Started Jan 21 08:16:33 PM PST 24
Finished Jan 21 08:18:39 PM PST 24
Peak memory 281660 kb
Host smart-d649c8d2-8422-4054-b5af-ba7712f2c1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797477249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_underflow_overf
low.1797477249
Directory /workspace/49.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3894726381
Short name T1768
Test name
Test status
Simulation time 11938257534 ps
CPU time 33.15 seconds
Started Jan 21 08:16:49 PM PST 24
Finished Jan 21 08:17:24 PM PST 24
Peak memory 250440 kb
Host smart-effb954c-add4-4bf3-b84d-de949c04f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894726381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3894726381
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1260676896
Short name T311
Test name
Test status
Simulation time 1105248672357 ps
CPU time 919.09 seconds
Started Jan 21 08:16:57 PM PST 24
Finished Jan 21 08:32:18 PM PST 24
Peak memory 274332 kb
Host smart-e9e655b8-228a-4e50-ab36-920eb6184419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260676896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1260676896
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.862422237
Short name T1196
Test name
Test status
Simulation time 13997931181 ps
CPU time 53.87 seconds
Started Jan 21 08:16:58 PM PST 24
Finished Jan 21 08:17:54 PM PST 24
Peak memory 250296 kb
Host smart-e7cbcd24-52d8-4d9e-9587-009575aec1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862422237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.862422237
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.972596113
Short name T46
Test name
Test status
Simulation time 656922022 ps
CPU time 5.11 seconds
Started Jan 21 08:16:49 PM PST 24
Finished Jan 21 08:16:56 PM PST 24
Peak memory 224728 kb
Host smart-1dbc1875-5492-4201-8969-38201fa6d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972596113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.972596113
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2170948549
Short name T114
Test name
Test status
Simulation time 3271392343 ps
CPU time 11.05 seconds
Started Jan 21 08:16:49 PM PST 24
Finished Jan 21 08:17:02 PM PST 24
Peak memory 221180 kb
Host smart-20dbe40e-3434-4db6-a365-d83581229892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170948549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2170948549
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intr.2779032996
Short name T1068
Test name
Test status
Simulation time 4586397460 ps
CPU time 27.09 seconds
Started Jan 21 08:16:35 PM PST 24
Finished Jan 21 08:17:05 PM PST 24
Peak memory 222104 kb
Host smart-0d562362-b503-4a1b-b837-d652058fdc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779032996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intr.2779032996
Directory /workspace/49.spi_device_intr/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1462293304
Short name T1396
Test name
Test status
Simulation time 853543883 ps
CPU time 11.05 seconds
Started Jan 21 08:16:47 PM PST 24
Finished Jan 21 08:16:59 PM PST 24
Peak memory 233752 kb
Host smart-48324ff7-e9cc-47a7-97c4-a0800e555097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462293304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1462293304
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4084907618
Short name T1217
Test name
Test status
Simulation time 6709298198 ps
CPU time 11.01 seconds
Started Jan 21 08:16:47 PM PST 24
Finished Jan 21 08:17:00 PM PST 24
Peak memory 247212 kb
Host smart-741052d6-2c36-4259-adcd-25c280ccc72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084907618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4084907618
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1533562988
Short name T1347
Test name
Test status
Simulation time 1766537567 ps
CPU time 4.78 seconds
Started Jan 21 08:51:38 PM PST 24
Finished Jan 21 08:52:23 PM PST 24
Peak memory 218952 kb
Host smart-6a0b6abf-13f9-405e-815c-458bb8b19615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533562988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1533562988
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1054078421
Short name T10
Test name
Test status
Simulation time 1026633272 ps
CPU time 6.86 seconds
Started Jan 21 09:31:43 PM PST 24
Finished Jan 21 09:32:16 PM PST 24
Peak memory 234696 kb
Host smart-ff08e1fb-31c9-4c42-8120-37a2dda8be0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1054078421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1054078421
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_rx_async_fifo_reset.3980428399
Short name T1309
Test name
Test status
Simulation time 119370887 ps
CPU time 0.94 seconds
Started Jan 21 08:16:44 PM PST 24
Finished Jan 21 08:16:46 PM PST 24
Peak memory 208832 kb
Host smart-32482ea1-ea2c-411e-a7ce-59309c9ca67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980428399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_async_fifo_reset.3980428399
Directory /workspace/49.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_rx_timeout.193863898
Short name T68
Test name
Test status
Simulation time 2542564099 ps
CPU time 6.37 seconds
Started Jan 21 08:16:49 PM PST 24
Finished Jan 21 08:16:58 PM PST 24
Peak memory 217284 kb
Host smart-312bef22-3257-4e4b-9f2e-7b413558d005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193863898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_timeout.193863898
Directory /workspace/49.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/49.spi_device_smoke.412374075
Short name T1194
Test name
Test status
Simulation time 69070220 ps
CPU time 1.05 seconds
Started Jan 21 08:16:32 PM PST 24
Finished Jan 21 08:16:36 PM PST 24
Peak memory 208740 kb
Host smart-74ec4159-2985-4785-9cf5-1a65053c80b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412374075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_smoke.412374075
Directory /workspace/49.spi_device_smoke/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2327031526
Short name T1255
Test name
Test status
Simulation time 507153285297 ps
CPU time 2155.65 seconds
Started Jan 21 08:16:56 PM PST 24
Finished Jan 21 08:52:54 PM PST 24
Peak memory 323884 kb
Host smart-1022848e-7f7b-4c81-820d-bd638f789f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327031526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2327031526
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.439009661
Short name T1425
Test name
Test status
Simulation time 12855296742 ps
CPU time 19.58 seconds
Started Jan 21 08:16:45 PM PST 24
Finished Jan 21 08:17:07 PM PST 24
Peak memory 217316 kb
Host smart-822240dd-f32e-41f4-b8a5-f1cfe8655e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439009661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.439009661
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.819021101
Short name T733
Test name
Test status
Simulation time 263667764 ps
CPU time 3.8 seconds
Started Jan 21 08:16:51 PM PST 24
Finished Jan 21 08:16:56 PM PST 24
Peak memory 217288 kb
Host smart-9701b476-24c7-43e5-84e8-963600d25b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819021101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.819021101
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3820906204
Short name T1209
Test name
Test status
Simulation time 105304424 ps
CPU time 0.89 seconds
Started Jan 21 08:16:48 PM PST 24
Finished Jan 21 08:16:51 PM PST 24
Peak memory 207236 kb
Host smart-49b8da52-3d6b-4045-85e3-3fb61f91ffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820906204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3820906204
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tx_async_fifo_reset.1890051781
Short name T1774
Test name
Test status
Simulation time 56373882 ps
CPU time 0.81 seconds
Started Jan 21 08:16:45 PM PST 24
Finished Jan 21 08:16:48 PM PST 24
Peak memory 207700 kb
Host smart-eb5f4b57-45a1-45d2-8648-d9316378395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890051781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tx_async_fifo_reset.1890051781
Directory /workspace/49.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_txrx.4187081089
Short name T601
Test name
Test status
Simulation time 91754815847 ps
CPU time 138.74 seconds
Started Jan 21 08:16:35 PM PST 24
Finished Jan 21 08:18:57 PM PST 24
Peak memory 279684 kb
Host smart-abf37d7e-d07b-4e79-a265-4b14fd1369b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187081089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_txrx.4187081089
Directory /workspace/49.spi_device_txrx/latest

Test location /workspace/coverage/default/49.spi_device_upload.1112816106
Short name T337
Test name
Test status
Simulation time 25055334458 ps
CPU time 29.51 seconds
Started Jan 21 08:16:48 PM PST 24
Finished Jan 21 08:17:20 PM PST 24
Peak memory 254796 kb
Host smart-d2a69ffe-c253-4d2b-9556-2e49812681dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112816106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1112816106
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_abort.229415261
Short name T802
Test name
Test status
Simulation time 17927334 ps
CPU time 0.76 seconds
Started Jan 21 07:54:13 PM PST 24
Finished Jan 21 07:54:16 PM PST 24
Peak memory 206100 kb
Host smart-c56d482d-2866-418c-b3fc-497efbba4c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229415261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_abort.229415261
Directory /workspace/5.spi_device_abort/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2609223831
Short name T1735
Test name
Test status
Simulation time 14628322 ps
CPU time 0.73 seconds
Started Jan 21 08:43:13 PM PST 24
Finished Jan 21 08:43:14 PM PST 24
Peak memory 206924 kb
Host smart-5e56e34f-535d-40bb-8127-e21fb3c4ad53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609223831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
609223831
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_bit_transfer.3467633053
Short name T1074
Test name
Test status
Simulation time 474471028 ps
CPU time 2.76 seconds
Started Jan 21 07:54:13 PM PST 24
Finished Jan 21 07:54:18 PM PST 24
Peak memory 216112 kb
Host smart-0bc74c03-eda6-4733-b4cf-e4a81d76c0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467633053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_bit_transfer.3467633053
Directory /workspace/5.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/5.spi_device_byte_transfer.2010021094
Short name T1386
Test name
Test status
Simulation time 731846029 ps
CPU time 2.75 seconds
Started Jan 21 10:56:44 PM PST 24
Finished Jan 21 10:56:49 PM PST 24
Peak memory 217260 kb
Host smart-8a19c402-8d56-47ac-a36f-d7b20b56c218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010021094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_byte_transfer.2010021094
Directory /workspace/5.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.701082585
Short name T1566
Test name
Test status
Simulation time 2051085255 ps
CPU time 4.11 seconds
Started Jan 21 08:53:25 PM PST 24
Finished Jan 21 08:53:47 PM PST 24
Peak memory 241856 kb
Host smart-2477f5cd-c952-4451-b968-eb541c273320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701082585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.701082585
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3304995823
Short name T1527
Test name
Test status
Simulation time 17763137 ps
CPU time 0.82 seconds
Started Jan 21 07:54:15 PM PST 24
Finished Jan 21 07:54:18 PM PST 24
Peak memory 208012 kb
Host smart-fc458c8c-362c-49d9-b55f-5ef6970b8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304995823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3304995823
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_dummy_item_extra_dly.840826979
Short name T297
Test name
Test status
Simulation time 153990199397 ps
CPU time 326.65 seconds
Started Jan 21 07:54:10 PM PST 24
Finished Jan 21 07:59:39 PM PST 24
Peak memory 272512 kb
Host smart-fdfce839-37a4-4efe-a293-0bfe4b4ce2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840826979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_dummy_item_extra_dly.840826979
Directory /workspace/5.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/5.spi_device_extreme_fifo_size.1957900808
Short name T1157
Test name
Test status
Simulation time 72903867125 ps
CPU time 3698.27 seconds
Started Jan 21 09:11:51 PM PST 24
Finished Jan 21 10:13:33 PM PST 24
Peak memory 221468 kb
Host smart-ab6a94e4-ae54-4241-9baa-70953b2e8122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957900808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_extreme_fifo_size.1957900808
Directory /workspace/5.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/5.spi_device_fifo_full.454583272
Short name T51
Test name
Test status
Simulation time 23541147245 ps
CPU time 1395.08 seconds
Started Jan 21 07:54:13 PM PST 24
Finished Jan 21 08:17:31 PM PST 24
Peak memory 287764 kb
Host smart-3b46b396-066e-44bb-905d-6493f6f20faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454583272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_full.454583272
Directory /workspace/5.spi_device_fifo_full/latest

Test location /workspace/coverage/default/5.spi_device_fifo_underflow_overflow.629242855
Short name T1637
Test name
Test status
Simulation time 23255216404 ps
CPU time 155.61 seconds
Started Jan 21 07:54:10 PM PST 24
Finished Jan 21 07:56:48 PM PST 24
Peak memory 286028 kb
Host smart-1a6a29f6-6dbc-4caa-9c4b-3d9d817ca8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629242855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_underflow_overflo
w.629242855
Directory /workspace/5.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.511278141
Short name T1124
Test name
Test status
Simulation time 6802053464 ps
CPU time 75.47 seconds
Started Jan 21 07:54:21 PM PST 24
Finished Jan 21 07:55:38 PM PST 24
Peak memory 256232 kb
Host smart-9c95f8ff-e59f-40be-b2ad-7687705679b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511278141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.511278141
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1410378429
Short name T128
Test name
Test status
Simulation time 404431652076 ps
CPU time 513.59 seconds
Started Jan 21 07:54:19 PM PST 24
Finished Jan 21 08:02:54 PM PST 24
Peak memory 282648 kb
Host smart-9c5f6186-1c5f-4584-86d2-bae8dad2241b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410378429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1410378429
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2810203589
Short name T1349
Test name
Test status
Simulation time 843586378 ps
CPU time 9.56 seconds
Started Jan 21 07:54:19 PM PST 24
Finished Jan 21 07:54:30 PM PST 24
Peak memory 233412 kb
Host smart-51b6ff35-5a19-40b5-8cc4-59554d9dca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810203589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2810203589
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3361544442
Short name T1698
Test name
Test status
Simulation time 263748850 ps
CPU time 4.72 seconds
Started Jan 21 08:50:56 PM PST 24
Finished Jan 21 08:51:33 PM PST 24
Peak memory 238596 kb
Host smart-75023819-649b-411e-8536-b006d77c6d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361544442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3361544442
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intr.2294726025
Short name T1315
Test name
Test status
Simulation time 50864498377 ps
CPU time 39.21 seconds
Started Jan 21 08:18:43 PM PST 24
Finished Jan 21 08:19:31 PM PST 24
Peak memory 220460 kb
Host smart-ed7fc9ea-de9f-40d4-acea-d788a3035cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294726025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intr.2294726025
Directory /workspace/5.spi_device_intr/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3244282017
Short name T275
Test name
Test status
Simulation time 87211071306 ps
CPU time 28.07 seconds
Started Jan 21 07:54:21 PM PST 24
Finished Jan 21 07:54:51 PM PST 24
Peak memory 257496 kb
Host smart-33bd0e84-ea1b-4737-b06e-7444c5a53b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244282017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3244282017
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2950000598
Short name T1365
Test name
Test status
Simulation time 30606190 ps
CPU time 1.08 seconds
Started Jan 21 07:54:10 PM PST 24
Finished Jan 21 07:54:14 PM PST 24
Peak memory 218264 kb
Host smart-97e07a20-55db-4ed5-b53a-fbfec6427a56
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950000598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2950000598
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3524911615
Short name T1362
Test name
Test status
Simulation time 9612481034 ps
CPU time 19.17 seconds
Started Jan 21 08:12:27 PM PST 24
Finished Jan 21 08:12:48 PM PST 24
Peak memory 242072 kb
Host smart-f5c12a3f-f841-4e6d-983a-52258dd21013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524911615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3524911615
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3954183678
Short name T731
Test name
Test status
Simulation time 49550489 ps
CPU time 3.21 seconds
Started Jan 21 07:54:14 PM PST 24
Finished Jan 21 07:54:19 PM PST 24
Peak memory 234756 kb
Host smart-75df1981-1cc8-4314-a9c7-37a2c7269a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954183678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3954183678
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_perf.3186185473
Short name T507
Test name
Test status
Simulation time 18077181189 ps
CPU time 610.45 seconds
Started Jan 21 07:54:15 PM PST 24
Finished Jan 21 08:04:27 PM PST 24
Peak memory 266564 kb
Host smart-86686981-2d36-4ae5-95f9-f8c3ba3cc5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186185473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_perf.3186185473
Directory /workspace/5.spi_device_perf/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.4115629483
Short name T679
Test name
Test status
Simulation time 40664358 ps
CPU time 0.78 seconds
Started Jan 21 07:54:11 PM PST 24
Finished Jan 21 07:54:14 PM PST 24
Peak memory 217064 kb
Host smart-7fb9d02e-84a0-4eaf-836d-fb341f8c80ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115629483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.4115629483
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2337974904
Short name T909
Test name
Test status
Simulation time 197775234 ps
CPU time 4.76 seconds
Started Jan 21 07:54:21 PM PST 24
Finished Jan 21 07:54:26 PM PST 24
Peak memory 236284 kb
Host smart-0c22722b-3ad4-4431-91e9-1e08c7a98c6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2337974904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2337974904
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_rx_async_fifo_reset.1416659188
Short name T1259
Test name
Test status
Simulation time 139335290 ps
CPU time 0.95 seconds
Started Jan 21 09:11:55 PM PST 24
Finished Jan 21 09:12:02 PM PST 24
Peak memory 208852 kb
Host smart-116f09be-be5a-4cac-9436-2b34f53a5229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416659188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_async_fifo_reset.1416659188
Directory /workspace/5.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_rx_timeout.2299378260
Short name T1469
Test name
Test status
Simulation time 1756706077 ps
CPU time 5.68 seconds
Started Jan 21 07:54:15 PM PST 24
Finished Jan 21 07:54:23 PM PST 24
Peak memory 217236 kb
Host smart-4599dcf5-cf8c-42fa-b680-4bc590a0d6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299378260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_timeout.2299378260
Directory /workspace/5.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/5.spi_device_smoke.4206711393
Short name T1705
Test name
Test status
Simulation time 86669885 ps
CPU time 1.19 seconds
Started Jan 21 07:54:00 PM PST 24
Finished Jan 21 07:54:08 PM PST 24
Peak memory 208736 kb
Host smart-f5eb11a8-dbd6-40fa-ad43-3e517ec56b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206711393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_smoke.4206711393
Directory /workspace/5.spi_device_smoke/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2679221700
Short name T1706
Test name
Test status
Simulation time 81716416504 ps
CPU time 479.44 seconds
Started Jan 21 07:54:19 PM PST 24
Finished Jan 21 08:02:20 PM PST 24
Peak memory 299684 kb
Host smart-5b144cc1-02ee-40f5-a49a-0ede94f1d560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679221700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2679221700
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1093923899
Short name T1712
Test name
Test status
Simulation time 5273719474 ps
CPU time 43.88 seconds
Started Jan 21 08:56:03 PM PST 24
Finished Jan 21 08:57:19 PM PST 24
Peak memory 217528 kb
Host smart-fd016f28-f85a-4937-a4ff-3f67691f1e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093923899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1093923899
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3921211160
Short name T615
Test name
Test status
Simulation time 9399884116 ps
CPU time 24.86 seconds
Started Jan 21 09:12:20 PM PST 24
Finished Jan 21 09:12:49 PM PST 24
Peak memory 217316 kb
Host smart-27e34fd6-e4a9-4e46-bf17-59fe34cd4ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921211160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3921211160
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.4005154647
Short name T1281
Test name
Test status
Simulation time 41516004 ps
CPU time 1.05 seconds
Started Jan 21 07:54:11 PM PST 24
Finished Jan 21 07:54:14 PM PST 24
Peak memory 208368 kb
Host smart-158b1275-60a7-4112-9165-9748028c3834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005154647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4005154647
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2050761962
Short name T1748
Test name
Test status
Simulation time 151945048 ps
CPU time 1.26 seconds
Started Jan 21 07:54:16 PM PST 24
Finished Jan 21 07:54:19 PM PST 24
Peak memory 208340 kb
Host smart-72d26aa5-20ef-49cc-b080-87d6534f019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050761962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2050761962
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tx_async_fifo_reset.997342561
Short name T1320
Test name
Test status
Simulation time 22664643 ps
CPU time 0.8 seconds
Started Jan 21 07:54:16 PM PST 24
Finished Jan 21 07:54:19 PM PST 24
Peak memory 208752 kb
Host smart-4dee0204-09cd-44a3-9d91-3e6e74a64d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997342561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tx_async_fifo_reset.997342561
Directory /workspace/5.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_txrx.3911907717
Short name T1512
Test name
Test status
Simulation time 42574108504 ps
CPU time 368.4 seconds
Started Jan 21 07:53:58 PM PST 24
Finished Jan 21 08:00:12 PM PST 24
Peak memory 237964 kb
Host smart-9cdf8c7c-2132-4c86-88e9-d880361c1a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911907717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_txrx.3911907717
Directory /workspace/5.spi_device_txrx/latest

Test location /workspace/coverage/default/5.spi_device_upload.3265692680
Short name T317
Test name
Test status
Simulation time 291871076 ps
CPU time 2.92 seconds
Started Jan 21 08:31:59 PM PST 24
Finished Jan 21 08:32:02 PM PST 24
Peak memory 219028 kb
Host smart-689b734d-253f-4d71-99c3-3f8810348bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265692680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3265692680
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_abort.3103052737
Short name T1227
Test name
Test status
Simulation time 90219759 ps
CPU time 0.78 seconds
Started Jan 21 07:54:30 PM PST 24
Finished Jan 21 07:54:33 PM PST 24
Peak memory 207108 kb
Host smart-532e3e50-dae2-48da-9713-bd4a391b4adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103052737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_abort.3103052737
Directory /workspace/6.spi_device_abort/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.842642686
Short name T1616
Test name
Test status
Simulation time 26358143 ps
CPU time 0.75 seconds
Started Jan 21 08:51:01 PM PST 24
Finished Jan 21 08:51:41 PM PST 24
Peak memory 206928 kb
Host smart-da1cc4b5-b7e9-43d9-a683-dabb8efba7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842642686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.842642686
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_bit_transfer.826761608
Short name T563
Test name
Test status
Simulation time 225120733 ps
CPU time 2.36 seconds
Started Jan 21 07:54:37 PM PST 24
Finished Jan 21 07:54:42 PM PST 24
Peak memory 217244 kb
Host smart-c5cb3fbd-7917-4b4c-9c90-ecfb7b343565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826761608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_bit_transfer.826761608
Directory /workspace/6.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/6.spi_device_byte_transfer.872606321
Short name T589
Test name
Test status
Simulation time 240145588 ps
CPU time 3.28 seconds
Started Jan 21 08:56:20 PM PST 24
Finished Jan 21 08:57:03 PM PST 24
Peak memory 217212 kb
Host smart-ef150c08-b352-4549-b566-385b2d525924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872606321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_byte_transfer.872606321
Directory /workspace/6.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1719611225
Short name T1327
Test name
Test status
Simulation time 650879012 ps
CPU time 4.04 seconds
Started Jan 21 07:54:30 PM PST 24
Finished Jan 21 07:54:37 PM PST 24
Peak memory 238896 kb
Host smart-ff4f44ea-063f-4307-bc6e-0d76967ad6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719611225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1719611225
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2814133485
Short name T160
Test name
Test status
Simulation time 15591594 ps
CPU time 0.77 seconds
Started Jan 21 07:54:30 PM PST 24
Finished Jan 21 07:54:33 PM PST 24
Peak memory 208004 kb
Host smart-58dad66e-8733-4ae2-a534-439d3dc8aaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814133485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2814133485
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_dummy_item_extra_dly.4222536508
Short name T1668
Test name
Test status
Simulation time 36619365063 ps
CPU time 329.27 seconds
Started Jan 21 07:54:21 PM PST 24
Finished Jan 21 07:59:52 PM PST 24
Peak memory 286528 kb
Host smart-050932fa-2403-4786-9d50-fe4cad9c5ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222536508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_dummy_item_extra_dly.4222536508
Directory /workspace/6.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/6.spi_device_extreme_fifo_size.3292910345
Short name T1159
Test name
Test status
Simulation time 483380476233 ps
CPU time 2484.87 seconds
Started Jan 21 07:54:19 PM PST 24
Finished Jan 21 08:35:46 PM PST 24
Peak memory 222524 kb
Host smart-771effbd-95ad-4bec-885b-16fe8828a241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292910345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_extreme_fifo_size.3292910345
Directory /workspace/6.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/6.spi_device_fifo_full.1987516522
Short name T1563
Test name
Test status
Simulation time 46434942595 ps
CPU time 830.53 seconds
Started Jan 21 07:54:16 PM PST 24
Finished Jan 21 08:08:09 PM PST 24
Peak memory 306240 kb
Host smart-f599ffbe-c024-4772-aa32-60173048fe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987516522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_full.1987516522
Directory /workspace/6.spi_device_fifo_full/latest

Test location /workspace/coverage/default/6.spi_device_fifo_underflow_overflow.3206505949
Short name T54
Test name
Test status
Simulation time 145014242144 ps
CPU time 859.57 seconds
Started Jan 21 07:54:21 PM PST 24
Finished Jan 21 08:08:41 PM PST 24
Peak memory 594196 kb
Host smart-52bd7845-78ce-4d55-8e74-a206b4b6b274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206505949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_underflow_overfl
ow.3206505949
Directory /workspace/6.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2953473585
Short name T1357
Test name
Test status
Simulation time 10233288849 ps
CPU time 90.5 seconds
Started Jan 21 07:54:31 PM PST 24
Finished Jan 21 07:56:03 PM PST 24
Peak memory 250264 kb
Host smart-cccd2745-cf0b-4e59-88b1-7f5408d9bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953473585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2953473585
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1360799816
Short name T318
Test name
Test status
Simulation time 44906199830 ps
CPU time 65.26 seconds
Started Jan 21 08:23:18 PM PST 24
Finished Jan 21 08:24:24 PM PST 24
Peak memory 240388 kb
Host smart-88d07240-c219-42a0-9b05-49f184ace8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360799816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1360799816
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3983961860
Short name T1223
Test name
Test status
Simulation time 1443143985 ps
CPU time 4.25 seconds
Started Jan 21 07:54:30 PM PST 24
Finished Jan 21 07:54:36 PM PST 24
Peak memory 219580 kb
Host smart-fdc3af6b-03f3-42aa-b487-5e4e2c5a2d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983961860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3983961860
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intr.3592591390
Short name T1392
Test name
Test status
Simulation time 5260939757 ps
CPU time 32.25 seconds
Started Jan 21 07:54:23 PM PST 24
Finished Jan 21 07:54:57 PM PST 24
Peak memory 232940 kb
Host smart-4b67aa24-0786-4641-ba68-2d64756707d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592591390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intr.3592591390
Directory /workspace/6.spi_device_intr/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1917400481
Short name T1348
Test name
Test status
Simulation time 9597051148 ps
CPU time 9.65 seconds
Started Jan 21 07:54:30 PM PST 24
Finished Jan 21 07:54:42 PM PST 24
Peak memory 251188 kb
Host smart-8c8df115-7852-4b69-965a-e6d8f6ce8df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917400481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1917400481
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2382929140
Short name T1175
Test name
Test status
Simulation time 53682510 ps
CPU time 1.09 seconds
Started Jan 21 07:54:29 PM PST 24
Finished Jan 21 07:54:32 PM PST 24
Peak memory 219312 kb
Host smart-653cb09c-ceee-468b-ae25-9322eb49cd62
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382929140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2382929140
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4026994603
Short name T979
Test name
Test status
Simulation time 3077508172 ps
CPU time 6.66 seconds
Started Jan 21 07:54:33 PM PST 24
Finished Jan 21 07:54:42 PM PST 24
Peak memory 218940 kb
Host smart-9d3e33cb-6133-494b-ba4e-f9c704cdd79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026994603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4026994603
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4182394610
Short name T1544
Test name
Test status
Simulation time 11585252017 ps
CPU time 27.01 seconds
Started Jan 21 07:54:29 PM PST 24
Finished Jan 21 07:54:57 PM PST 24
Peak memory 220164 kb
Host smart-b4927fae-ca45-481f-99b3-305cc5aaeed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182394610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4182394610
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_perf.1869061883
Short name T730
Test name
Test status
Simulation time 102675443762 ps
CPU time 1736.5 seconds
Started Jan 21 07:54:30 PM PST 24
Finished Jan 21 08:23:29 PM PST 24
Peak memory 274180 kb
Host smart-9e9bd895-368d-475e-9539-e3098c4da830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869061883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_perf.1869061883
Directory /workspace/6.spi_device_perf/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2527954545
Short name T863
Test name
Test status
Simulation time 15408481 ps
CPU time 0.75 seconds
Started Jan 21 07:54:27 PM PST 24
Finished Jan 21 07:54:29 PM PST 24
Peak memory 217100 kb
Host smart-d4b446aa-854d-401b-976b-9ffb20c25d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527954545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2527954545
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2064658171
Short name T602
Test name
Test status
Simulation time 76221510 ps
CPU time 3.68 seconds
Started Jan 21 07:54:33 PM PST 24
Finished Jan 21 07:54:38 PM PST 24
Peak memory 226408 kb
Host smart-0dfcc302-946a-4fc0-a2c8-346cc61cb6c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2064658171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2064658171
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_rx_async_fifo_reset.4082699237
Short name T1243
Test name
Test status
Simulation time 175539784 ps
CPU time 0.99 seconds
Started Jan 21 07:54:32 PM PST 24
Finished Jan 21 07:54:34 PM PST 24
Peak memory 208788 kb
Host smart-01045602-06ce-44ba-beaa-2f9fa588c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082699237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_async_fifo_reset.4082699237
Directory /workspace/6.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_rx_timeout.3941449290
Short name T1340
Test name
Test status
Simulation time 2135659761 ps
CPU time 5.7 seconds
Started Jan 21 07:54:25 PM PST 24
Finished Jan 21 07:54:32 PM PST 24
Peak memory 217204 kb
Host smart-34f8e572-8c75-4a5f-95f4-48e06969b12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941449290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_timeout.3941449290
Directory /workspace/6.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/6.spi_device_smoke.1435680125
Short name T668
Test name
Test status
Simulation time 84171748 ps
CPU time 1.34 seconds
Started Jan 21 08:51:09 PM PST 24
Finished Jan 21 08:51:57 PM PST 24
Peak memory 217180 kb
Host smart-7102c618-394e-4f4a-a116-5a09eff88a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435680125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_smoke.1435680125
Directory /workspace/6.spi_device_smoke/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.430866926
Short name T89
Test name
Test status
Simulation time 615245579705 ps
CPU time 448.7 seconds
Started Jan 21 08:18:41 PM PST 24
Finished Jan 21 08:26:12 PM PST 24
Peak memory 301852 kb
Host smart-5cf0e5e8-e083-44e4-b618-8d1ae657404c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430866926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.430866926
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.322150943
Short name T1480
Test name
Test status
Simulation time 21062481264 ps
CPU time 86.67 seconds
Started Jan 21 07:54:36 PM PST 24
Finished Jan 21 07:56:05 PM PST 24
Peak memory 217384 kb
Host smart-2a26d3b5-0a4e-4bdd-8810-a5b9be6516cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322150943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.322150943
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.271610400
Short name T1079
Test name
Test status
Simulation time 966249048 ps
CPU time 3.64 seconds
Started Jan 21 07:54:31 PM PST 24
Finished Jan 21 07:54:36 PM PST 24
Peak memory 217260 kb
Host smart-449a1630-ccc7-4349-9a32-05631fb7f4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271610400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.271610400
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2956362057
Short name T927
Test name
Test status
Simulation time 148133262 ps
CPU time 1.7 seconds
Started Jan 21 07:54:28 PM PST 24
Finished Jan 21 07:54:31 PM PST 24
Peak memory 217428 kb
Host smart-b32b6d25-5a4d-4dc8-9815-27c8ae338e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956362057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2956362057
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3093576967
Short name T129
Test name
Test status
Simulation time 15196635 ps
CPU time 0.73 seconds
Started Jan 21 07:54:27 PM PST 24
Finished Jan 21 07:54:29 PM PST 24
Peak memory 207260 kb
Host smart-4aca7a25-bfd3-4117-bbdc-d3e0490d29b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093576967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3093576967
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tx_async_fifo_reset.261528032
Short name T1027
Test name
Test status
Simulation time 83349595 ps
CPU time 0.87 seconds
Started Jan 21 07:54:33 PM PST 24
Finished Jan 21 07:54:37 PM PST 24
Peak memory 207720 kb
Host smart-878fea8d-2bdf-4905-a5e4-1bed68682c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261528032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tx_async_fifo_reset.261528032
Directory /workspace/6.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_txrx.128177780
Short name T693
Test name
Test status
Simulation time 354328778300 ps
CPU time 361.99 seconds
Started Jan 21 07:54:19 PM PST 24
Finished Jan 21 08:00:23 PM PST 24
Peak memory 269576 kb
Host smart-1358a63f-3cdc-4e65-9c94-69864b9b2315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128177780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_txrx.128177780
Directory /workspace/6.spi_device_txrx/latest

Test location /workspace/coverage/default/6.spi_device_upload.3175660301
Short name T1105
Test name
Test status
Simulation time 9103379521 ps
CPU time 33.12 seconds
Started Jan 21 07:54:31 PM PST 24
Finished Jan 21 07:55:06 PM PST 24
Peak memory 250240 kb
Host smart-4c571e42-713f-4931-90f7-2324d7fed0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175660301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3175660301
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_abort.647890747
Short name T1044
Test name
Test status
Simulation time 71605059 ps
CPU time 0.79 seconds
Started Jan 21 08:19:54 PM PST 24
Finished Jan 21 08:19:57 PM PST 24
Peak memory 207080 kb
Host smart-be9035e0-4413-40b3-adbf-d1d43876c33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647890747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_abort.647890747
Directory /workspace/7.spi_device_abort/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3709422901
Short name T1613
Test name
Test status
Simulation time 25637738 ps
CPU time 0.72 seconds
Started Jan 21 07:54:59 PM PST 24
Finished Jan 21 07:55:01 PM PST 24
Peak memory 206920 kb
Host smart-231f58f3-4fbb-4e78-8c77-301b229042ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709422901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
709422901
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_bit_transfer.2087217721
Short name T695
Test name
Test status
Simulation time 169457284 ps
CPU time 3.15 seconds
Started Jan 21 07:54:45 PM PST 24
Finished Jan 21 07:54:50 PM PST 24
Peak memory 217180 kb
Host smart-547f0a42-2b0d-4bb0-acca-75e14ca15523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087217721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_bit_transfer.2087217721
Directory /workspace/7.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/7.spi_device_byte_transfer.3359493141
Short name T1055
Test name
Test status
Simulation time 285948860 ps
CPU time 3.74 seconds
Started Jan 21 07:54:34 PM PST 24
Finished Jan 21 07:54:41 PM PST 24
Peak memory 217140 kb
Host smart-0ff66706-f875-4bc6-a4f8-8d6ef3e9a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359493141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_byte_transfer.3359493141
Directory /workspace/7.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2505724825
Short name T1078
Test name
Test status
Simulation time 852616368 ps
CPU time 5.13 seconds
Started Jan 21 07:54:51 PM PST 24
Finished Jan 21 07:54:58 PM PST 24
Peak memory 218676 kb
Host smart-ec0b3e74-3ca6-42d2-bb60-839d3817c0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505724825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2505724825
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.706018819
Short name T1025
Test name
Test status
Simulation time 20713659 ps
CPU time 0.79 seconds
Started Jan 21 07:54:35 PM PST 24
Finished Jan 21 07:54:39 PM PST 24
Peak memory 207960 kb
Host smart-7e1747ec-fa92-403e-b53a-5697d6f34f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706018819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.706018819
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_dummy_item_extra_dly.1902522336
Short name T1529
Test name
Test status
Simulation time 17375513846 ps
CPU time 110.27 seconds
Started Jan 21 07:54:34 PM PST 24
Finished Jan 21 07:56:27 PM PST 24
Peak memory 241744 kb
Host smart-004c0119-6c82-457d-8ffd-45e038d251a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902522336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_dummy_item_extra_dly.1902522336
Directory /workspace/7.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/7.spi_device_extreme_fifo_size.4242987357
Short name T1432
Test name
Test status
Simulation time 3123811652 ps
CPU time 28.28 seconds
Started Jan 21 07:54:37 PM PST 24
Finished Jan 21 07:55:08 PM PST 24
Peak memory 230412 kb
Host smart-13520dcd-584b-4677-9606-2e26e7fd360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242987357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_extreme_fifo_size.4242987357
Directory /workspace/7.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/7.spi_device_fifo_full.3127781295
Short name T848
Test name
Test status
Simulation time 150423219597 ps
CPU time 778.56 seconds
Started Jan 21 07:54:35 PM PST 24
Finished Jan 21 08:07:36 PM PST 24
Peak memory 263892 kb
Host smart-24bc8e52-4b43-4a18-833c-3b6c2928d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127781295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_full.3127781295
Directory /workspace/7.spi_device_fifo_full/latest

Test location /workspace/coverage/default/7.spi_device_fifo_underflow_overflow.3955918027
Short name T1585
Test name
Test status
Simulation time 105026074570 ps
CPU time 420.24 seconds
Started Jan 21 09:09:59 PM PST 24
Finished Jan 21 09:17:19 PM PST 24
Peak memory 409040 kb
Host smart-508eaa1a-481f-4fec-9bfc-1886a4edf7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955918027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_underflow_overfl
ow.3955918027
Directory /workspace/7.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2793843872
Short name T754
Test name
Test status
Simulation time 1252335528 ps
CPU time 19.76 seconds
Started Jan 21 07:54:50 PM PST 24
Finished Jan 21 07:55:11 PM PST 24
Peak memory 240220 kb
Host smart-c206c553-589b-471d-8800-3f0201dcdbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793843872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2793843872
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.700566543
Short name T251
Test name
Test status
Simulation time 48559370249 ps
CPU time 105.63 seconds
Started Jan 21 07:54:48 PM PST 24
Finished Jan 21 07:56:35 PM PST 24
Peak memory 258408 kb
Host smart-66fcc838-1f80-41ad-8a97-f5d9ffeefd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700566543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.700566543
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.861226835
Short name T742
Test name
Test status
Simulation time 22358784899 ps
CPU time 36.58 seconds
Started Jan 21 08:35:17 PM PST 24
Finished Jan 21 08:35:55 PM PST 24
Peak memory 241940 kb
Host smart-a171fb45-bc2a-40a0-8c65-40f0af3c2d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861226835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.861226835
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1723348470
Short name T1626
Test name
Test status
Simulation time 1213922207 ps
CPU time 5.86 seconds
Started Jan 21 07:54:52 PM PST 24
Finished Jan 21 07:54:59 PM PST 24
Peak memory 225532 kb
Host smart-dc1ef9f1-9f0e-41da-bb29-7f4315ed229f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723348470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1723348470
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intr.3067322449
Short name T77
Test name
Test status
Simulation time 38012502650 ps
CPU time 64.16 seconds
Started Jan 21 07:54:36 PM PST 24
Finished Jan 21 07:55:43 PM PST 24
Peak memory 233684 kb
Host smart-52aac0be-34ee-42f2-bfec-2ef62c96eec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067322449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intr.3067322449
Directory /workspace/7.spi_device_intr/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1721169543
Short name T1414
Test name
Test status
Simulation time 1287565854 ps
CPU time 6.68 seconds
Started Jan 21 07:54:50 PM PST 24
Finished Jan 21 07:54:58 PM PST 24
Peak memory 241544 kb
Host smart-b4e0da91-440e-4cce-a272-ab3f0f8885dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721169543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1721169543
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3433820186
Short name T47
Test name
Test status
Simulation time 94211227 ps
CPU time 1.1 seconds
Started Jan 21 07:54:37 PM PST 24
Finished Jan 21 07:54:40 PM PST 24
Peak memory 219500 kb
Host smart-9c86f85a-275b-41ce-86d2-01f99ec0ae13
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433820186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3433820186
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.452436747
Short name T760
Test name
Test status
Simulation time 10065601146 ps
CPU time 12.8 seconds
Started Jan 21 07:54:47 PM PST 24
Finished Jan 21 07:55:01 PM PST 24
Peak memory 227900 kb
Host smart-406659d9-32f6-447b-9c89-7d5adb6600f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452436747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
452436747
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2981971135
Short name T1526
Test name
Test status
Simulation time 5964495701 ps
CPU time 24.3 seconds
Started Jan 21 07:54:54 PM PST 24
Finished Jan 21 07:55:19 PM PST 24
Peak memory 253936 kb
Host smart-2f508dc7-39eb-4b97-b00c-2908a06b16a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981971135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2981971135
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_perf.1359021451
Short name T611
Test name
Test status
Simulation time 66786807344 ps
CPU time 352.46 seconds
Started Jan 21 07:54:37 PM PST 24
Finished Jan 21 08:00:32 PM PST 24
Peak memory 252192 kb
Host smart-1e8619a9-0375-4752-91d7-6b99814ff0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359021451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_perf.1359021451
Directory /workspace/7.spi_device_perf/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2033602589
Short name T1670
Test name
Test status
Simulation time 18899718 ps
CPU time 0.8 seconds
Started Jan 21 08:22:36 PM PST 24
Finished Jan 21 08:22:37 PM PST 24
Peak memory 217092 kb
Host smart-c53145ea-1266-46a6-9820-23ffdf47514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033602589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2033602589
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3493026762
Short name T1691
Test name
Test status
Simulation time 2164686559 ps
CPU time 4.15 seconds
Started Jan 21 07:54:52 PM PST 24
Finished Jan 21 07:54:57 PM PST 24
Peak memory 218952 kb
Host smart-312f441d-96d9-4e87-a376-ef78c243fad4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493026762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3493026762
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_rx_async_fifo_reset.3196263472
Short name T618
Test name
Test status
Simulation time 94750590 ps
CPU time 0.89 seconds
Started Jan 21 07:54:44 PM PST 24
Finished Jan 21 07:54:46 PM PST 24
Peak memory 208788 kb
Host smart-bdbb1678-3711-4391-82b9-1bbe7291ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196263472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_async_fifo_reset.3196263472
Directory /workspace/7.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_rx_timeout.1852833793
Short name T579
Test name
Test status
Simulation time 519592727 ps
CPU time 5.84 seconds
Started Jan 21 07:54:33 PM PST 24
Finished Jan 21 07:54:41 PM PST 24
Peak memory 217228 kb
Host smart-3c5f02e3-f765-46f5-9dc2-77429263708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852833793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_timeout.1852833793
Directory /workspace/7.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/7.spi_device_smoke.670576146
Short name T843
Test name
Test status
Simulation time 26548861 ps
CPU time 1.03 seconds
Started Jan 21 07:54:36 PM PST 24
Finished Jan 21 07:54:40 PM PST 24
Peak memory 208292 kb
Host smart-7f4b7ce4-18ef-493e-a6b7-ded5cc4f808f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670576146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_smoke.670576146
Directory /workspace/7.spi_device_smoke/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2192130241
Short name T1218
Test name
Test status
Simulation time 40190166805 ps
CPU time 192.59 seconds
Started Jan 21 07:54:42 PM PST 24
Finished Jan 21 07:57:56 PM PST 24
Peak memory 217380 kb
Host smart-a8bad22e-a38c-4b1f-8a5c-46fb9717ae11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192130241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2192130241
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.378431781
Short name T1312
Test name
Test status
Simulation time 7598560401 ps
CPU time 6.88 seconds
Started Jan 21 07:54:43 PM PST 24
Finished Jan 21 07:54:52 PM PST 24
Peak memory 217276 kb
Host smart-b5bf5fe1-ad15-4abb-a66f-2eb9ac7f6697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378431781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.378431781
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.124412693
Short name T1166
Test name
Test status
Simulation time 89349581 ps
CPU time 1.53 seconds
Started Jan 21 07:54:48 PM PST 24
Finished Jan 21 07:54:51 PM PST 24
Peak memory 217256 kb
Host smart-704c3257-909f-485c-9e98-58913a759ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124412693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.124412693
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3958046232
Short name T1620
Test name
Test status
Simulation time 133965145 ps
CPU time 0.79 seconds
Started Jan 21 09:12:15 PM PST 24
Finished Jan 21 09:12:21 PM PST 24
Peak memory 207252 kb
Host smart-7ee61dcb-a12e-4f69-a082-eb60628c877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958046232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3958046232
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tx_async_fifo_reset.2808346749
Short name T870
Test name
Test status
Simulation time 18450622 ps
CPU time 0.82 seconds
Started Jan 21 07:54:44 PM PST 24
Finished Jan 21 07:54:46 PM PST 24
Peak memory 208724 kb
Host smart-cc33a891-0cbd-4fee-90c3-d94446c576cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808346749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tx_async_fifo_reset.2808346749
Directory /workspace/7.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_txrx.1918075096
Short name T986
Test name
Test status
Simulation time 81589465855 ps
CPU time 433.42 seconds
Started Jan 21 07:54:37 PM PST 24
Finished Jan 21 08:01:53 PM PST 24
Peak memory 322048 kb
Host smart-aae299a5-81ae-47e6-aad6-331e2f6356ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918075096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_txrx.1918075096
Directory /workspace/7.spi_device_txrx/latest

Test location /workspace/coverage/default/7.spi_device_upload.1864178721
Short name T336
Test name
Test status
Simulation time 2044498293 ps
CPU time 8.99 seconds
Started Jan 21 07:54:48 PM PST 24
Finished Jan 21 07:54:58 PM PST 24
Peak memory 236788 kb
Host smart-81c7578e-ca71-46a1-af95-f3dfcd03352f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864178721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1864178721
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_abort.4066539249
Short name T698
Test name
Test status
Simulation time 25041690 ps
CPU time 0.76 seconds
Started Jan 21 07:55:08 PM PST 24
Finished Jan 21 07:55:10 PM PST 24
Peak memory 207104 kb
Host smart-f8339754-0104-4565-a1c7-32ec20cf91f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066539249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_abort.4066539249
Directory /workspace/8.spi_device_abort/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2982567443
Short name T1110
Test name
Test status
Simulation time 13002506 ps
CPU time 0.76 seconds
Started Jan 21 07:55:13 PM PST 24
Finished Jan 21 07:55:15 PM PST 24
Peak memory 206960 kb
Host smart-3afea15c-4158-4c88-89af-a6be095c2cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982567443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
982567443
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_bit_transfer.4146887450
Short name T1660
Test name
Test status
Simulation time 1350620138 ps
CPU time 2.09 seconds
Started Jan 21 07:55:01 PM PST 24
Finished Jan 21 07:55:05 PM PST 24
Peak memory 217188 kb
Host smart-9c1f8c13-a5d8-4232-899c-a5c874470923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146887450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_bit_transfer.4146887450
Directory /workspace/8.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/8.spi_device_byte_transfer.387740283
Short name T664
Test name
Test status
Simulation time 568931959 ps
CPU time 3.24 seconds
Started Jan 21 07:55:02 PM PST 24
Finished Jan 21 07:55:06 PM PST 24
Peak memory 217184 kb
Host smart-50a5b3a2-500d-4909-af33-24d63b498b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387740283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_byte_transfer.387740283
Directory /workspace/8.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2754610384
Short name T1150
Test name
Test status
Simulation time 1147957030 ps
CPU time 6.76 seconds
Started Jan 21 07:55:07 PM PST 24
Finished Jan 21 07:55:15 PM PST 24
Peak memory 225492 kb
Host smart-12e2d4cd-a9a1-4e9b-baa4-5e50d6bccc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754610384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2754610384
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2063490447
Short name T893
Test name
Test status
Simulation time 42221533 ps
CPU time 0.83 seconds
Started Jan 21 07:55:02 PM PST 24
Finished Jan 21 07:55:04 PM PST 24
Peak memory 208044 kb
Host smart-16079be3-e626-4a0b-9dae-3d9459e38ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063490447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2063490447
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_dummy_item_extra_dly.3505106987
Short name T566
Test name
Test status
Simulation time 192311416924 ps
CPU time 461.61 seconds
Started Jan 21 07:55:02 PM PST 24
Finished Jan 21 08:02:45 PM PST 24
Peak memory 262076 kb
Host smart-44b6b58d-954b-4e73-a0f1-1197d183e939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505106987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_dummy_item_extra_dly.3505106987
Directory /workspace/8.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/8.spi_device_extreme_fifo_size.2663908891
Short name T1420
Test name
Test status
Simulation time 178223268222 ps
CPU time 1203.9 seconds
Started Jan 21 07:54:58 PM PST 24
Finished Jan 21 08:15:03 PM PST 24
Peak memory 221624 kb
Host smart-86692ee1-76d1-4c3d-8fde-5edf01467d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663908891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_extreme_fifo_size.2663908891
Directory /workspace/8.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/8.spi_device_fifo_full.3630548532
Short name T1304
Test name
Test status
Simulation time 69137035907 ps
CPU time 826.36 seconds
Started Jan 21 07:54:59 PM PST 24
Finished Jan 21 08:08:47 PM PST 24
Peak memory 310716 kb
Host smart-5455dadf-d475-4849-8d85-d627299ee003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630548532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_full.3630548532
Directory /workspace/8.spi_device_fifo_full/latest

Test location /workspace/coverage/default/8.spi_device_fifo_underflow_overflow.1546276546
Short name T1263
Test name
Test status
Simulation time 13329526999 ps
CPU time 244.77 seconds
Started Jan 21 07:54:57 PM PST 24
Finished Jan 21 07:59:03 PM PST 24
Peak memory 332632 kb
Host smart-1c197ff0-90a5-4fcc-ab56-acb4268c0212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546276546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_underflow_overfl
ow.1546276546
Directory /workspace/8.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.232758720
Short name T340
Test name
Test status
Simulation time 93569675905 ps
CPU time 243.56 seconds
Started Jan 21 07:55:13 PM PST 24
Finished Jan 21 07:59:17 PM PST 24
Peak memory 267692 kb
Host smart-a09a95bc-093d-4afe-8bcd-e386c78f6c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232758720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.232758720
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1698821790
Short name T238
Test name
Test status
Simulation time 70340931310 ps
CPU time 74.07 seconds
Started Jan 21 07:55:15 PM PST 24
Finished Jan 21 07:56:30 PM PST 24
Peak memory 267348 kb
Host smart-a1f48e14-f0cf-465f-ba7f-3d4bfcbc2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698821790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1698821790
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3203964288
Short name T1692
Test name
Test status
Simulation time 10280554167 ps
CPU time 49.76 seconds
Started Jan 21 07:55:04 PM PST 24
Finished Jan 21 07:55:55 PM PST 24
Peak memory 238284 kb
Host smart-f88ac63b-2358-438e-9f2a-d6f156bbf7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203964288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3203964288
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2812352054
Short name T480
Test name
Test status
Simulation time 154709638 ps
CPU time 2.49 seconds
Started Jan 21 07:55:07 PM PST 24
Finished Jan 21 07:55:11 PM PST 24
Peak memory 218784 kb
Host smart-efbc52be-381a-4275-8911-7e484df5adbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812352054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2812352054
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intr.1348267734
Short name T648
Test name
Test status
Simulation time 10393867584 ps
CPU time 51.82 seconds
Started Jan 21 07:54:58 PM PST 24
Finished Jan 21 07:55:51 PM PST 24
Peak memory 233680 kb
Host smart-c66932d2-e1fa-4b32-b9b9-ac7920d92ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348267734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intr.1348267734
Directory /workspace/8.spi_device_intr/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.456283142
Short name T287
Test name
Test status
Simulation time 746393042 ps
CPU time 7.98 seconds
Started Jan 21 07:55:08 PM PST 24
Finished Jan 21 07:55:17 PM PST 24
Peak memory 228640 kb
Host smart-fb37f0fe-9a82-41f3-9575-b810029609aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456283142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.456283142
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3288396229
Short name T1130
Test name
Test status
Simulation time 50030688 ps
CPU time 1.1 seconds
Started Jan 21 07:54:56 PM PST 24
Finished Jan 21 07:54:58 PM PST 24
Peak memory 219380 kb
Host smart-b2d9d8af-aa88-45ec-ab75-22ef9470e1e8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288396229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3288396229
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.14310392
Short name T1289
Test name
Test status
Simulation time 406996138 ps
CPU time 7.39 seconds
Started Jan 21 07:55:08 PM PST 24
Finished Jan 21 07:55:17 PM PST 24
Peak memory 233708 kb
Host smart-ccc399ec-c7da-4eec-9fc7-ce1f2ac066f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14310392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.14310392
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2284187971
Short name T301
Test name
Test status
Simulation time 33749612497 ps
CPU time 28.82 seconds
Started Jan 21 07:55:08 PM PST 24
Finished Jan 21 07:55:38 PM PST 24
Peak memory 233864 kb
Host smart-70894a2b-c11f-41ad-be09-dbc745ab2c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284187971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2284187971
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_perf.2341404866
Short name T1052
Test name
Test status
Simulation time 26092452214 ps
CPU time 336.41 seconds
Started Jan 21 07:55:02 PM PST 24
Finished Jan 21 08:00:40 PM PST 24
Peak memory 268644 kb
Host smart-e0a29689-1f89-4a69-9588-67bcd379543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341404866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_perf.2341404866
Directory /workspace/8.spi_device_perf/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3540205254
Short name T107
Test name
Test status
Simulation time 46090352 ps
CPU time 0.76 seconds
Started Jan 21 07:54:59 PM PST 24
Finished Jan 21 07:55:01 PM PST 24
Peak memory 217080 kb
Host smart-eea67e1e-bced-4f1e-8673-f143ba99d18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540205254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3540205254
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1981165023
Short name T203
Test name
Test status
Simulation time 747240612 ps
CPU time 3.84 seconds
Started Jan 21 08:25:51 PM PST 24
Finished Jan 21 08:25:57 PM PST 24
Peak memory 220980 kb
Host smart-30fa1c84-f0a1-4c53-8d0f-39f9a3942b78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1981165023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1981165023
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_rx_async_fifo_reset.2070303046
Short name T41
Test name
Test status
Simulation time 43476493 ps
CPU time 0.88 seconds
Started Jan 21 07:55:02 PM PST 24
Finished Jan 21 07:55:04 PM PST 24
Peak memory 208820 kb
Host smart-ec5c6c8d-b43d-4dde-8259-e359c870fe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070303046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_async_fifo_reset.2070303046
Directory /workspace/8.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_rx_timeout.2546918640
Short name T1250
Test name
Test status
Simulation time 1959682612 ps
CPU time 5.17 seconds
Started Jan 21 07:55:01 PM PST 24
Finished Jan 21 07:55:07 PM PST 24
Peak memory 217264 kb
Host smart-6043b1d8-cd21-432f-aff9-c5ecec2718a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546918640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_timeout.2546918640
Directory /workspace/8.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/8.spi_device_smoke.2382075129
Short name T1464
Test name
Test status
Simulation time 16262269 ps
CPU time 1.1 seconds
Started Jan 21 07:54:58 PM PST 24
Finished Jan 21 07:55:01 PM PST 24
Peak memory 208344 kb
Host smart-c7336938-46d4-469f-adcf-e3bba3183783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382075129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_smoke.2382075129
Directory /workspace/8.spi_device_smoke/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1290973741
Short name T153
Test name
Test status
Simulation time 153260145856 ps
CPU time 6204.37 seconds
Started Jan 21 07:55:11 PM PST 24
Finished Jan 21 09:38:37 PM PST 24
Peak memory 348576 kb
Host smart-bd8eb8b2-5a3b-4f80-877f-1a442f9433d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290973741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1290973741
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.487710341
Short name T1084
Test name
Test status
Simulation time 2308921062 ps
CPU time 28.94 seconds
Started Jan 21 07:55:04 PM PST 24
Finished Jan 21 07:55:34 PM PST 24
Peak memory 217436 kb
Host smart-b821b63c-8f29-42de-b0d3-69af7c7e8e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487710341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.487710341
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2619948496
Short name T719
Test name
Test status
Simulation time 2072648720 ps
CPU time 11.14 seconds
Started Jan 21 07:55:05 PM PST 24
Finished Jan 21 07:55:17 PM PST 24
Peak memory 217200 kb
Host smart-7958bfc9-d7b7-46f1-9a31-8d444bd701a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619948496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2619948496
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2772829765
Short name T755
Test name
Test status
Simulation time 643603620 ps
CPU time 3.56 seconds
Started Jan 21 07:55:07 PM PST 24
Finished Jan 21 07:55:12 PM PST 24
Peak memory 217296 kb
Host smart-e36c22dc-f225-4230-a525-ffe0f623f366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772829765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2772829765
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.513622292
Short name T1440
Test name
Test status
Simulation time 84074320 ps
CPU time 0.91 seconds
Started Jan 21 07:55:08 PM PST 24
Finished Jan 21 07:55:10 PM PST 24
Peak memory 207500 kb
Host smart-84fd73f1-dba7-4801-bb66-c63da12f5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513622292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.513622292
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.2968969724
Short name T1009
Test name
Test status
Simulation time 142831416 ps
CPU time 0.78 seconds
Started Jan 21 07:55:07 PM PST 24
Finished Jan 21 07:55:09 PM PST 24
Peak memory 208732 kb
Host smart-39efaed9-1e09-4993-a6ae-43070ac87768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968969724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tx_async_fifo_reset.2968969724
Directory /workspace/8.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_txrx.101144681
Short name T931
Test name
Test status
Simulation time 105398704904 ps
CPU time 130.66 seconds
Started Jan 21 07:54:57 PM PST 24
Finished Jan 21 07:57:09 PM PST 24
Peak memory 250148 kb
Host smart-466aafb4-395f-4d59-a87f-a9ec2635e87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101144681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_txrx.101144681
Directory /workspace/8.spi_device_txrx/latest

Test location /workspace/coverage/default/8.spi_device_upload.1659376256
Short name T655
Test name
Test status
Simulation time 3464114276 ps
CPU time 5.54 seconds
Started Jan 21 07:55:03 PM PST 24
Finished Jan 21 07:55:09 PM PST 24
Peak memory 219528 kb
Host smart-a7ae9fca-2375-4fbe-9a80-8e4509b9e3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659376256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1659376256
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_abort.2731670223
Short name T490
Test name
Test status
Simulation time 14411659 ps
CPU time 0.78 seconds
Started Jan 21 07:55:29 PM PST 24
Finished Jan 21 07:55:31 PM PST 24
Peak memory 207072 kb
Host smart-cd6e7fb5-bcb0-4511-9b88-30ac45a08d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731670223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_abort.2731670223
Directory /workspace/9.spi_device_abort/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.821641827
Short name T535
Test name
Test status
Simulation time 21912199 ps
CPU time 0.75 seconds
Started Jan 21 07:55:34 PM PST 24
Finished Jan 21 07:55:37 PM PST 24
Peak memory 206952 kb
Host smart-7ba06509-afd1-4918-ba1f-30594bbdbc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821641827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.821641827
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_bit_transfer.1471940413
Short name T548
Test name
Test status
Simulation time 397555879 ps
CPU time 3.42 seconds
Started Jan 21 07:55:29 PM PST 24
Finished Jan 21 07:55:33 PM PST 24
Peak memory 217236 kb
Host smart-6943ed18-32d5-4e45-9d49-7149e51e7161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471940413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_bit_transfer.1471940413
Directory /workspace/9.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/9.spi_device_byte_transfer.2156746305
Short name T1502
Test name
Test status
Simulation time 383330804 ps
CPU time 2.99 seconds
Started Jan 21 07:55:29 PM PST 24
Finished Jan 21 07:55:33 PM PST 24
Peak memory 217240 kb
Host smart-b781075e-e6f9-414e-976b-7c0b3ad96fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156746305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_byte_transfer.2156746305
Directory /workspace/9.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.320809108
Short name T625
Test name
Test status
Simulation time 3104572661 ps
CPU time 11.77 seconds
Started Jan 21 07:55:25 PM PST 24
Finished Jan 21 07:55:38 PM PST 24
Peak memory 221628 kb
Host smart-96128003-2f90-4a93-bdca-4d0aed932ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320809108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.320809108
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1944519875
Short name T1061
Test name
Test status
Simulation time 69674255 ps
CPU time 0.87 seconds
Started Jan 21 07:55:18 PM PST 24
Finished Jan 21 07:55:20 PM PST 24
Peak memory 208060 kb
Host smart-cee945bd-703e-4b0f-b987-c4b86d1b3221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944519875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1944519875
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.2705495456
Short name T1598
Test name
Test status
Simulation time 53938857120 ps
CPU time 391.8 seconds
Started Jan 21 07:55:28 PM PST 24
Finished Jan 21 08:02:01 PM PST 24
Peak memory 288520 kb
Host smart-9a411a26-4ba3-40a5-af23-390301a62fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705495456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_dummy_item_extra_dly.2705495456
Directory /workspace/9.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/9.spi_device_extreme_fifo_size.2058769538
Short name T914
Test name
Test status
Simulation time 215514674089 ps
CPU time 955.62 seconds
Started Jan 21 07:55:19 PM PST 24
Finished Jan 21 08:11:17 PM PST 24
Peak memory 218664 kb
Host smart-7debe1d2-f547-4bda-8db5-30259989ee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058769538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_extreme_fifo_size.2058769538
Directory /workspace/9.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/9.spi_device_fifo_full.3371289018
Short name T1207
Test name
Test status
Simulation time 79920633944 ps
CPU time 487.42 seconds
Started Jan 21 07:55:18 PM PST 24
Finished Jan 21 08:03:27 PM PST 24
Peak memory 250132 kb
Host smart-280446ed-814b-4558-a860-34ee4974a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371289018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_full.3371289018
Directory /workspace/9.spi_device_fifo_full/latest

Test location /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.319455270
Short name T226
Test name
Test status
Simulation time 154518855049 ps
CPU time 695.1 seconds
Started Jan 21 07:55:20 PM PST 24
Finished Jan 21 08:06:57 PM PST 24
Peak memory 471252 kb
Host smart-4b25ceb2-e0a3-4b80-a7a9-7c88b4b65fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319455270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_underflow_overflo
w.319455270
Directory /workspace/9.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1889113643
Short name T1490
Test name
Test status
Simulation time 38925218584 ps
CPU time 99.55 seconds
Started Jan 21 07:55:37 PM PST 24
Finished Jan 21 07:57:18 PM PST 24
Peak memory 250220 kb
Host smart-2db62559-8259-453b-a976-5039a7ceca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889113643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1889113643
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2316415932
Short name T30
Test name
Test status
Simulation time 47947264444 ps
CPU time 162.24 seconds
Started Jan 21 07:55:32 PM PST 24
Finished Jan 21 07:58:15 PM PST 24
Peak memory 254196 kb
Host smart-7f1e1a95-009c-406a-85de-b8d0d55c8b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316415932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2316415932
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3193043
Short name T1328
Test name
Test status
Simulation time 33216141773 ps
CPU time 142.06 seconds
Started Jan 21 07:55:31 PM PST 24
Finished Jan 21 07:57:54 PM PST 24
Peak memory 255748 kb
Host smart-f5d98ec2-eb00-4ea4-83db-91d50be8e860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.3193043
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.990457302
Short name T928
Test name
Test status
Simulation time 29642930047 ps
CPU time 48.85 seconds
Started Jan 21 07:55:27 PM PST 24
Finished Jan 21 07:56:16 PM PST 24
Peak memory 250172 kb
Host smart-c02424b7-0400-40e0-9fef-48911dd0bfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990457302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.990457302
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3949085971
Short name T1107
Test name
Test status
Simulation time 3537121733 ps
CPU time 4.95 seconds
Started Jan 21 07:55:28 PM PST 24
Finished Jan 21 07:55:34 PM PST 24
Peak memory 221240 kb
Host smart-db290a45-356f-4b62-a573-b3e31604bd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949085971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3949085971
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intr.2447377956
Short name T830
Test name
Test status
Simulation time 21067366285 ps
CPU time 67.68 seconds
Started Jan 21 07:55:29 PM PST 24
Finished Jan 21 07:56:38 PM PST 24
Peak memory 234788 kb
Host smart-69fd9572-62d8-4a73-9088-d39e6fd0e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447377956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intr.2447377956
Directory /workspace/9.spi_device_intr/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1720782203
Short name T1426
Test name
Test status
Simulation time 12820689859 ps
CPU time 36.2 seconds
Started Jan 21 07:55:27 PM PST 24
Finished Jan 21 07:56:04 PM PST 24
Peak memory 228796 kb
Host smart-4fd7fca9-63ed-4253-8c8a-403a364c9e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720782203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1720782203
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3149752840
Short name T516
Test name
Test status
Simulation time 15687765 ps
CPU time 1.04 seconds
Started Jan 21 07:55:23 PM PST 24
Finished Jan 21 07:55:25 PM PST 24
Peak memory 219348 kb
Host smart-f9a736b8-f096-47d9-ab6c-7368c291776a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149752840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3149752840
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1036530029
Short name T324
Test name
Test status
Simulation time 376753580 ps
CPU time 6.23 seconds
Started Jan 21 07:55:26 PM PST 24
Finished Jan 21 07:55:33 PM PST 24
Peak memory 224368 kb
Host smart-e2d6d88d-07b7-43e3-9f3b-edd0f06f276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036530029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1036530029
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4147327708
Short name T1203
Test name
Test status
Simulation time 43586030600 ps
CPU time 23.51 seconds
Started Jan 21 07:55:30 PM PST 24
Finished Jan 21 07:55:55 PM PST 24
Peak memory 248008 kb
Host smart-4a1d6f75-6ea0-4783-ac80-5896df87b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147327708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4147327708
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_perf.828761251
Short name T1306
Test name
Test status
Simulation time 10731244656 ps
CPU time 404.82 seconds
Started Jan 21 07:55:18 PM PST 24
Finished Jan 21 08:02:04 PM PST 24
Peak memory 266328 kb
Host smart-a7eb4d0f-01e3-4469-bf1d-fafc74debba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828761251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_perf.828761251
Directory /workspace/9.spi_device_perf/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.4041348312
Short name T1509
Test name
Test status
Simulation time 15582290 ps
CPU time 0.75 seconds
Started Jan 21 07:55:25 PM PST 24
Finished Jan 21 07:55:27 PM PST 24
Peak memory 216952 kb
Host smart-60ce3c3c-b02a-46f7-a408-36130bfa8e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041348312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.4041348312
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1542109605
Short name T797
Test name
Test status
Simulation time 712748995 ps
CPU time 5.29 seconds
Started Jan 21 07:55:29 PM PST 24
Finished Jan 21 07:55:36 PM PST 24
Peak memory 221140 kb
Host smart-83fe3c81-c1d2-4fa6-bc90-4210e67b6a4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1542109605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1542109605
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.4109551377
Short name T790
Test name
Test status
Simulation time 50536639 ps
CPU time 0.99 seconds
Started Jan 21 07:55:24 PM PST 24
Finished Jan 21 07:55:25 PM PST 24
Peak memory 208776 kb
Host smart-407c97cb-c3d2-4334-b81e-091248df08bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109551377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_async_fifo_reset.4109551377
Directory /workspace/9.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_rx_timeout.1216388284
Short name T662
Test name
Test status
Simulation time 894895889 ps
CPU time 7.83 seconds
Started Jan 21 07:55:27 PM PST 24
Finished Jan 21 07:55:36 PM PST 24
Peak memory 217152 kb
Host smart-c5024a63-6195-47db-b4a1-8b1e6487eb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216388284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_timeout.1216388284
Directory /workspace/9.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/9.spi_device_smoke.1184766396
Short name T1064
Test name
Test status
Simulation time 53994180 ps
CPU time 1.16 seconds
Started Jan 21 07:55:18 PM PST 24
Finished Jan 21 07:55:21 PM PST 24
Peak memory 208324 kb
Host smart-3b6bc797-be00-464a-a472-10be8e058c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184766396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_smoke.1184766396
Directory /workspace/9.spi_device_smoke/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1688650710
Short name T319
Test name
Test status
Simulation time 603422398833 ps
CPU time 1010.05 seconds
Started Jan 21 07:55:33 PM PST 24
Finished Jan 21 08:12:25 PM PST 24
Peak memory 388760 kb
Host smart-caa8e853-1fb2-4d5a-ac43-206985ceee01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688650710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1688650710
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.650139176
Short name T67
Test name
Test status
Simulation time 11357765858 ps
CPU time 90.39 seconds
Started Jan 21 07:55:23 PM PST 24
Finished Jan 21 07:56:54 PM PST 24
Peak memory 217408 kb
Host smart-3a0d95e3-16f2-4cf5-936f-9733a0de07bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650139176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.650139176
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.159194540
Short name T1274
Test name
Test status
Simulation time 4551166532 ps
CPU time 5.45 seconds
Started Jan 21 07:55:22 PM PST 24
Finished Jan 21 07:55:28 PM PST 24
Peak memory 217348 kb
Host smart-9e132e1d-be86-4421-9eda-7038b38f8053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159194540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.159194540
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3053201930
Short name T488
Test name
Test status
Simulation time 512200892 ps
CPU time 4.32 seconds
Started Jan 21 07:55:29 PM PST 24
Finished Jan 21 07:55:35 PM PST 24
Peak memory 217308 kb
Host smart-a6844534-f8c3-4d3e-80ca-1d7aae7cecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053201930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3053201930
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1694492895
Short name T1760
Test name
Test status
Simulation time 93014653 ps
CPU time 1.11 seconds
Started Jan 21 07:55:26 PM PST 24
Finished Jan 21 07:55:28 PM PST 24
Peak memory 208364 kb
Host smart-b4f695d2-3cb9-44a7-b338-4d188a5b3111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694492895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1694492895
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tx_async_fifo_reset.2291298961
Short name T1220
Test name
Test status
Simulation time 14788411 ps
CPU time 0.8 seconds
Started Jan 21 07:55:29 PM PST 24
Finished Jan 21 07:55:31 PM PST 24
Peak memory 207672 kb
Host smart-36defa39-ad2a-4d3b-85a0-7fd1dddf0be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291298961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tx_async_fifo_reset.2291298961
Directory /workspace/9.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_txrx.4242911622
Short name T498
Test name
Test status
Simulation time 12347981827 ps
CPU time 100.04 seconds
Started Jan 21 07:55:19 PM PST 24
Finished Jan 21 07:57:01 PM PST 24
Peak memory 266428 kb
Host smart-007b249b-1355-4dff-a475-aea4a27182cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242911622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_txrx.4242911622
Directory /workspace/9.spi_device_txrx/latest

Test location /workspace/coverage/default/9.spi_device_upload.2735848976
Short name T883
Test name
Test status
Simulation time 411805791 ps
CPU time 3.6 seconds
Started Jan 21 07:55:23 PM PST 24
Finished Jan 21 07:55:28 PM PST 24
Peak memory 226808 kb
Host smart-a16143df-f307-4510-ab27-6dd072823574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735848976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2735848976
Directory /workspace/9.spi_device_upload/latest
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