Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7708964	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6692074

1

T1

1

T2

110

T3

2103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10116942	1			T1	61		T2	337		T3	10742
values[0x0]	2140948	1			T2	49		T3	692		T7	464
values[0x1]	2143148	1			T2	43		T3	723		T7	438

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5520892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8880146

1

T1

24

T2

223

T3

5221

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57425	1			T3	1		T7	3		T8	5
valid_sources[0x01]	49687	1			T8	6		T9	2		T12	10
valid_sources[0x02]	57796	1			T8	1		T9	4		T11	2
valid_sources[0x03]	64152	1			T7	8		T8	7		T9	2
valid_sources[0x04]	64363	1			T8	1		T9	9		T12	11
valid_sources[0x05]	53532	1			T7	3		T8	3		T9	5
valid_sources[0x06]	62467	1			T7	1		T8	5		T9	4
valid_sources[0x07]	51764	1			T7	5		T8	8		T9	1
valid_sources[0x08]	59261	1			T10	45		T11	1		T12	3
valid_sources[0x09]	55082	1			T7	5		T8	3		T9	2
valid_sources[0x0a]	49180	1			T7	1		T8	9		T9	8
valid_sources[0x0b]	52022	1			T7	6		T8	6		T9	2
valid_sources[0x0c]	51229	1			T8	3		T12	5		T17	33
valid_sources[0x0d]	49113	1			T8	1		T9	1		T12	11
valid_sources[0x0e]	59181	1			T3	2		T7	1		T8	4
valid_sources[0x0f]	52232	1			T7	4		T8	7		T12	5
valid_sources[0x10]	55913	1			T8	4		T9	1		T11	2
valid_sources[0x11]	71762	1			T8	8		T9	1		T12	11
valid_sources[0x12]	52066	1			T7	1		T8	8		T9	2
valid_sources[0x13]	56131	1			T8	3		T11	10		T12	4
valid_sources[0x14]	53750	1			T8	6		T9	1		T12	8
valid_sources[0x15]	54416	1			T3	216		T8	7		T9	1
valid_sources[0x16]	54172	1			T3	82		T7	4		T8	4
valid_sources[0x17]	53909	1			T3	9		T7	3		T9	1
valid_sources[0x18]	49376	1			T8	4		T9	1		T12	6
valid_sources[0x19]	48751	1			T8	5		T12	8		T17	23
valid_sources[0x1a]	60894	1			T8	4		T9	5		T11	1
valid_sources[0x1b]	55431	1			T7	5		T8	5		T12	5
valid_sources[0x1c]	54768	1			T7	6		T8	5		T9	11
valid_sources[0x1d]	51707	1			T7	9		T8	5		T9	2
valid_sources[0x1e]	52810	1			T7	19		T8	11		T9	2
valid_sources[0x1f]	55319	1			T7	9		T8	9		T9	12
valid_sources[0x20]	57346	1			T7	7		T8	7		T9	5
valid_sources[0x21]	49684	1			T3	2		T7	1		T8	5
valid_sources[0x22]	61991	1			T7	5		T8	4		T9	4
valid_sources[0x23]	52953	1			T3	1		T7	4		T8	5
valid_sources[0x24]	55514	1			T3	1		T7	4		T8	6
valid_sources[0x25]	60733	1			T3	1		T7	10		T8	3
valid_sources[0x26]	56408	1			T3	1		T8	4		T9	1
valid_sources[0x27]	53081	1			T3	1		T7	1		T8	3
valid_sources[0x28]	52576	1			T7	1		T8	3		T9	2
valid_sources[0x29]	57137	1			T3	2		T8	7		T9	3
valid_sources[0x2a]	59682	1			T3	3		T7	5		T8	9
valid_sources[0x2b]	55516	1			T3	1742		T7	1		T8	1
valid_sources[0x2c]	54312	1			T7	3		T8	5		T9	6
valid_sources[0x2d]	64504	1			T3	482		T9	2		T11	36
valid_sources[0x2e]	51852	1			T3	28		T8	2		T9	3
valid_sources[0x2f]	72684	1			T3	100		T8	4		T11	16
valid_sources[0x30]	53675	1			T7	2		T8	8		T9	4
valid_sources[0x31]	56054	1			T7	6		T8	1		T9	2
valid_sources[0x32]	52134	1			T3	139		T7	4		T9	3
valid_sources[0x33]	62080	1			T8	8		T9	2		T11	13
valid_sources[0x34]	56239	1			T3	1		T8	9		T9	6
valid_sources[0x35]	62796	1			T7	1		T8	3		T9	1
valid_sources[0x36]	65483	1			T9	2		T12	9		T17	20
valid_sources[0x37]	63842	1			T7	1		T8	5		T9	3
valid_sources[0x38]	68751	1			T7	5		T9	20		T12	3
valid_sources[0x39]	58681	1			T7	1		T8	3		T9	17
valid_sources[0x3a]	50122	1			T7	1		T8	8		T11	6
valid_sources[0x3b]	55750	1			T7	11		T8	5		T12	8
valid_sources[0x3c]	55271	1			T3	43		T7	4		T8	1
valid_sources[0x3d]	58093	1			T3	612		T7	2		T8	4
valid_sources[0x3e]	51326	1			T3	57		T7	5		T8	6
valid_sources[0x3f]	57353	1			T7	1		T8	3		T9	1
valid_sources[0x40]	60298	1			T7	1		T8	4		T9	5
valid_sources[0x41]	78278	1			T7	5		T8	1		T9	2
valid_sources[0x42]	53671	1			T3	30		T7	2		T8	3
valid_sources[0x43]	52928	1			T7	2		T8	2		T9	7
valid_sources[0x44]	52638	1			T3	2		T8	2		T12	9
valid_sources[0x45]	55789	1			T7	6		T8	5		T9	2
valid_sources[0x46]	61032	1			T7	3		T8	1		T9	2
valid_sources[0x47]	53481	1			T8	9		T9	7		T11	2
valid_sources[0x48]	53794	1			T7	2		T8	9		T9	3
valid_sources[0x49]	55354	1			T3	1		T7	13		T8	6
valid_sources[0x4a]	54191	1			T7	1		T8	9		T11	7
valid_sources[0x4b]	48506	1			T7	1		T8	11		T9	9
valid_sources[0x4c]	56855	1			T7	1		T8	3		T9	3
valid_sources[0x4d]	53571	1			T7	1		T8	1		T9	4
valid_sources[0x4e]	55767	1			T7	17		T8	1		T9	14
valid_sources[0x4f]	63152	1			T8	11		T9	4		T12	10
valid_sources[0x50]	54186	1			T7	1		T8	4		T9	5
valid_sources[0x51]	55869	1			T3	1		T7	2		T8	4
valid_sources[0x52]	51755	1			T8	6		T9	7		T11	15
valid_sources[0x53]	49966	1			T7	6		T8	8		T9	6
valid_sources[0x54]	58247	1			T3	341		T7	28		T8	7
valid_sources[0x55]	54865	1			T7	1		T8	8		T9	2
valid_sources[0x56]	52231	1			T7	3		T8	7		T9	7
valid_sources[0x57]	60821	1			T8	5		T9	4		T11	5
valid_sources[0x58]	55174	1			T7	18		T8	2		T12	7
valid_sources[0x59]	52423	1			T8	3		T9	3		T11	3
valid_sources[0x5a]	59324	1			T3	99		T8	7		T9	9
valid_sources[0x5b]	49819	1			T8	3		T9	7		T12	7
valid_sources[0x5c]	72532	1			T7	3		T8	5		T9	6
valid_sources[0x5d]	64198	1			T7	10		T11	12		T12	5
valid_sources[0x5e]	53497	1			T3	354		T7	2		T8	2
valid_sources[0x5f]	53438	1			T8	3		T9	2		T11	6
valid_sources[0x60]	54969	1			T7	1		T8	4		T9	4
valid_sources[0x61]	55769	1			T3	1		T7	2		T8	5
valid_sources[0x62]	63763	1			T7	6		T12	6		T17	16
valid_sources[0x63]	62103	1			T7	4		T8	4		T9	1
valid_sources[0x64]	57968	1			T7	3		T8	2		T9	12
valid_sources[0x65]	54672	1			T8	1		T9	3		T12	3
valid_sources[0x66]	57297	1			T7	4		T8	4		T12	8
valid_sources[0x67]	61292	1			T3	149		T8	4		T9	3
valid_sources[0x68]	51737	1			T7	13		T8	5		T9	1
valid_sources[0x69]	58575	1			T7	7		T8	7		T11	9
valid_sources[0x6a]	51877	1			T3	46		T7	3		T8	10
valid_sources[0x6b]	62235	1			T7	3		T8	6		T12	7
valid_sources[0x6c]	48709	1			T3	574		T8	10		T9	1
valid_sources[0x6d]	64624	1			T3	2		T7	2		T8	1
valid_sources[0x6e]	63624	1			T3	403		T8	9		T12	8
valid_sources[0x6f]	53799	1			T3	1		T7	1		T8	3
valid_sources[0x70]	53109	1			T8	10		T9	2		T12	4
valid_sources[0x71]	55816	1			T3	2		T7	15		T8	2
valid_sources[0x72]	53396	1			T7	1		T9	2		T11	9
valid_sources[0x73]	52346	1			T3	1		T7	2		T8	3
valid_sources[0x74]	58228	1			T7	6		T8	6		T11	8
valid_sources[0x75]	49163	1			T7	3		T8	3		T9	1
valid_sources[0x76]	53013	1			T3	263		T7	4		T8	4
valid_sources[0x77]	54063	1			T7	3		T8	6		T9	2
valid_sources[0x78]	61629	1			T8	2		T9	4		T11	21
valid_sources[0x79]	61871	1			T7	1		T8	9		T9	2
valid_sources[0x7a]	52353	1			T7	3		T8	6		T9	6
valid_sources[0x7b]	53517	1			T2	429		T8	1		T9	4
valid_sources[0x7c]	54204	1			T3	53		T7	7		T8	3
valid_sources[0x7d]	51755	1			T7	2		T8	5		T12	4
valid_sources[0x7e]	56104	1			T7	1		T8	1		T11	4
valid_sources[0x7f]	58265	1			T7	1		T8	4		T9	6
valid_sources[0x80]	61544	1			T7	3		T8	25		T9	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2751312

1

T1

1

T2

29

T3

862

values[0x0]

all_enables

biggest_size

1979223

1

T2

43

T3

606

T7

463

values[0x1]

all_enables

biggest_size

1961539

1

T2

38

T3

635

T7

437