Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

7726085

1

T1

60

T2

319

T3

10054

full_word

6690933

1

T1

1

T2

110

T3

2103

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	14416668	1			T1	61		T2	429		T3	12157
auto[TlIntgErrCmd]	119	1			T72	6		T74	10		T78	1
auto[TlIntgErrData]	119	1			T72	7		T74	9		T78	5
auto[TlIntgErrBoth]	112	1			T72	7		T74	1		T78	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10117694

1

T1

61

T2

337

T3

10742

auto[1]

4299324

1

T2

92

T3

1415

T7

902

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7366199	1			T1	60		T2	308		T3	9880
auto[TlIntgErrNone]	partial	auto[1]	359571	1			T2	11		T3	174		T7	2
auto[TlIntgErrNone]	full_word	auto[0]	2751341	1			T1	1		T2	29		T3	862
auto[TlIntgErrNone]	full_word	auto[1]	3939557	1			T2	81		T3	1241		T7	900
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T72	3		T74	4		T77	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T72	3		T74	5		T78	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T74	1		T152	1		T153	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T154	1		T82	2		T155	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T72	3		T74	5		T78	2
auto[TlIntgErrData]	partial	auto[1]	62	1			T72	3		T74	3		T78	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T72	1		T74	1		T92	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T78	1		T154	1		T93	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T72	3		T74	1		T78	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T72	3		T78	1		T77	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T72	1		T92	1		T82	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T92	1		T82	3		T94	1