Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	134	134	100.00
Total Bits 0->1	67	67	100.00
Total Bits 1->0	67	67	100.00

Ports	5	5	100.00
Port Bits	134	134	100.00
Port Bits 0->1	67	67	100.00
Port Bits 1->0	67	67	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T20,T23,T29	Yes	T1,T2,T3	INPUT
oh_i[5:0]	Yes	Yes	*T2,*T3,*T11	Yes	T2,T3,T11	INPUT
oh_i[6]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[7]	Yes	Yes	*T8,*T11,*T12	Yes	T8,T11,T12	INPUT
oh_i[8]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[13:9]	Yes	Yes	T11,T13,T4	Yes	T11,T13,T4	INPUT
oh_i[17:14]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[57:18]	Yes	Yes	*T7,*T8,*T9	Yes	T7,T8,T9	INPUT
oh_i[58]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[59]	Yes	Yes	*T2,*T3,*T17	Yes	T2,T3,T17	INPUT
oh_i[60]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[69:61]	Yes	Yes	T3,T18,*T22	Yes	T3,T18,T22	INPUT
oh_i[70]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[71]	Yes	Yes	*T2,*T3,*T17	Yes	T2,T3,T17	INPUT
oh_i[72]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[6:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
err_o	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT

*Tests covering at least one bit in the range