Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577947680	61648	0	0
DepthKnown_A	577947680	577824082	0	0
RvalidKnown_A	577947680	577824082	0	0
WreadyKnown_A	577947680	577824082	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	61648	0	0
T4	314426	641	0	0
T5	591984	64	0	0
T6	63231	0	0	0
T14	177435	0	0	0
T15	7937	0	0	0
T18	66879	0	0	0
T19	5782	0	0	0
T22	1292	0	0	0
T23	0	326	0	0
T24	0	100	0	0
T25	0	100	0	0
T27	0	129	0	0
T28	0	321	0	0
T29	0	544	0	0
T30	0	424	0	0
T31	0	175	0	0
T32	1270	0	0	0
T33	990	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577947680	154227	0	0
DepthKnown_A	577947680	577824082	0	0
RvalidKnown_A	577947680	577824082	0	0
WreadyKnown_A	577947680	577824082	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	154227	0	0
T4	314426	2950	0	0
T5	591984	331	0	0
T6	63231	0	0	0
T14	177435	0	0	0
T15	7937	0	0	0
T18	66879	0	0	0
T19	5782	0	0	0
T22	1292	0	0	0
T23	0	1034	0	0
T24	0	100	0	0
T25	0	100	0	0
T27	0	545	0	0
T28	0	321	0	0
T29	0	544	0	0
T30	0	1090	0	0
T31	0	175	0	0
T32	1270	0	0	0
T33	990	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577947680	12848728	0	0
DepthKnown_A	577947680	577824082	0	0
RvalidKnown_A	577947680	577824082	0	0
WreadyKnown_A	577947680	577824082	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	12848728	0	0
T1	2048	61	0	0
T2	11842	429	0	0
T3	380270	12454	0	0
T7	55033	79	0	0
T8	152980	326	0	0
T9	68355	49	0	0
T10	1520	45	0	0
T11	19483	82	0	0
T12	566282	959	0	0
T16	950	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	577947680	27269434	0	0
DepthKnown_A	577947680	577824082	0	0
RvalidKnown_A	577947680	577824082	0	0
WreadyKnown_A	577947680	577824082	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	27269434	0	0
T1	2048	182	0	0
T2	11842	429	0	0
T3	380270	54640	0	0
T7	55033	79	0	0
T8	152980	326	0	0
T9	68355	49	0	0
T10	1520	45	0	0
T11	19483	82	0	0
T12	566282	3987	0	0
T16	950	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577947680	577824082	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0