Unified Coverage Report :: Module :: spi_p2s

Module : spi_p2s

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57	100.00	69.23			69.05	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_p2s	84.57	100.00	69.23			69.05	100.00

---

Module Instance : tb.dut.u_p2s

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57	100.00	69.23			69.05	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57	100.00	69.23			69.05	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.65	95.15	86.84	96.92		88.89	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_p2s

	Line No.	Total	Covered	Percent
TOTAL		37	37	100.00
ALWAYS	70	5	5	100.00
CONT_ASSIGN	91	1	1	100.00
ALWAYS	110	5	5	100.00
ALWAYS	122	4	4	100.00
CONT_ASSIGN	142	1	1	100.00
ALWAYS	146	5	5	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	182	6	6	100.00
CONT_ASSIGN	191	1	1	100.00
ALWAYS	195	5	5	100.00
ALWAYS	213	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
72	1	1
74	1	1
78	1	1
82	1	1
91	1	1
110	1	1
112	1	1
113	1	1
114	1	1
115	1	1
122	1	1
124	1	1
128	1	1
132	1	1
142	1	1
146	1	1
148	1	1
150	1	1
155	1	1
160	1	1
178	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
			MISSING_ELSE
191	1	1
195	1	1
197	1	1
198	1	1
199	1	1
200	1	1
213	1	1
214	1	1
216	1	1

---

Cond Coverage for Module : spi_p2s

	Total	Covered	Percent
Conditions	52	36	69.23
Logical	52	36	69.23
Non-Logical	0	0
Event	0	0

 LINE       91
 EXPRESSION (csb_i ? 4'b0 : out_enable)
             --1--

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (cnt == 3'h6)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       114
 EXPRESSION (cnt == 3'h2)
            ------1------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T4,T7

 LINE       115
 EXPRESSION (cnt == 3'b0)
            ------1------

-1-	Status	Tests
0	Covered	T3,T7,T13
1	Covered	T3,T7,T13

 LINE       124
 EXPRESSION (order_i ? ({1'b0, out_shift_d[7:1]}) : ({out_shift_d[6:0], 1'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Not Covered

 LINE       128
 EXPRESSION (order_i ? ({2'b0, out_shift_d[7:2]}) : ({out_shift_d[5:0], 2'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Not Covered

 LINE       132
 EXPRESSION (order_i ? ({4'b0, out_shift_d[7:4]}) : ({out_shift_d[3:0], 4'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T3,T7,T13
1	Not Covered

 LINE       142
 EXPRESSION (first_beat ? data_i : out_shift)
             -----1----

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[0] : data_i[0]) : (((!first_beat)) ? out_shift[7] : data_i[7]))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       150
 SUB-EXPRESSION (((!first_beat)) ? out_shift[0] : data_i[0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       150
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7] : data_i[7])
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       155
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[1:0] : data_i[1:0]) : (((!first_beat)) ? out_shift[7:6] : data_i[7:6]))
             ---1---

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Not Covered

 LINE       155
 SUB-EXPRESSION (((!first_beat)) ? out_shift[1:0] : data_i[1:0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:6] : data_i[7:6])
                 -------1-------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T4,T7

 LINE       160
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[3:0] : data_i[3:0]) : (((!first_beat)) ? out_shift[7:4] : data_i[7:4]))
             ---1---

-1-	Status	Tests
0	Covered	T3,T7,T13
1	Not Covered

 LINE       160
 SUB-EXPRESSION (((!first_beat)) ? out_shift[3:0] : data_i[3:0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:4] : data_i[7:4])
                 -------1-------

-1-	Status	Tests
0	Covered	T3,T7,T13
1	Covered	T3,T7,T13

 LINE       186
 EXPRESSION (data_valid_i && ((tx_state != TxIdle) || (cpha_i == 1'b0)))
             ------1-----    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Not Covered
1	1	Covered	T3,T4,T7

 LINE       186
 SUB-EXPRESSION ((tx_state != TxIdle) || (cpha_i == 1'b0))
                 ----------1---------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T7
1	0	Not Covered

 LINE       186
 SUB-EXPRESSION (tx_state != TxIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T4,T7

 LINE       186
 SUB-EXPRESSION (cpha_i == 1'b0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T7

 LINE       191
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       198
 EXPRESSION (cnt == 3'('h00000007))
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       199
 EXPRESSION (cnt == 3'('h00000003))
            -----------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T4,T7

 LINE       200
 EXPRESSION (cnt == 3'('b1))
            --------1-------

-1-	Status	Tests
0	Covered	T3,T7,T13
1	Covered	T3,T7,T13

---

Branch Coverage for Module : spi_p2s

	Line No.	Total	Covered	Percent
Branches		42	29	69.05
TERNARY	91	2	2	100.00
TERNARY	142	2	2	100.00
CASE	72	4	3	75.00
CASE	112	4	3	75.00
CASE	122	7	4	57.14
CASE	148	13	6	46.15
IF	182	4	4	100.00
CASE	197	4	3	75.00
IF	213	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	91	(csb_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	142	(first_beat) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	72	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T1,T2,T3
DualIO	Covered	T3,T4,T7
QuadIO	Covered	T3,T7,T13
default	Not Covered

	LineNo.	Expression
-1-:	112	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T1,T2,T3
DualIO	Covered	T3,T4,T7
QuadIO	Covered	T3,T7,T13
default	Not Covered

	LineNo.	Expression
-1-:	122	case (io_mode)
-2-:	124	(order_i) ? 
-3-:	128	(order_i) ? 
-4-:	132	(order_i) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
SingleIO	1	-	-	Not Covered
SingleIO	0	-	-	Covered	T3,T4,T6
DualIO	-	1	-	Not Covered
DualIO	-	0	-	Covered	T3,T4,T7
QuadIO	-	-	1	Not Covered
QuadIO	-	-	0	Covered	T3,T7,T13
default	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	case (io_mode)
-2-:	150	(order_i) ? 
-3-:	150	((!first_beat)) ? 
-4-:	150	((!first_beat)) ? 
-5-:	155	(order_i) ? 
-6-:	155	((!first_beat)) ? 
-7-:	155	((!first_beat)) ? 
-8-:	160	(order_i) ? 
-9-:	160	((!first_beat)) ? 
-10-:	160	((!first_beat)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
SingleIO	1	1	-	-	-	-	-	-	-	Not Covered
SingleIO	1	0	-	-	-	-	-	-	-	Not Covered
SingleIO	0	-	1	-	-	-	-	-	-	Covered	T3,T7,T8
SingleIO	0	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
DualIO	-	-	-	1	1	-	-	-	-	Not Covered
DualIO	-	-	-	1	0	-	-	-	-	Not Covered
DualIO	-	-	-	0	-	1	-	-	-	Covered	T3,T4,T7
DualIO	-	-	-	0	-	0	-	-	-	Covered	T3,T4,T7
QuadIO	-	-	-	-	-	-	1	1	-	Not Covered
QuadIO	-	-	-	-	-	-	1	0	-	Not Covered
QuadIO	-	-	-	-	-	-	0	-	1	Covered	T3,T7,T13
QuadIO	-	-	-	-	-	-	0	-	0	Covered	T3,T7,T13
default	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	182	if ((!rst_ni))
-2-:	184	if (last_beat)
-3-:	186	if ((data_valid_i && ((tx_state != TxIdle) || (cpha_i == 1'b0))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T7
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	197	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T1,T2,T3
DualIO	Covered	T3,T4,T7
QuadIO	Covered	T3,T7,T13
default	Not Covered

	LineNo.	Expression
-1-:	213	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

---

Assert Coverage for Module : spi_p2s

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoModeChangeValid_A	195715085	9278	0	0
IoModeDefault_A	195715085	32286	0	0

IoModeChangeValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195715085	9278	0	0
T3	87567	20	0	0
T4	113156	9	0	0
T5	1	0	0	0
T6	2006	0	0	0
T7	119844	28	0	0
T8	43441	1	0	0
T9	1	0	0	0
T10	673	0	0	0
T11	0	19	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	10	0	0
T16	0	25	0	0
T17	0	13	0	0
T18	133268	0	0	0
T19	1866	0	0	0

IoModeDefault_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195715085	32286	0	0
T3	87567	5	0	0
T4	113156	2	0	0
T5	1	0	0	0
T6	2006	0	0	0
T7	119844	531	0	0
T8	43441	1	0	0
T9	1	0	0	0
T10	673	0	0	0
T11	0	72	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	3	0	0
T18	133268	0	0	0
T19	1866	0	0	0