Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.65	95.15	86.84	96.92		88.89	95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.65	95.15	86.84	96.92		88.89	95.45

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.65	95.15	86.84	96.92		88.89	95.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	98.51	94.87	98.60	89.36	97.29	96.40

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_edge_0	100.00	100.00	100.00			100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	96.74	100.00	87.80		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	84.57	100.00	69.23			69.05	100.00
u_passthrough	89.52	92.89	88.99		75.00	90.74	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	93.14	97.16	93.19		87.50	87.82	100.00
u_reg	99.60	99.49	99.25	100.00		99.28	100.00
u_s2p	86.75	100.00	78.57			68.42	100.00
u_scanmode_sync	100.00						100.00
u_sck_csb_edge	94.44	100.00	83.33			100.00
u_sck_tog_edge	100.00	100.00	100.00			100.00
u_spi_tpm	96.43	99.76	93.53		91.67	97.18	100.00
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	95.45	100.00	81.82			100.00	100.00
u_spid_status	96.26	100.00	89.13			95.89	100.00
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	87.03	100.00	70.73			96.43	80.95
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.12	81.67	59.07			62.50	81.25
u_tlul2sram_ingress	86.46	87.92	73.84			84.09	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_upload	91.14	98.60	73.71		100.00	94.12	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		227	216	95.15
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
ALWAYS	506	4	4	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
ALWAYS	533	0	0
ALWAYS	533	2	2	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
ALWAYS	547	0	0
ALWAYS	547	12	12	100.00
CONT_ASSIGN	611	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
ALWAYS	766	6	6	100.00
ALWAYS	792	4	4	100.00
CONT_ASSIGN	811	1	1	100.00
ALWAYS	833	3	3	100.00
ALWAYS	839	8	8	100.00
ALWAYS	877	28	28	100.00
CONT_ASSIGN	956	1	1	100.00
CONT_ASSIGN	957	1	1	100.00
ALWAYS	1000	5	3	60.00
ALWAYS	1011	13	13	100.00
ALWAYS	1048	3	3	100.00
CONT_ASSIGN	1183	1	1	100.00
CONT_ASSIGN	1186	1	1	100.00
CONT_ASSIGN	1190	1	1	100.00
CONT_ASSIGN	1191	1	1	100.00
CONT_ASSIGN	1192	1	1	100.00
CONT_ASSIGN	1194	1	1	100.00
CONT_ASSIGN	1195	1	1	100.00
CONT_ASSIGN	1198	1	1	100.00
CONT_ASSIGN	1244	1	0	0.00
CONT_ASSIGN	1274	1	0	0.00
CONT_ASSIGN	1357	1	1	100.00
CONT_ASSIGN	1358	1	1	100.00
CONT_ASSIGN	1359	1	1	100.00
CONT_ASSIGN	1360	1	1	100.00
CONT_ASSIGN	1361	1	1	100.00
CONT_ASSIGN	1363	1	1	100.00
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
CONT_ASSIGN	1375	1	1	100.00
CONT_ASSIGN	1377	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1384	1	1	100.00
CONT_ASSIGN	1387	1	1	100.00
CONT_ASSIGN	1390	1	1	100.00
CONT_ASSIGN	1393	1	1	100.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1403	1	1	100.00
CONT_ASSIGN	1404	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1545	1	0	0.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1554	1	1	100.00
CONT_ASSIGN	1555	1	1	100.00
CONT_ASSIGN	1556	1	1	100.00
CONT_ASSIGN	1557	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1569	1	1	100.00
CONT_ASSIGN	1569	1	1	100.00
CONT_ASSIGN	1569	1	1	100.00
CONT_ASSIGN	1569	1	1	100.00
CONT_ASSIGN	1569	1	1	100.00
CONT_ASSIGN	1572	1	1	100.00
CONT_ASSIGN	1573	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1575	1	1	100.00
CONT_ASSIGN	1576	1	1	100.00
CONT_ASSIGN	1577	1	1	100.00
CONT_ASSIGN	1579	1	1	100.00
CONT_ASSIGN	1583	1	1	100.00
CONT_ASSIGN	1585	1	1	100.00
CONT_ASSIGN	1586	1	1	100.00
CONT_ASSIGN	1593	1	1	100.00
CONT_ASSIGN	1595	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1601	1	1	100.00
CONT_ASSIGN	1603	1	1	100.00
CONT_ASSIGN	1604	1	1	100.00
CONT_ASSIGN	1615	1	1	100.00
CONT_ASSIGN	1616	1	1	100.00
CONT_ASSIGN	1617	1	1	100.00
CONT_ASSIGN	1618	1	1	100.00
CONT_ASSIGN	1671	1	1	100.00
CONT_ASSIGN	1673	1	1	100.00
ALWAYS	1678	4	4	100.00
ALWAYS	1687	0	0
ALWAYS	1687	9	9	100.00
CONT_ASSIGN	1704	1	1	100.00
CONT_ASSIGN	1704	1	1	100.00
CONT_ASSIGN	1704	1	1	100.00
CONT_ASSIGN	1704	1	1	100.00
CONT_ASSIGN	1705	1	1	100.00
CONT_ASSIGN	1705	1	1	100.00
CONT_ASSIGN	1705	1	0	0.00
CONT_ASSIGN	1705	1	0	0.00
CONT_ASSIGN	1706	1	1	100.00
CONT_ASSIGN	1706	1	1	100.00
CONT_ASSIGN	1706	1	0	0.00
CONT_ASSIGN	1706	1	0	0.00
CONT_ASSIGN	1707	1	1	100.00
CONT_ASSIGN	1707	1	1	100.00
CONT_ASSIGN	1707	1	0	0.00
CONT_ASSIGN	1707	1	0	0.00
CONT_ASSIGN	1709	1	1	100.00
CONT_ASSIGN	1709	1	1	100.00
CONT_ASSIGN	1709	1	1	100.00
CONT_ASSIGN	1709	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1711	1	1	100.00
CONT_ASSIGN	1711	1	1	100.00
CONT_ASSIGN	1711	1	1	100.00
CONT_ASSIGN	1711	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1757	1	1	100.00
CONT_ASSIGN	1758	1	1	100.00
CONT_ASSIGN	1760	1	1	100.00
CONT_ASSIGN	1761	1	1	100.00
CONT_ASSIGN	1762	1	1	100.00
CONT_ASSIGN	1818	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
175	1	1
309	1	1
368	1	1
369	1	1
370	1	1
371	1	1
374	1	1
375	1	1
377	1	1
392	1	1
494	1	1
501	1	1
503	1	1
506	1	1
507	1	1
508	1	1
509	1	1
			MISSING_ELSE
514	1	1
520	1	1
523	1	1
524	1	1
528	1	1
533	1	1
534	1	1
538	1	1
539	1	1
547	1	1
548	1	1
567	1	1
568	1	1
572	1	1
573	1	1
575	1	1
576	1	1
578	1	1
579	1	1
581	1	1
582	1	1
611	1	1
612	1	1
613	1	1
766	2	2
767	1	1
768	1	1
769	1	1
770	1	1
			MISSING_ELSE
792	2	2
793	1	1
794	1	1
			MISSING_ELSE
811	1	1
833	2	2
834	1	1
839	1	1
841	1	1
842	1	1
849	1	1
853	1	1
854	1	1
858	1	1
859	1	1
877	1	1
878	1	1
879	1	1
880	1	1
882	1	1
884	1	1
890	1	1
893	1	1
894	1	1
896	1	1
898	1	1
900	1	1
904	1	1
906	1	1
907	1	1
908	1	1
911	1	1
913	1	1
914	1	1
915	1	1
920	1	1
922	1	1
923	1	1
924	1	1
928	1	1
930	1	1
931	1	1
932	1	1
956	1	1
957	1	1
1000	1	1
1001	0	1
1002	0	1
1004	1	1
1005	1	1
1011	1	1
1012	1	1
1014	1	1
1016	1	1
1017	1	1
1021	1	1
1023	1	1
1024	1	1
1028	1	1
1029	1	1
1030	1	1
1032	1	1
1033	1	1
1048	2	2
1049	1	1
1183	1	1
1186	1	1
1190	1	1
1191	1	1
1192	1	1
1194	1	1
1195	1	1
1198	1	1
1244	0	1
1274	0	1
1357	1	1
1358	1	1
1359	1	1
1360	1	1
1361	1	1
1363	1	1
1367	1	1
1374	1	1
1375	1	1
1377	1	1
1381	1	1
1384	1	1
1387	1	1
1390	1	1
1393	1	1
1396	1	1
1403	1	1
1404	1	1
1443	1	1
1545	0	1
1553	1	1
1554	1	1
1555	1	1
1556	1	1
1557	1	1
1560	1	1
1569	5	5
1572	1	1
1573	1	1
1574	1	1
1575	1	1
1576	1	1
1577	1	1
1579	1	1
1583	1	1
1585	1	1
1586	1	1
1593	1	1
1595	1	1
1597	1	1
1601	1	1
1603	1	1
1604	1	1
1615	1	1
1616	1	1
1617	1	1
1618	1	1
1671	1	1
1673	1	1
1678	1	1
1679	1	1
1680	1	1
1681	1	1
			MISSING_ELSE
1687	1	1
1688	1	1
1690	1	1
1693	1	1
1694	1	1
1695	1	1
1696	1	1
1698	1	1
1699	1	1
1704	4	4
1705	2	4
1706	2	4
1707	2	4
1709	4	4
1710	4	4
1711	4	4
1754	1	1
1755	1	1
1756	1	1
1757	1	1
1758	1	1
1760	1	1
1761	1	1
1762	1	1
1818	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	38	33	86.84
Logical	38	33	86.84
Non-Logical	0	0
Event	0	0

 LINE       175
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T11,T12

 LINE       666
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       677
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T10

 LINE       811
 EXPRESSION (spi_clk_pos_edge | spi_clk_neg_edge)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
1	0	Covered	T6,T7,T10

 LINE       863
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T11,T12

 LINE       1014
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T20,T24
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       1183
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T7

 LINE       1194
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T11,T12

 LINE       1195
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T11,T12

 LINE       1403
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T11

 LINE       1404
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T11

 LINE       1680
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1680
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1680
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1818
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T46

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	57	52	91.23
Total Bits	454	440	96.92
Total Bits 0->1	227	220	96.92
Total Bits 1->0	227	220	96.92

Ports	57	52	91.23
Port Bits	454	440	96.92
Port Bits 0->1	227	220	96.92
Port Bits 1->0	227	220	96.92

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T47,T12	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T18,T13	Yes	T2,T18,T13	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T9,T25	Yes	T2,T9,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T5,T47	Yes	T1,T5,T47	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T5,T47	Yes	T1,T5,T47	OUTPUT
cio_sck_i	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
cio_csb_i	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
cio_sd_o[3:0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
cio_tpm_csb_i	Yes	Yes	T6,T7,T10	Yes	T6,T7,T10	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T8,*T13,*T14	Yes	T8,T13,T14	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T11,T12,T27	Yes	T8,T13,T14	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
sck_monitor_o	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		36	32	88.89
IF	506	3	3	100.00
IF	766	4	4	100.00
IF	792	3	3	100.00
IF	833	2	2	100.00
CASE	849	4	4	100.00
CASE	890	7	5	71.43
IF	1000	2	1	50.00
IF	1014	5	4	80.00
IF	1048	2	2	100.00
IF	1680	2	2	100.00
IF	1690	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	506	if ((!rst_ni))
-2-:	508	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	766	if ((!tpm_rst_n))
-2-:	767	if (spi_clk_csb_rst_pulse)
-3-:	769	if (spi_clk_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T10
0	0	1	Covered	T6,T7,T10
0	0	0	Covered	T6,T7,T10

	LineNo.	Expression
-1-:	792	if ((!rst_ni))
-2-:	793	if (sys_csb_pos_pulse_stretch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	833	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	849	case (cmd_dp_sel)
-2-:	863	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T3,T4,T7
DpUpload	-	Covered	T7,T11,T12
default	1	Covered	T7,T11,T12
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	890	case (spi_mode)
-2-:	896	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T3,T4,T7
FlashMode PassThrough	DpReadStatus	Covered	T7,T8,T13
FlashMode PassThrough	DpReadJEDEC	Covered	T7,T11,T12
FlashMode PassThrough	DpUpload	Covered	T7,T11,T12
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	1000	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1014	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1021	case (spi_mode)
-3-:	1028	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T10
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T8,T13,T11
0	PassThrough	0	Covered	T8,T13,T14
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1048	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	1680	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1690	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	638532305	638448223	0	0
CioSdoEnOKnown	638532305	638448223	0	0
CioSdoEnOffWhenInactive	638532305	638448223	0	0
CsPulseWidth_A	638532305	540160119	0	0
FpvSecCmRegWeOnehotCheck_A	638532305	100	0	0
InterceptLevel_M	195715085	0	0	0
IntrReadbufFlipOKnown	638532305	638448223	0	0
IntrReadbufWatermarkOKnown	638532305	638448223	0	0
IntrTpmHeaderNotEmptyOKnown	638532305	638448223	0	0
IntrUploadCmdfifoNotEmptyOKnown	638532305	638448223	0	0
IntrUploadPayloadNotEmptyOKnown	638532305	638448223	0	0
IntrUploadPayloadOverflowOKnown	638532305	638448223	0	0
PayloadStartIdxWidthMatch_A	941	941	0	0
SpiModeKnown_A	638532305	638448223	0	0
TpmEnableWhenTpmCsbIdle_M	638532305	353	0	0
TpmRdfifoNotFull_A	638532305	294156	0	0
TpmWrPtrMatch_A	941	941	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	638532305	2283792	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	638532305	57411	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	638532305	2536	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	638532305	1947	0	0
scanmodeKnown	638532305	638532305	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

CsPulseWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	540160119	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	7623	0	0
T7	621057	475048	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	2183	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	100	0	0
T15	8664	0	0	0
T23	14534	0	0	0
T47	3523	10	0	0
T55	8150	30	0	0
T56	0	20	0	0
T57	0	30	0	0
T58	0	10	0	0
T59	301776	0	0	0
T60	113627	0	0	0
T61	398768	0	0	0
T62	436120	0	0	0
T63	5322	0	0	0
T64	975982	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	195715085	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	941	941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638448223	0	0
T1	866	779	0	0
T2	1529	1463	0	0
T3	359319	359260	0	0
T4	456091	456031	0	0
T5	1230	1177	0	0
T6	8157	8101	0	0
T7	621057	621035	0	0
T8	24913	24854	0	0
T9	1308	1251	0	0
T10	3995	3919	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	353	0	0
T6	8157	1	0	0
T7	621057	2	0	0
T8	24913	0	0	0
T9	1308	0	0	0
T10	3995	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	296381	0	0	0
T18	146455	1	0	0
T19	4735	1	0	0
T20	936	0	0	0
T21	442804	1	0	0
T22	0	1	0	0
T23	0	1	0	0

TpmRdfifoNotFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	294156	0	0
T6	8157	4	0	0
T7	621057	3528	0	0
T8	24913	0	0	0
T9	1308	0	0	0
T10	3995	0	0	0
T11	0	247	0	0
T12	0	7221	0	0
T13	296381	0	0	0
T18	146455	1186	0	0
T19	4735	0	0	0
T20	936	0	0	0
T21	442804	775	0	0
T22	0	794	0	0
T23	0	34	0	0
T26	0	973	0	0
T27	0	1170	0	0

TpmWrPtrMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	941	941	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	2283792	0	0
T2	1529	100	0	0
T3	359319	2112	0	0
T4	456091	1344	0	0
T5	1230	0	0	0
T6	8157	0	0	0
T7	621057	19136	0	0
T8	24913	832	0	0
T9	1308	100	0	0
T10	3995	0	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T18	146455	0	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	57411	0	0
T2	1529	100	0	0
T3	359319	0	0	0
T4	456091	0	0	0
T5	1230	0	0	0
T6	8157	0	0	0
T7	621057	636	0	0
T8	24913	0	0	0
T9	1308	100	0	0
T10	3995	0	0	0
T11	0	256	0	0
T12	0	651	0	0
T18	146455	0	0	0
T26	0	128	0	0
T27	0	128	0	0
T28	0	933	0	0
T29	0	327	0	0
T30	0	64	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	2536	0	0
T7	621057	32	0	0
T8	24913	0	0	0
T9	1308	0	0	0
T10	3995	0	0	0
T11	0	12	0	0
T12	0	40	0	0
T13	296381	0	0	0
T18	146455	0	0	0
T19	4735	0	0	0
T20	936	0	0	0
T21	442804	0	0	0
T22	391096	0	0	0
T26	0	6	0	0
T27	0	5	0	0
T28	0	46	0	0
T29	0	13	0	0
T30	0	1	0	0
T33	0	16	0	0
T36	0	7	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	1947	0	0
T7	621057	23	0	0
T8	24913	0	0	0
T9	1308	0	0	0
T10	3995	0	0	0
T11	0	10	0	0
T12	0	36	0	0
T13	296381	0	0	0
T18	146455	0	0	0
T19	4735	0	0	0
T20	936	0	0	0
T21	442804	0	0	0
T22	391096	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T28	0	32	0	0
T29	0	9	0	0
T30	0	1	0	0
T33	0	11	0	0
T36	0	7	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	638532305	0	0
T1	866	866	0	0
T2	1529	1529	0	0
T3	359319	359319	0	0
T4	456091	456091	0	0
T5	1230	1230	0	0
T6	8157	8157	0	0
T7	621057	621057	0	0
T8	24913	24913	0	0
T9	1308	1308	0	0
T10	3995	3995	0	0