Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.65	95.15	86.84	96.92		88.89	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.65	95.15	86.84	96.92		88.89	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T4,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T4,T7

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1915596915	3474	0	0
SrcPulseCheck_M	587142468	3474	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1915596915	3474	0	0
T3	718638	11	0	0
T4	912182	5	0	0
T5	2460	0	0	0
T6	16314	0	0	0
T7	1863171	32	0	0
T8	74739	0	0	0
T9	3924	0	0	0
T10	11985	0	0	0
T11	0	12	0	0
T12	0	40	0	0
T13	296381	0	0	0
T15	0	7	0	0
T17	0	4	0	0
T18	439365	0	0	0
T19	14205	0	0	0
T20	936	0	0	0
T21	442804	0	0	0
T22	391096	0	0	0
T26	0	6	0	0
T27	0	5	0	0
T28	0	46	0	0
T29	0	13	0	0
T30	0	1	0	0
T33	0	16	0	0
T36	0	7	0	0
T119	0	7	0	0
T120	0	9	0	0
T121	0	7	0	0
T122	0	7	0	0
T123	0	28	0	0
T124	0	7	0	0
T125	0	3	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	587142468	3474	0	0
T3	175132	11	0	0
T4	226310	5	0	0
T6	4010	0	0	0
T7	359529	32	0	0
T8	130320	0	0	0
T10	2016	0	0	0
T11	0	12	0	0
T12	0	40	0	0
T13	216762	0	0	0
T14	1260	0	0	0
T15	11758	7	0	0
T17	0	4	0	0
T18	399801	0	0	0
T19	5595	0	0	0
T21	170493	0	0	0
T22	56367	0	0	0
T26	0	6	0	0
T27	0	5	0	0
T28	0	46	0	0
T29	0	13	0	0
T30	0	1	0	0
T33	0	16	0	0
T36	0	7	0	0
T119	0	7	0	0
T120	0	9	0	0
T121	0	7	0	0
T122	0	7	0	0
T123	0	28	0	0
T124	0	7	0	0
T125	0	3	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T15
1	0	Covered	T3,T4,T15
1	1	Covered	T3,T4,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T15
1	0	Covered	T3,T4,T15
1	1	Covered	T3,T4,T15

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	638532305	371	0	0
SrcPulseCheck_M	195714156	371	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	371	0	0
T3	359319	6	0	0
T4	456091	3	0	0
T5	1230	0	0	0
T6	8157	0	0	0
T7	621057	0	0	0
T8	24913	0	0	0
T9	1308	0	0	0
T10	3995	0	0	0
T15	0	2	0	0
T17	0	2	0	0
T18	146455	0	0	0
T19	4735	0	0	0
T120	0	5	0	0
T121	0	2	0	0
T122	0	2	0	0
T123	0	14	0	0
T124	0	2	0	0
T125	0	3	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	195714156	371	0	0
T3	87566	6	0	0
T4	113155	3	0	0
T6	2005	0	0	0
T7	119843	0	0	0
T8	43440	0	0	0
T10	672	0	0	0
T13	72254	0	0	0
T15	0	2	0	0
T17	0	2	0	0
T18	133267	0	0	0
T19	1865	0	0	0
T21	56831	0	0	0
T120	0	5	0	0
T121	0	2	0	0
T122	0	2	0	0
T123	0	14	0	0
T124	0	2	0	0
T125	0	3	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T15
1	0	Covered	T3,T4,T15
1	1	Covered	T3,T4,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T15
1	0	Covered	T3,T4,T15
1	1	Covered	T3,T4,T15

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	638532305	567	0	0
SrcPulseCheck_M	195714156	567	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	567	0	0
T3	359319	5	0	0
T4	456091	2	0	0
T5	1230	0	0	0
T6	8157	0	0	0
T7	621057	0	0	0
T8	24913	0	0	0
T9	1308	0	0	0
T10	3995	0	0	0
T15	0	5	0	0
T17	0	2	0	0
T18	146455	0	0	0
T19	4735	0	0	0
T119	0	7	0	0
T120	0	4	0	0
T121	0	5	0	0
T122	0	5	0	0
T123	0	14	0	0
T124	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	195714156	567	0	0
T3	87566	5	0	0
T4	113155	2	0	0
T6	2005	0	0	0
T7	119843	0	0	0
T8	43440	0	0	0
T10	672	0	0	0
T13	72254	0	0	0
T15	0	5	0	0
T17	0	2	0	0
T18	133267	0	0	0
T19	1865	0	0	0
T21	56831	0	0	0
T119	0	7	0	0
T120	0	4	0	0
T121	0	5	0	0
T122	0	5	0	0
T123	0	14	0	0
T124	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T7,T11,T12
1	0	Covered	T7,T11,T12
1	1	Covered	T7,T11,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T12
1	0	Covered	T7,T11,T12
1	1	Covered	T7,T11,T12

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	638532305	2536	0	0
SrcPulseCheck_M	195714156	2536	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638532305	2536	0	0
T7	621057	32	0	0
T8	24913	0	0	0
T9	1308	0	0	0
T10	3995	0	0	0
T11	0	12	0	0
T12	0	40	0	0
T13	296381	0	0	0
T18	146455	0	0	0
T19	4735	0	0	0
T20	936	0	0	0
T21	442804	0	0	0
T22	391096	0	0	0
T26	0	6	0	0
T27	0	5	0	0
T28	0	46	0	0
T29	0	13	0	0
T30	0	1	0	0
T33	0	16	0	0
T36	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	195714156	2536	0	0
T7	119843	32	0	0
T8	43440	0	0	0
T10	672	0	0	0
T11	0	12	0	0
T12	0	40	0	0
T13	72254	0	0	0
T14	1260	0	0	0
T15	11758	0	0	0
T18	133267	0	0	0
T19	1865	0	0	0
T21	56831	0	0	0
T22	56367	0	0	0
T26	0	6	0	0
T27	0	5	0	0
T28	0	46	0	0
T29	0	13	0	0
T30	0	1	0	0
T33	0	16	0	0
T36	0	7	0	0