Unified Coverage Report :: Module :: spi_passthrough

Module : spi_passthrough

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.00	92.35	87.88		75.00	89.80	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_passthrough	89.00	92.35	87.88		75.00	89.80	100.00

---

Module Instance : tb.dut.u_passthrough

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.00	92.35	87.88		75.00	89.80	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.52	92.89	88.99		75.00	90.74	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.65	95.15	86.84	96.92		88.89	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pt_isck_cg	100.00	100.00	100.00			100.00
u_pt_sck_cg	100.00	100.00	100.00			100.00
u_read_half_cycle	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_passthrough

	Line No.	Total	Covered	Percent
TOTAL		196	181	92.35
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
ALWAYS	346	4	4	100.00
ALWAYS	355	4	4	100.00
ALWAYS	359	3	3	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	370	4	4	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
ALWAYS	386	4	4	100.00
ALWAYS	410	8	8	100.00
ALWAYS	424	4	4	100.00
ALWAYS	435	4	4	100.00
CONT_ASSIGN	449	0	0
ALWAYS	459	4	4	100.00
CONT_ASSIGN	473	1	1	100.00
ALWAYS	476	3	3	100.00
CONT_ASSIGN	485	1	1	100.00
ALWAYS	488	3	3	100.00
ALWAYS	496	6	6	100.00
CONT_ASSIGN	507	1	1	100.00
ALWAYS	516	3	3	100.00
ALWAYS	530	4	4	100.00
ALWAYS	538	3	3	100.00
ALWAYS	543	6	6	100.00
ALWAYS	549	3	3	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
ALWAYS	571	5	5	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
ALWAYS	592	6	6	100.00
CONT_ASSIGN	599	1	1	100.00
ALWAYS	606	6	4	66.67
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	619	1	1	100.00
ALWAYS	623	3	3	100.00
CONT_ASSIGN	626	1	1	100.00
ALWAYS	672	8	4	50.00
ALWAYS	693	3	3	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
ALWAYS	735	3	3	100.00
ALWAYS	743	68	59	86.76

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
281	1	1
286	1	1
336	1	1
343	1	1
346	1	1
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
355	2	2
356	2	2
			MISSING_ELSE
359	2	2
360	1	1
365	1	1
370	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
382	1	1
383	1	1
386	1	1
387	1	1
388	1	1
396	1	1
			MISSING_ELSE
410	1	1
411	1	1
412	1	1
413	1	1
414	1	1
415	1	1
416	1	1
417	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
424	1	1
425	1	1
426	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
437	1	1
440	1	1
			MISSING_ELSE
449		unreachable
459	1	1
461	1	1
464	1	1
466	1	1
			MISSING_ELSE
473	1	1
476	1	1
477	1	1
478	1	1
			MISSING_ELSE
485	1	1
488	1	1
489	1	1
491	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
			MISSING_ELSE
507	1	1
516	2	2
517	1	1
530	1	1
531	1	1
532	1	1
533	1	1
			MISSING_ELSE
538	2	2
539	1	1
543	2	2
544	2	2
545	2	2
			MISSING_ELSE
549	2	2
550	1	1
553	1	1
556	1	1
571	1	1
572	1	1
573	1	1
575	1	1
576	1	1
580	1	1
582	1	1
585	1	1
586	1	1
592	2	2
593	1	1
594	1	1
595	1	1
596	1	1
			MISSING_ELSE
599	1	1
606	1	1
607	1	1
608	1	1
609	0	1
610	1	1
611	0	1
			MISSING_ELSE
614	1	1
619	1	1
623	2	2
624	1	1
626	1	1
672	1	1
673	1	1
674	1	1
676	1	1
678	0	1
679	0	1
682	0	1
683	0	1
693	2	2
694	1	1
716	1	1
718	1	1
724	1	1
727	1	1
735	1	1
736	1	1
738	1	1
743	1	1
746	1	1
749	1	1
752	1	1
755	1	1
758	1	1
761	1	1
762	1	1
765	1	1
766	1	1
768	1	1
770	1	1
771	1	1
772	1	1
773	1	1
774	1	1
777	1	1
778	1	1
788	1	1
789	1	1
791	1	1
792	1	1
793	1	1
795	1	1
796	1	1
797	1	1
799	1	1
800	1	1
802	1	1
804	1	1
			MISSING_ELSE
808	1	1
810	1	1
811	1	1
			MISSING_ELSE
816	0	1
817	0	1
819	0	1
820	0	1
822	0	1
828	1	1
829	1	1
830	1	1
835	1	1
838	1	1
839	1	1
844	1	1
847	1	1
848	1	1
852	1	1
853	1	1
854	1	1
856	1	1
857	1	1
858	0	1
860	0	1
			MISSING_ELSE
866	1	1
867	1	1
868	0	1
870	0	1
871	1	1
872	1	1
874	1	1
875	1	1
876	1	1
878	1	1
879	1	1
881	1	1
883	1	1
886	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spi_passthrough

	Total	Covered	Percent
Conditions	99	87	87.88
Logical	99	87	87.88
Non-Logical	0	0
Event	0	0

 LINE       281
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T13,T14

 LINE       365
 SUB-EXPRESSION (filter | csb_deassert)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14

 LINE       372
 EXPRESSION (bitcnt != '1)
            -------1------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T4,T7

 LINE       382
 EXPRESSION (bitcnt == 6'(6))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       383
 EXPRESSION (bitcnt == 6'(7))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       414
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b1})
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T4,T7

 LINE       416
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b0})
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T7,T13

 LINE       477
 EXPRESSION (addr_mode == Addr4B)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T16

 LINE       485
 EXPRESSION (st == StAddress)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T16

 LINE       500
 EXPRESSION (addrcnt_outclk != '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T13,T14,T16

 LINE       507
 EXPRESSION (cfg_addr_mask_i[addrcnt_outclk] ? cfg_addr_value_i[addrcnt_outclk] : host_s_i[0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T8

 LINE       532
 EXPRESSION ((payloadcnt != '0) && payload_replace)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T13,T11,T12
1	0	Covered	T3,T4,T7
1	1	Covered	T13,T11,T12

 LINE       532
 SUB-EXPRESSION (payloadcnt != '0)
                ---------1--------

-1-	Status	Tests
0	Covered	T13,T11,T12
1	Covered	T3,T4,T7

 LINE       553
 EXPRESSION (payloadcnt == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T11,T12

 LINE       556
 EXPRESSION (cfg_payload_mask_i[payloadcnt_outclk] ? cfg_payload_data_i[payloadcnt_outclk] : host_s_i[0])
             ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T13

 LINE       580
 EXPRESSION (addr_phase_outclk & cmd_info_addr_swap_en_outclk)
             --------1--------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T11,T31
1	0	Covered	T13,T14,T11
1	1	Covered	T16,T11,T31

 LINE       582
 EXPRESSION (payload_replace_outclk & cmd_info_payload_swap_en_outclk)
             -----------1----------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T32
1	0	Covered	T13,T14,T11
1	1	Covered	T11,T31,T12

 LINE       585
 EXPRESSION (addr_swap_en | payload_swap_en)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T31,T12
1	0	Covered	T16,T11,T31

 LINE       586
 EXPRESSION (addr_swap_en ? addr_swap : payload_swap)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T11,T31

 LINE       595
 EXPRESSION (st == StHighZ)
            -------1-------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T13,T14,T16

 LINE       599
 EXPRESSION (dummycnt == '0)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 EXPRESSION (st == StMByte)
            -------1-------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Not Covered

 LINE       614
 EXPRESSION (mbyte_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       619
 EXPRESSION (swap_en ? ({host_s_i[3:1], swap_data}) : host_s_i)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T11,T31

 LINE       718
 EXPRESSION (cfg_cpol_i ? pt_gated_isck_inv : pt_gated_sck)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       724
 EXPRESSION (host_csb_i | csb_deassert_outclk)
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T2,T3

 LINE       727
 EXPRESSION (is_active && ((!passthrough_block_i)))
             ----1----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T27
1	1	Covered	T8,T13,T14

 LINE       772
 EXPRESSION (cmd_8th && cmd_filter[host_s_i[0]])
             ---1---    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       777
 EXPRESSION (cmd_8th && cmd_info_d.valid)
             ---1---    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T16
1	1	Covered	T8,T13,T14

 LINE       788
 EXPRESSION (cmd_info_d.addr_mode != AddrDisabled)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T13,T14,T16

 LINE       797
 EXPRESSION (cmd_info_d.payload_en != 4'b0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T12,T33,T34
1	Covered	T8,T13,T14

 LINE       799
 EXPRESSION (cmd_info_d.payload_dir == PayloadOut)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T14,T11,T31
1	Covered	T8,T13,T16

 LINE       854
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadOut))
             ------1------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T16
1	0	Not Covered
1	1	Covered	T13,T14,T16

 LINE       854
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T13,T14,T16

 LINE       857
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadIn))
             ------1------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       857
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T13,T14,T16
1	Not Covered

 LINE       866
 EXPRESSION (addrcnt_outclk == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T13,T14,T16
1	Covered	T13,T14,T16

 LINE       876
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut))
             --------------1--------------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T27
1	0	Covered	T13,T11,T12
1	1	Covered	T16,T11,T31

 LINE       876
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T11,T12,T27
1	Covered	T13,T16,T11

 LINE       876
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T13,T11,T12
1	Covered	T16,T11,T31

 LINE       879
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn))
             --------------1--------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T13,T11,T12

 LINE       879
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T11,T12,T27
1	Covered	T13,T11,T12

 LINE       879
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T11,T12,T27
1	Covered	T13,T11,T12

---

FSM Coverage for Module : spi_passthrough

Summary for FSM :: st

	Total	Covered	Percent
States	7	6	85.71	(Not included in score)
Transitions	12	9	75.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAddress	789	Covered	T13,T14,T16
StDriving	802	Covered	T13,T14,T11
StFilter	773	Covered	T8,T13,T14
StHighZ	793	Covered	T13,T14,T16
StIdle	771	Covered	T1,T2,T3
StMByte	822	Not Covered
StWait	800	Covered	T8,T13,T14

transitions	Line No.	Covered	Tests
StAddress->StDriving	881	Covered	T13,T11,T12
StAddress->StHighZ	872	Covered	T13,T14,T16
StAddress->StMByte	868	Not Covered
StAddress->StWait	878	Covered	T16,T11,T31
StHighZ->StDriving	858	Not Covered
StHighZ->StWait	856	Covered	T13,T14,T16
StIdle->StAddress	789	Covered	T13,T14,T16
StIdle->StDriving	802	Covered	T14,T11,T31
StIdle->StFilter	773	Covered	T8,T13,T14
StIdle->StHighZ	793	Covered	T12,T27,T35
StIdle->StWait	800	Covered	T8,T13,T16
StMByte->StHighZ	817	Not Covered

---

Branch Coverage for Module : spi_passthrough

	Line No.	Total	Covered	Percent
Branches		98	88	89.80
TERNARY	507	2	2	100.00
TERNARY	556	2	2	100.00
TERNARY	586	2	2	100.00
TERNARY	619	2	2	100.00
TERNARY	718	2	1	50.00
IF	346	3	3	100.00
IF	355	3	3	100.00
IF	359	2	2	100.00
IF	370	3	3	100.00
IF	386	3	3	100.00
IF	411	2	2	100.00
IF	424	3	3	100.00
IF	435	3	3	100.00
IF	461	2	2	100.00
IF	477	2	2	100.00
IF	488	2	2	100.00
IF	496	4	4	100.00
IF	516	2	2	100.00
IF	530	3	3	100.00
IF	538	2	2	100.00
IF	543	4	4	100.00
IF	549	2	2	100.00
IF	571	2	2	100.00
IF	592	4	4	100.00
IF	606	4	2	50.00
IF	623	2	2	100.00
CASE	676	3	1	33.33
IF	693	2	2	100.00
IF	735	2	2	100.00
CASE	768	24	19	79.17

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	507	(cfg_addr_mask_i[addrcnt_outclk]) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	(cfg_payload_mask_i[payloadcnt_outclk]) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	(addr_swap_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T11,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	619	(swap_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T11,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	(cfg_cpol_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	348	if ((bitcnt < 6'(8)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	355	if ((!rst_ni))
-2-:	356	if (filter)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	359	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	370	if ((!rst_ni))
-2-:	372	if ((bitcnt != '1))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	386	if ((!rst_ni))
-2-:	388	if (cmd_7th)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	411	if (cmd_7th)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	424	if ((!rst_ni))
-2-:	426	if (cmd_7th)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	435	if ((!rst_ni))
-2-:	437	if (cmd_info_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	461	if (cmd_8th)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	477	if ((addr_mode == Addr4B))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	496	if ((!rst_ni))
-2-:	498	if (addr_set_q)
-3-:	500	if ((addrcnt_outclk != '0))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T14,T16
0	0	1	Covered	T13,T14,T16
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	516	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	530	if ((!rst_ni))
-2-:	532	if (((payloadcnt != '0) && payload_replace))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T13,T11,T12
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	538	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	543	if ((!rst_ni))
-2-:	544	if (payload_replace_set)
-3-:	545	if (payload_replace_clr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T14,T11
0	0	1	Covered	T13,T11,T12
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	549	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	571	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	592	if ((!rst_ni))
-2-:	593	if (dummy_set)
-3-:	595	if ((st == StHighZ))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T14,T16
0	0	1	Covered	T13,T14,T16
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	606	if ((!rst_ni))
-2-:	608	if (mbyte_set)
-3-:	610	if ((st == StMByte))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	623	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	676	case (cmd_info.read_pipeline_mode)

Branches:

-1-	Status	Tests
RdPipeTwoStageFullCycle	Not Covered
RdPipeTwoStageHalfCycle	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	693	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	735	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	768	case (st)
-2-:	770	if ((!is_active))
-3-:	772	if ((cmd_8th && cmd_filter[host_s_i[0]]))
-4-:	777	if ((cmd_8th && cmd_info_d.valid))
-5-:	788	if ((cmd_info_d.addr_mode != AddrDisabled))
-6-:	792	if (cmd_info_d.dummy_en)
-7-:	797	if ((cmd_info_d.payload_en != 4'b0))
-8-:	799	if ((cmd_info_d.payload_dir == PayloadOut))
-9-:	808	if (cmd_8th)
-10-:	816	if (mbytecnt_zero)
-11-:	854	if ((dummycnt_zero && (cmd_info.payload_dir == PayloadOut)))
-12-:	857	if ((dummycnt_zero && (cmd_info.payload_dir == PayloadIn)))
-13-:	866	if ((addrcnt_outclk == '0))
-14-:	867	if (cmd_info.mbyte_en)
-15-:	871	if (cmd_info.dummy_en)
-16-:	876	if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut)))
-17-:	879	if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T14
StIdle	0	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T16
StIdle	0	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T27,T35
StIdle	0	0	1	0	0	1	1	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T16
StIdle	0	0	1	0	0	1	0	-	-	-	-	-	-	-	-	-	Covered	T14,T11,T31
StIdle	0	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T12,T33,T34
StIdle	0	0	0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T8,T13,T16
StIdle	0	0	0	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T8,T13,T14
StMByte	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StMByte	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StFilter	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T14
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T14
StDriving	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T11
StHighZ	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T14,T16
StHighZ	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	Not Covered
StHighZ	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T13,T14,T16
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	Covered	T13,T14,T16
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	Covered	T16,T11,T31
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	1	Covered	T13,T11,T12
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	0	Covered	T11,T12,T27
StAddress	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T13,T14,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_passthrough

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PassThroughStKnown_A	195714156	151204231	0	0
PayloadSwapConstraint_M	195714156	2083568	0	0

PassThroughStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195714156	151204231	0	0
T3	87566	86642	0	0
T4	113155	112848	0	0
T6	2005	0	0	0
T7	119843	899000	0	0
T8	43440	43440	0	0
T10	672	0	0	0
T11	0	356092	0	0
T13	72254	72254	0	0
T14	0	1260	0	0
T15	0	11522	0	0
T16	0	205894	0	0
T17	0	144328	0	0
T18	133267	0	0	0
T19	1865	0	0	0
T21	56831	0	0	0

PayloadSwapConstraint_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	195714156	2083568	0	0
T11	399457	20920	0	0
T12	377669	27648	0	0
T27	0	72096	0	0
T28	0	7224	0	0
T29	0	10296	0	0
T30	0	5208	0	0
T31	91698	0	0	0
T32	48456	13872	0	0
T33	0	5552	0	0
T34	0	11752	0	0
T36	0	6264	0	0
T37	187201	0	0	0
T38	16	0	0	0
T39	1353	0	0	0
T40	1580	0	0	0
T41	46435	0	0	0
T42	148819	0	0	0