Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
4136 |
0 |
0 |
T73 |
32181 |
2 |
0 |
0 |
T74 |
9978 |
88 |
0 |
0 |
T75 |
2489 |
2 |
0 |
0 |
T76 |
1776 |
1 |
0 |
0 |
T77 |
5389 |
276 |
0 |
0 |
T78 |
18573 |
5 |
0 |
0 |
T80 |
0 |
330 |
0 |
0 |
T82 |
0 |
330 |
0 |
0 |
T91 |
971 |
0 |
0 |
0 |
T92 |
2381 |
0 |
0 |
0 |
T93 |
1219 |
0 |
0 |
0 |
T94 |
1419 |
0 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
T126 |
0 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2006 |
0 |
0 |
T73 |
32181 |
17 |
0 |
0 |
T75 |
2489 |
6 |
0 |
0 |
T79 |
93031 |
61 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
79 |
0 |
0 |
T97 |
40258 |
232 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
4 |
0 |
0 |
T111 |
0 |
4 |
0 |
0 |
T117 |
10163 |
17 |
0 |
0 |
T127 |
0 |
14 |
0 |
0 |
T128 |
0 |
137 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
1976 |
0 |
0 |
T73 |
32181 |
35 |
0 |
0 |
T75 |
2489 |
3 |
0 |
0 |
T79 |
93031 |
60 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
73 |
0 |
0 |
T97 |
40258 |
244 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
9 |
0 |
0 |
T117 |
10163 |
6 |
0 |
0 |
T127 |
0 |
32 |
0 |
0 |
T128 |
0 |
119 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
45 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
3537 |
0 |
0 |
T73 |
32181 |
46 |
0 |
0 |
T75 |
2489 |
5 |
0 |
0 |
T79 |
93031 |
204 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
264 |
0 |
0 |
T97 |
40258 |
234 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
1 |
0 |
0 |
T111 |
0 |
26 |
0 |
0 |
T117 |
10163 |
62 |
0 |
0 |
T127 |
0 |
86 |
0 |
0 |
T128 |
0 |
364 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
12500 |
0 |
0 |
T73 |
32181 |
318 |
0 |
0 |
T75 |
2489 |
8 |
0 |
0 |
T79 |
93031 |
973 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
791 |
0 |
0 |
T97 |
40258 |
270 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T111 |
0 |
129 |
0 |
0 |
T117 |
10163 |
151 |
0 |
0 |
T127 |
0 |
217 |
0 |
0 |
T128 |
0 |
1821 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
13073 |
0 |
0 |
T73 |
32181 |
202 |
0 |
0 |
T75 |
2489 |
5 |
0 |
0 |
T79 |
93031 |
1319 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
4 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
826 |
0 |
0 |
T97 |
40258 |
281 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
3 |
0 |
0 |
T117 |
10163 |
18 |
0 |
0 |
T127 |
0 |
87 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
11534 |
0 |
0 |
T73 |
32181 |
328 |
0 |
0 |
T75 |
2489 |
3 |
0 |
0 |
T79 |
93031 |
795 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
1196 |
0 |
0 |
T97 |
40258 |
240 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
54 |
0 |
0 |
T111 |
0 |
123 |
0 |
0 |
T117 |
10163 |
17 |
0 |
0 |
T127 |
0 |
361 |
0 |
0 |
T128 |
0 |
2029 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
13316 |
0 |
0 |
T73 |
32181 |
439 |
0 |
0 |
T75 |
2489 |
5 |
0 |
0 |
T79 |
93031 |
1027 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
1559 |
0 |
0 |
T97 |
40258 |
233 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
1 |
0 |
0 |
T111 |
0 |
157 |
0 |
0 |
T117 |
10163 |
276 |
0 |
0 |
T127 |
0 |
486 |
0 |
0 |
T128 |
0 |
2007 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
12529 |
0 |
0 |
T73 |
32181 |
519 |
0 |
0 |
T75 |
2489 |
7 |
0 |
0 |
T79 |
93031 |
1149 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
1186 |
0 |
0 |
T97 |
40258 |
229 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
63 |
0 |
0 |
T117 |
10163 |
245 |
0 |
0 |
T127 |
0 |
384 |
0 |
0 |
T128 |
0 |
1769 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
901 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
11852 |
0 |
0 |
T73 |
32181 |
243 |
0 |
0 |
T75 |
2489 |
2 |
0 |
0 |
T79 |
93031 |
888 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
1369 |
0 |
0 |
T97 |
40258 |
279 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
53 |
0 |
0 |
T117 |
10163 |
266 |
0 |
0 |
T127 |
0 |
405 |
0 |
0 |
T128 |
0 |
1819 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
547 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
12901 |
0 |
0 |
T73 |
32181 |
290 |
0 |
0 |
T74 |
9978 |
3 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
821 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
1374 |
0 |
0 |
T97 |
40258 |
218 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
3 |
0 |
0 |
T111 |
0 |
147 |
0 |
0 |
T117 |
10163 |
215 |
0 |
0 |
T127 |
0 |
353 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
12242 |
0 |
0 |
T73 |
32181 |
450 |
0 |
0 |
T75 |
2489 |
5 |
0 |
0 |
T79 |
93031 |
633 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
1153 |
0 |
0 |
T97 |
40258 |
237 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
4 |
0 |
0 |
T111 |
0 |
1 |
0 |
0 |
T117 |
10163 |
134 |
0 |
0 |
T127 |
0 |
457 |
0 |
0 |
T128 |
0 |
2084 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5996 |
0 |
0 |
T73 |
32181 |
156 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
304 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
408 |
0 |
0 |
T97 |
40258 |
227 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
25 |
0 |
0 |
T111 |
0 |
5 |
0 |
0 |
T117 |
10163 |
97 |
0 |
0 |
T127 |
0 |
127 |
0 |
0 |
T128 |
0 |
875 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6164 |
0 |
0 |
T73 |
32181 |
221 |
0 |
0 |
T75 |
2489 |
7 |
0 |
0 |
T79 |
93031 |
417 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
476 |
0 |
0 |
T97 |
40258 |
268 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
19 |
0 |
0 |
T111 |
0 |
73 |
0 |
0 |
T117 |
10163 |
158 |
0 |
0 |
T127 |
0 |
117 |
0 |
0 |
T128 |
0 |
790 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5726 |
0 |
0 |
T73 |
32181 |
118 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
415 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
279 |
0 |
0 |
T97 |
40258 |
277 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
45 |
0 |
0 |
T117 |
10163 |
56 |
0 |
0 |
T127 |
0 |
114 |
0 |
0 |
T128 |
0 |
716 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
353 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5483 |
0 |
0 |
T73 |
32181 |
60 |
0 |
0 |
T75 |
2489 |
4 |
0 |
0 |
T79 |
93031 |
505 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
431 |
0 |
0 |
T97 |
40258 |
225 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
1 |
0 |
0 |
T111 |
0 |
3 |
0 |
0 |
T117 |
10163 |
171 |
0 |
0 |
T127 |
0 |
126 |
0 |
0 |
T128 |
0 |
967 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6246 |
0 |
0 |
T73 |
32181 |
123 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
520 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
424 |
0 |
0 |
T97 |
40258 |
252 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
55 |
0 |
0 |
T117 |
10163 |
102 |
0 |
0 |
T127 |
0 |
152 |
0 |
0 |
T128 |
0 |
951 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
219 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6400 |
0 |
0 |
T73 |
32181 |
142 |
0 |
0 |
T75 |
2489 |
2 |
0 |
0 |
T79 |
93031 |
419 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
640 |
0 |
0 |
T97 |
40258 |
248 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
21 |
0 |
0 |
T111 |
0 |
49 |
0 |
0 |
T117 |
10163 |
11 |
0 |
0 |
T127 |
0 |
142 |
0 |
0 |
T128 |
0 |
934 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5898 |
0 |
0 |
T73 |
32181 |
97 |
0 |
0 |
T79 |
93031 |
395 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
65780 |
563 |
0 |
0 |
T97 |
40258 |
191 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
12 |
0 |
0 |
T111 |
0 |
51 |
0 |
0 |
T117 |
10163 |
141 |
0 |
0 |
T127 |
0 |
131 |
0 |
0 |
T128 |
0 |
938 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
225 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5629 |
0 |
0 |
T73 |
32181 |
212 |
0 |
0 |
T75 |
2489 |
5 |
0 |
0 |
T79 |
93031 |
380 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
487 |
0 |
0 |
T97 |
40258 |
259 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
1 |
0 |
0 |
T117 |
10163 |
109 |
0 |
0 |
T127 |
0 |
127 |
0 |
0 |
T128 |
0 |
812 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
169 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6482 |
0 |
0 |
T73 |
32181 |
22 |
0 |
0 |
T75 |
2489 |
8 |
0 |
0 |
T79 |
93031 |
542 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
471 |
0 |
0 |
T97 |
40258 |
250 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
21 |
0 |
0 |
T111 |
0 |
65 |
0 |
0 |
T117 |
10163 |
167 |
0 |
0 |
T127 |
0 |
194 |
0 |
0 |
T128 |
0 |
957 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6070 |
0 |
0 |
T73 |
32181 |
150 |
0 |
0 |
T79 |
93031 |
469 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
65780 |
608 |
0 |
0 |
T97 |
40258 |
286 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T111 |
0 |
68 |
0 |
0 |
T117 |
10163 |
58 |
0 |
0 |
T127 |
0 |
95 |
0 |
0 |
T128 |
0 |
803 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
333 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6189 |
0 |
0 |
T73 |
32181 |
176 |
0 |
0 |
T75 |
2489 |
2 |
0 |
0 |
T79 |
93031 |
364 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
492 |
0 |
0 |
T97 |
40258 |
250 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
17 |
0 |
0 |
T111 |
0 |
42 |
0 |
0 |
T117 |
10163 |
71 |
0 |
0 |
T127 |
0 |
169 |
0 |
0 |
T128 |
0 |
1129 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6425 |
0 |
0 |
T73 |
32181 |
88 |
0 |
0 |
T75 |
2489 |
7 |
0 |
0 |
T79 |
93031 |
460 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
547 |
0 |
0 |
T97 |
40258 |
211 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
17 |
0 |
0 |
T111 |
0 |
4 |
0 |
0 |
T117 |
10163 |
8 |
0 |
0 |
T127 |
0 |
135 |
0 |
0 |
T128 |
0 |
899 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6038 |
0 |
0 |
T73 |
32181 |
111 |
0 |
0 |
T75 |
2489 |
5 |
0 |
0 |
T79 |
93031 |
429 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
574 |
0 |
0 |
T97 |
40258 |
268 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
41 |
0 |
0 |
T111 |
0 |
2 |
0 |
0 |
T117 |
10163 |
67 |
0 |
0 |
T127 |
0 |
128 |
0 |
0 |
T128 |
0 |
1034 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5629 |
0 |
0 |
T73 |
32181 |
104 |
0 |
0 |
T75 |
2489 |
7 |
0 |
0 |
T79 |
93031 |
427 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
429 |
0 |
0 |
T97 |
40258 |
244 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
3 |
0 |
0 |
T117 |
10163 |
93 |
0 |
0 |
T127 |
0 |
104 |
0 |
0 |
T128 |
0 |
830 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
217 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6484 |
0 |
0 |
T73 |
32181 |
108 |
0 |
0 |
T75 |
2489 |
9 |
0 |
0 |
T79 |
93031 |
308 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
664 |
0 |
0 |
T97 |
40258 |
224 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T111 |
0 |
1 |
0 |
0 |
T117 |
10163 |
54 |
0 |
0 |
T127 |
0 |
220 |
0 |
0 |
T128 |
0 |
780 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5885 |
0 |
0 |
T73 |
32181 |
88 |
0 |
0 |
T75 |
2489 |
8 |
0 |
0 |
T79 |
93031 |
349 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
531 |
0 |
0 |
T97 |
40258 |
213 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
9 |
0 |
0 |
T111 |
0 |
55 |
0 |
0 |
T117 |
10163 |
94 |
0 |
0 |
T127 |
0 |
104 |
0 |
0 |
T128 |
0 |
974 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5938 |
0 |
0 |
T73 |
32181 |
152 |
0 |
0 |
T74 |
9978 |
4 |
0 |
0 |
T75 |
2489 |
2 |
0 |
0 |
T79 |
93031 |
355 |
0 |
0 |
T88 |
0 |
7 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
425 |
0 |
0 |
T97 |
40258 |
282 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
44 |
0 |
0 |
T117 |
10163 |
18 |
0 |
0 |
T127 |
0 |
130 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5242 |
0 |
0 |
T73 |
32181 |
146 |
0 |
0 |
T74 |
9978 |
3 |
0 |
0 |
T75 |
2489 |
8 |
0 |
0 |
T79 |
93031 |
334 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
447 |
0 |
0 |
T97 |
40258 |
248 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T117 |
10163 |
5 |
0 |
0 |
T127 |
0 |
147 |
0 |
0 |
T128 |
0 |
730 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
196 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6184 |
0 |
0 |
T73 |
32181 |
188 |
0 |
0 |
T75 |
2489 |
6 |
0 |
0 |
T79 |
93031 |
461 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
646 |
0 |
0 |
T97 |
40258 |
265 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
5 |
0 |
0 |
T117 |
10163 |
105 |
0 |
0 |
T127 |
0 |
86 |
0 |
0 |
T128 |
0 |
1057 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
281 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5254 |
0 |
0 |
T73 |
32181 |
94 |
0 |
0 |
T79 |
93031 |
305 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
65780 |
605 |
0 |
0 |
T97 |
40258 |
215 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
2 |
0 |
0 |
T111 |
0 |
35 |
0 |
0 |
T117 |
10163 |
64 |
0 |
0 |
T127 |
0 |
110 |
0 |
0 |
T128 |
0 |
506 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
191 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5323 |
0 |
0 |
T73 |
32181 |
182 |
0 |
0 |
T75 |
2489 |
3 |
0 |
0 |
T79 |
93031 |
322 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
434 |
0 |
0 |
T97 |
40258 |
282 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
47 |
0 |
0 |
T117 |
10163 |
15 |
0 |
0 |
T127 |
0 |
213 |
0 |
0 |
T128 |
0 |
527 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
264 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6129 |
0 |
0 |
T73 |
32181 |
137 |
0 |
0 |
T75 |
2489 |
2 |
0 |
0 |
T79 |
93031 |
454 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T88 |
0 |
4 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
587 |
0 |
0 |
T97 |
40258 |
241 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
1 |
0 |
0 |
T117 |
10163 |
63 |
0 |
0 |
T127 |
0 |
110 |
0 |
0 |
T128 |
0 |
906 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
5607 |
0 |
0 |
T73 |
32181 |
129 |
0 |
0 |
T75 |
2489 |
5 |
0 |
0 |
T79 |
93031 |
402 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
485 |
0 |
0 |
T97 |
40258 |
230 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
26 |
0 |
0 |
T111 |
0 |
6 |
0 |
0 |
T117 |
10163 |
109 |
0 |
0 |
T127 |
0 |
184 |
0 |
0 |
T128 |
0 |
820 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
6762 |
0 |
0 |
T73 |
32181 |
171 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
416 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
624 |
0 |
0 |
T97 |
40258 |
218 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
66 |
0 |
0 |
T117 |
10163 |
100 |
0 |
0 |
T127 |
0 |
200 |
0 |
0 |
T128 |
0 |
1084 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
390 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2417 |
0 |
0 |
T73 |
32181 |
30 |
0 |
0 |
T75 |
2489 |
9 |
0 |
0 |
T79 |
93031 |
120 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T88 |
0 |
2 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
101 |
0 |
0 |
T97 |
40258 |
235 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
12 |
0 |
0 |
T111 |
0 |
14 |
0 |
0 |
T117 |
10163 |
12 |
0 |
0 |
T127 |
0 |
34 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2401 |
0 |
0 |
T73 |
32181 |
36 |
0 |
0 |
T75 |
2489 |
5 |
0 |
0 |
T79 |
93031 |
68 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
98 |
0 |
0 |
T97 |
40258 |
238 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T111 |
0 |
2 |
0 |
0 |
T117 |
10163 |
18 |
0 |
0 |
T127 |
0 |
33 |
0 |
0 |
T128 |
0 |
173 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2406 |
0 |
0 |
T73 |
32181 |
3 |
0 |
0 |
T75 |
2489 |
9 |
0 |
0 |
T79 |
93031 |
95 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
93 |
0 |
0 |
T97 |
40258 |
268 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
4 |
0 |
0 |
T111 |
0 |
7 |
0 |
0 |
T117 |
10163 |
26 |
0 |
0 |
T127 |
0 |
48 |
0 |
0 |
T128 |
0 |
163 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2309 |
0 |
0 |
T73 |
32181 |
38 |
0 |
0 |
T75 |
2489 |
2 |
0 |
0 |
T79 |
93031 |
82 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
126 |
0 |
0 |
T97 |
40258 |
225 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
13 |
0 |
0 |
T117 |
10163 |
17 |
0 |
0 |
T127 |
0 |
23 |
0 |
0 |
T128 |
0 |
198 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
66 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
3130 |
0 |
0 |
T73 |
32181 |
37 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
202 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
210 |
0 |
0 |
T97 |
40258 |
247 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
10 |
0 |
0 |
T111 |
0 |
12 |
0 |
0 |
T117 |
10163 |
52 |
0 |
0 |
T127 |
0 |
83 |
0 |
0 |
T128 |
0 |
323 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
4533 |
0 |
0 |
T34 |
748075 |
0 |
0 |
0 |
T49 |
4676 |
80 |
0 |
0 |
T51 |
0 |
13 |
0 |
0 |
T73 |
0 |
76 |
0 |
0 |
T75 |
0 |
5 |
0 |
0 |
T79 |
0 |
225 |
0 |
0 |
T97 |
0 |
253 |
0 |
0 |
T117 |
0 |
82 |
0 |
0 |
T131 |
0 |
30 |
0 |
0 |
T132 |
0 |
16 |
0 |
0 |
T133 |
0 |
26 |
0 |
0 |
T134 |
302444 |
0 |
0 |
0 |
T135 |
114700 |
0 |
0 |
0 |
T136 |
17191 |
0 |
0 |
0 |
T137 |
78968 |
0 |
0 |
0 |
T138 |
499211 |
0 |
0 |
0 |
T139 |
669962 |
0 |
0 |
0 |
T140 |
735739 |
0 |
0 |
0 |
T141 |
138053 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2464 |
0 |
0 |
T73 |
32181 |
37 |
0 |
0 |
T79 |
93031 |
117 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
65780 |
108 |
0 |
0 |
T97 |
40258 |
267 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
10 |
0 |
0 |
T117 |
10163 |
4 |
0 |
0 |
T127 |
0 |
23 |
0 |
0 |
T128 |
0 |
157 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
53 |
0 |
0 |
T142 |
0 |
4 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2386 |
0 |
0 |
T73 |
32181 |
28 |
0 |
0 |
T75 |
2489 |
6 |
0 |
0 |
T79 |
93031 |
100 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
111 |
0 |
0 |
T97 |
40258 |
219 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
5 |
0 |
0 |
T117 |
10163 |
7 |
0 |
0 |
T127 |
0 |
20 |
0 |
0 |
T128 |
0 |
218 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
50 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2077 |
0 |
0 |
T73 |
32181 |
7 |
0 |
0 |
T75 |
2489 |
7 |
0 |
0 |
T79 |
93031 |
56 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T88 |
0 |
8 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
91 |
0 |
0 |
T97 |
40258 |
258 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
6 |
0 |
0 |
T117 |
10163 |
12 |
0 |
0 |
T127 |
0 |
25 |
0 |
0 |
T128 |
0 |
97 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2106 |
0 |
0 |
T73 |
32181 |
12 |
0 |
0 |
T75 |
2489 |
9 |
0 |
0 |
T79 |
93031 |
51 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
99 |
0 |
0 |
T97 |
40258 |
236 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
8 |
0 |
0 |
T117 |
10163 |
21 |
0 |
0 |
T127 |
0 |
13 |
0 |
0 |
T128 |
0 |
141 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
25 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2121 |
0 |
0 |
T73 |
32181 |
11 |
0 |
0 |
T75 |
2489 |
7 |
0 |
0 |
T79 |
93031 |
78 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
57 |
0 |
0 |
T97 |
40258 |
267 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T117 |
10163 |
18 |
0 |
0 |
T127 |
0 |
37 |
0 |
0 |
T128 |
0 |
98 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
21 |
0 |
0 |
T142 |
0 |
6 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2225 |
0 |
0 |
T73 |
32181 |
17 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
69 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
70 |
0 |
0 |
T97 |
40258 |
234 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
1 |
0 |
0 |
T117 |
10163 |
15 |
0 |
0 |
T127 |
0 |
27 |
0 |
0 |
T128 |
0 |
134 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
28 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2974 |
0 |
0 |
T73 |
32181 |
40 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
127 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T87 |
0 |
3 |
0 |
0 |
T88 |
0 |
8 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
119 |
0 |
0 |
T97 |
40258 |
251 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
17 |
0 |
0 |
T117 |
10163 |
22 |
0 |
0 |
T127 |
0 |
38 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2223 |
0 |
0 |
T73 |
32181 |
22 |
0 |
0 |
T74 |
9978 |
8 |
0 |
0 |
T75 |
2489 |
3 |
0 |
0 |
T79 |
93031 |
75 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
70 |
0 |
0 |
T97 |
40258 |
287 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
5 |
0 |
0 |
T117 |
10163 |
15 |
0 |
0 |
T127 |
0 |
37 |
0 |
0 |
T128 |
0 |
130 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
3747 |
0 |
0 |
T73 |
32181 |
65 |
0 |
0 |
T79 |
93031 |
205 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
65780 |
306 |
0 |
0 |
T97 |
40258 |
263 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
15 |
0 |
0 |
T117 |
10163 |
46 |
0 |
0 |
T127 |
0 |
83 |
0 |
0 |
T128 |
0 |
434 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
112 |
0 |
0 |
T142 |
0 |
10 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2403 |
0 |
0 |
T73 |
32181 |
30 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
93 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
118 |
0 |
0 |
T97 |
40258 |
242 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
4 |
0 |
0 |
T111 |
0 |
4 |
0 |
0 |
T117 |
10163 |
19 |
0 |
0 |
T127 |
0 |
34 |
0 |
0 |
T128 |
0 |
201 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
1984 |
0 |
0 |
T73 |
32181 |
27 |
0 |
0 |
T75 |
2489 |
4 |
0 |
0 |
T79 |
93031 |
59 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
73 |
0 |
0 |
T97 |
40258 |
256 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
2 |
0 |
0 |
T117 |
10163 |
19 |
0 |
0 |
T127 |
0 |
13 |
0 |
0 |
T128 |
0 |
129 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
27 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2106 |
0 |
0 |
T73 |
32181 |
16 |
0 |
0 |
T74 |
9978 |
7 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
94 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
74 |
0 |
0 |
T97 |
40258 |
241 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
2 |
0 |
0 |
T117 |
10163 |
8 |
0 |
0 |
T127 |
0 |
22 |
0 |
0 |
T128 |
0 |
87 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2160 |
0 |
0 |
T73 |
32181 |
15 |
0 |
0 |
T75 |
2489 |
9 |
0 |
0 |
T79 |
93031 |
83 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
98 |
0 |
0 |
T97 |
40258 |
263 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
2 |
0 |
0 |
T117 |
10163 |
14 |
0 |
0 |
T127 |
0 |
30 |
0 |
0 |
T128 |
0 |
93 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
46 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2086 |
0 |
0 |
T73 |
32181 |
24 |
0 |
0 |
T75 |
2489 |
4 |
0 |
0 |
T79 |
93031 |
58 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
76 |
0 |
0 |
T97 |
40258 |
272 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T111 |
0 |
6 |
0 |
0 |
T117 |
10163 |
13 |
0 |
0 |
T127 |
0 |
19 |
0 |
0 |
T128 |
0 |
102 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
34 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2140 |
0 |
0 |
T73 |
32181 |
24 |
0 |
0 |
T75 |
2489 |
4 |
0 |
0 |
T79 |
93031 |
64 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
55 |
0 |
0 |
T97 |
40258 |
260 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
6 |
0 |
0 |
T111 |
0 |
4 |
0 |
0 |
T117 |
10163 |
13 |
0 |
0 |
T127 |
0 |
31 |
0 |
0 |
T128 |
0 |
134 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
641010073 |
2055 |
0 |
0 |
T73 |
32181 |
25 |
0 |
0 |
T75 |
2489 |
1 |
0 |
0 |
T79 |
93031 |
47 |
0 |
0 |
T83 |
4079 |
0 |
0 |
0 |
T90 |
1578 |
0 |
0 |
0 |
T95 |
0 |
64 |
0 |
0 |
T97 |
40258 |
268 |
0 |
0 |
T99 |
31900 |
0 |
0 |
0 |
T100 |
1321 |
0 |
0 |
0 |
T104 |
0 |
7 |
0 |
0 |
T117 |
10163 |
10 |
0 |
0 |
T127 |
0 |
29 |
0 |
0 |
T128 |
0 |
122 |
0 |
0 |
T129 |
6114 |
0 |
0 |
0 |
T130 |
0 |
26 |
0 |
0 |