Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.64	95.11	86.84	96.92		88.89	95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.64	95.11	86.84	96.92		88.89	95.45

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.64	95.11	86.84	96.92		88.89	95.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.85	98.50	94.92	98.60	89.36	97.30	96.40

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_edge_0	100.00	100.00	100.00			100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	96.74	100.00	87.80		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	84.73	100.00	71.43			67.50	100.00
u_passthrough	89.66	92.75	89.22		75.00	91.35	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	93.14	97.16	93.19		87.50	87.82	100.00
u_reg	99.61	99.49	99.26	100.00		99.28	100.00
u_s2p	86.75	100.00	78.57			68.42	100.00
u_scanmode_sync	100.00						100.00
u_sck_csb_edge	94.44	100.00	83.33			100.00
u_sck_tog_edge	100.00	100.00	100.00			100.00
u_spi_tpm	96.43	99.76	93.53		91.67	97.18	100.00
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	95.45	100.00	81.82			100.00	100.00
u_spid_status	96.26	100.00	89.13			95.89	100.00
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	87.03	100.00	70.73			96.43	80.95
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.12	81.67	59.07			62.50	81.25
u_tlul2sram_ingress	86.46	87.92	73.84			84.09	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_upload	91.14	98.60	73.71		100.00	94.12	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		225	214	95.11
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	367	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
ALWAYS	502	4	4	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
ALWAYS	529	0	0
ALWAYS	529	2	2	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
ALWAYS	543	0	0
ALWAYS	543	12	12	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	608	1	1	100.00
CONT_ASSIGN	609	1	1	100.00
ALWAYS	762	6	6	100.00
ALWAYS	788	4	4	100.00
CONT_ASSIGN	807	1	1	100.00
ALWAYS	829	3	3	100.00
ALWAYS	835	8	8	100.00
ALWAYS	873	28	28	100.00
CONT_ASSIGN	952	1	1	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	996	5	3	60.00
ALWAYS	1007	13	13	100.00
ALWAYS	1044	3	3	100.00
CONT_ASSIGN	1178	1	1	100.00
CONT_ASSIGN	1181	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1186	1	1	100.00
CONT_ASSIGN	1187	1	1	100.00
CONT_ASSIGN	1189	1	1	100.00
CONT_ASSIGN	1190	1	1	100.00
CONT_ASSIGN	1193	1	1	100.00
CONT_ASSIGN	1239	1	0	0.00
CONT_ASSIGN	1269	1	0	0.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1353	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1355	1	1	100.00
CONT_ASSIGN	1356	1	1	100.00
CONT_ASSIGN	1358	1	1	100.00
CONT_ASSIGN	1362	1	1	100.00
CONT_ASSIGN	1369	1	1	100.00
CONT_ASSIGN	1370	1	1	100.00
CONT_ASSIGN	1372	1	1	100.00
CONT_ASSIGN	1376	1	1	100.00
CONT_ASSIGN	1379	1	1	100.00
CONT_ASSIGN	1382	1	1	100.00
CONT_ASSIGN	1385	1	1	100.00
CONT_ASSIGN	1388	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1438	1	1	100.00
CONT_ASSIGN	1536	1	0	0.00
CONT_ASSIGN	1544	1	1	100.00
CONT_ASSIGN	1545	1	1	100.00
CONT_ASSIGN	1546	1	1	100.00
CONT_ASSIGN	1547	1	1	100.00
CONT_ASSIGN	1548	1	1	100.00
CONT_ASSIGN	1551	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1565	1	1	100.00
CONT_ASSIGN	1566	1	1	100.00
CONT_ASSIGN	1567	1	1	100.00
CONT_ASSIGN	1568	1	1	100.00
CONT_ASSIGN	1570	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1576	1	1	100.00
CONT_ASSIGN	1577	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1586	1	1	100.00
CONT_ASSIGN	1588	1	1	100.00
CONT_ASSIGN	1592	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1595	1	1	100.00
CONT_ASSIGN	1606	1	1	100.00
CONT_ASSIGN	1607	1	1	100.00
CONT_ASSIGN	1608	1	1	100.00
CONT_ASSIGN	1609	1	1	100.00
CONT_ASSIGN	1662	1	1	100.00
CONT_ASSIGN	1664	1	1	100.00
ALWAYS	1669	4	4	100.00
ALWAYS	1678	0	0
ALWAYS	1678	9	9	100.00
CONT_ASSIGN	1695	1	1	100.00
CONT_ASSIGN	1695	1	1	100.00
CONT_ASSIGN	1695	1	1	100.00
CONT_ASSIGN	1695	1	1	100.00
CONT_ASSIGN	1696	1	1	100.00
CONT_ASSIGN	1696	1	1	100.00
CONT_ASSIGN	1696	1	0	0.00
CONT_ASSIGN	1696	1	0	0.00
CONT_ASSIGN	1697	1	1	100.00
CONT_ASSIGN	1697	1	1	100.00
CONT_ASSIGN	1697	1	0	0.00
CONT_ASSIGN	1697	1	0	0.00
CONT_ASSIGN	1698	1	1	100.00
CONT_ASSIGN	1698	1	1	100.00
CONT_ASSIGN	1698	1	0	0.00
CONT_ASSIGN	1698	1	0	0.00
CONT_ASSIGN	1700	1	1	100.00
CONT_ASSIGN	1700	1	1	100.00
CONT_ASSIGN	1700	1	1	100.00
CONT_ASSIGN	1700	1	1	100.00
CONT_ASSIGN	1701	1	1	100.00
CONT_ASSIGN	1701	1	1	100.00
CONT_ASSIGN	1701	1	1	100.00
CONT_ASSIGN	1701	1	1	100.00
CONT_ASSIGN	1702	1	1	100.00
CONT_ASSIGN	1702	1	1	100.00
CONT_ASSIGN	1702	1	1	100.00
CONT_ASSIGN	1702	1	1	100.00
CONT_ASSIGN	1745	1	1	100.00
CONT_ASSIGN	1746	1	1	100.00
CONT_ASSIGN	1747	1	1	100.00
CONT_ASSIGN	1748	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1753	1	1	100.00
CONT_ASSIGN	1809	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
175	1	1
307	1	1
366	1	1
367	1	1
370	1	1
371	1	1
373	1	1
388	1	1
490	1	1
497	1	1
499	1	1
502	1	1
503	1	1
504	1	1
505	1	1
			MISSING_ELSE
510	1	1
516	1	1
519	1	1
520	1	1
524	1	1
529	1	1
530	1	1
534	1	1
535	1	1
543	1	1
544	1	1
563	1	1
564	1	1
568	1	1
569	1	1
571	1	1
572	1	1
574	1	1
575	1	1
577	1	1
578	1	1
607	1	1
608	1	1
609	1	1
762	2	2
763	1	1
764	1	1
765	1	1
766	1	1
			MISSING_ELSE
788	2	2
789	1	1
790	1	1
			MISSING_ELSE
807	1	1
829	2	2
830	1	1
835	1	1
837	1	1
838	1	1
845	1	1
849	1	1
850	1	1
854	1	1
855	1	1
873	1	1
874	1	1
875	1	1
876	1	1
878	1	1
880	1	1
886	1	1
889	1	1
890	1	1
892	1	1
894	1	1
896	1	1
900	1	1
902	1	1
903	1	1
904	1	1
907	1	1
909	1	1
910	1	1
911	1	1
916	1	1
918	1	1
919	1	1
920	1	1
924	1	1
926	1	1
927	1	1
928	1	1
952	1	1
953	1	1
996	1	1
997	0	1
998	0	1
1000	1	1
1001	1	1
1007	1	1
1008	1	1
1010	1	1
1012	1	1
1013	1	1
1017	1	1
1019	1	1
1020	1	1
1024	1	1
1025	1	1
1026	1	1
1028	1	1
1029	1	1
1044	2	2
1045	1	1
1178	1	1
1181	1	1
1185	1	1
1186	1	1
1187	1	1
1189	1	1
1190	1	1
1193	1	1
1239	0	1
1269	0	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1356	1	1
1358	1	1
1362	1	1
1369	1	1
1370	1	1
1372	1	1
1376	1	1
1379	1	1
1382	1	1
1385	1	1
1388	1	1
1391	1	1
1398	1	1
1399	1	1
1438	1	1
1536	0	1
1544	1	1
1545	1	1
1546	1	1
1547	1	1
1548	1	1
1551	1	1
1560	5	5
1563	1	1
1564	1	1
1565	1	1
1566	1	1
1567	1	1
1568	1	1
1570	1	1
1574	1	1
1576	1	1
1577	1	1
1584	1	1
1586	1	1
1588	1	1
1592	1	1
1594	1	1
1595	1	1
1606	1	1
1607	1	1
1608	1	1
1609	1	1
1662	1	1
1664	1	1
1669	1	1
1670	1	1
1671	1	1
1672	1	1
			MISSING_ELSE
1678	1	1
1679	1	1
1681	1	1
1684	1	1
1685	1	1
1686	1	1
1687	1	1
1689	1	1
1690	1	1
1695	4	4
1696	2	4
1697	2	4
1698	2	4
1700	4	4
1701	4	4
1702	4	4
1745	1	1
1746	1	1
1747	1	1
1748	1	1
1749	1	1
1751	1	1
1752	1	1
1753	1	1
1809	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	38	33	86.84
Logical	38	33	86.84
Non-Logical	0	0
Event	0	0

 LINE       175
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T11

 LINE       662
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       673
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       807
 EXPRESSION (spi_clk_pos_edge | spi_clk_neg_edge)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7

 LINE       859
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T11

 LINE       1010
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T41
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       1178
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T6,T7

 LINE       1189
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T13

 LINE       1190
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T13

 LINE       1398
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T13

 LINE       1399
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T13

 LINE       1671
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1671
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1671
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1809
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T42,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T42,T43

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	57	52	91.23
Total Bits	454	440	96.92
Total Bits 0->1	227	220	96.92
Total Bits 1->0	227	220	96.92

Ports	57	52	91.23
Port Bits	454	440	96.92
Port Bits 0->1	227	220	96.92
Port Bits 1->0	227	220	96.92

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T22,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T12,T13	Yes	T1,T12,T13	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T25,T44	Yes	T24,T25,T44	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T5	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T42,T43	Yes	T2,T42,T43	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T42,T43	Yes	T2,T42,T43	OUTPUT
cio_sck_i	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
cio_csb_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
cio_sd_o[3:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
cio_tpm_csb_i	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T5,*T7,*T13	Yes	T5,T7,T13	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T7,T28,T34	Yes	T5,T7,T13	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T22,T31,T45	Yes	T22,T31,T45	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T22,T30,T31	Yes	T22,T30,T31	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T4,T46,T47	Yes	T4,T46,T47	INPUT
sck_monitor_o	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		36	32	88.89
IF	502	3	3	100.00
IF	762	4	4	100.00
IF	788	3	3	100.00
IF	829	2	2	100.00
CASE	845	4	4	100.00
CASE	886	7	5	71.43
IF	996	2	1	50.00
IF	1010	5	4	80.00
IF	1044	2	2	100.00
IF	1671	2	2	100.00
IF	1681	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	502	if ((!rst_ni))
-2-:	504	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	762	if ((!tpm_rst_n))
-2-:	763	if (spi_clk_csb_rst_pulse)
-3-:	765	if (spi_clk_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T7
0	0	1	Covered	T1,T6,T7
0	0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	789	if (sys_csb_pos_pulse_stretch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	829	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	845	case (cmd_dp_sel)
-2-:	859	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T3,T5,T6
DpUpload	-	Covered	T6,T7,T11
default	1	Covered	T6,T7,T11
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	886	case (spi_mode)
-2-:	892	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T3,T5,T6
FlashMode PassThrough	DpReadStatus	Covered	T6,T7,T17
FlashMode PassThrough	DpReadJEDEC	Covered	T6,T7,T11
FlashMode PassThrough	DpUpload	Covered	T6,T7,T11
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	996	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1010	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1017	case (spi_mode)
-3-:	1024	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T7
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T7,T14,T17
0	PassThrough	0	Covered	T5,T7,T13
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1044	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	1671	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1681	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	574941707	574858285	0	0
CioSdoEnOKnown	574941707	574858285	0	0
CioSdoEnOffWhenInactive	574941707	574858285	0	0
CsPulseWidth_A	574941707	476619574	0	0
FpvSecCmRegWeOnehotCheck_A	574941707	80	0	0
InterceptLevel_M	183605490	0	0	0
IntrReadbufFlipOKnown	574941707	574858285	0	0
IntrReadbufWatermarkOKnown	574941707	574858285	0	0
IntrTpmHeaderNotEmptyOKnown	574941707	574858285	0	0
IntrUploadCmdfifoNotEmptyOKnown	574941707	574858285	0	0
IntrUploadPayloadNotEmptyOKnown	574941707	574858285	0	0
IntrUploadPayloadOverflowOKnown	574941707	574858285	0	0
PayloadStartIdxWidthMatch_A	939	939	0	0
SpiModeKnown_A	574941707	574858285	0	0
TpmEnableWhenTpmCsbIdle_M	574941707	355	0	0
TpmRdfifoNotFull_A	574941707	301593	0	0
TpmWrPtrMatch_A	939	939	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	574941707	2234384	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	574941707	57034	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	574941707	2611	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	574941707	1965	0	0
scanmodeKnown	574941707	574941707	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

CsPulseWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	476619574	0	0
T1	11786	1264	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	131230	0	0
T7	283083	273800	0	0
T8	1029	773	0	0
T9	986066	56742	0	0
T10	366182	59558	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	80	0	0
T37	417412	0	0	0
T45	4781	0	0	0
T47	816	0	0	0
T48	6890	20	0	0
T49	0	10	0	0
T50	0	10	0	0
T51	0	30	0	0
T52	0	10	0	0
T53	1322	0	0	0
T54	2313	0	0	0
T55	32965	0	0	0
T56	303453	0	0	0
T57	575813	0	0	0
T58	44026	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	183605490	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574858285	0	0
T1	11786	11698	0	0
T2	1175	1116	0	0
T3	99011	98940	0	0
T4	1201	1110	0	0
T5	724174	724086	0	0
T6	257954	257948	0	0
T7	283083	283046	0	0
T8	1029	935	0	0
T9	986066	985973	0	0
T10	366182	366101	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	355	0	0
T1	11786	1	0	0
T2	1175	0	0	0
T3	99011	0	0	0
T4	1201	0	0	0
T5	724174	0	0	0
T6	257954	1	0	0
T7	283083	2	0	0
T8	1029	0	0	0
T9	986066	1	0	0
T10	366182	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0

TpmRdfifoNotFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	301593	0	0
T1	11786	55	0	0
T2	1175	0	0	0
T3	99011	0	0	0
T4	1201	0	0	0
T5	724174	0	0	0
T6	257954	2462	0	0
T7	283083	456	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	1534	0	0
T11	0	934	0	0
T18	0	1047	0	0
T21	0	212	0	0
T59	0	4	0	0
T60	0	115	0	0
T61	0	2081	0	0

TpmWrPtrMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	2234384	0	0
T3	99011	832	0	0
T4	1201	0	0	0
T5	724174	832	0	0
T6	257954	3328	0	0
T7	283083	27456	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T12	55763	832	0	0
T13	12915	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	57034	0	0
T6	257954	64	0	0
T7	283083	1102	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	352	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	960	0	0
T23	0	481	0	0
T27	0	64	0	0
T28	0	130	0	0
T29	0	97	0	0
T30	0	288	0	0
T31	0	1256	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	2611	0	0
T6	257954	2	0	0
T7	283083	45	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	20	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	26	0	0
T23	0	11	0	0
T28	0	6	0	0
T29	0	7	0	0
T30	0	10	0	0
T31	0	52	0	0
T34	0	2	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	1965	0	0
T6	257954	1	0	0
T7	283083	27	0	0
T8	1029	0	0	0
T9	986066	0	0	0
T10	366182	0	0	0
T11	0	15	0	0
T12	55763	0	0	0
T13	12915	0	0	0
T14	180624	0	0	0
T15	15846	0	0	0
T16	13719	0	0	0
T22	0	18	0	0
T23	0	10	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	5	0	0
T30	0	7	0	0
T31	0	37	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	574941707	574941707	0	0
T1	11786	11786	0	0
T2	1175	1175	0	0
T3	99011	99011	0	0
T4	1201	1201	0	0
T5	724174	724174	0	0
T6	257954	257954	0	0
T7	283083	283083	0	0
T8	1029	1029	0	0
T9	986066	986066	0	0
T10	366182	366182	0	0