Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
3812 |
0 |
0 |
T44 |
33408 |
1 |
0 |
0 |
T70 |
7539 |
145 |
0 |
0 |
T72 |
0 |
194 |
0 |
0 |
T73 |
0 |
236 |
0 |
0 |
T74 |
0 |
1 |
0 |
0 |
T75 |
0 |
1 |
0 |
0 |
T76 |
0 |
3 |
0 |
0 |
T81 |
0 |
210 |
0 |
0 |
T82 |
0 |
113 |
0 |
0 |
T92 |
1196 |
0 |
0 |
0 |
T93 |
816 |
0 |
0 |
0 |
T94 |
3078 |
0 |
0 |
0 |
T95 |
241105 |
0 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
0 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T135 |
0 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1989 |
0 |
0 |
T44 |
33408 |
43 |
0 |
0 |
T76 |
0 |
65 |
0 |
0 |
T88 |
0 |
110 |
0 |
0 |
T95 |
241105 |
404 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
15 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
21 |
0 |
0 |
T111 |
0 |
223 |
0 |
0 |
T112 |
0 |
9 |
0 |
0 |
T136 |
0 |
9 |
0 |
0 |
T137 |
0 |
246 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1973 |
0 |
0 |
T44 |
33408 |
47 |
0 |
0 |
T76 |
0 |
90 |
0 |
0 |
T88 |
0 |
108 |
0 |
0 |
T95 |
241105 |
415 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
11 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
12 |
0 |
0 |
T111 |
0 |
261 |
0 |
0 |
T112 |
0 |
6 |
0 |
0 |
T136 |
0 |
9 |
0 |
0 |
T137 |
0 |
187 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2559 |
0 |
0 |
T44 |
33408 |
95 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T76 |
0 |
161 |
0 |
0 |
T88 |
0 |
188 |
0 |
0 |
T95 |
241105 |
398 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
11 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
8 |
0 |
0 |
T110 |
0 |
31 |
0 |
0 |
T136 |
0 |
15 |
0 |
0 |
T137 |
0 |
210 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
11394 |
0 |
0 |
T44 |
33408 |
493 |
0 |
0 |
T71 |
0 |
5 |
0 |
0 |
T76 |
0 |
1582 |
0 |
0 |
T88 |
0 |
1738 |
0 |
0 |
T95 |
241105 |
392 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
5 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
58 |
0 |
0 |
T110 |
0 |
116 |
0 |
0 |
T136 |
0 |
22 |
0 |
0 |
T137 |
0 |
198 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
11885 |
0 |
0 |
T44 |
33408 |
633 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T76 |
0 |
1418 |
0 |
0 |
T88 |
0 |
2157 |
0 |
0 |
T95 |
241105 |
418 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
0 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
60 |
0 |
0 |
T110 |
0 |
332 |
0 |
0 |
T111 |
0 |
236 |
0 |
0 |
T136 |
0 |
19 |
0 |
0 |
T137 |
0 |
246 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
10868 |
0 |
0 |
T44 |
33408 |
441 |
0 |
0 |
T76 |
0 |
757 |
0 |
0 |
T88 |
0 |
2107 |
0 |
0 |
T95 |
241105 |
415 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
142 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
136 |
0 |
0 |
T111 |
0 |
222 |
0 |
0 |
T136 |
0 |
13 |
0 |
0 |
T137 |
0 |
200 |
0 |
0 |
T138 |
0 |
1161 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
11321 |
0 |
0 |
T44 |
33408 |
657 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T76 |
0 |
1304 |
0 |
0 |
T88 |
0 |
1718 |
0 |
0 |
T95 |
241105 |
451 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
10 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
53 |
0 |
0 |
T110 |
0 |
232 |
0 |
0 |
T136 |
0 |
10 |
0 |
0 |
T137 |
0 |
224 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
10690 |
0 |
0 |
T44 |
33408 |
707 |
0 |
0 |
T76 |
0 |
1399 |
0 |
0 |
T88 |
0 |
1848 |
0 |
0 |
T95 |
241105 |
389 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
1 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
2 |
0 |
0 |
T110 |
0 |
91 |
0 |
0 |
T111 |
0 |
227 |
0 |
0 |
T136 |
0 |
14 |
0 |
0 |
T137 |
0 |
211 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
10454 |
0 |
0 |
T44 |
33408 |
707 |
0 |
0 |
T76 |
0 |
1196 |
0 |
0 |
T88 |
0 |
1760 |
0 |
0 |
T95 |
241105 |
410 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
107 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
47 |
0 |
0 |
T110 |
0 |
8 |
0 |
0 |
T111 |
0 |
260 |
0 |
0 |
T136 |
0 |
18 |
0 |
0 |
T137 |
0 |
213 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
12107 |
0 |
0 |
T44 |
33408 |
295 |
0 |
0 |
T76 |
0 |
1686 |
0 |
0 |
T88 |
0 |
1701 |
0 |
0 |
T95 |
241105 |
435 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
130 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
8 |
0 |
0 |
T110 |
0 |
114 |
0 |
0 |
T111 |
0 |
194 |
0 |
0 |
T136 |
0 |
8 |
0 |
0 |
T137 |
0 |
186 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
11810 |
0 |
0 |
T44 |
33408 |
672 |
0 |
0 |
T76 |
0 |
1120 |
0 |
0 |
T88 |
0 |
1825 |
0 |
0 |
T95 |
241105 |
383 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
111 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
48 |
0 |
0 |
T110 |
0 |
362 |
0 |
0 |
T111 |
0 |
213 |
0 |
0 |
T136 |
0 |
12 |
0 |
0 |
T137 |
0 |
235 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
4740 |
0 |
0 |
T44 |
33408 |
201 |
0 |
0 |
T76 |
0 |
335 |
0 |
0 |
T88 |
0 |
609 |
0 |
0 |
T95 |
241105 |
402 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
52 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
7 |
0 |
0 |
T110 |
0 |
158 |
0 |
0 |
T111 |
0 |
202 |
0 |
0 |
T136 |
0 |
9 |
0 |
0 |
T137 |
0 |
208 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5558 |
0 |
0 |
T44 |
33408 |
412 |
0 |
0 |
T76 |
0 |
432 |
0 |
0 |
T88 |
0 |
891 |
0 |
0 |
T95 |
241105 |
366 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
43 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
13 |
0 |
0 |
T111 |
0 |
247 |
0 |
0 |
T112 |
0 |
1 |
0 |
0 |
T136 |
0 |
11 |
0 |
0 |
T137 |
0 |
230 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5864 |
0 |
0 |
T44 |
33408 |
273 |
0 |
0 |
T76 |
0 |
398 |
0 |
0 |
T88 |
0 |
957 |
0 |
0 |
T95 |
241105 |
378 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
77 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
6 |
0 |
0 |
T110 |
0 |
135 |
0 |
0 |
T111 |
0 |
227 |
0 |
0 |
T136 |
0 |
9 |
0 |
0 |
T137 |
0 |
247 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5528 |
0 |
0 |
T44 |
33408 |
233 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T76 |
0 |
721 |
0 |
0 |
T88 |
0 |
725 |
0 |
0 |
T95 |
241105 |
399 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
126 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
5 |
0 |
0 |
T110 |
0 |
15 |
0 |
0 |
T136 |
0 |
5 |
0 |
0 |
T137 |
0 |
238 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5512 |
0 |
0 |
T44 |
33408 |
329 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T76 |
0 |
350 |
0 |
0 |
T88 |
0 |
1030 |
0 |
0 |
T95 |
241105 |
423 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
47 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
33 |
0 |
0 |
T110 |
0 |
137 |
0 |
0 |
T136 |
0 |
10 |
0 |
0 |
T137 |
0 |
227 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
6317 |
0 |
0 |
T44 |
33408 |
194 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T76 |
0 |
733 |
0 |
0 |
T88 |
0 |
795 |
0 |
0 |
T95 |
241105 |
476 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
51 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
38 |
0 |
0 |
T110 |
0 |
78 |
0 |
0 |
T136 |
0 |
21 |
0 |
0 |
T137 |
0 |
245 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
6064 |
0 |
0 |
T44 |
33408 |
325 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T76 |
0 |
658 |
0 |
0 |
T88 |
0 |
902 |
0 |
0 |
T95 |
241105 |
416 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
7 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
23 |
0 |
0 |
T110 |
0 |
114 |
0 |
0 |
T136 |
0 |
22 |
0 |
0 |
T137 |
0 |
222 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5752 |
0 |
0 |
T44 |
33408 |
320 |
0 |
0 |
T71 |
0 |
6 |
0 |
0 |
T76 |
0 |
552 |
0 |
0 |
T88 |
0 |
808 |
0 |
0 |
T95 |
241105 |
467 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
73 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
21 |
0 |
0 |
T110 |
0 |
57 |
0 |
0 |
T136 |
0 |
13 |
0 |
0 |
T137 |
0 |
272 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5570 |
0 |
0 |
T44 |
33408 |
229 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T76 |
0 |
535 |
0 |
0 |
T88 |
0 |
997 |
0 |
0 |
T95 |
241105 |
382 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
6 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
91 |
0 |
0 |
T111 |
0 |
258 |
0 |
0 |
T136 |
0 |
11 |
0 |
0 |
T137 |
0 |
226 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5681 |
0 |
0 |
T44 |
33408 |
384 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T76 |
0 |
585 |
0 |
0 |
T88 |
0 |
727 |
0 |
0 |
T95 |
241105 |
392 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
42 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
21 |
0 |
0 |
T110 |
0 |
4 |
0 |
0 |
T136 |
0 |
6 |
0 |
0 |
T137 |
0 |
240 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5963 |
0 |
0 |
T44 |
33408 |
146 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T76 |
0 |
645 |
0 |
0 |
T88 |
0 |
829 |
0 |
0 |
T95 |
241105 |
389 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
44 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
5 |
0 |
0 |
T111 |
0 |
230 |
0 |
0 |
T136 |
0 |
13 |
0 |
0 |
T137 |
0 |
218 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5724 |
0 |
0 |
T44 |
33408 |
356 |
0 |
0 |
T71 |
0 |
7 |
0 |
0 |
T76 |
0 |
488 |
0 |
0 |
T88 |
0 |
901 |
0 |
0 |
T95 |
241105 |
462 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
11 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
1 |
0 |
0 |
T110 |
0 |
140 |
0 |
0 |
T136 |
0 |
5 |
0 |
0 |
T137 |
0 |
201 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5346 |
0 |
0 |
T44 |
33408 |
139 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T76 |
0 |
573 |
0 |
0 |
T88 |
0 |
729 |
0 |
0 |
T95 |
241105 |
322 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
102 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
3 |
0 |
0 |
T111 |
0 |
184 |
0 |
0 |
T136 |
0 |
16 |
0 |
0 |
T137 |
0 |
236 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5704 |
0 |
0 |
T44 |
33408 |
245 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T76 |
0 |
561 |
0 |
0 |
T81 |
0 |
4 |
0 |
0 |
T95 |
241105 |
384 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
99 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
3 |
0 |
0 |
T110 |
0 |
53 |
0 |
0 |
T136 |
0 |
4 |
0 |
0 |
T137 |
0 |
233 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
6339 |
0 |
0 |
T44 |
33408 |
302 |
0 |
0 |
T76 |
0 |
721 |
0 |
0 |
T88 |
0 |
925 |
0 |
0 |
T95 |
241105 |
368 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
102 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
110 |
0 |
0 |
T111 |
0 |
219 |
0 |
0 |
T112 |
0 |
1 |
0 |
0 |
T136 |
0 |
19 |
0 |
0 |
T137 |
0 |
216 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5848 |
0 |
0 |
T44 |
33408 |
227 |
0 |
0 |
T76 |
0 |
645 |
0 |
0 |
T88 |
0 |
695 |
0 |
0 |
T95 |
241105 |
442 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
40 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
122 |
0 |
0 |
T111 |
0 |
163 |
0 |
0 |
T112 |
0 |
4 |
0 |
0 |
T136 |
0 |
13 |
0 |
0 |
T137 |
0 |
223 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5616 |
0 |
0 |
T44 |
33408 |
376 |
0 |
0 |
T71 |
0 |
7 |
0 |
0 |
T76 |
0 |
367 |
0 |
0 |
T88 |
0 |
976 |
0 |
0 |
T95 |
241105 |
365 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
42 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
25 |
0 |
0 |
T110 |
0 |
115 |
0 |
0 |
T136 |
0 |
9 |
0 |
0 |
T137 |
0 |
252 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5133 |
0 |
0 |
T44 |
33408 |
288 |
0 |
0 |
T71 |
0 |
8 |
0 |
0 |
T76 |
0 |
398 |
0 |
0 |
T88 |
0 |
868 |
0 |
0 |
T95 |
241105 |
410 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
46 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
93 |
0 |
0 |
T111 |
0 |
229 |
0 |
0 |
T136 |
0 |
16 |
0 |
0 |
T137 |
0 |
219 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5454 |
0 |
0 |
T44 |
33408 |
292 |
0 |
0 |
T71 |
0 |
13 |
0 |
0 |
T76 |
0 |
452 |
0 |
0 |
T88 |
0 |
967 |
0 |
0 |
T95 |
241105 |
434 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
6 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
62 |
0 |
0 |
T111 |
0 |
219 |
0 |
0 |
T136 |
0 |
20 |
0 |
0 |
T137 |
0 |
186 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5436 |
0 |
0 |
T44 |
33408 |
220 |
0 |
0 |
T76 |
0 |
491 |
0 |
0 |
T88 |
0 |
944 |
0 |
0 |
T95 |
241105 |
452 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
57 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
69 |
0 |
0 |
T111 |
0 |
229 |
0 |
0 |
T112 |
0 |
8 |
0 |
0 |
T136 |
0 |
15 |
0 |
0 |
T137 |
0 |
221 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5854 |
0 |
0 |
T44 |
33408 |
238 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T76 |
0 |
476 |
0 |
0 |
T88 |
0 |
754 |
0 |
0 |
T95 |
241105 |
388 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
89 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
26 |
0 |
0 |
T110 |
0 |
68 |
0 |
0 |
T136 |
0 |
6 |
0 |
0 |
T137 |
0 |
271 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
6049 |
0 |
0 |
T44 |
33408 |
304 |
0 |
0 |
T71 |
0 |
10 |
0 |
0 |
T76 |
0 |
556 |
0 |
0 |
T88 |
0 |
870 |
0 |
0 |
T95 |
241105 |
325 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
85 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
9 |
0 |
0 |
T111 |
0 |
211 |
0 |
0 |
T136 |
0 |
16 |
0 |
0 |
T137 |
0 |
212 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5792 |
0 |
0 |
T44 |
33408 |
171 |
0 |
0 |
T76 |
0 |
727 |
0 |
0 |
T88 |
0 |
960 |
0 |
0 |
T95 |
241105 |
392 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
46 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
23 |
0 |
0 |
T110 |
0 |
134 |
0 |
0 |
T111 |
0 |
177 |
0 |
0 |
T136 |
0 |
7 |
0 |
0 |
T137 |
0 |
217 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
5650 |
0 |
0 |
T44 |
33408 |
222 |
0 |
0 |
T76 |
0 |
583 |
0 |
0 |
T88 |
0 |
772 |
0 |
0 |
T95 |
241105 |
407 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
10 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
42 |
0 |
0 |
T110 |
0 |
90 |
0 |
0 |
T111 |
0 |
214 |
0 |
0 |
T136 |
0 |
13 |
0 |
0 |
T137 |
0 |
247 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2161 |
0 |
0 |
T44 |
33408 |
39 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T76 |
0 |
107 |
0 |
0 |
T88 |
0 |
159 |
0 |
0 |
T95 |
241105 |
402 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
20 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
7 |
0 |
0 |
T111 |
0 |
195 |
0 |
0 |
T136 |
0 |
8 |
0 |
0 |
T137 |
0 |
213 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2301 |
0 |
0 |
T44 |
33408 |
68 |
0 |
0 |
T76 |
0 |
107 |
0 |
0 |
T88 |
0 |
148 |
0 |
0 |
T95 |
241105 |
361 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
9 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
11 |
0 |
0 |
T111 |
0 |
217 |
0 |
0 |
T112 |
0 |
9 |
0 |
0 |
T136 |
0 |
18 |
0 |
0 |
T137 |
0 |
210 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2238 |
0 |
0 |
T44 |
33408 |
47 |
0 |
0 |
T71 |
0 |
6 |
0 |
0 |
T76 |
0 |
84 |
0 |
0 |
T88 |
0 |
168 |
0 |
0 |
T95 |
241105 |
386 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
12 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
2 |
0 |
0 |
T110 |
0 |
20 |
0 |
0 |
T136 |
0 |
22 |
0 |
0 |
T137 |
0 |
205 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2192 |
0 |
0 |
T44 |
33408 |
77 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T76 |
0 |
86 |
0 |
0 |
T88 |
0 |
180 |
0 |
0 |
T95 |
241105 |
392 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
4 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
4 |
0 |
0 |
T110 |
0 |
19 |
0 |
0 |
T136 |
0 |
14 |
0 |
0 |
T137 |
0 |
248 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2946 |
0 |
0 |
T44 |
33408 |
83 |
0 |
0 |
T71 |
0 |
8 |
0 |
0 |
T76 |
0 |
159 |
0 |
0 |
T88 |
0 |
274 |
0 |
0 |
T95 |
241105 |
356 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
24 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
3 |
0 |
0 |
T110 |
0 |
25 |
0 |
0 |
T136 |
0 |
22 |
0 |
0 |
T137 |
0 |
246 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
4530 |
0 |
0 |
T24 |
1215 |
0 |
0 |
0 |
T44 |
0 |
138 |
0 |
0 |
T71 |
0 |
10 |
0 |
0 |
T80 |
691731 |
6 |
0 |
0 |
T92 |
0 |
27 |
0 |
0 |
T95 |
0 |
454 |
0 |
0 |
T98 |
0 |
39 |
0 |
0 |
T109 |
0 |
9 |
0 |
0 |
T110 |
0 |
15 |
0 |
0 |
T120 |
975 |
0 |
0 |
0 |
T121 |
119554 |
0 |
0 |
0 |
T122 |
38572 |
0 |
0 |
0 |
T123 |
19688 |
0 |
0 |
0 |
T130 |
533199 |
0 |
0 |
0 |
T136 |
0 |
3 |
0 |
0 |
T139 |
0 |
13 |
0 |
0 |
T140 |
853556 |
0 |
0 |
0 |
T141 |
192378 |
0 |
0 |
0 |
T142 |
6282 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2230 |
0 |
0 |
T44 |
33408 |
48 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T76 |
0 |
108 |
0 |
0 |
T88 |
0 |
132 |
0 |
0 |
T95 |
241105 |
420 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
16 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
14 |
0 |
0 |
T111 |
0 |
236 |
0 |
0 |
T136 |
0 |
12 |
0 |
0 |
T137 |
0 |
216 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2320 |
0 |
0 |
T44 |
33408 |
51 |
0 |
0 |
T71 |
0 |
6 |
0 |
0 |
T76 |
0 |
112 |
0 |
0 |
T88 |
0 |
202 |
0 |
0 |
T95 |
241105 |
400 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
14 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
6 |
0 |
0 |
T110 |
0 |
27 |
0 |
0 |
T136 |
0 |
12 |
0 |
0 |
T137 |
0 |
200 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2047 |
0 |
0 |
T44 |
33408 |
34 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T76 |
0 |
77 |
0 |
0 |
T88 |
0 |
125 |
0 |
0 |
T95 |
241105 |
431 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
10 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
3 |
0 |
0 |
T110 |
0 |
12 |
0 |
0 |
T136 |
0 |
10 |
0 |
0 |
T137 |
0 |
245 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1958 |
0 |
0 |
T44 |
33408 |
18 |
0 |
0 |
T76 |
0 |
98 |
0 |
0 |
T81 |
0 |
10 |
0 |
0 |
T88 |
0 |
99 |
0 |
0 |
T95 |
241105 |
362 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
7 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
8 |
0 |
0 |
T111 |
0 |
222 |
0 |
0 |
T136 |
0 |
19 |
0 |
0 |
T137 |
0 |
243 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1868 |
0 |
0 |
T44 |
33408 |
26 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T76 |
0 |
61 |
0 |
0 |
T88 |
0 |
89 |
0 |
0 |
T95 |
241105 |
437 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
9 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
13 |
0 |
0 |
T111 |
0 |
200 |
0 |
0 |
T136 |
0 |
17 |
0 |
0 |
T137 |
0 |
196 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1956 |
0 |
0 |
T44 |
33408 |
28 |
0 |
0 |
T76 |
0 |
80 |
0 |
0 |
T88 |
0 |
134 |
0 |
0 |
T95 |
241105 |
467 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
6 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
2 |
0 |
0 |
T111 |
0 |
242 |
0 |
0 |
T112 |
0 |
6 |
0 |
0 |
T136 |
0 |
10 |
0 |
0 |
T137 |
0 |
214 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2942 |
0 |
0 |
T44 |
33408 |
77 |
0 |
0 |
T71 |
0 |
7 |
0 |
0 |
T76 |
0 |
158 |
0 |
0 |
T88 |
0 |
302 |
0 |
0 |
T95 |
241105 |
403 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
2 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
6 |
0 |
0 |
T110 |
0 |
54 |
0 |
0 |
T136 |
0 |
6 |
0 |
0 |
T137 |
0 |
245 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1951 |
0 |
0 |
T44 |
33408 |
31 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T76 |
0 |
84 |
0 |
0 |
T88 |
0 |
122 |
0 |
0 |
T95 |
241105 |
441 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
11 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
9 |
0 |
0 |
T110 |
0 |
11 |
0 |
0 |
T136 |
0 |
7 |
0 |
0 |
T137 |
0 |
235 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
3137 |
0 |
0 |
T44 |
33408 |
132 |
0 |
0 |
T76 |
0 |
122 |
0 |
0 |
T88 |
0 |
349 |
0 |
0 |
T95 |
241105 |
387 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
24 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
6 |
0 |
0 |
T110 |
0 |
10 |
0 |
0 |
T111 |
0 |
241 |
0 |
0 |
T136 |
0 |
10 |
0 |
0 |
T137 |
0 |
210 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2089 |
0 |
0 |
T44 |
33408 |
51 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T76 |
0 |
93 |
0 |
0 |
T88 |
0 |
193 |
0 |
0 |
T95 |
241105 |
337 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
7 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
14 |
0 |
0 |
T111 |
0 |
193 |
0 |
0 |
T136 |
0 |
10 |
0 |
0 |
T137 |
0 |
219 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1855 |
0 |
0 |
T44 |
33408 |
46 |
0 |
0 |
T76 |
0 |
79 |
0 |
0 |
T88 |
0 |
102 |
0 |
0 |
T95 |
241105 |
402 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
5 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
7 |
0 |
0 |
T111 |
0 |
232 |
0 |
0 |
T136 |
0 |
6 |
0 |
0 |
T137 |
0 |
190 |
0 |
0 |
T138 |
0 |
79 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
2046 |
0 |
0 |
T44 |
33408 |
30 |
0 |
0 |
T76 |
0 |
57 |
0 |
0 |
T88 |
0 |
139 |
0 |
0 |
T95 |
241105 |
445 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
11 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
2 |
0 |
0 |
T110 |
0 |
14 |
0 |
0 |
T111 |
0 |
241 |
0 |
0 |
T136 |
0 |
15 |
0 |
0 |
T137 |
0 |
186 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1856 |
0 |
0 |
T44 |
33408 |
40 |
0 |
0 |
T76 |
0 |
40 |
0 |
0 |
T88 |
0 |
106 |
0 |
0 |
T95 |
241105 |
392 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
2 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T111 |
0 |
192 |
0 |
0 |
T136 |
0 |
10 |
0 |
0 |
T137 |
0 |
244 |
0 |
0 |
T138 |
0 |
73 |
0 |
0 |
T143 |
0 |
12 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1883 |
0 |
0 |
T44 |
33408 |
48 |
0 |
0 |
T76 |
0 |
63 |
0 |
0 |
T88 |
0 |
110 |
0 |
0 |
T95 |
241105 |
359 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
5 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
7 |
0 |
0 |
T111 |
0 |
186 |
0 |
0 |
T112 |
0 |
9 |
0 |
0 |
T136 |
0 |
6 |
0 |
0 |
T137 |
0 |
216 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1899 |
0 |
0 |
T44 |
33408 |
44 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T76 |
0 |
78 |
0 |
0 |
T88 |
0 |
114 |
0 |
0 |
T95 |
241105 |
398 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
14 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T110 |
0 |
6 |
0 |
0 |
T111 |
0 |
259 |
0 |
0 |
T136 |
0 |
2 |
0 |
0 |
T137 |
0 |
191 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577415372 |
1930 |
0 |
0 |
T44 |
33408 |
28 |
0 |
0 |
T76 |
0 |
86 |
0 |
0 |
T88 |
0 |
105 |
0 |
0 |
T95 |
241105 |
400 |
0 |
0 |
T96 |
1286 |
0 |
0 |
0 |
T97 |
611 |
0 |
0 |
0 |
T98 |
7070 |
8 |
0 |
0 |
T99 |
16050 |
0 |
0 |
0 |
T100 |
754 |
0 |
0 |
0 |
T105 |
1250 |
0 |
0 |
0 |
T106 |
11077 |
0 |
0 |
0 |
T107 |
1552 |
0 |
0 |
0 |
T109 |
0 |
5 |
0 |
0 |
T110 |
0 |
11 |
0 |
0 |
T111 |
0 |
219 |
0 |
0 |
T136 |
0 |
12 |
0 |
0 |
T137 |
0 |
234 |
0 |
0 |