Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7871909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6778848

1

T1

1027

T2

28

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10293711	1			T1	303		T2	1		T3	1
values[0x0]	2176137	1			T1	435		T2	14		T3	4
values[0x1]	2180909	1			T1	453		T2	20		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5641883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9008874

1

T1

1061

T2

28

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	64160	1			T5	48		T7	5		T8	69
valid_sources[0x01]	65253	1			T5	287		T7	3		T8	20
valid_sources[0x02]	57359	1			T2	1		T5	143		T7	6
valid_sources[0x03]	56680	1			T5	9		T8	53		T10	8
valid_sources[0x04]	56600	1			T2	1		T5	58		T7	3
valid_sources[0x05]	53660	1			T5	18		T7	2		T8	70
valid_sources[0x06]	56872	1			T5	106		T7	1		T8	34
valid_sources[0x07]	60109	1			T1	10		T5	74		T7	8
valid_sources[0x08]	55297	1			T5	47		T7	13		T8	37
valid_sources[0x09]	56971	1			T5	110		T8	91		T10	2
valid_sources[0x0a]	53482	1			T5	265		T7	18		T8	57
valid_sources[0x0b]	58466	1			T5	52		T7	3		T8	41
valid_sources[0x0c]	57824	1			T5	73		T8	41		T10	7
valid_sources[0x0d]	52968	1			T5	28		T7	19		T8	47
valid_sources[0x0e]	56673	1			T5	37		T7	13		T8	30
valid_sources[0x0f]	53655	1			T5	226		T7	4		T8	61
valid_sources[0x10]	59414	1			T5	66		T7	3		T8	86
valid_sources[0x11]	54451	1			T5	23		T7	6		T8	33
valid_sources[0x12]	57117	1			T5	325		T8	84		T10	6
valid_sources[0x13]	54677	1			T5	192		T7	11		T8	46
valid_sources[0x14]	55648	1			T5	39		T8	75		T10	17
valid_sources[0x15]	60095	1			T5	44		T6	138		T7	3
valid_sources[0x16]	58269	1			T1	416		T2	1		T5	132
valid_sources[0x17]	54276	1			T2	1		T5	104		T7	16
valid_sources[0x18]	56008	1			T2	1		T5	59		T7	8
valid_sources[0x19]	59093	1			T5	134		T7	12		T8	63
valid_sources[0x1a]	54500	1			T3	1		T5	10		T7	5
valid_sources[0x1b]	54885	1			T5	201		T7	2		T8	74
valid_sources[0x1c]	54438	1			T5	11		T7	7		T8	46
valid_sources[0x1d]	54508	1			T5	111		T7	8		T8	43
valid_sources[0x1e]	58453	1			T5	9		T7	6		T8	79
valid_sources[0x1f]	56592	1			T5	7		T7	1		T8	55
valid_sources[0x20]	55591	1			T5	3		T7	4		T8	80
valid_sources[0x21]	53554	1			T5	165		T7	10		T8	43
valid_sources[0x22]	64294	1			T2	1		T5	64		T7	1
valid_sources[0x23]	55330	1			T2	3		T5	134		T6	3
valid_sources[0x24]	57696	1			T5	107		T7	4		T8	56
valid_sources[0x25]	56889	1			T5	18		T7	6		T8	55
valid_sources[0x26]	57622	1			T5	44		T7	2		T8	51
valid_sources[0x27]	60207	1			T1	524		T5	234		T7	8
valid_sources[0x28]	51424	1			T5	201		T7	5		T8	52
valid_sources[0x29]	57344	1			T5	702		T6	4		T7	7
valid_sources[0x2a]	57050	1			T5	4		T7	3		T8	47
valid_sources[0x2b]	54274	1			T5	91		T8	78		T10	13
valid_sources[0x2c]	58277	1			T1	1		T3	1		T4	3
valid_sources[0x2d]	54021	1			T5	140		T8	52		T10	4
valid_sources[0x2e]	56486	1			T1	1		T5	97		T7	6
valid_sources[0x2f]	59168	1			T5	183		T7	1		T8	61
valid_sources[0x30]	55482	1			T5	73		T7	11		T8	38
valid_sources[0x31]	56158	1			T5	156		T7	5		T8	40
valid_sources[0x32]	57883	1			T5	211		T7	5		T8	57
valid_sources[0x33]	53501	1			T5	46		T7	8		T8	48
valid_sources[0x34]	56754	1			T5	96		T7	3		T8	103
valid_sources[0x35]	56580	1			T3	2		T5	58		T7	28
valid_sources[0x36]	57136	1			T2	1		T5	49		T7	1
valid_sources[0x37]	54358	1			T2	1		T5	6		T7	1
valid_sources[0x38]	55291	1			T5	24		T7	1		T8	77
valid_sources[0x39]	60836	1			T5	79		T7	5		T8	28
valid_sources[0x3a]	59212	1			T5	128		T8	51		T10	4
valid_sources[0x3b]	54934	1			T5	5		T7	18		T8	67
valid_sources[0x3c]	69040	1			T5	15		T8	42		T10	19
valid_sources[0x3d]	54202	1			T5	150		T6	11		T7	7
valid_sources[0x3e]	55173	1			T5	50		T7	2		T8	54
valid_sources[0x3f]	54413	1			T5	77		T7	1		T8	68
valid_sources[0x40]	58761	1			T5	65		T7	8		T8	76
valid_sources[0x41]	58329	1			T5	187		T7	1		T8	85
valid_sources[0x42]	56577	1			T5	42		T7	3		T8	52
valid_sources[0x43]	54547	1			T5	128		T7	3		T8	54
valid_sources[0x44]	56173	1			T5	268		T8	28		T10	5
valid_sources[0x45]	55504	1			T5	176		T7	3		T8	45
valid_sources[0x46]	59847	1			T5	147		T7	12		T8	57
valid_sources[0x47]	55684	1			T1	1		T5	100		T7	4
valid_sources[0x48]	59481	1			T5	352		T7	7		T8	37
valid_sources[0x49]	52834	1			T5	121		T6	6		T7	3
valid_sources[0x4a]	59587	1			T1	9		T2	1		T5	52
valid_sources[0x4b]	55688	1			T5	69		T7	16		T8	30
valid_sources[0x4c]	58657	1			T5	69		T7	3		T8	40
valid_sources[0x4d]	61197	1			T5	57		T7	9		T8	64
valid_sources[0x4e]	57229	1			T5	218		T7	26		T8	61
valid_sources[0x4f]	64756	1			T5	337		T7	5		T8	72
valid_sources[0x50]	53460	1			T5	49		T7	3		T8	37
valid_sources[0x51]	55921	1			T5	65		T7	7		T8	35
valid_sources[0x52]	53289	1			T5	197		T7	2		T8	42
valid_sources[0x53]	68548	1			T5	49		T7	15		T8	64
valid_sources[0x54]	56144	1			T5	10		T7	16		T8	56
valid_sources[0x55]	55216	1			T4	10		T5	240		T7	12
valid_sources[0x56]	55875	1			T5	10		T7	13		T8	71
valid_sources[0x57]	57151	1			T5	54		T7	1		T8	43
valid_sources[0x58]	56006	1			T5	64		T7	19		T8	35
valid_sources[0x59]	60879	1			T5	87		T7	5		T8	44
valid_sources[0x5a]	55682	1			T5	168		T7	1		T8	36
valid_sources[0x5b]	56612	1			T5	322		T7	2		T8	80
valid_sources[0x5c]	55277	1			T5	7		T7	2		T8	61
valid_sources[0x5d]	55582	1			T3	1		T5	179		T7	19
valid_sources[0x5e]	56912	1			T5	63		T6	78		T7	14
valid_sources[0x5f]	58142	1			T5	14		T7	7		T8	48
valid_sources[0x60]	56062	1			T5	98		T7	4		T8	91
valid_sources[0x61]	56654	1			T5	23		T8	67		T10	15
valid_sources[0x62]	65703	1			T2	1		T5	87		T7	8
valid_sources[0x63]	58915	1			T5	166		T8	46		T10	14
valid_sources[0x64]	57897	1			T5	3		T7	11		T8	44
valid_sources[0x65]	53345	1			T5	219		T7	17		T8	44
valid_sources[0x66]	52619	1			T5	150		T7	5		T8	37
valid_sources[0x67]	58643	1			T5	28		T7	6		T8	33
valid_sources[0x68]	60031	1			T5	45		T7	7		T8	50
valid_sources[0x69]	54994	1			T5	107		T7	26		T8	52
valid_sources[0x6a]	54530	1			T5	258		T7	5		T8	81
valid_sources[0x6b]	57302	1			T5	69		T7	8		T8	86
valid_sources[0x6c]	59305	1			T2	2		T5	34		T7	7
valid_sources[0x6d]	57176	1			T2	1		T5	74		T7	5
valid_sources[0x6e]	55338	1			T5	6		T7	1		T8	55
valid_sources[0x6f]	56896	1			T4	3		T5	35		T7	4
valid_sources[0x70]	58834	1			T5	70		T8	27		T10	3
valid_sources[0x71]	54882	1			T2	1		T5	62		T7	10
valid_sources[0x72]	56960	1			T8	56		T10	6		T11	251
valid_sources[0x73]	60141	1			T6	46		T7	12		T8	56
valid_sources[0x74]	53913	1			T5	156		T7	9		T8	72
valid_sources[0x75]	55288	1			T5	152		T7	9		T8	39
valid_sources[0x76]	61500	1			T5	27		T7	2		T8	72
valid_sources[0x77]	54622	1			T5	64		T7	6		T8	80
valid_sources[0x78]	55320	1			T2	1		T5	96		T7	8
valid_sources[0x79]	55037	1			T5	140		T8	46		T10	11
valid_sources[0x7a]	55819	1			T5	59		T7	14		T8	54
valid_sources[0x7b]	54445	1			T5	199		T7	10		T8	75
valid_sources[0x7c]	55514	1			T2	1		T5	529		T7	6
valid_sources[0x7d]	57024	1			T5	72		T6	18		T7	10
valid_sources[0x7e]	56507	1			T5	21		T7	4		T8	66
valid_sources[0x7f]	56426	1			T5	35		T7	2		T8	44
valid_sources[0x80]	54605	1			T5	270		T6	47		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2790378

1

T1

146

T2

1

T5

5437

values[0x0]

all_enables

biggest_size

2003489

1

T1

434

T2

13

T3

2

values[0x1]

all_enables

biggest_size

1984981

1

T1

447

T2

14

T4

2