Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

7891299

1

T1

164

T2

7

T3

9

full_word

6777853

1

T1

1027

T2

28

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	14668742	1			T1	1191		T2	35		T3	11
auto[TlIntgErrCmd]	137	1			T74	2		T76	9		T79	12
auto[TlIntgErrData]	131	1			T74	2		T76	8		T79	5
auto[TlIntgErrBoth]	142	1			T74	6		T76	13		T79	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10294748

1

T1

303

T2

1

T3

1

auto[1]

4374404

1

T1

888

T2

34

T3

10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7504157	1			T1	157		T3	1		T4	1
auto[TlIntgErrNone]	partial	auto[1]	386765	1			T1	7		T2	7		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	2790415	1			T1	146		T2	1		T5	5437
auto[TlIntgErrNone]	full_word	auto[1]	3987405	1			T1	881		T2	27		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T74	1		T76	3		T79	4
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T74	1		T76	6		T79	8
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T135	1		T161	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T101	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T74	1		T76	3		T79	1
auto[TlIntgErrData]	partial	auto[1]	62	1			T76	5		T79	3		T97	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T74	1		T98	1		T99	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T79	1		T99	1		T161	2
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T74	2		T76	6		T79	1
auto[TlIntgErrBoth]	partial	auto[1]	78	1			T74	3		T76	7		T79	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T162	3		T163	1		T164	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T74	1		T97	1		T102	1