Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	95.11	86.84	96.92		88.89	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	95.11	86.84	96.92		88.89	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	100.00	86.11		100.00	97.87	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1754017152	3068	0	0
SrcPulseCheck_M	554650572	3068	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1754017152	3068	0	0
T5	795405	10	0	0
T6	7507	0	0	0
T7	505147	0	0	0
T8	427377	15	0	0
T9	4920	0	0	0
T10	917046	0	0	0
T11	202200	10	0	0
T12	150813	0	0	0
T13	36161	0	0	0
T14	0	7	0	0
T16	0	24	0	0
T17	0	1	0	0
T18	566176	0	0	0
T21	3178	0	0	0
T24	0	26	0	0
T25	0	24	0	0
T26	0	8	0	0
T33	0	27	0	0
T35	16288	7	0	0
T36	56006	7	0	0
T52	0	2	0	0
T70	73392	4	0	0
T71	156462	7	0	0
T85	339250	0	0	0
T123	0	13	0	0
T124	0	7	0	0
T125	0	7	0	0
T126	0	7	0	0
T127	0	7	0	0
T128	0	7	0	0
T129	2304	0	0	0
T130	219050	0	0	0
T131	21730	0	0	0
T132	91476	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	554650572	3068	0	0
T5	778957	10	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	15	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	10	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	7	0	0
T16	0	24	0	0
T17	0	1	0	0
T18	508304	0	0	0
T24	0	26	0	0
T25	0	24	0	0
T26	0	8	0	0
T32	17453	0	0	0
T33	0	27	0	0
T35	28470	7	0	0
T36	47432	7	0	0
T52	0	2	0	0
T70	197942	4	0	0
T71	34494	7	0	0
T72	376576	0	0	0
T85	316484	0	0	0
T123	0	13	0	0
T124	0	7	0	0
T125	0	7	0	0
T126	0	7	0	0
T127	0	7	0	0
T128	0	7	0	0
T130	39988	0	0	0
T131	59376	0	0	0
T132	11060	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T35,T36,T71
1	0	Covered	T35,T36,T71
1	1	Covered	T35,T36,T71

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T35,T36,T71
1	0	Covered	T35,T36,T71
1	1	Covered	T35,T36,T71

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	584672384	303	0	0
SrcPulseCheck_M	184883524	303	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	303	0	0
T18	283088	0	0	0
T35	8144	2	0	0
T36	28003	2	0	0
T52	0	2	0	0
T70	36696	0	0	0
T71	78231	2	0	0
T85	169625	0	0	0
T123	0	7	0	0
T124	0	2	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	0	2	0	0
T128	0	2	0	0
T129	1152	0	0	0
T130	109525	0	0	0
T131	10865	0	0	0
T132	45738	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	303	0	0
T18	254152	0	0	0
T35	14235	2	0	0
T36	23716	2	0	0
T52	0	2	0	0
T70	98971	0	0	0
T71	17247	2	0	0
T72	188288	0	0	0
T85	158242	0	0	0
T123	0	7	0	0
T124	0	2	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	0	2	0	0
T128	0	2	0	0
T130	19994	0	0	0
T131	29688	0	0	0
T132	5530	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T35,T36,T70
1	0	Covered	T35,T36,T70
1	1	Covered	T35,T36,T70

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T35,T36,T70
1	0	Covered	T35,T36,T70
1	1	Covered	T35,T36,T70

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	584672384	490	0	0
SrcPulseCheck_M	184883524	490	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	490	0	0
T18	283088	0	0	0
T35	8144	5	0	0
T36	28003	5	0	0
T70	36696	4	0	0
T71	78231	5	0	0
T85	169625	0	0	0
T123	0	6	0	0
T124	0	5	0	0
T125	0	5	0	0
T126	0	5	0	0
T127	0	5	0	0
T128	0	5	0	0
T129	1152	0	0	0
T130	109525	0	0	0
T131	10865	0	0	0
T132	45738	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	490	0	0
T18	254152	0	0	0
T35	14235	5	0	0
T36	23716	5	0	0
T70	98971	4	0	0
T71	17247	5	0	0
T72	188288	0	0	0
T85	158242	0	0	0
T123	0	6	0	0
T124	0	5	0	0
T125	0	5	0	0
T126	0	5	0	0
T127	0	5	0	0
T128	0	5	0	0
T130	19994	0	0	0
T131	29688	0	0	0
T132	5530	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	584672384	2275	0	0
SrcPulseCheck_M	184883524	2275	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	2275	0	0
T5	795405	10	0	0
T6	7507	0	0	0
T7	505147	0	0	0
T8	427377	15	0	0
T9	4920	0	0	0
T10	917046	0	0	0
T11	202200	10	0	0
T12	150813	0	0	0
T13	36161	0	0	0
T14	0	7	0	0
T16	0	24	0	0
T17	0	1	0	0
T21	3178	0	0	0
T24	0	26	0	0
T25	0	24	0	0
T26	0	8	0	0
T33	0	27	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	2275	0	0
T5	778957	10	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	15	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	10	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	7	0	0
T16	0	24	0	0
T17	0	1	0	0
T24	0	26	0	0
T25	0	24	0	0
T26	0	8	0	0
T32	17453	0	0	0
T33	0	27	0	0