Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587149954	55602	0	0
DepthKnown_A	587149954	587020114	0	0
RvalidKnown_A	587149954	587020114	0	0
WreadyKnown_A	587149954	587020114	0	0
gen_passthru_fifo.paramCheckPass	1105	1105	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	55602	0	0
T5	795405	128	0	0
T6	7507	0	0	0
T7	505147	0	0	0
T8	427377	195	0	0
T9	4920	0	0	0
T10	917046	0	0	0
T11	202200	321	0	0
T12	150813	0	0	0
T13	36161	0	0	0
T14	0	192	0	0
T16	0	835	0	0
T17	0	58	0	0
T21	3178	100	0	0
T22	0	100	0	0
T24	0	409	0	0
T25	0	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1105	1105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587149954	144837	0	0
DepthKnown_A	587149954	587020114	0	0
RvalidKnown_A	587149954	587020114	0	0
WreadyKnown_A	587149954	587020114	0	0
gen_passthru_fifo.paramCheckPass	1105	1105	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	144837	0	0
T5	795405	577	0	0
T6	7507	0	0	0
T7	505147	0	0	0
T8	427377	195	0	0
T9	4920	0	0	0
T10	917046	0	0	0
T11	202200	939	0	0
T12	150813	0	0	0
T13	36161	0	0	0
T14	0	923	0	0
T16	0	3775	0	0
T17	0	299	0	0
T21	3178	298	0	0
T22	0	417	0	0
T24	0	1288	0	0
T25	0	2487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1105	1105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587149954	13272017	0	0
DepthKnown_A	587149954	587020114	0	0
RvalidKnown_A	587149954	587020114	0	0
WreadyKnown_A	587149954	587020114	0	0
gen_passthru_fifo.paramCheckPass	1105	1105	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	13272017	0	0
T1	32029	369	0	0
T2	5090	35	0	0
T3	886	11	0	0
T4	1100	19	0	0
T5	795405	28633	0	0
T6	7507	54	0	0
T7	505147	807	0	0
T8	427377	5281	0	0
T9	4920	46	0	0
T10	917046	1311	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1105	1105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587149954	29533470	0	0
DepthKnown_A	587149954	587020114	0	0
RvalidKnown_A	587149954	587020114	0	0
WreadyKnown_A	587149954	587020114	0	0
gen_passthru_fifo.paramCheckPass	1105	1105	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	29533470	0	0
T1	32029	1630	0	0
T2	5090	35	0	0
T3	886	11	0	0
T4	1100	19	0	0
T5	795405	82332	0	0
T6	7507	54	0	0
T7	505147	807	0	0
T8	427377	5263	0	0
T9	4920	72	0	0
T10	917046	1308	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587149954	587020114	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1105	1105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0