Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T5,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=4,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	769555908	728432021	0	0
CheckNGreaterZero_A	1860	1860	0	0
GntImpliesReady_A	769555908	2748085	0	0
GntImpliesValid_A	769555908	2748085	0	0
GrantKnown_A	769555908	728432021	0	0
IdxKnown_A	769555908	728432021	0	0
IndexIsCorrect_A	769555908	2748085	0	0
LockArbDecision_A	769555908	0	0	0
NoReadyValidNoGrant_A	769555908	0	0	0
ReadyAndValidImplyGrant_A	769555908	2748085	0	0
ReqAndReadyImplyGrant_A	769555908	2748085	0	0
ReqImpliesValid_A	769555908	2748085	0	0
ReqStaysHighUntilGranted0_M	769555908	0	0	0
RoundRobin_A	769555908	0	0	930
ValidKnown_A	769555908	728432021	0	0
gen_data_port_assertion.DataFlow_A	769555908	2748085	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	728432021	0	0
T1	128153	127688	0	0
T2	5882	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	1574362	1432751	0	0
T6	16899	16841	0	0
T7	755987	755908	0	0
T8	1172718	1170342	0	0
T9	13208	13111	0	0
T10	1069318	1069238	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1860	1860	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	2748085	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	1574362	11116	0	0
T6	16899	832	0	0
T7	755987	832	0	0
T8	1172718	13238	0	0
T9	13208	832	0	0
T10	1069318	832	0	0
T11	939211	9527	0	0
T12	49339	832	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T21	0	200	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	2748085	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	1574362	11116	0	0
T6	16899	832	0	0
T7	755987	832	0	0
T8	1172718	13238	0	0
T9	13208	832	0	0
T10	1069318	832	0	0
T11	939211	9527	0	0
T12	49339	832	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T21	0	200	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	728432021	0	0
T1	128153	127688	0	0
T2	5882	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	1574362	1432751	0	0
T6	16899	16841	0	0
T7	755987	755908	0	0
T8	1172718	1170342	0	0
T9	13208	13111	0	0
T10	1069318	1069238	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	728432021	0	0
T1	128153	127688	0	0
T2	5882	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	1574362	1432751	0	0
T6	16899	16841	0	0
T7	755987	755908	0	0
T8	1172718	1170342	0	0
T9	13208	13111	0	0
T10	1069318	1069238	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	2748085	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	1574362	11116	0	0
T6	16899	832	0	0
T7	755987	832	0	0
T8	1172718	13238	0	0
T9	13208	832	0	0
T10	1069318	832	0	0
T11	939211	9527	0	0
T12	49339	832	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T21	0	200	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	2748085	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	1574362	11116	0	0
T6	16899	832	0	0
T7	755987	832	0	0
T8	1172718	13238	0	0
T9	13208	832	0	0
T10	1069318	832	0	0
T11	939211	9527	0	0
T12	49339	832	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T21	0	200	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	2748085	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	1574362	11116	0	0
T6	16899	832	0	0
T7	755987	832	0	0
T8	1172718	13238	0	0
T9	13208	832	0	0
T10	1069318	832	0	0
T11	939211	9527	0	0
T12	49339	832	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T21	0	200	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	2748085	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	1574362	11116	0	0
T6	16899	832	0	0
T7	755987	832	0	0
T8	1172718	13238	0	0
T9	13208	832	0	0
T10	1069318	832	0	0
T11	939211	9527	0	0
T12	49339	832	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T21	0	200	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	0	0	930

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	728432021	0	0
T1	128153	127688	0	0
T2	5882	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	1574362	1432751	0	0
T6	16899	16841	0	0
T7	755987	755908	0	0
T8	1172718	1170342	0	0
T9	13208	13111	0	0
T10	1069318	1069238	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769555908	2748085	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	1574362	11116	0	0
T6	16899	832	0	0
T7	755987	832	0	0
T8	1172718	13238	0	0
T9	13208	832	0	0
T10	1069318	832	0	0
T11	939211	9527	0	0
T12	49339	832	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T21	0	200	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T5,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	184883524	143843844	0	0
CheckNGreaterZero_A	930	930	0	0
GntImpliesReady_A	184883524	559299	0	0
GntImpliesValid_A	184883524	559299	0	0
GrantKnown_A	184883524	143843844	0	0
IdxKnown_A	184883524	143843844	0	0
IndexIsCorrect_A	184883524	559299	0	0
LockArbDecision_A	184883524	0	0	0
NoReadyValidNoGrant_A	184883524	0	0	0
ReadyAndValidImplyGrant_A	184883524	559299	0	0
ReqAndReadyImplyGrant_A	184883524	559299	0	0
ReqImpliesValid_A	184883524	559299	0	0
ReqStaysHighUntilGranted0_M	184883524	0	0	0
RoundRobin_A	184883524	0	0	0
ValidKnown_A	184883524	143843844	0	0
gen_data_port_assertion.DataFlow_A	184883524	559299	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	143843844	0	0
T1	96124	95721	0	0
T2	792	0	0	0
T5	778957	637424	0	0
T6	9392	9392	0	0
T7	250840	250840	0	0
T8	745341	743026	0	0
T9	8288	8288	0	0
T10	152272	152272	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	930	930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	559299	0	0
T5	778957	2651	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	4695	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	1701	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	559299	0	0
T5	778957	2651	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	4695	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	1701	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	143843844	0	0
T1	96124	95721	0	0
T2	792	0	0	0
T5	778957	637424	0	0
T6	9392	9392	0	0
T7	250840	250840	0	0
T8	745341	743026	0	0
T9	8288	8288	0	0
T10	152272	152272	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	143843844	0	0
T1	96124	95721	0	0
T2	792	0	0	0
T5	778957	637424	0	0
T6	9392	9392	0	0
T7	250840	250840	0	0
T8	745341	743026	0	0
T9	8288	8288	0	0
T10	152272	152272	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	559299	0	0
T5	778957	2651	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	4695	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	1701	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	559299	0	0
T5	778957	2651	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	4695	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	1701	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	559299	0	0
T5	778957	2651	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	4695	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	1701	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	559299	0	0
T5	778957	2651	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	4695	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	1701	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	143843844	0	0
T1	96124	95721	0	0
T2	792	0	0	0
T5	778957	637424	0	0
T6	9392	9392	0	0
T7	250840	250840	0	0
T8	745341	743026	0	0
T9	8288	8288	0	0
T10	152272	152272	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	559299	0	0
T5	778957	2651	0	0
T6	9392	0	0	0
T7	250840	0	0	0
T8	745341	4695	0	0
T9	8288	0	0	0
T10	152272	0	0	0
T11	939211	1701	0	0
T12	49339	0	0	0
T13	16216	0	0	0
T14	0	781	0	0
T16	0	9734	0	0
T17	0	235	0	0
T24	0	8527	0	0
T25	0	5446	0	0
T26	0	526	0	0
T32	17453	0	0	0
T33	0	7343	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	584672384	584588177	0	0
CheckNGreaterZero_A	930	930	0	0
GntImpliesReady_A	584672384	2188786	0	0
GntImpliesValid_A	584672384	2188786	0	0
GrantKnown_A	584672384	584588177	0	0
IdxKnown_A	584672384	584588177	0	0
IndexIsCorrect_A	584672384	2188786	0	0
LockArbDecision_A	584672384	0	0	0
NoReadyValidNoGrant_A	584672384	0	0	0
ReadyAndValidImplyGrant_A	584672384	2188786	0	0
ReqAndReadyImplyGrant_A	584672384	2188786	0	0
ReqImpliesValid_A	584672384	2188786	0	0
ReqStaysHighUntilGranted0_M	584672384	0	0	0
RoundRobin_A	584672384	0	0	930
ValidKnown_A	584672384	584588177	0	0
gen_data_port_assertion.DataFlow_A	584672384	2188786	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	584588177	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	930	930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	2188786	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	795405	8465	0	0
T6	7507	832	0	0
T7	505147	832	0	0
T8	427377	8543	0	0
T9	4920	832	0	0
T10	917046	832	0	0
T11	0	7826	0	0
T12	0	832	0	0
T21	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	2188786	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	795405	8465	0	0
T6	7507	832	0	0
T7	505147	832	0	0
T8	427377	8543	0	0
T9	4920	832	0	0
T10	917046	832	0	0
T11	0	7826	0	0
T12	0	832	0	0
T21	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	584588177	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	584588177	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	2188786	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	795405	8465	0	0
T6	7507	832	0	0
T7	505147	832	0	0
T8	427377	8543	0	0
T9	4920	832	0	0
T10	917046	832	0	0
T11	0	7826	0	0
T12	0	832	0	0
T21	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	2188786	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	795405	8465	0	0
T6	7507	832	0	0
T7	505147	832	0	0
T8	427377	8543	0	0
T9	4920	832	0	0
T10	917046	832	0	0
T11	0	7826	0	0
T12	0	832	0	0
T21	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	2188786	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	795405	8465	0	0
T6	7507	832	0	0
T7	505147	832	0	0
T8	427377	8543	0	0
T9	4920	832	0	0
T10	917046	832	0	0
T11	0	7826	0	0
T12	0	832	0	0
T21	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	2188786	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	795405	8465	0	0
T6	7507	832	0	0
T7	505147	832	0	0
T8	427377	8543	0	0
T9	4920	832	0	0
T10	917046	832	0	0
T11	0	7826	0	0
T12	0	832	0	0
T21	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	0	0	930

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	584588177	0	0
T1	32029	31967	0	0
T2	5090	4990	0	0
T3	886	790	0	0
T4	1100	1010	0	0
T5	795405	795327	0	0
T6	7507	7449	0	0
T7	505147	505068	0	0
T8	427377	427316	0	0
T9	4920	4823	0	0
T10	917046	916966	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584672384	2188786	0	0
T1	32029	832	0	0
T2	5090	0	0	0
T3	886	0	0	0
T4	1100	0	0	0
T5	795405	8465	0	0
T6	7507	832	0	0
T7	505147	832	0	0
T8	427377	8543	0	0
T9	4920	832	0	0
T10	917046	832	0	0
T11	0	7826	0	0
T12	0	832	0	0
T21	0	200	0	0