Unified Coverage Report :: Module :: spi_readcmd

Module : spi_readcmd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	96.32	100.00		80.00	84.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_readcmd	92.19	96.32	100.00		80.00	84.62	100.00

---

Module Instance : tb.dut.u_readcmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	96.32	100.00		80.00	84.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14	97.16	93.19		87.50	87.82	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	95.11	86.84	96.92		88.89	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr_latch_pulse	100.00	100.00	100.00			100.00
u_readbuffer	96.23	97.30	97.14			90.48	100.00
u_readsram	94.65	97.81	85.71		100.00	89.71	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_readcmd

	Line No.	Total	Covered	Percent
TOTAL		136	131	96.32
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	349	4	4	100.00
ALWAYS	365	4	4	100.00
CONT_ASSIGN	374	1	1	100.00
ALWAYS	377	12	12	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
ALWAYS	423	3	3	100.00
ALWAYS	431	7	7	100.00
ALWAYS	452	6	6	100.00
CONT_ASSIGN	461	1	1	100.00
ALWAYS	465	12	12	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
ALWAYS	509	8	8	100.00
CONT_ASSIGN	525	1	1	100.00
ALWAYS	530	5	5	100.00
ALWAYS	548	4	4	100.00
CONT_ASSIGN	561	1	1	100.00
ALWAYS	571	3	3	100.00
ALWAYS	579	48	43	89.58
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
179	1	1
182	1	1
185	1	1
188	1	1
329	1	1
336	1	1
349	1	1
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
370	1	1
			MISSING_ELSE
374	1	1
377	1	1
378	1	1
380	1	1
382	1	1
383	1	1
386	1	1
387	1	1
389	1	1
390	1	1
391	1	1
393	1	1
394	1	1
			MISSING_ELSE
400	1	1
401	1	1
404	1	1
420	1	1
423	1	1
424	1	1
426	1	1
431	1	1
432	1	1
439	1	1
441	1	1
442	1	1
443	1	1
445	1	1
			==> MISSING_ELSE
452	1	1
453	1	1
454	1	1
456	1	1
457	1	1
458	1	1
			MISSING_ELSE
461	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
474	1	1
475	1	1
476	1	1
477	1	1
478	1	1
			MISSING_ELSE
492	1	1
493	1	1
496	1	1
497	1	1
509	2	2
510	1	1
512	1	1
513	1	1
516	1	1
517	1	1
519	1	1
			MISSING_ELSE
525	1	1
530	1	1
531	1	1
532	1	1
534	1	1
535	1	1
548	1	1
549	1	1
550	1	1
556	1	1
			MISSING_ELSE
561	1	1
571	1	1
572	1	1
574	1	1
579	1	1
581	1	1
584	1	1
585	1	1
586	1	1
587	1	1
589	1	1
590	1	1
592	1	1
593	1	1
595	1	1
597	1	1
598	1	1
600	1	1
602	1	1
605	1	1
607	1	1
			MISSING_ELSE
612	1	1
614	1	1
615	1	1
			MISSING_ELSE
618	1	1
621	1	1
627	1	1
630	1	1
631	1	1
632	1	1
637	1	1
639	1	1
644	0	1
			MISSING_ELSE
655	0	1
656	0	1
658	0	1
			==> MISSING_ELSE
663	1	1
664	1	1
665	1	1
666	1	1
			MISSING_ELSE
671	1	1
675	1	1
680	1	1
681	1	1
682	1	1
683	1	1
687	1	1
689	1	1
692	1	1
695	1	1
696	1	1
			MISSING_ELSE
701	0	1
716	1	1
717	1	1

---

Cond Coverage for Module : spi_readcmd

	Total	Covered	Percent
Conditions	66	66	100.00
Logical	66	66	100.00
Non-Logical	0	0
Event	0	0

 LINE       329
 EXPRESSION (sel_dp_i == DpReadSFDP)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

 LINE       336
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       367
 EXPRESSION ((main_st == MainOutput) && (sel_dp_i == DpReadCmd) && addr_latch_en && ( ! (mailbox_en_i && addr_q_in_mailbox) ) && spid_in_flashmode)
             -----------1-----------    -----------2-----------    ------3------    --------------------4--------------------    --------5--------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T1,T14,T16
1	0	1	1	1	Covered	T14,T16,T24
1	1	0	1	1	Covered	T1,T35,T36
1	1	1	0	1	Covered	T1,T14,T16
1	1	1	1	0	Covered	T5,T6,T7
1	1	1	1	1	Covered	T1,T35,T36

 LINE       367
 SUB-EXPRESSION (main_st == MainOutput)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T5,T6

 LINE       367
 SUB-EXPRESSION (sel_dp_i == DpReadCmd)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T5,T6

 LINE       367
 SUB-EXPRESSION ( ! (mailbox_en_i && addr_q_in_mailbox) )
                    -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T5,T8

 LINE       367
 SUB-EXPRESSION (mailbox_en_i && addr_q_in_mailbox)
                 ------1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T8

 LINE       387
 EXPRESSION (addr_shift_en && s2p_valid_i)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       400
 EXPRESSION (addr_cnt_d == 5'd2)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       401
 EXPRESSION (addr_cnt_d == 5'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       404
 EXPRESSION (addr_cnt_d == 5'b0)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       439
 EXPRESSION ((cmdinfo_addr_mode == Addr4B) ? 5'd31 : 5'd23)
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T5,T6,T7

 LINE       439
 SUB-EXPRESSION (cmdinfo_addr_mode == Addr4B)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T5,T6,T7

 LINE       441
 EXPRESSION (addr_cnt_q == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (mailbox_masked_addr_d == mailbox_addr_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       497
 EXPRESSION (mailbox_masked_addr_q == mailbox_addr_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       510
 EXPRESSION (sram_req && mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox)
             ----1---    ------2-----    -----------3----------    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T5,T8
1	0	1	1	Covered	T5,T11,T16
1	1	0	1	Covered	T5,T8,T11
1	1	1	0	Covered	T1,T5,T6
1	1	1	1	Covered	T1,T5,T8

 LINE       513
 EXPRESSION (mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox && (bitcnt == 3'b0))
             ------1-----    -----------2----------    --------3--------    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T11,T16
1	0	1	1	Covered	T5,T8,T9
1	1	0	1	Covered	T1,T5,T6
1	1	1	0	Covered	T1,T5,T8
1	1	1	1	Covered	T1,T5,T8

 LINE       513
 SUB-EXPRESSION (bitcnt == 3'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       517
 EXPRESSION (((!addr_d_in_mailbox)) && (bitcnt == 3'b0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       517
 SUB-EXPRESSION (bitcnt == 3'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       561
 EXPRESSION ((main_st == MainOutput) && (addr_q[9:0] == '1))
             -----------1-----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T11
1	0	Covered	T1,T5,T6
1	1	Covered	T5,T7,T8

 LINE       561
 SUB-EXPRESSION (main_st == MainOutput)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       561
 SUB-EXPRESSION (addr_q[9:0] == '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       687
 EXPRESSION (bitcnt == 3'b0)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       730
 EXPRESSION (sel_dp_i == DpReadSFDP)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

---

FSM Coverage for Module : spi_readcmd

Summary for FSM :: main_st

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: main_st

---

states	Line No.	Covered	Tests
MainAddress	605	Covered	T1,T5,T6
MainDummy	637	Covered	T1,T5,T6
MainError	648	Not Covered
MainMByte	644	Excluded
MainOutput	630	Covered	T1,T5,T6
MainReset	601	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
MainAddress->MainDummy	637	Covered	T1,T5,T6
MainAddress->MainError	648	Not Covered
MainAddress->MainMByte	644	Excluded
MainAddress->MainOutput	630	Covered	T5,T8,T11
MainDummy->MainOutput	664	Covered	T1,T5,T6
MainMByte->MainDummy	656	Excluded
MainReset->MainAddress	605	Covered	T1,T5,T6

---

Branch Coverage for Module : spi_readcmd

	Line No.	Total	Covered	Percent
Branches		65	55	84.62
IF	349	3	3	100.00
IF	365	3	3	100.00
IF	380	5	5	100.00
IF	423	2	2	100.00
IF	432	5	4	80.00
IF	452	4	4	100.00
IF	465	10	8	80.00
IF	509	5	5	100.00
IF	530	2	2	100.00
IF	548	3	3	100.00
IF	571	2	2	100.00
CASE	600	21	14	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	349	if ((!rst_ni))
-2-:	351	if (addr_latch_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	365	if ((!sys_rst_ni))
-2-:	367	if ((((((main_st == MainOutput) && (sel_dp_i == DpReadCmd)) && addr_latch_en) && (!(mailbox_en_i && addr_q_in_mailbox))) && spid_in_flashmode))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T35,T36
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	380	if (addr_ready_in_word)
-2-:	383	if (addr_ready_in_halfword)
-3-:	387	if ((addr_shift_en && s2p_valid_i))
-4-:	391	if (addr_inc)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T5,T6
0	1	-	-	Covered	T1,T5,T6
0	0	1	-	Covered	T1,T5,T6
0	0	0	1	Covered	T1,T5,T6
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	423	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	432	if (addr_cnt_set)
-2-:	439	((cmdinfo_addr_mode == Addr4B)) ? 
-3-:	441	if ((addr_cnt_q == '0))
-4-:	443	if (addr_shift_en)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T6,T7
1	0	-	-	Covered	T1,T5,T7
0	-	1	-	Covered	T1,T2,T3
0	-	0	1	Covered	T1,T5,T6
0	-	0	0	Not Covered

	LineNo.	Expression
-1-:	452	if ((!rst_ni))
-2-:	454	if (load_dummycnt)
-3-:	457	if ((!dummycnt_eq_zero))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	465	if ((!rst_ni))
-2-:	467	if (bitcnt_update)
-3-:	468	case (cmd_info_i.payload_en)
-4-:	474	if (bitcnt_dec)
-5-:	475	case (cmd_info_i.payload_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	4'b0010	-	-	Covered	T1,T5,T7
0	1	4'b0011	-	-	Covered	T5,T6,T8
0	1	4'b1111	-	-	Covered	T1,T5,T7
0	1	default	-	-	Not Covered
0	0	-	1	4'b0010	Covered	T1,T5,T7
0	0	-	1	4'b0011	Covered	T5,T6,T8
0	0	-	1	4'b1111	Covered	T1,T5,T7
0	0	-	1	default	Not Covered
0	0	-	0	-	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	509	if ((!rst_ni))
-2-:	510	if ((((sram_req && mailbox_en_i) && cfg_intercept_en_mbx_i) && addr_d_in_mailbox))
-3-:	513	if ((((mailbox_en_i && cfg_intercept_en_mbx_i) && addr_d_in_mailbox) && (bitcnt == 3'b0)))
-4-:	517	if (((!addr_d_in_mailbox) && (bitcnt == 3'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T5,T8
0	0	1	-	Covered	T1,T5,T8
0	0	0	1	Covered	T1,T5,T6
0	0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	530	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	548	if ((!sys_rst_ni))
-2-:	550	if (readbuf_flip)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	571	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	600	case (main_st)
-2-:	602	if ((sel_dp_i inside {DpReadCmd, DpReadSFDP}))
-3-:	614	if (addr_ready_in_word)
-4-:	618	if (addr_latched)
-5-:	627	case ({cmd_info_i.mbyte_en, cmd_info_i.dummy_en})
-6-:	655	if (s2p_valid_i)
-7-:	663	if (dummycnt_eq_zero)
-8-:	680	case (cmd_info_i.payload_en)
-9-:	687	if ((bitcnt == 3'b0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
MainReset	1	-	-	-	-	-	-	-	Covered	T1,T5,T6
MainReset	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
MainAddress	-	1	-	-	-	-	-	-	Covered	T1,T5,T6
MainAddress	-	0	-	-	-	-	-	-	Covered	T1,T5,T6
MainAddress	-	-	1	2'b00	-	-	-	-	Covered	T5,T8,T11
MainAddress	-	-	1	2'b01	-	-	-	-	Covered	T1,T5,T6
MainAddress	-	-	1	2'b1z	-	-	-	-	Not Covered
MainAddress	-	-	1	default	-	-	-	-	Not Covered
MainAddress	-	-	0	-	-	-	-	-	Covered	T1,T5,T6
MainMByte	-	-	-	-	1	-	-	-	Not Covered
MainMByte	-	-	-	-	0	-	-	-	Not Covered
MainDummy	-	-	-	-	-	1	-	-	Covered	T1,T5,T6
MainDummy	-	-	-	-	-	0	-	-	Covered	T1,T5,T6
MainOutput	-	-	-	-	-	-	4'b0010	-	Covered	T1,T5,T7
MainOutput	-	-	-	-	-	-	4'b0011	-	Covered	T5,T6,T8
MainOutput	-	-	-	-	-	-	4'b1111	-	Covered	T1,T5,T7
MainOutput	-	-	-	-	-	-	default	-	Not Covered
MainOutput	-	-	-	-	-	-	-	1	Covered	T1,T5,T6
MainOutput	-	-	-	-	-	-	-	0	Covered	T1,T5,T6
MainError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_readcmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrIncNotAssertInAddressState_A	184883524	5641528	0	0
MailboxSizeMatch_M	184883524	143843844	0	0
ValidCmdConfig_A	184883524	256033	0	0

AddrIncNotAssertInAddressState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	5641528	0	0
T1	96124	2647	0	0
T2	792	0	0	0
T5	778957	31313	0	0
T6	9392	256	0	0
T7	250840	6814	0	0
T8	745341	45082	0	0
T9	8288	1024	0	0
T10	152272	1536	0	0
T11	939211	18038	0	0
T12	49339	4358	0	0
T34	0	10	0	0

MailboxSizeMatch_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	143843844	0	0
T1	96124	95721	0	0
T2	792	0	0	0
T5	778957	637424	0	0
T6	9392	9392	0	0
T7	250840	250840	0	0
T8	745341	743026	0	0
T9	8288	8288	0	0
T10	152272	152272	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

ValidCmdConfig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	256033	0	0
T1	96124	207	0	0
T2	792	0	0	0
T5	778957	1156	0	0
T6	9392	62	0	0
T7	250840	154	0	0
T8	745341	1363	0	0
T9	8288	62	0	0
T10	152272	92	0	0
T11	939211	770	0	0
T12	49339	92	0	0
T34	0	46	0	0