Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
3371 |
0 |
0 |
T74 |
11058 |
2 |
0 |
0 |
T76 |
80055 |
3 |
0 |
0 |
T77 |
8545 |
1 |
0 |
0 |
T78 |
3433 |
161 |
0 |
0 |
T79 |
52272 |
2 |
0 |
0 |
T80 |
2892 |
2 |
0 |
0 |
T97 |
29135 |
6 |
0 |
0 |
T98 |
26747 |
2 |
0 |
0 |
T99 |
53363 |
5 |
0 |
0 |
T100 |
56100 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2020 |
0 |
0 |
T93 |
12738 |
24 |
0 |
0 |
T104 |
117325 |
789 |
0 |
0 |
T110 |
4031 |
4 |
0 |
0 |
T116 |
4294 |
2 |
0 |
0 |
T133 |
75934 |
292 |
0 |
0 |
T134 |
12815 |
20 |
0 |
0 |
T135 |
61794 |
55 |
0 |
0 |
T136 |
160634 |
285 |
0 |
0 |
T137 |
98832 |
114 |
0 |
0 |
T138 |
6143 |
2 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2024 |
0 |
0 |
T75 |
6445 |
5 |
0 |
0 |
T93 |
12738 |
10 |
0 |
0 |
T104 |
117325 |
787 |
0 |
0 |
T105 |
3631 |
3 |
0 |
0 |
T110 |
4031 |
6 |
0 |
0 |
T133 |
75934 |
229 |
0 |
0 |
T134 |
12815 |
45 |
0 |
0 |
T135 |
61794 |
47 |
0 |
0 |
T136 |
160634 |
323 |
0 |
0 |
T137 |
98832 |
131 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2458 |
0 |
0 |
T75 |
6445 |
9 |
0 |
0 |
T93 |
12738 |
29 |
0 |
0 |
T104 |
117325 |
827 |
0 |
0 |
T105 |
3631 |
16 |
0 |
0 |
T116 |
4294 |
12 |
0 |
0 |
T133 |
75934 |
292 |
0 |
0 |
T134 |
12815 |
28 |
0 |
0 |
T135 |
61794 |
98 |
0 |
0 |
T136 |
160634 |
256 |
0 |
0 |
T137 |
98832 |
217 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
8487 |
0 |
0 |
T75 |
6445 |
55 |
0 |
0 |
T93 |
12738 |
111 |
0 |
0 |
T104 |
117325 |
733 |
0 |
0 |
T105 |
3631 |
7 |
0 |
0 |
T116 |
4294 |
3 |
0 |
0 |
T133 |
75934 |
341 |
0 |
0 |
T134 |
12815 |
21 |
0 |
0 |
T135 |
61794 |
884 |
0 |
0 |
T136 |
160634 |
340 |
0 |
0 |
T137 |
98832 |
1792 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
8529 |
0 |
0 |
T75 |
6445 |
53 |
0 |
0 |
T93 |
12738 |
141 |
0 |
0 |
T104 |
117325 |
809 |
0 |
0 |
T105 |
3631 |
3 |
0 |
0 |
T110 |
4031 |
52 |
0 |
0 |
T133 |
75934 |
272 |
0 |
0 |
T134 |
12815 |
40 |
0 |
0 |
T135 |
61794 |
624 |
0 |
0 |
T136 |
160634 |
250 |
0 |
0 |
T137 |
98832 |
2222 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
7943 |
0 |
0 |
T93 |
12738 |
145 |
0 |
0 |
T104 |
117325 |
784 |
0 |
0 |
T105 |
3631 |
8 |
0 |
0 |
T110 |
4031 |
57 |
0 |
0 |
T116 |
4294 |
94 |
0 |
0 |
T133 |
75934 |
320 |
0 |
0 |
T134 |
12815 |
18 |
0 |
0 |
T135 |
61794 |
663 |
0 |
0 |
T136 |
160634 |
341 |
0 |
0 |
T137 |
98832 |
1559 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
8994 |
0 |
0 |
T75 |
6445 |
81 |
0 |
0 |
T93 |
12738 |
8 |
0 |
0 |
T104 |
117325 |
728 |
0 |
0 |
T105 |
3631 |
8 |
0 |
0 |
T110 |
4031 |
9 |
0 |
0 |
T133 |
75934 |
310 |
0 |
0 |
T134 |
12815 |
38 |
0 |
0 |
T135 |
61794 |
593 |
0 |
0 |
T136 |
160634 |
288 |
0 |
0 |
T137 |
98832 |
1930 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
8465 |
0 |
0 |
T75 |
6445 |
15 |
0 |
0 |
T93 |
12738 |
14 |
0 |
0 |
T104 |
117325 |
735 |
0 |
0 |
T105 |
3631 |
5 |
0 |
0 |
T110 |
4031 |
4 |
0 |
0 |
T133 |
75934 |
308 |
0 |
0 |
T134 |
12815 |
37 |
0 |
0 |
T135 |
61794 |
506 |
0 |
0 |
T136 |
160634 |
234 |
0 |
0 |
T137 |
98832 |
1719 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
7732 |
0 |
0 |
T75 |
6445 |
2 |
0 |
0 |
T93 |
12738 |
21 |
0 |
0 |
T104 |
117325 |
898 |
0 |
0 |
T105 |
3631 |
4 |
0 |
0 |
T110 |
4031 |
2 |
0 |
0 |
T133 |
75934 |
342 |
0 |
0 |
T134 |
12815 |
21 |
0 |
0 |
T135 |
61794 |
759 |
0 |
0 |
T136 |
160634 |
229 |
0 |
0 |
T137 |
98832 |
1722 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
7721 |
0 |
0 |
T75 |
6445 |
60 |
0 |
0 |
T93 |
12738 |
253 |
0 |
0 |
T104 |
117325 |
801 |
0 |
0 |
T105 |
3631 |
6 |
0 |
0 |
T110 |
4031 |
77 |
0 |
0 |
T116 |
4294 |
3 |
0 |
0 |
T133 |
75934 |
318 |
0 |
0 |
T135 |
61794 |
594 |
0 |
0 |
T136 |
160634 |
228 |
0 |
0 |
T137 |
98832 |
1755 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
7659 |
0 |
0 |
T75 |
6445 |
71 |
0 |
0 |
T93 |
12738 |
124 |
0 |
0 |
T104 |
117325 |
779 |
0 |
0 |
T105 |
3631 |
3 |
0 |
0 |
T110 |
4031 |
76 |
0 |
0 |
T133 |
75934 |
261 |
0 |
0 |
T134 |
12815 |
54 |
0 |
0 |
T135 |
61794 |
848 |
0 |
0 |
T136 |
160634 |
298 |
0 |
0 |
T137 |
98832 |
1515 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4167 |
0 |
0 |
T75 |
6445 |
8 |
0 |
0 |
T93 |
12738 |
63 |
0 |
0 |
T104 |
117325 |
836 |
0 |
0 |
T105 |
3631 |
12 |
0 |
0 |
T110 |
4031 |
5 |
0 |
0 |
T133 |
75934 |
269 |
0 |
0 |
T134 |
12815 |
17 |
0 |
0 |
T135 |
61794 |
269 |
0 |
0 |
T136 |
160634 |
275 |
0 |
0 |
T137 |
98832 |
662 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4650 |
0 |
0 |
T75 |
6445 |
36 |
0 |
0 |
T93 |
12738 |
69 |
0 |
0 |
T104 |
117325 |
829 |
0 |
0 |
T105 |
3631 |
3 |
0 |
0 |
T110 |
4031 |
20 |
0 |
0 |
T133 |
75934 |
252 |
0 |
0 |
T134 |
12815 |
34 |
0 |
0 |
T135 |
61794 |
214 |
0 |
0 |
T136 |
160634 |
256 |
0 |
0 |
T137 |
98832 |
945 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4374 |
0 |
0 |
T75 |
6445 |
8 |
0 |
0 |
T93 |
12738 |
95 |
0 |
0 |
T104 |
117325 |
792 |
0 |
0 |
T105 |
3631 |
14 |
0 |
0 |
T110 |
4031 |
20 |
0 |
0 |
T133 |
75934 |
308 |
0 |
0 |
T134 |
12815 |
27 |
0 |
0 |
T135 |
61794 |
180 |
0 |
0 |
T136 |
160634 |
266 |
0 |
0 |
T137 |
98832 |
809 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4535 |
0 |
0 |
T75 |
6445 |
24 |
0 |
0 |
T93 |
12738 |
61 |
0 |
0 |
T104 |
117325 |
755 |
0 |
0 |
T116 |
4294 |
6 |
0 |
0 |
T133 |
75934 |
324 |
0 |
0 |
T134 |
12815 |
11 |
0 |
0 |
T135 |
61794 |
327 |
0 |
0 |
T136 |
160634 |
246 |
0 |
0 |
T137 |
98832 |
970 |
0 |
0 |
T138 |
6143 |
36 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4858 |
0 |
0 |
T75 |
6445 |
38 |
0 |
0 |
T93 |
12738 |
108 |
0 |
0 |
T104 |
117325 |
798 |
0 |
0 |
T105 |
3631 |
6 |
0 |
0 |
T110 |
4031 |
5 |
0 |
0 |
T133 |
75934 |
309 |
0 |
0 |
T134 |
12815 |
17 |
0 |
0 |
T135 |
61794 |
375 |
0 |
0 |
T136 |
160634 |
312 |
0 |
0 |
T137 |
98832 |
728 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4361 |
0 |
0 |
T75 |
6445 |
8 |
0 |
0 |
T93 |
12738 |
76 |
0 |
0 |
T104 |
117325 |
757 |
0 |
0 |
T105 |
3631 |
2 |
0 |
0 |
T110 |
4031 |
34 |
0 |
0 |
T133 |
75934 |
277 |
0 |
0 |
T134 |
12815 |
23 |
0 |
0 |
T135 |
61794 |
195 |
0 |
0 |
T136 |
160634 |
292 |
0 |
0 |
T137 |
98832 |
794 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4315 |
0 |
0 |
T75 |
6445 |
31 |
0 |
0 |
T93 |
12738 |
13 |
0 |
0 |
T104 |
117325 |
827 |
0 |
0 |
T105 |
3631 |
11 |
0 |
0 |
T110 |
4031 |
28 |
0 |
0 |
T133 |
75934 |
304 |
0 |
0 |
T134 |
12815 |
16 |
0 |
0 |
T135 |
61794 |
237 |
0 |
0 |
T136 |
160634 |
322 |
0 |
0 |
T137 |
98832 |
644 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4748 |
0 |
0 |
T75 |
6445 |
19 |
0 |
0 |
T93 |
12738 |
125 |
0 |
0 |
T104 |
117325 |
890 |
0 |
0 |
T105 |
3631 |
7 |
0 |
0 |
T110 |
4031 |
9 |
0 |
0 |
T133 |
75934 |
262 |
0 |
0 |
T134 |
12815 |
31 |
0 |
0 |
T135 |
61794 |
296 |
0 |
0 |
T136 |
160634 |
265 |
0 |
0 |
T137 |
98832 |
699 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4320 |
0 |
0 |
T82 |
14050 |
3 |
0 |
0 |
T93 |
12738 |
11 |
0 |
0 |
T104 |
117325 |
769 |
0 |
0 |
T105 |
3631 |
12 |
0 |
0 |
T116 |
4294 |
36 |
0 |
0 |
T133 |
75934 |
268 |
0 |
0 |
T134 |
12815 |
16 |
0 |
0 |
T135 |
61794 |
289 |
0 |
0 |
T136 |
160634 |
286 |
0 |
0 |
T137 |
98832 |
752 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4601 |
0 |
0 |
T75 |
6445 |
7 |
0 |
0 |
T93 |
12738 |
79 |
0 |
0 |
T104 |
117325 |
775 |
0 |
0 |
T105 |
3631 |
6 |
0 |
0 |
T116 |
4294 |
2 |
0 |
0 |
T133 |
75934 |
308 |
0 |
0 |
T134 |
12815 |
44 |
0 |
0 |
T135 |
61794 |
219 |
0 |
0 |
T136 |
160634 |
247 |
0 |
0 |
T137 |
98832 |
699 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4506 |
0 |
0 |
T75 |
6445 |
38 |
0 |
0 |
T93 |
12738 |
80 |
0 |
0 |
T104 |
117325 |
712 |
0 |
0 |
T105 |
3631 |
15 |
0 |
0 |
T110 |
4031 |
20 |
0 |
0 |
T133 |
75934 |
250 |
0 |
0 |
T134 |
12815 |
30 |
0 |
0 |
T135 |
61794 |
265 |
0 |
0 |
T136 |
160634 |
242 |
0 |
0 |
T137 |
98832 |
789 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4561 |
0 |
0 |
T75 |
6445 |
3 |
0 |
0 |
T93 |
12738 |
28 |
0 |
0 |
T104 |
117325 |
795 |
0 |
0 |
T105 |
3631 |
12 |
0 |
0 |
T116 |
4294 |
55 |
0 |
0 |
T133 |
75934 |
200 |
0 |
0 |
T134 |
12815 |
1 |
0 |
0 |
T135 |
61794 |
271 |
0 |
0 |
T136 |
160634 |
263 |
0 |
0 |
T137 |
98832 |
916 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4646 |
0 |
0 |
T75 |
6445 |
22 |
0 |
0 |
T93 |
12738 |
37 |
0 |
0 |
T104 |
117325 |
833 |
0 |
0 |
T105 |
3631 |
5 |
0 |
0 |
T116 |
4294 |
3 |
0 |
0 |
T133 |
75934 |
281 |
0 |
0 |
T134 |
12815 |
22 |
0 |
0 |
T135 |
61794 |
221 |
0 |
0 |
T136 |
160634 |
244 |
0 |
0 |
T137 |
98832 |
1095 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4190 |
0 |
0 |
T75 |
6445 |
4 |
0 |
0 |
T93 |
12738 |
95 |
0 |
0 |
T104 |
117325 |
749 |
0 |
0 |
T105 |
3631 |
2 |
0 |
0 |
T110 |
4031 |
5 |
0 |
0 |
T133 |
75934 |
290 |
0 |
0 |
T134 |
12815 |
18 |
0 |
0 |
T135 |
61794 |
282 |
0 |
0 |
T136 |
160634 |
235 |
0 |
0 |
T137 |
98832 |
776 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4971 |
0 |
0 |
T75 |
6445 |
31 |
0 |
0 |
T93 |
12738 |
106 |
0 |
0 |
T104 |
117325 |
812 |
0 |
0 |
T105 |
3631 |
6 |
0 |
0 |
T110 |
4031 |
16 |
0 |
0 |
T133 |
75934 |
280 |
0 |
0 |
T134 |
12815 |
10 |
0 |
0 |
T135 |
61794 |
310 |
0 |
0 |
T136 |
160634 |
273 |
0 |
0 |
T137 |
98832 |
1031 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4605 |
0 |
0 |
T75 |
6445 |
1 |
0 |
0 |
T93 |
12738 |
13 |
0 |
0 |
T104 |
117325 |
785 |
0 |
0 |
T105 |
3631 |
15 |
0 |
0 |
T110 |
4031 |
5 |
0 |
0 |
T133 |
75934 |
255 |
0 |
0 |
T134 |
12815 |
51 |
0 |
0 |
T135 |
61794 |
336 |
0 |
0 |
T136 |
160634 |
246 |
0 |
0 |
T137 |
98832 |
961 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4457 |
0 |
0 |
T75 |
6445 |
8 |
0 |
0 |
T93 |
12738 |
108 |
0 |
0 |
T104 |
117325 |
828 |
0 |
0 |
T105 |
3631 |
6 |
0 |
0 |
T116 |
4294 |
1 |
0 |
0 |
T133 |
75934 |
265 |
0 |
0 |
T134 |
12815 |
22 |
0 |
0 |
T135 |
61794 |
249 |
0 |
0 |
T136 |
160634 |
291 |
0 |
0 |
T137 |
98832 |
746 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4343 |
0 |
0 |
T75 |
6445 |
4 |
0 |
0 |
T93 |
12738 |
8 |
0 |
0 |
T104 |
117325 |
829 |
0 |
0 |
T110 |
4031 |
14 |
0 |
0 |
T116 |
4294 |
42 |
0 |
0 |
T133 |
75934 |
293 |
0 |
0 |
T134 |
12815 |
28 |
0 |
0 |
T135 |
61794 |
184 |
0 |
0 |
T136 |
160634 |
227 |
0 |
0 |
T137 |
98832 |
776 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4208 |
0 |
0 |
T75 |
6445 |
31 |
0 |
0 |
T93 |
12738 |
54 |
0 |
0 |
T104 |
117325 |
763 |
0 |
0 |
T105 |
3631 |
7 |
0 |
0 |
T110 |
4031 |
28 |
0 |
0 |
T133 |
75934 |
228 |
0 |
0 |
T134 |
12815 |
27 |
0 |
0 |
T135 |
61794 |
288 |
0 |
0 |
T136 |
160634 |
311 |
0 |
0 |
T137 |
98832 |
827 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
3992 |
0 |
0 |
T75 |
6445 |
2 |
0 |
0 |
T93 |
12738 |
68 |
0 |
0 |
T104 |
117325 |
772 |
0 |
0 |
T105 |
3631 |
14 |
0 |
0 |
T110 |
4031 |
25 |
0 |
0 |
T133 |
75934 |
339 |
0 |
0 |
T134 |
12815 |
18 |
0 |
0 |
T135 |
61794 |
229 |
0 |
0 |
T136 |
160634 |
258 |
0 |
0 |
T137 |
98832 |
620 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4399 |
0 |
0 |
T75 |
6445 |
27 |
0 |
0 |
T93 |
12738 |
53 |
0 |
0 |
T104 |
117325 |
755 |
0 |
0 |
T105 |
3631 |
8 |
0 |
0 |
T116 |
4294 |
7 |
0 |
0 |
T133 |
75934 |
268 |
0 |
0 |
T134 |
12815 |
18 |
0 |
0 |
T135 |
61794 |
324 |
0 |
0 |
T136 |
160634 |
296 |
0 |
0 |
T137 |
98832 |
536 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4558 |
0 |
0 |
T75 |
6445 |
11 |
0 |
0 |
T93 |
12738 |
118 |
0 |
0 |
T104 |
117325 |
771 |
0 |
0 |
T105 |
3631 |
4 |
0 |
0 |
T110 |
4031 |
23 |
0 |
0 |
T133 |
75934 |
303 |
0 |
0 |
T134 |
12815 |
40 |
0 |
0 |
T135 |
61794 |
201 |
0 |
0 |
T136 |
160634 |
253 |
0 |
0 |
T137 |
98832 |
1048 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4625 |
0 |
0 |
T75 |
6445 |
45 |
0 |
0 |
T93 |
12738 |
65 |
0 |
0 |
T104 |
117325 |
872 |
0 |
0 |
T105 |
3631 |
2 |
0 |
0 |
T110 |
4031 |
35 |
0 |
0 |
T133 |
75934 |
263 |
0 |
0 |
T134 |
12815 |
21 |
0 |
0 |
T135 |
61794 |
217 |
0 |
0 |
T136 |
160634 |
253 |
0 |
0 |
T137 |
98832 |
785 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
4423 |
0 |
0 |
T75 |
6445 |
21 |
0 |
0 |
T93 |
12738 |
51 |
0 |
0 |
T104 |
117325 |
779 |
0 |
0 |
T105 |
3631 |
8 |
0 |
0 |
T110 |
4031 |
28 |
0 |
0 |
T133 |
75934 |
274 |
0 |
0 |
T134 |
12815 |
21 |
0 |
0 |
T135 |
61794 |
210 |
0 |
0 |
T136 |
160634 |
274 |
0 |
0 |
T137 |
98832 |
918 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2071 |
0 |
0 |
T93 |
12738 |
10 |
0 |
0 |
T104 |
117325 |
745 |
0 |
0 |
T105 |
3631 |
8 |
0 |
0 |
T110 |
4031 |
6 |
0 |
0 |
T116 |
4294 |
4 |
0 |
0 |
T133 |
75934 |
282 |
0 |
0 |
T134 |
12815 |
6 |
0 |
0 |
T135 |
61794 |
42 |
0 |
0 |
T136 |
160634 |
227 |
0 |
0 |
T137 |
98832 |
220 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2143 |
0 |
0 |
T93 |
12738 |
20 |
0 |
0 |
T104 |
117325 |
764 |
0 |
0 |
T105 |
3631 |
3 |
0 |
0 |
T110 |
4031 |
3 |
0 |
0 |
T116 |
4294 |
1 |
0 |
0 |
T133 |
75934 |
289 |
0 |
0 |
T134 |
12815 |
8 |
0 |
0 |
T135 |
61794 |
67 |
0 |
0 |
T136 |
160634 |
284 |
0 |
0 |
T137 |
98832 |
160 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2039 |
0 |
0 |
T93 |
12738 |
26 |
0 |
0 |
T104 |
117325 |
742 |
0 |
0 |
T105 |
3631 |
4 |
0 |
0 |
T110 |
4031 |
4 |
0 |
0 |
T116 |
4294 |
9 |
0 |
0 |
T133 |
75934 |
325 |
0 |
0 |
T134 |
12815 |
15 |
0 |
0 |
T135 |
61794 |
45 |
0 |
0 |
T136 |
160634 |
233 |
0 |
0 |
T137 |
98832 |
146 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2145 |
0 |
0 |
T75 |
6445 |
7 |
0 |
0 |
T93 |
12738 |
29 |
0 |
0 |
T104 |
117325 |
783 |
0 |
0 |
T105 |
3631 |
4 |
0 |
0 |
T110 |
4031 |
3 |
0 |
0 |
T133 |
75934 |
286 |
0 |
0 |
T134 |
12815 |
41 |
0 |
0 |
T135 |
61794 |
51 |
0 |
0 |
T136 |
160634 |
297 |
0 |
0 |
T137 |
98832 |
160 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2535 |
0 |
0 |
T93 |
12738 |
23 |
0 |
0 |
T104 |
117325 |
812 |
0 |
0 |
T105 |
3631 |
3 |
0 |
0 |
T110 |
4031 |
4 |
0 |
0 |
T116 |
4294 |
1 |
0 |
0 |
T133 |
75934 |
272 |
0 |
0 |
T134 |
12815 |
17 |
0 |
0 |
T135 |
61794 |
129 |
0 |
0 |
T136 |
160634 |
280 |
0 |
0 |
T137 |
98832 |
266 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
3732 |
0 |
0 |
T11 |
202200 |
11 |
0 |
0 |
T12 |
150813 |
0 |
0 |
0 |
T13 |
36161 |
0 |
0 |
0 |
T14 |
432542 |
0 |
0 |
0 |
T15 |
29119 |
0 |
0 |
0 |
T21 |
3178 |
0 |
0 |
0 |
T32 |
18259 |
0 |
0 |
0 |
T34 |
4679 |
0 |
0 |
0 |
T45 |
78158 |
0 |
0 |
0 |
T84 |
5182 |
0 |
0 |
0 |
T139 |
0 |
47 |
0 |
0 |
T140 |
0 |
21 |
0 |
0 |
T141 |
0 |
18 |
0 |
0 |
T142 |
0 |
44 |
0 |
0 |
T143 |
0 |
47 |
0 |
0 |
T144 |
0 |
7 |
0 |
0 |
T145 |
0 |
40 |
0 |
0 |
T146 |
0 |
29 |
0 |
0 |
T147 |
0 |
60 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2139 |
0 |
0 |
T75 |
6445 |
12 |
0 |
0 |
T93 |
12738 |
22 |
0 |
0 |
T104 |
117325 |
786 |
0 |
0 |
T105 |
3631 |
4 |
0 |
0 |
T110 |
4031 |
2 |
0 |
0 |
T133 |
75934 |
269 |
0 |
0 |
T134 |
12815 |
18 |
0 |
0 |
T135 |
61794 |
51 |
0 |
0 |
T136 |
160634 |
265 |
0 |
0 |
T137 |
98832 |
198 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2135 |
0 |
0 |
T75 |
6445 |
11 |
0 |
0 |
T92 |
18776 |
7 |
0 |
0 |
T93 |
12738 |
30 |
0 |
0 |
T104 |
117325 |
800 |
0 |
0 |
T105 |
3631 |
1 |
0 |
0 |
T110 |
4031 |
9 |
0 |
0 |
T133 |
75934 |
287 |
0 |
0 |
T134 |
12815 |
31 |
0 |
0 |
T135 |
61794 |
37 |
0 |
0 |
T136 |
160634 |
272 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2034 |
0 |
0 |
T75 |
6445 |
10 |
0 |
0 |
T93 |
12738 |
17 |
0 |
0 |
T104 |
117325 |
830 |
0 |
0 |
T105 |
3631 |
10 |
0 |
0 |
T116 |
4294 |
1 |
0 |
0 |
T133 |
75934 |
321 |
0 |
0 |
T134 |
12815 |
16 |
0 |
0 |
T135 |
61794 |
50 |
0 |
0 |
T136 |
160634 |
261 |
0 |
0 |
T137 |
98832 |
97 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
1975 |
0 |
0 |
T75 |
6445 |
2 |
0 |
0 |
T93 |
12738 |
10 |
0 |
0 |
T104 |
117325 |
825 |
0 |
0 |
T105 |
3631 |
1 |
0 |
0 |
T116 |
4294 |
1 |
0 |
0 |
T133 |
75934 |
293 |
0 |
0 |
T134 |
12815 |
17 |
0 |
0 |
T135 |
61794 |
33 |
0 |
0 |
T136 |
160634 |
263 |
0 |
0 |
T137 |
98832 |
99 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2010 |
0 |
0 |
T75 |
6445 |
4 |
0 |
0 |
T93 |
12738 |
12 |
0 |
0 |
T104 |
117325 |
766 |
0 |
0 |
T110 |
4031 |
5 |
0 |
0 |
T116 |
4294 |
3 |
0 |
0 |
T133 |
75934 |
310 |
0 |
0 |
T134 |
12815 |
9 |
0 |
0 |
T135 |
61794 |
40 |
0 |
0 |
T136 |
160634 |
321 |
0 |
0 |
T137 |
98832 |
110 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
1924 |
0 |
0 |
T75 |
6445 |
7 |
0 |
0 |
T93 |
12738 |
7 |
0 |
0 |
T104 |
117325 |
806 |
0 |
0 |
T105 |
3631 |
12 |
0 |
0 |
T110 |
4031 |
2 |
0 |
0 |
T133 |
75934 |
219 |
0 |
0 |
T134 |
12815 |
10 |
0 |
0 |
T135 |
61794 |
27 |
0 |
0 |
T136 |
160634 |
282 |
0 |
0 |
T137 |
98832 |
133 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2629 |
0 |
0 |
T75 |
6445 |
8 |
0 |
0 |
T93 |
12738 |
23 |
0 |
0 |
T104 |
117325 |
767 |
0 |
0 |
T105 |
3631 |
9 |
0 |
0 |
T116 |
4294 |
4 |
0 |
0 |
T133 |
75934 |
316 |
0 |
0 |
T134 |
12815 |
34 |
0 |
0 |
T135 |
61794 |
91 |
0 |
0 |
T136 |
160634 |
354 |
0 |
0 |
T137 |
98832 |
257 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2044 |
0 |
0 |
T75 |
6445 |
2 |
0 |
0 |
T93 |
12738 |
20 |
0 |
0 |
T104 |
117325 |
800 |
0 |
0 |
T105 |
3631 |
8 |
0 |
0 |
T116 |
4294 |
3 |
0 |
0 |
T133 |
75934 |
290 |
0 |
0 |
T134 |
12815 |
11 |
0 |
0 |
T135 |
61794 |
65 |
0 |
0 |
T136 |
160634 |
307 |
0 |
0 |
T137 |
98832 |
111 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2816 |
0 |
0 |
T75 |
6445 |
14 |
0 |
0 |
T93 |
12738 |
29 |
0 |
0 |
T104 |
117325 |
817 |
0 |
0 |
T105 |
3631 |
3 |
0 |
0 |
T116 |
4294 |
26 |
0 |
0 |
T133 |
75934 |
322 |
0 |
0 |
T135 |
61794 |
184 |
0 |
0 |
T136 |
160634 |
251 |
0 |
0 |
T137 |
98832 |
351 |
0 |
0 |
T138 |
6143 |
38 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2177 |
0 |
0 |
T75 |
6445 |
5 |
0 |
0 |
T93 |
12738 |
18 |
0 |
0 |
T104 |
117325 |
820 |
0 |
0 |
T105 |
3631 |
1 |
0 |
0 |
T110 |
4031 |
3 |
0 |
0 |
T133 |
75934 |
260 |
0 |
0 |
T134 |
12815 |
3 |
0 |
0 |
T135 |
61794 |
61 |
0 |
0 |
T136 |
160634 |
224 |
0 |
0 |
T137 |
98832 |
216 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2023 |
0 |
0 |
T75 |
6445 |
6 |
0 |
0 |
T93 |
12738 |
12 |
0 |
0 |
T104 |
117325 |
811 |
0 |
0 |
T105 |
3631 |
9 |
0 |
0 |
T116 |
4294 |
8 |
0 |
0 |
T133 |
75934 |
321 |
0 |
0 |
T134 |
12815 |
11 |
0 |
0 |
T135 |
61794 |
27 |
0 |
0 |
T136 |
160634 |
312 |
0 |
0 |
T137 |
98832 |
110 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
1898 |
0 |
0 |
T92 |
18776 |
5 |
0 |
0 |
T93 |
12738 |
23 |
0 |
0 |
T104 |
117325 |
786 |
0 |
0 |
T116 |
4294 |
3 |
0 |
0 |
T133 |
75934 |
277 |
0 |
0 |
T134 |
12815 |
15 |
0 |
0 |
T135 |
61794 |
42 |
0 |
0 |
T136 |
160634 |
276 |
0 |
0 |
T137 |
98832 |
124 |
0 |
0 |
T138 |
6143 |
4 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
2031 |
0 |
0 |
T75 |
6445 |
4 |
0 |
0 |
T93 |
12738 |
11 |
0 |
0 |
T104 |
117325 |
867 |
0 |
0 |
T105 |
3631 |
4 |
0 |
0 |
T110 |
4031 |
3 |
0 |
0 |
T133 |
75934 |
300 |
0 |
0 |
T134 |
12815 |
5 |
0 |
0 |
T135 |
61794 |
52 |
0 |
0 |
T136 |
160634 |
252 |
0 |
0 |
T137 |
98832 |
133 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
1938 |
0 |
0 |
T82 |
14050 |
7 |
0 |
0 |
T93 |
12738 |
9 |
0 |
0 |
T104 |
117325 |
815 |
0 |
0 |
T105 |
3631 |
15 |
0 |
0 |
T116 |
4294 |
2 |
0 |
0 |
T133 |
75934 |
314 |
0 |
0 |
T134 |
12815 |
28 |
0 |
0 |
T135 |
61794 |
48 |
0 |
0 |
T136 |
160634 |
244 |
0 |
0 |
T137 |
98832 |
137 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
1695 |
0 |
0 |
T75 |
6445 |
5 |
0 |
0 |
T93 |
12738 |
14 |
0 |
0 |
T104 |
117325 |
692 |
0 |
0 |
T105 |
3631 |
1 |
0 |
0 |
T133 |
75934 |
239 |
0 |
0 |
T134 |
12815 |
22 |
0 |
0 |
T135 |
61794 |
23 |
0 |
0 |
T136 |
160634 |
215 |
0 |
0 |
T137 |
98832 |
132 |
0 |
0 |
T138 |
6143 |
10 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
587149954 |
1899 |
0 |
0 |
T75 |
6445 |
6 |
0 |
0 |
T93 |
12738 |
11 |
0 |
0 |
T104 |
117325 |
750 |
0 |
0 |
T105 |
3631 |
8 |
0 |
0 |
T116 |
4294 |
1 |
0 |
0 |
T133 |
75934 |
343 |
0 |
0 |
T134 |
12815 |
17 |
0 |
0 |
T135 |
61794 |
36 |
0 |
0 |
T136 |
160634 |
240 |
0 |
0 |
T137 |
98832 |
132 |
0 |
0 |