Unified Coverage Report :: Module :: spi_cmdparse

Module : spi_cmdparse

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.74	100.00	87.80		100.00	95.92	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cmdparse	96.74	100.00	87.80		100.00	95.92	100.00

---

Module Instance : tb.dut.u_cmdparse

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.74	100.00	87.80		100.00	95.92	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.74	100.00	87.80		100.00	95.92	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	95.11	86.84	96.92		88.89	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_cmdparse

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
CONT_ASSIGN	81	1	1	100.00
ALWAYS	86	3	3	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
ALWAYS	181	4	4	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	204	4	4	100.00
ALWAYS	223	6	6	100.00
ALWAYS	238	7	7	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
ALWAYS	268	5	5	100.00
CONT_ASSIGN	284	1	1	100.00
ALWAYS	288	11	11	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
ALWAYS	312	4	4	100.00
ALWAYS	320	48	48	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	1	1
86	1	1
87	1	1
88	1	1
152	1	1
156	1	1
181	1	1
182	1	1
183	1	1
185	1	1
			MISSING_ELSE
190	1	1
192	1	1
194	1	1
196	1	1
198	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
223	1	1
224	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
238	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
			MISSING_ELSE
258	1	1
259	1	1
268	1	1
274	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
284	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
293	2	2
			MISSING_ELSE
294	2	2
			MISSING_ELSE
295	2	2
			MISSING_ELSE
			MISSING_ELSE
300	1	1
307	1	1
308	1	1
309	1	1
312	1	1
313	1	1
314	1	1
315	1	1
			==> MISSING_ELSE
320	1	1
322	1	1
323	1	1
325	1	1
326	1	1
328	1	1
330	1	1
332	1	1
334	1	1
335	1	1
337	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
345	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
356	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
369	1	1
377	1	1
381	1	1
382	1	1
386	1	1
389	1	1
393	1	1
396	1	1
406	1	1
408	1	1
409	1	1
			MISSING_ELSE
414	1	1
416	1	1
418	1	1
420	1	1
422	1	1
424	1	1
426	1	1
429	1	1
431	1	1

---

Cond Coverage for Module : spi_cmdparse

	Total	Covered	Percent
Conditions	82	72	87.80
Logical	82	72	87.80
Non-Logical	0	0
Event	0	0

 LINE       183
 EXPRESSION (cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode))
             ---------------------1--------------------    ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       183
 SUB-EXPRESSION (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)
                ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       190
 EXPRESSION (cmd_info_i[CmdInfoReadJedecId].valid && (data_i == cmd_info_i[CmdInfoReadJedecId].opcode))
             ------------------1-----------------    ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

 LINE       190
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadJedecId].opcode)
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       192
 EXPRESSION (cmd_info_i[CmdInfoReadSfdp].valid && (data_i == cmd_info_i[CmdInfoReadSfdp].opcode))
             ----------------1----------------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

 LINE       192
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadSfdp].opcode)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       194
 EXPRESSION (cmd_info_i[CmdInfoEn4B].valid && (data_i == cmd_info_i[CmdInfoEn4B].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

 LINE       194
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEn4B].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       196
 EXPRESSION (cmd_info_i[CmdInfoEx4B].valid && (data_i == cmd_info_i[CmdInfoEx4B].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

 LINE       196
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEx4B].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       198
 EXPRESSION (cmd_info_i[CmdInfoWrEn].valid && (data_i == cmd_info_i[CmdInfoWrEn].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

 LINE       198
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrEn].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       200
 EXPRESSION (cmd_info_i[CmdInfoWrDi].valid && (data_i == cmd_info_i[CmdInfoWrDi].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

 LINE       200
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrDi].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       206
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       206
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       245
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T5,T6

 LINE       245
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T12
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       247
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       276
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T5,T6

 LINE       276
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       300
 EXPRESSION ((cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle) || (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle))
             -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       300
 SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle)
                -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       300
 SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle)
                -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       307
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       308
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       309
 EXPRESSION (in_flashmode || in_passthrough)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       332
 EXPRESSION (module_active && data_valid_i && cmd_info_d.valid)
             ------1------    ------2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T5,T7
1	1	1	Covered	T1,T5,T6

 LINE       389
 EXPRESSION (opcode_en4b ? DpEn4B : DpEx4B)
             -----1-----

-1-	Status	Tests
0	Covered	T5,T8,T11
1	Covered	T5,T8,T11

 LINE       396
 EXPRESSION (opcode_wren ? DpWrEn : DpWrDi)
             -----1-----

-1-	Status	Tests
0	Covered	T5,T8,T11
1	Covered	T5,T8,T11

 LINE       406
 EXPRESSION (module_active && data_valid_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T7

---

FSM Coverage for Module : spi_cmdparse

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAddr4B	386	Covered	T5,T8,T11
StIdle	245	Covered	T1,T2,T3
StJedec	351	Covered	T5,T8,T45
StReadCmd	377	Covered	T1,T5,T6
StSfdp	363	Covered	T5,T8,T11
StStatus	340	Covered	T5,T7,T8
StUpload	381	Covered	T5,T8,T11
StWait	345	Covered	T1,T5,T6
StWrEn	393	Covered	T5,T8,T11

transitions	Line No.	Covered	Tests
StIdle->StAddr4B	386	Covered	T5,T8,T11
StIdle->StJedec	351	Covered	T5,T8,T45
StIdle->StReadCmd	377	Covered	T1,T5,T6
StIdle->StSfdp	363	Covered	T5,T8,T11
StIdle->StStatus	340	Covered	T5,T7,T8
StIdle->StUpload	381	Covered	T5,T8,T11
StIdle->StWait	345	Covered	T1,T5,T6
StIdle->StWrEn	393	Covered	T5,T8,T11

---

Branch Coverage for Module : spi_cmdparse

	Line No.	Total	Covered	Percent
Branches		49	47	95.92
IF	183	2	2	100.00
IF	206	2	2	100.00
IF	223	3	3	100.00
IF	245	2	2	100.00
IF	276	2	2	100.00
IF	288	8	8	100.00
IF	312	3	2	66.67
CASE	330	27	26	96.30

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	if ((cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode)))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	if ((!rst_ni))
-2-:	231	if (latch_cmdinfo)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	245	if ((((st == StIdle) && module_active) && data_valid_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	276	if ((((st == StIdle) && module_active) && data_valid_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))
-2-:	292	if (intercept_d)
-3-:	293	if (opcode_readstatus)
-4-:	294	if (opcode_readjedec)
-5-:	295	if (opcode_readsfdp)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	Covered	T5,T7,T8
0	1	0	-	-	Covered	T5,T8,T11
0	1	-	1	-	Covered	T5,T8,T45
0	1	-	0	-	Covered	T5,T7,T8
0	1	-	-	1	Covered	T5,T8,T11
0	1	-	-	0	Covered	T5,T7,T8
0	0	-	-	-	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	312	if ((!rst_ni))
-2-:	314	if (module_active)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	330	case (st)
-2-:	332	if (((module_active && data_valid_i) && cmd_info_d.valid))
-3-:	337	case (1'b1)
-4-:	339	if (in_flashmode)
-5-:	341	if (cfg_intercept_en_status_i)
-6-:	350	if (in_flashmode)
-7-:	352	if (cfg_intercept_en_jedec_i)
-8-:	362	if (in_flashmode)
-9-:	364	if (cfg_intercept_en_sfdp_i)
-10-:	389	(opcode_en4b) ? 
-11-:	396	(opcode_wren) ? 
-12-:	406	if ((module_active && data_valid_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
StIdle	1	opcode_readstatus	1	-	-	-	-	-	-	-	-	Covered	T14,T16,T24
StIdle	1	opcode_readstatus	0	1	-	-	-	-	-	-	-	Covered	T5,T7,T8
StIdle	1	opcode_readstatus	0	0	-	-	-	-	-	-	-	Covered	T12,T34,T72
StIdle	1	opcode_readjedec	-	-	1	-	-	-	-	-	-	Covered	T14,T16,T24
StIdle	1	opcode_readjedec	-	-	0	1	-	-	-	-	-	Covered	T5,T8,T45
StIdle	1	opcode_readjedec	-	-	0	0	-	-	-	-	-	Covered	T5,T7,T8
StIdle	1	opcode_readsfdp	-	-	-	-	1	-	-	-	-	Covered	T14,T16,T24
StIdle	1	opcode_readsfdp	-	-	-	-	0	1	-	-	-	Covered	T5,T8,T11
StIdle	1	opcode_readsfdp	-	-	-	-	0	0	-	-	-	Covered	T5,T8,T11
StIdle	1	opcode_readcmd	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
StIdle	1	upload	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T11
StIdle	1	opcode_en4b opcode_ex4b	-	-	-	-	-	-	1	-	-	Covered	T5,T8,T11
StIdle	1	opcode_en4b opcode_ex4b	-	-	-	-	-	-	0	-	-	Covered	T5,T8,T11
StIdle	1	opcode_wren opcode_wrdi	-	-	-	-	-	-	-	1	-	Covered	T5,T8,T11
StIdle	1	opcode_wren opcode_wrdi	-	-	-	-	-	-	-	0	-	Covered	T5,T8,T11
StIdle	1	default	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
StIdle	0	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T7
StIdle	0	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StStatus	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T8
StJedec	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T45
StSfdp	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T11
StReadCmd	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
StUpload	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T11
StAddr4B	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T11
StWrEn	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T11
StWait	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_cmdparse

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CmdOnlySelDpKnown_A	184883524	143843844	0	0
OnlyOneDatapath_A	184883524	71130	0	0
SelDpKnown_A	184883524	143843844	0	0
StKnown_A	184883524	143843844	0	0

CmdOnlySelDpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	143843844	0	0
T1	96124	95721	0	0
T2	792	0	0	0
T5	778957	637424	0	0
T6	9392	9392	0	0
T7	250840	250840	0	0
T8	745341	743026	0	0
T9	8288	8288	0	0
T10	152272	152272	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

OnlyOneDatapath_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	71130	0	0
T1	96124	26	0	0
T2	792	0	0	0
T5	778957	264	0	0
T6	9392	4	0	0
T7	250840	38	0	0
T8	745341	463	0	0
T9	8288	2	0	0
T10	152272	18	0	0
T11	939211	225	0	0
T12	49339	16	0	0
T13	0	34	0	0

SelDpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	143843844	0	0
T1	96124	95721	0	0
T2	792	0	0	0
T5	778957	637424	0	0
T6	9392	9392	0	0
T7	250840	250840	0	0
T8	745341	743026	0	0
T9	8288	8288	0	0
T10	152272	152272	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0

StKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184883524	143843844	0	0
T1	96124	95721	0	0
T2	792	0	0	0
T5	778957	637424	0	0
T6	9392	9392	0	0
T7	250840	250840	0	0
T8	745341	743026	0	0
T9	8288	8288	0	0
T10	152272	152272	0	0
T11	939211	698213	0	0
T12	49339	49156	0	0
T13	0	15312	0	0