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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 98.50 94.91 98.60 89.36 97.31 96.40 98.19


Total test records in report: 1105
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T1020 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4187256805 Feb 21 12:41:34 PM PST 24 Feb 21 12:41:35 PM PST 24 52056048 ps
T1021 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1518064151 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:07 PM PST 24 44003816 ps
T87 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3367289614 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:26 PM PST 24 126703604 ps
T1022 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.96668484 Feb 21 12:41:16 PM PST 24 Feb 21 12:41:18 PM PST 24 168106384 ps
T161 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3214095473 Feb 21 12:41:34 PM PST 24 Feb 21 12:41:56 PM PST 24 5392057842 ps
T1023 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2149883084 Feb 21 12:41:59 PM PST 24 Feb 21 12:42:01 PM PST 24 15151158 ps
T1024 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1832550758 Feb 21 12:41:02 PM PST 24 Feb 21 12:41:19 PM PST 24 1284567661 ps
T93 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2290253282 Feb 21 12:41:19 PM PST 24 Feb 21 12:41:23 PM PST 24 127407523 ps
T137 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3769342169 Feb 21 12:41:08 PM PST 24 Feb 21 12:41:30 PM PST 24 5490820238 ps
T113 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1987089599 Feb 21 12:41:30 PM PST 24 Feb 21 12:41:46 PM PST 24 212639964 ps
T114 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4030734512 Feb 21 12:41:26 PM PST 24 Feb 21 12:41:28 PM PST 24 41843679 ps
T1025 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2545626658 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:56 PM PST 24 26505713 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.780025764 Feb 21 12:41:07 PM PST 24 Feb 21 12:41:39 PM PST 24 1985559238 ps
T94 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3716064916 Feb 21 12:41:51 PM PST 24 Feb 21 12:41:53 PM PST 24 92534097 ps
T116 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1036932544 Feb 21 12:41:05 PM PST 24 Feb 21 12:41:07 PM PST 24 42970989 ps
T1026 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3534092925 Feb 21 12:41:46 PM PST 24 Feb 21 12:41:47 PM PST 24 15837695 ps
T138 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.115291026 Feb 21 12:41:21 PM PST 24 Feb 21 12:41:23 PM PST 24 127997730 ps
T1027 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2249349605 Feb 21 12:43:46 PM PST 24 Feb 21 12:43:50 PM PST 24 15504546 ps
T1028 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3496530854 Feb 21 12:41:18 PM PST 24 Feb 21 12:41:19 PM PST 24 15281395 ps
T1029 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2028624673 Feb 21 12:41:19 PM PST 24 Feb 21 12:41:21 PM PST 24 91343483 ps
T1030 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1348613585 Feb 21 12:41:24 PM PST 24 Feb 21 12:41:25 PM PST 24 37172563 ps
T90 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.223143649 Feb 21 12:41:04 PM PST 24 Feb 21 12:41:07 PM PST 24 382287411 ps
T1031 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2735232893 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:27 PM PST 24 284128506 ps
T1032 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1802274047 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:57 PM PST 24 57467803 ps
T1033 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.756647335 Feb 21 12:41:25 PM PST 24 Feb 21 12:41:28 PM PST 24 151577242 ps
T88 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1551344643 Feb 21 12:41:00 PM PST 24 Feb 21 12:41:05 PM PST 24 97301827 ps
T96 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2744413923 Feb 21 12:41:27 PM PST 24 Feb 21 12:41:29 PM PST 24 51803564 ps
T1034 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3624875956 Feb 21 12:41:51 PM PST 24 Feb 21 12:41:52 PM PST 24 13745767 ps
T1035 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1189031918 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:32 PM PST 24 1891825749 ps
T95 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3586298758 Feb 21 12:41:14 PM PST 24 Feb 21 12:41:17 PM PST 24 432252690 ps
T1036 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3007613241 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:26 PM PST 24 182682141 ps
T91 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1225298356 Feb 21 12:41:22 PM PST 24 Feb 21 12:41:27 PM PST 24 2483802720 ps
T1037 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1193689344 Feb 21 12:41:24 PM PST 24 Feb 21 12:41:27 PM PST 24 363704580 ps
T1038 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.702715361 Feb 21 12:41:25 PM PST 24 Feb 21 12:41:27 PM PST 24 107411186 ps
T1039 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2593932173 Feb 21 12:41:54 PM PST 24 Feb 21 12:42:01 PM PST 24 17484753 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1110251914 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:25 PM PST 24 63887401 ps
T162 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2657018564 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:39 PM PST 24 778726704 ps
T1041 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4126002518 Feb 21 12:41:44 PM PST 24 Feb 21 12:41:50 PM PST 24 224786813 ps
T1042 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1385297502 Feb 21 12:41:05 PM PST 24 Feb 21 12:41:07 PM PST 24 92599603 ps
T159 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4150078211 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:58 PM PST 24 238332638 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.672761412 Feb 21 12:41:02 PM PST 24 Feb 21 12:41:06 PM PST 24 763321480 ps
T1044 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2890648436 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:06 PM PST 24 14800908 ps
T1045 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4074115530 Feb 21 12:41:22 PM PST 24 Feb 21 12:41:25 PM PST 24 251361567 ps
T1046 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1113031314 Feb 21 12:41:25 PM PST 24 Feb 21 12:41:26 PM PST 24 25813560 ps
T1047 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1990576054 Feb 21 12:41:27 PM PST 24 Feb 21 12:41:35 PM PST 24 279792577 ps
T1048 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1030166434 Feb 21 12:41:34 PM PST 24 Feb 21 12:41:37 PM PST 24 45734910 ps
T1049 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3576645547 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:25 PM PST 24 24166285 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1189957771 Feb 21 12:41:26 PM PST 24 Feb 21 12:41:29 PM PST 24 65089831 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1595224976 Feb 21 12:41:20 PM PST 24 Feb 21 12:41:23 PM PST 24 45511298 ps
T1052 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.251728513 Feb 21 12:41:29 PM PST 24 Feb 21 12:41:37 PM PST 24 238810755 ps
T1053 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1255228326 Feb 21 12:41:00 PM PST 24 Feb 21 12:41:02 PM PST 24 19041774 ps
T1054 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.891971926 Feb 21 12:41:21 PM PST 24 Feb 21 12:41:24 PM PST 24 146317280 ps
T1055 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4135755055 Feb 21 12:43:41 PM PST 24 Feb 21 12:43:42 PM PST 24 17998697 ps
T1056 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1368771873 Feb 21 12:43:19 PM PST 24 Feb 21 12:43:20 PM PST 24 31212211 ps
T1057 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3061744877 Feb 21 12:41:58 PM PST 24 Feb 21 12:42:00 PM PST 24 39089324 ps
T1058 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.884326969 Feb 21 12:42:13 PM PST 24 Feb 21 12:42:15 PM PST 24 29120197 ps
T1059 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.450960671 Feb 21 12:41:40 PM PST 24 Feb 21 12:41:52 PM PST 24 37197709 ps
T163 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3622050024 Feb 21 12:41:24 PM PST 24 Feb 21 12:41:39 PM PST 24 2809766490 ps
T1060 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.265353852 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:57 PM PST 24 31056949 ps
T1061 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3316537389 Feb 21 12:41:24 PM PST 24 Feb 21 12:41:27 PM PST 24 86987887 ps
T1062 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1365235541 Feb 21 12:41:26 PM PST 24 Feb 21 12:41:31 PM PST 24 655242624 ps
T1063 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1768531910 Feb 21 12:41:11 PM PST 24 Feb 21 12:41:19 PM PST 24 1238603666 ps
T1064 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2830850764 Feb 21 12:41:53 PM PST 24 Feb 21 12:41:54 PM PST 24 14210988 ps
T1065 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2580451889 Feb 21 12:41:17 PM PST 24 Feb 21 12:41:20 PM PST 24 325812886 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4276466163 Feb 21 12:41:26 PM PST 24 Feb 21 12:41:30 PM PST 24 321799322 ps
T1067 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2257338339 Feb 21 12:41:01 PM PST 24 Feb 21 12:41:03 PM PST 24 11955483 ps
T1068 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.408419535 Feb 21 12:41:20 PM PST 24 Feb 21 12:41:24 PM PST 24 513015479 ps
T1069 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1059775165 Feb 21 12:41:26 PM PST 24 Feb 21 12:41:30 PM PST 24 138012798 ps
T1070 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.718272089 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:28 PM PST 24 151091034 ps
T1071 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1190779842 Feb 21 12:41:26 PM PST 24 Feb 21 12:41:28 PM PST 24 34798676 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2796042940 Feb 21 12:41:24 PM PST 24 Feb 21 12:41:25 PM PST 24 24943835 ps
T1073 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2674864828 Feb 21 12:41:20 PM PST 24 Feb 21 12:41:24 PM PST 24 336146225 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1265120096 Feb 21 12:41:17 PM PST 24 Feb 21 12:41:22 PM PST 24 187686120 ps
T1075 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1992926972 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:55 PM PST 24 14957922 ps
T164 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2157448733 Feb 21 12:41:04 PM PST 24 Feb 21 12:41:19 PM PST 24 533992283 ps
T1076 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2255570598 Feb 21 12:41:27 PM PST 24 Feb 21 12:41:32 PM PST 24 211467875 ps
T1077 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3359964214 Feb 21 12:41:20 PM PST 24 Feb 21 12:41:25 PM PST 24 108264011 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1282153529 Feb 21 12:41:03 PM PST 24 Feb 21 12:41:05 PM PST 24 204869491 ps
T1079 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1526227891 Feb 21 12:41:45 PM PST 24 Feb 21 12:41:46 PM PST 24 15031112 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3400044913 Feb 21 12:41:22 PM PST 24 Feb 21 12:41:24 PM PST 24 98971825 ps
T1081 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3600122373 Feb 21 12:41:17 PM PST 24 Feb 21 12:41:20 PM PST 24 388726839 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2372198691 Feb 21 12:41:08 PM PST 24 Feb 21 12:41:11 PM PST 24 918329878 ps
T1083 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3590457226 Feb 21 12:41:30 PM PST 24 Feb 21 12:41:33 PM PST 24 70304361 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1614420187 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:26 PM PST 24 165042267 ps
T1085 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3458847044 Feb 21 12:41:09 PM PST 24 Feb 21 12:41:15 PM PST 24 1202560148 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1306955175 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:31 PM PST 24 332951511 ps
T1087 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3131165819 Feb 21 12:41:45 PM PST 24 Feb 21 12:41:51 PM PST 24 3891927389 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3140601438 Feb 21 12:41:14 PM PST 24 Feb 21 12:41:19 PM PST 24 79092048 ps
T1089 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.574702192 Feb 21 12:41:33 PM PST 24 Feb 21 12:41:36 PM PST 24 48318798 ps
T1090 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3273773746 Feb 21 12:41:33 PM PST 24 Feb 21 12:41:34 PM PST 24 14668970 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.161114172 Feb 21 12:41:29 PM PST 24 Feb 21 12:41:33 PM PST 24 45836654 ps
T1092 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1152432787 Feb 21 12:41:19 PM PST 24 Feb 21 12:41:22 PM PST 24 27895422 ps
T1093 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4142144151 Feb 21 12:41:22 PM PST 24 Feb 21 12:41:28 PM PST 24 200573084 ps
T1094 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2701849832 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:57 PM PST 24 102088426 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4024815176 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:10 PM PST 24 213231625 ps
T1096 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4075221379 Feb 21 12:41:45 PM PST 24 Feb 21 12:41:49 PM PST 24 47644324 ps
T1097 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2879962649 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:08 PM PST 24 15860683 ps
T1098 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.803575016 Feb 21 12:41:33 PM PST 24 Feb 21 12:41:36 PM PST 24 413713640 ps
T1099 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3563912707 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:56 PM PST 24 11968761 ps
T1100 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3633147508 Feb 21 12:41:23 PM PST 24 Feb 21 12:41:28 PM PST 24 185716906 ps
T1101 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.618092202 Feb 21 12:41:12 PM PST 24 Feb 21 12:41:15 PM PST 24 166979422 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1927434313 Feb 21 12:41:32 PM PST 24 Feb 21 12:41:33 PM PST 24 13198543 ps
T1103 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2295871633 Feb 21 12:41:22 PM PST 24 Feb 21 12:41:24 PM PST 24 23084930 ps
T1104 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.529309570 Feb 21 12:41:11 PM PST 24 Feb 21 12:41:13 PM PST 24 58001061 ps
T1105 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.147095344 Feb 21 12:41:16 PM PST 24 Feb 21 12:41:17 PM PST 24 21672970 ps

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.935160590
Short name T5
Test name
Test status
Simulation time 88378376718 ps
CPU time 106.4 seconds
Started Feb 21 02:27:03 PM PST 24
Finished Feb 21 02:28:50 PM PST 24
Peak memory 253480 kb
Host smart-c2329709-3d84-4972-b245-0b1fd0e54d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935160590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.935160590
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3529470609
Short name T11
Test name
Test status
Simulation time 20220079522 ps
CPU time 181.84 seconds
Started Feb 21 02:27:40 PM PST 24
Finished Feb 21 02:30:43 PM PST 24
Peak memory 257480 kb
Host smart-5428f6f2-3d30-4d67-b866-4707bdd7b7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529470609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3529470609
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.293274043
Short name T16
Test name
Test status
Simulation time 23729005718 ps
CPU time 167.49 seconds
Started Feb 21 02:23:45 PM PST 24
Finished Feb 21 02:26:33 PM PST 24
Peak memory 272796 kb
Host smart-cbd8357b-1c15-4871-9c0c-6ed8f6325e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293274043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.293274043
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3815863514
Short name T75
Test name
Test status
Simulation time 322342059 ps
CPU time 2.01 seconds
Started Feb 21 12:41:13 PM PST 24
Finished Feb 21 12:41:18 PM PST 24
Peak memory 213868 kb
Host smart-893d3c69-10e1-4bb9-8842-ac407aadc15e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815863514 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3815863514
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1233167219
Short name T30
Test name
Test status
Simulation time 854459730802 ps
CPU time 393.66 seconds
Started Feb 21 02:23:04 PM PST 24
Finished Feb 21 02:29:38 PM PST 24
Peak memory 253656 kb
Host smart-d67a97ae-c28f-4da7-bdcf-78b53013b202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233167219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1233167219
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3142739573
Short name T44
Test name
Test status
Simulation time 53499657 ps
CPU time 0.72 seconds
Started Feb 21 02:21:13 PM PST 24
Finished Feb 21 02:21:14 PM PST 24
Peak memory 216348 kb
Host smart-8fd86a84-f10c-4623-ba50-b8fe5845e8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142739573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3142739573
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3044506792
Short name T29
Test name
Test status
Simulation time 77659348603 ps
CPU time 529.73 seconds
Started Feb 21 02:23:40 PM PST 24
Finished Feb 21 02:32:31 PM PST 24
Peak memory 256180 kb
Host smart-043f22b4-e2e3-4d05-b267-def79ebe7708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044506792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3044506792
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2398279865
Short name T168
Test name
Test status
Simulation time 114119471043 ps
CPU time 816 seconds
Started Feb 21 02:25:53 PM PST 24
Finished Feb 21 02:39:30 PM PST 24
Peak memory 283736 kb
Host smart-5bcba204-9ac7-45d0-955b-3009d0d55959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398279865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2398279865
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.382645272
Short name T38
Test name
Test status
Simulation time 127445563 ps
CPU time 1.28 seconds
Started Feb 21 02:21:51 PM PST 24
Finished Feb 21 02:21:53 PM PST 24
Peak memory 235960 kb
Host smart-40200c9f-c282-4594-9ef3-c29eecf6ec40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382645272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.382645272
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2181419564
Short name T104
Test name
Test status
Simulation time 11732769947 ps
CPU time 25.52 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:53 PM PST 24
Peak memory 206832 kb
Host smart-07a378de-491b-4435-8903-a9f65b2b9c9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181419564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2181419564
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.782697125
Short name T141
Test name
Test status
Simulation time 43540199792 ps
CPU time 351.22 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:29:36 PM PST 24
Peak memory 273396 kb
Host smart-6f337be7-bde9-4f64-ab29-3a4dcf7527d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782697125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.782697125
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3511329822
Short name T123
Test name
Test status
Simulation time 621366800 ps
CPU time 11.28 seconds
Started Feb 21 02:25:59 PM PST 24
Finished Feb 21 02:26:10 PM PST 24
Peak memory 240292 kb
Host smart-152936c7-878c-4e79-8da8-e62d0fff5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511329822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3511329822
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.640468208
Short name T118
Test name
Test status
Simulation time 6828351130 ps
CPU time 113.31 seconds
Started Feb 21 02:25:15 PM PST 24
Finished Feb 21 02:27:08 PM PST 24
Peak memory 264856 kb
Host smart-76ec2dfa-3b8f-4f7f-97d6-85d361832785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640468208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.640468208
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.873555031
Short name T178
Test name
Test status
Simulation time 38355850569 ps
CPU time 247.33 seconds
Started Feb 21 02:26:12 PM PST 24
Finished Feb 21 02:30:20 PM PST 24
Peak memory 298120 kb
Host smart-f0d17c5b-83cd-4f68-a7b7-b98246e4705c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873555031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.873555031
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2808756055
Short name T99
Test name
Test status
Simulation time 6670498127 ps
CPU time 13.28 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:42:03 PM PST 24
Peak memory 215188 kb
Host smart-123085fa-0181-4c44-9109-092173843d75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808756055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2808756055
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3146714950
Short name T31
Test name
Test status
Simulation time 285109136268 ps
CPU time 384 seconds
Started Feb 21 02:23:02 PM PST 24
Finished Feb 21 02:29:27 PM PST 24
Peak memory 264540 kb
Host smart-cf0220fb-73df-4b43-b9e2-e4bac9bff70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146714950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3146714950
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1246741332
Short name T92
Test name
Test status
Simulation time 193582219 ps
CPU time 4.63 seconds
Started Feb 21 12:41:14 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 214428 kb
Host smart-bddf4bb7-5483-46da-888a-23017df50481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246741332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1246741332
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.160873255
Short name T14
Test name
Test status
Simulation time 4325448232 ps
CPU time 56.69 seconds
Started Feb 21 02:23:55 PM PST 24
Finished Feb 21 02:24:53 PM PST 24
Peak memory 249464 kb
Host smart-5174f6db-71f6-4892-90af-cc4bb55f655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160873255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.160873255
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3231792235
Short name T197
Test name
Test status
Simulation time 68750543099 ps
CPU time 496.78 seconds
Started Feb 21 02:22:06 PM PST 24
Finished Feb 21 02:30:24 PM PST 24
Peak memory 258996 kb
Host smart-31c1ce90-c395-45f2-887c-95a9a623aed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231792235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3231792235
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1913565613
Short name T21
Test name
Test status
Simulation time 33131694 ps
CPU time 1.02 seconds
Started Feb 21 02:21:00 PM PST 24
Finished Feb 21 02:21:01 PM PST 24
Peak memory 217860 kb
Host smart-dda37578-6828-4cdf-ab2b-17a3b456ef46
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913565613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1913565613
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.593540868
Short name T27
Test name
Test status
Simulation time 1244494505429 ps
CPU time 682.2 seconds
Started Feb 21 02:22:34 PM PST 24
Finished Feb 21 02:33:57 PM PST 24
Peak memory 259488 kb
Host smart-f0cf4833-fe06-445f-9b97-1dee10c49270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593540868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
593540868
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.848435081
Short name T117
Test name
Test status
Simulation time 9175527418 ps
CPU time 116.46 seconds
Started Feb 21 02:23:00 PM PST 24
Finished Feb 21 02:24:57 PM PST 24
Peak memory 249680 kb
Host smart-6524129c-1eb0-43e2-897a-5f17d0165836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848435081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.848435081
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3111741757
Short name T8
Test name
Test status
Simulation time 25140132370 ps
CPU time 59.2 seconds
Started Feb 21 02:23:46 PM PST 24
Finished Feb 21 02:24:46 PM PST 24
Peak memory 257332 kb
Host smart-d84240fc-29c1-4b32-b1dd-f75e803b3d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111741757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3111741757
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2990369826
Short name T232
Test name
Test status
Simulation time 236518695027 ps
CPU time 390.32 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:31:45 PM PST 24
Peak memory 263676 kb
Host smart-76c5f77d-1064-4ace-b5b2-e3e0dea18860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990369826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2990369826
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1395477890
Short name T289
Test name
Test status
Simulation time 13624698 ps
CPU time 0.72 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:23:45 PM PST 24
Peak memory 204404 kb
Host smart-db2d22bc-f969-447f-9a9b-f6055918ab8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395477890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1395477890
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.402712066
Short name T150
Test name
Test status
Simulation time 490462923438 ps
CPU time 413.69 seconds
Started Feb 21 02:24:12 PM PST 24
Finished Feb 21 02:31:06 PM PST 24
Peak memory 249256 kb
Host smart-6ece0cbf-a54a-42ea-84e4-8203d2e3b477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402712066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.402712066
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3830356122
Short name T18
Test name
Test status
Simulation time 11323630124 ps
CPU time 45.22 seconds
Started Feb 21 02:24:56 PM PST 24
Finished Feb 21 02:25:42 PM PST 24
Peak memory 216508 kb
Host smart-c39309e6-02ab-411c-933f-4b2d1abe577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830356122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3830356122
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1551344643
Short name T88
Test name
Test status
Simulation time 97301827 ps
CPU time 2.73 seconds
Started Feb 21 12:41:00 PM PST 24
Finished Feb 21 12:41:05 PM PST 24
Peak memory 215212 kb
Host smart-72ecfe4c-fe31-4f4b-9cc1-77295c896abf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551344643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
551344643
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1568214770
Short name T961
Test name
Test status
Simulation time 397794433175 ps
CPU time 775.92 seconds
Started Feb 21 02:26:21 PM PST 24
Finished Feb 21 02:39:18 PM PST 24
Peak memory 273892 kb
Host smart-e8a485a9-f5d1-48f2-ae0d-4eabf3f73542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568214770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1568214770
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.78023016
Short name T101
Test name
Test status
Simulation time 1906206430 ps
CPU time 21.74 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:46 PM PST 24
Peak memory 215064 kb
Host smart-4d5314b7-c1f1-4e18-821f-045e9be74bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78023016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_t
l_intg_err.78023016
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2257584822
Short name T192
Test name
Test status
Simulation time 361328457309 ps
CPU time 577.83 seconds
Started Feb 21 02:20:57 PM PST 24
Finished Feb 21 02:30:36 PM PST 24
Peak memory 303328 kb
Host smart-4f7bb2ad-50b7-4cfc-b006-8c6f07413cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257584822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2257584822
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2727999863
Short name T495
Test name
Test status
Simulation time 5513629140 ps
CPU time 36.12 seconds
Started Feb 21 02:24:42 PM PST 24
Finished Feb 21 02:25:18 PM PST 24
Peak memory 237176 kb
Host smart-e492a9b9-437f-43a1-b34b-9b1a78c89cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727999863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2727999863
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2842023722
Short name T246
Test name
Test status
Simulation time 54937791790 ps
CPU time 140.72 seconds
Started Feb 21 02:25:47 PM PST 24
Finished Feb 21 02:28:09 PM PST 24
Peak memory 269936 kb
Host smart-f49bf597-4aed-4fb9-ae79-85f391fbdc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842023722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2842023722
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1827569253
Short name T263
Test name
Test status
Simulation time 45467060651 ps
CPU time 297.31 seconds
Started Feb 21 02:24:16 PM PST 24
Finished Feb 21 02:29:14 PM PST 24
Peak memory 273940 kb
Host smart-10e89480-cdf3-42e2-afba-cca7ba012764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827569253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1827569253
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2258577022
Short name T160
Test name
Test status
Simulation time 790305699 ps
CPU time 12.6 seconds
Started Feb 21 12:41:22 PM PST 24
Finished Feb 21 12:41:35 PM PST 24
Peak memory 215100 kb
Host smart-683fe592-7b76-41ef-9164-31280cba2948
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258577022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2258577022
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2657018564
Short name T162
Test name
Test status
Simulation time 778726704 ps
CPU time 14.95 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:39 PM PST 24
Peak memory 214980 kb
Host smart-608aefe2-34c1-4f5e-9b38-572639d016f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657018564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2657018564
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3214095473
Short name T161
Test name
Test status
Simulation time 5392057842 ps
CPU time 21.6 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:56 PM PST 24
Peak memory 215096 kb
Host smart-be37f8c9-6e89-479a-8442-0dca81981de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214095473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3214095473
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4150078211
Short name T159
Test name
Test status
Simulation time 238332638 ps
CPU time 3.26 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:58 PM PST 24
Peak memory 215280 kb
Host smart-0cafe086-ae36-4e26-81cd-6b05b31fe26d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150078211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4150078211
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2928624666
Short name T50
Test name
Test status
Simulation time 105376483 ps
CPU time 0.81 seconds
Started Feb 21 02:21:14 PM PST 24
Finished Feb 21 02:21:16 PM PST 24
Peak memory 205492 kb
Host smart-83c5a8d8-b259-43cc-80a9-3ec193001306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928624666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2928624666
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1370786348
Short name T176
Test name
Test status
Simulation time 90105161459 ps
CPU time 414.5 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:30:39 PM PST 24
Peak memory 255768 kb
Host smart-73909ab5-293c-4613-b614-cedc66e8050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370786348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1370786348
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3326784125
Short name T142
Test name
Test status
Simulation time 18913054996 ps
CPU time 260.32 seconds
Started Feb 21 02:24:31 PM PST 24
Finished Feb 21 02:28:52 PM PST 24
Peak memory 287228 kb
Host smart-7691271c-3948-4226-aef7-867b7c3113ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326784125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3326784125
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1545988983
Short name T146
Test name
Test status
Simulation time 12933796696 ps
CPU time 75.72 seconds
Started Feb 21 02:24:41 PM PST 24
Finished Feb 21 02:25:57 PM PST 24
Peak memory 249368 kb
Host smart-ac44eadb-15d0-4dab-8aa4-c1f406cc4dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545988983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1545988983
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3533381323
Short name T269
Test name
Test status
Simulation time 131827559844 ps
CPU time 239.94 seconds
Started Feb 21 02:22:08 PM PST 24
Finished Feb 21 02:26:09 PM PST 24
Peak memory 253200 kb
Host smart-dcd78fa4-85e6-4c0b-95b8-ab2be5d36937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533381323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3533381323
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_intercept.129600668
Short name T186
Test name
Test status
Simulation time 127702247 ps
CPU time 2.87 seconds
Started Feb 21 02:26:06 PM PST 24
Finished Feb 21 02:26:10 PM PST 24
Peak memory 216900 kb
Host smart-7a84ff18-a878-4126-bfc5-71b0e6d465d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129600668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.129600668
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3383621190
Short name T73
Test name
Test status
Simulation time 85459104848 ps
CPU time 308.91 seconds
Started Feb 21 02:26:23 PM PST 24
Finished Feb 21 02:31:33 PM PST 24
Peak memory 253964 kb
Host smart-0a91db02-d612-42c5-9f24-d24ab65fecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383621190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3383621190
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.568141027
Short name T61
Test name
Test status
Simulation time 97831077 ps
CPU time 1.16 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 215028 kb
Host smart-5891fc5d-4e6b-42c0-addd-ada6df2f297b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568141027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.568141027
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1987089599
Short name T113
Test name
Test status
Simulation time 212639964 ps
CPU time 14.91 seconds
Started Feb 21 12:41:30 PM PST 24
Finished Feb 21 12:41:46 PM PST 24
Peak memory 206948 kb
Host smart-965ba12c-e42d-43a5-8166-8be7332483be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987089599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1987089599
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.780025764
Short name T115
Test name
Test status
Simulation time 1985559238 ps
CPU time 30.95 seconds
Started Feb 21 12:41:07 PM PST 24
Finished Feb 21 12:41:39 PM PST 24
Peak memory 206992 kb
Host smart-8ac451e8-ae9b-452b-b113-44dc5556aefe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780025764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.780025764
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2642786225
Short name T1008
Test name
Test status
Simulation time 24291118 ps
CPU time 0.91 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 206068 kb
Host smart-54396a1e-a179-4453-8c72-f3e79cc85fcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642786225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2642786225
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1595224976
Short name T1051
Test name
Test status
Simulation time 45511298 ps
CPU time 3.13 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:23 PM PST 24
Peak memory 216652 kb
Host smart-640d5c91-9e47-4dff-9130-0be63c5e0f6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595224976 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1595224976
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1110251914
Short name T1040
Test name
Test status
Simulation time 63887401 ps
CPU time 1.15 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 206860 kb
Host smart-a392f617-2337-41b9-8a95-fc256e830ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110251914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
110251914
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.781615373
Short name T988
Test name
Test status
Simulation time 14325067 ps
CPU time 0.72 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 202920 kb
Host smart-1143d5e3-ffe1-450d-a0c6-a76004713526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781615373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.781615373
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2028624673
Short name T1029
Test name
Test status
Simulation time 91343483 ps
CPU time 1.29 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:21 PM PST 24
Peak memory 215160 kb
Host smart-18a8ee14-b18e-43fe-a300-cb6793453da4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028624673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2028624673
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1255228326
Short name T1053
Test name
Test status
Simulation time 19041774 ps
CPU time 0.65 seconds
Started Feb 21 12:41:00 PM PST 24
Finished Feb 21 12:41:02 PM PST 24
Peak memory 202852 kb
Host smart-7f66489a-8bf0-48de-b89e-30bf8acf2b51
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255228326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1255228326
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.505064492
Short name T1014
Test name
Test status
Simulation time 113404261 ps
CPU time 1.75 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 206700 kb
Host smart-99eca3e4-a218-44d7-832a-53f5bc6dec04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505064492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.505064492
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4142144151
Short name T1093
Test name
Test status
Simulation time 200573084 ps
CPU time 4.82 seconds
Started Feb 21 12:41:22 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 215372 kb
Host smart-b8a8f038-10bf-4638-86ed-d27c48cde350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142144151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
142144151
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3769342169
Short name T137
Test name
Test status
Simulation time 5490820238 ps
CPU time 21.4 seconds
Started Feb 21 12:41:08 PM PST 24
Finished Feb 21 12:41:30 PM PST 24
Peak memory 215180 kb
Host smart-e0cb77e4-5929-4f9f-a718-dbbff768a3e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769342169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3769342169
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1832550758
Short name T1024
Test name
Test status
Simulation time 1284567661 ps
CPU time 16.05 seconds
Started Feb 21 12:41:02 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 215080 kb
Host smart-42b4a2cc-beac-44df-9948-09c808f9c6f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832550758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1832550758
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4179994600
Short name T1010
Test name
Test status
Simulation time 393898137 ps
CPU time 12.01 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:32 PM PST 24
Peak memory 206824 kb
Host smart-dea31253-700a-4406-a56b-b2268b22e19e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179994600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4179994600
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4276466163
Short name T1066
Test name
Test status
Simulation time 321799322 ps
CPU time 2.92 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:30 PM PST 24
Peak memory 216152 kb
Host smart-474ee8f9-f077-4ce6-aea0-6a899771f9d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276466163 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4276466163
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.848920388
Short name T109
Test name
Test status
Simulation time 224146845 ps
CPU time 1.9 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:26 PM PST 24
Peak memory 214980 kb
Host smart-081f84d7-3287-41a7-afbd-110f670559a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848920388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.848920388
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.529309570
Short name T1104
Test name
Test status
Simulation time 58001061 ps
CPU time 0.74 seconds
Started Feb 21 12:41:11 PM PST 24
Finished Feb 21 12:41:13 PM PST 24
Peak memory 202960 kb
Host smart-36cc65d1-4a4f-4b4f-9e7a-9855c9eed8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529309570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.529309570
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2504086125
Short name T107
Test name
Test status
Simulation time 160775710 ps
CPU time 1.72 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 215120 kb
Host smart-1c09fb35-8348-4569-8a95-aef8eafb8290
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504086125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2504086125
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3368338119
Short name T1004
Test name
Test status
Simulation time 18751286 ps
CPU time 0.67 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 203168 kb
Host smart-0fc7dac8-c337-421b-bfd2-392b1b39c822
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368338119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3368338119
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3400044913
Short name T1080
Test name
Test status
Simulation time 98971825 ps
CPU time 1.88 seconds
Started Feb 21 12:41:22 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 206804 kb
Host smart-55dfd9c4-93b7-43f6-aacb-a9d5a7a8c017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400044913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3400044913
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.161114172
Short name T1091
Test name
Test status
Simulation time 45836654 ps
CPU time 3.5 seconds
Started Feb 21 12:41:29 PM PST 24
Finished Feb 21 12:41:33 PM PST 24
Peak memory 215380 kb
Host smart-153fd303-6b20-45de-98f0-5b4f3d53c032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161114172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.161114172
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1059775165
Short name T1069
Test name
Test status
Simulation time 138012798 ps
CPU time 3.59 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:30 PM PST 24
Peak memory 216928 kb
Host smart-b621a0c8-cf47-4ddd-a10a-23d5e90529f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059775165 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1059775165
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.756647335
Short name T1033
Test name
Test status
Simulation time 151577242 ps
CPU time 2.41 seconds
Started Feb 21 12:41:25 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 206932 kb
Host smart-de9de9d7-86ad-479d-b5ab-a0f5aae46b98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756647335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.756647335
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1113031314
Short name T1046
Test name
Test status
Simulation time 25813560 ps
CPU time 0.72 seconds
Started Feb 21 12:41:25 PM PST 24
Finished Feb 21 12:41:26 PM PST 24
Peak memory 202976 kb
Host smart-7cfcfa1f-fe93-46d8-94ef-4d39a3e98095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113031314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1113031314
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.618092202
Short name T1101
Test name
Test status
Simulation time 166979422 ps
CPU time 1.85 seconds
Started Feb 21 12:41:12 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 206572 kb
Host smart-dff5efea-0d44-405b-82d1-12ca61afc02c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618092202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.618092202
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2744413923
Short name T96
Test name
Test status
Simulation time 51803564 ps
CPU time 2.11 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:29 PM PST 24
Peak memory 216412 kb
Host smart-8ab00191-8e36-4755-a90f-ad4d52c4ecef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744413923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2744413923
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4016903549
Short name T1015
Test name
Test status
Simulation time 3310786722 ps
CPU time 21.54 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:42 PM PST 24
Peak memory 215232 kb
Host smart-18fb48ec-ea12-4a6c-8cbe-cc3143af0334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016903549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4016903549
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.376672338
Short name T80
Test name
Test status
Simulation time 29233321 ps
CPU time 2.18 seconds
Started Feb 21 12:41:35 PM PST 24
Finished Feb 21 12:41:37 PM PST 24
Peak memory 216304 kb
Host smart-e8d39a7a-6247-47ea-b091-2f58019a9783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376672338 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.376672338
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3007613241
Short name T1036
Test name
Test status
Simulation time 182682141 ps
CPU time 2.69 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:26 PM PST 24
Peak memory 206744 kb
Host smart-57c1f582-f476-4ba8-88d7-c7a992fcfacd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007613241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3007613241
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.767555016
Short name T1006
Test name
Test status
Simulation time 15372206 ps
CPU time 0.74 seconds
Started Feb 21 12:41:25 PM PST 24
Finished Feb 21 12:41:26 PM PST 24
Peak memory 202976 kb
Host smart-3d996c57-2fa1-4131-b406-ba49031a6d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767555016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.767555016
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1599239615
Short name T989
Test name
Test status
Simulation time 636500261 ps
CPU time 4.11 seconds
Started Feb 21 12:41:11 PM PST 24
Finished Feb 21 12:41:16 PM PST 24
Peak memory 215168 kb
Host smart-9e3d8f91-7520-420e-aa76-2e8e87adc7ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599239615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1599239615
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.718272089
Short name T1070
Test name
Test status
Simulation time 151091034 ps
CPU time 4.69 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 215176 kb
Host smart-6b07cae3-1283-446f-bb8f-866904af295b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718272089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.718272089
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2293258543
Short name T97
Test name
Test status
Simulation time 582742175 ps
CPU time 16.49 seconds
Started Feb 21 12:41:13 PM PST 24
Finished Feb 21 12:41:31 PM PST 24
Peak memory 215096 kb
Host smart-74fb45e1-ed3d-453a-a4c7-7899837cfbd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293258543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2293258543
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2580451889
Short name T1065
Test name
Test status
Simulation time 325812886 ps
CPU time 2.74 seconds
Started Feb 21 12:41:17 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 215936 kb
Host smart-5ecb477e-72c6-4c68-a38e-45e0d13f765e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580451889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2580451889
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3600122373
Short name T1081
Test name
Test status
Simulation time 388726839 ps
CPU time 2.66 seconds
Started Feb 21 12:41:17 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 214756 kb
Host smart-58aa70b5-ab50-46ff-9259-38feec605f7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600122373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3600122373
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.147095344
Short name T1105
Test name
Test status
Simulation time 21672970 ps
CPU time 0.66 seconds
Started Feb 21 12:41:16 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 203264 kb
Host smart-4185dd6d-bea1-452b-be31-0b13db2c2033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147095344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.147095344
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1002845847
Short name T990
Test name
Test status
Simulation time 107454183 ps
CPU time 1.82 seconds
Started Feb 21 12:41:25 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 206912 kb
Host smart-922e3b4c-f59a-4c6b-b872-4fe6d479c7fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002845847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1002845847
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3586298758
Short name T95
Test name
Test status
Simulation time 432252690 ps
CPU time 1.63 seconds
Started Feb 21 12:41:14 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 206304 kb
Host smart-8a2db9b5-909c-48a7-bb1b-b684d171f07a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586298758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3586298758
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.304170608
Short name T98
Test name
Test status
Simulation time 278648623 ps
CPU time 6.9 seconds
Started Feb 21 12:41:14 PM PST 24
Finished Feb 21 12:41:23 PM PST 24
Peak memory 214432 kb
Host smart-ebf484fd-e9ec-4204-9edd-e8dc8de9869b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304170608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.304170608
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.408419535
Short name T1068
Test name
Test status
Simulation time 513015479 ps
CPU time 3.87 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 216900 kb
Host smart-d381ebc7-c7e3-4118-8643-b454077b9c58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408419535 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.408419535
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3653121470
Short name T110
Test name
Test status
Simulation time 40344184 ps
CPU time 1.26 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 206844 kb
Host smart-6812b0f6-8601-4c3b-af45-59f060732847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653121470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3653121470
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3576645547
Short name T1049
Test name
Test status
Simulation time 24166285 ps
CPU time 0.73 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 202940 kb
Host smart-57f37448-16ba-4c9d-8c33-ffd03779a4cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576645547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3576645547
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3919197462
Short name T1002
Test name
Test status
Simulation time 110501631 ps
CPU time 3.62 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:31 PM PST 24
Peak memory 215176 kb
Host smart-f0f30544-e205-4406-9501-889607a8d298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919197462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3919197462
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4030734512
Short name T114
Test name
Test status
Simulation time 41843679 ps
CPU time 1.48 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 215084 kb
Host smart-3e2087b8-fc5d-4ca5-a040-4b53bc00cb7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030734512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4030734512
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2257338339
Short name T1067
Test name
Test status
Simulation time 11955483 ps
CPU time 0.7 seconds
Started Feb 21 12:41:01 PM PST 24
Finished Feb 21 12:41:03 PM PST 24
Peak memory 202820 kb
Host smart-7604befa-9c41-41f7-bd2a-74c82d833f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257338339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2257338339
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1193689344
Short name T1037
Test name
Test status
Simulation time 363704580 ps
CPU time 2.55 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 206848 kb
Host smart-87542883-8531-43a8-b560-a5f404f76ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193689344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1193689344
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2674864828
Short name T1073
Test name
Test status
Simulation time 336146225 ps
CPU time 3.89 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 216256 kb
Host smart-5c0655e2-2920-447d-b294-db3666b0af40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674864828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2674864828
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3900335879
Short name T76
Test name
Test status
Simulation time 2965036111 ps
CPU time 21.33 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:46 PM PST 24
Peak memory 215236 kb
Host smart-c5e306ee-8f2b-431b-bcba-3a453e035c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900335879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3900335879
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2290253282
Short name T93
Test name
Test status
Simulation time 127407523 ps
CPU time 3.25 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:23 PM PST 24
Peak memory 216488 kb
Host smart-fff7c6e7-b5d5-409c-8b2f-ca1484435e9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290253282 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2290253282
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2489264815
Short name T1007
Test name
Test status
Simulation time 45572621 ps
CPU time 2.45 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:29 PM PST 24
Peak memory 215164 kb
Host smart-8994f536-8aef-4b31-adf0-e450487f316a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489264815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2489264815
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.675545691
Short name T1005
Test name
Test status
Simulation time 75108576 ps
CPU time 0.74 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 203284 kb
Host smart-9ab40e09-8b9d-4542-bad3-74496ae437aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675545691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.675545691
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4074115530
Short name T1045
Test name
Test status
Simulation time 251361567 ps
CPU time 1.71 seconds
Started Feb 21 12:41:22 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 215148 kb
Host smart-7244c6ba-4a92-4fe5-9d6f-d318e9d91a17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074115530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4074115530
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1265120096
Short name T1074
Test name
Test status
Simulation time 187686120 ps
CPU time 4.16 seconds
Started Feb 21 12:41:17 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 215996 kb
Host smart-27984fb0-2539-40c2-83c7-8f2d519cdc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265120096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1265120096
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1990576054
Short name T1047
Test name
Test status
Simulation time 279792577 ps
CPU time 7.15 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:35 PM PST 24
Peak memory 216220 kb
Host smart-12dd4cdc-78ed-4ba1-9542-03fedcefcefa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990576054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1990576054
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.655232231
Short name T1019
Test name
Test status
Simulation time 139042255 ps
CPU time 4.48 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:39 PM PST 24
Peak memory 216652 kb
Host smart-30f5c7b8-42f7-43bc-bf96-2faecbb82016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655232231 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.655232231
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3590457226
Short name T1083
Test name
Test status
Simulation time 70304361 ps
CPU time 2.21 seconds
Started Feb 21 12:41:30 PM PST 24
Finished Feb 21 12:41:33 PM PST 24
Peak memory 215120 kb
Host smart-a4603a3e-5ac9-4685-af11-d74593bd59c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590457226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3590457226
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3624875956
Short name T1034
Test name
Test status
Simulation time 13745767 ps
CPU time 0.75 seconds
Started Feb 21 12:41:51 PM PST 24
Finished Feb 21 12:41:52 PM PST 24
Peak memory 203124 kb
Host smart-7fe8abf9-5c93-4bb7-9f0a-3cc06c191227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624875956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3624875956
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1030166434
Short name T1048
Test name
Test status
Simulation time 45734910 ps
CPU time 2.52 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:37 PM PST 24
Peak memory 206240 kb
Host smart-0bd6dd8f-2817-49c6-b843-e39736187124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030166434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1030166434
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3716064916
Short name T94
Test name
Test status
Simulation time 92534097 ps
CPU time 1.95 seconds
Started Feb 21 12:41:51 PM PST 24
Finished Feb 21 12:41:53 PM PST 24
Peak memory 215196 kb
Host smart-d79f6689-ec2d-4b81-8ad1-e424af75accd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716064916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3716064916
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4126002518
Short name T1041
Test name
Test status
Simulation time 224786813 ps
CPU time 6.35 seconds
Started Feb 21 12:41:44 PM PST 24
Finished Feb 21 12:41:50 PM PST 24
Peak memory 218244 kb
Host smart-255750dd-e9ed-4db8-ac49-3444bb68b621
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126002518 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4126002518
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1436442378
Short name T998
Test name
Test status
Simulation time 129807022 ps
CPU time 2.08 seconds
Started Feb 21 12:41:35 PM PST 24
Finished Feb 21 12:41:38 PM PST 24
Peak memory 215156 kb
Host smart-9c1798a5-84e4-4d29-8252-e249e1cd1b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436442378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1436442378
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.142754895
Short name T1016
Test name
Test status
Simulation time 21015591 ps
CPU time 0.7 seconds
Started Feb 21 12:41:44 PM PST 24
Finished Feb 21 12:41:45 PM PST 24
Peak memory 203264 kb
Host smart-9f0c65c5-e8a2-4bc4-a908-28a7fa00977c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142754895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.142754895
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.574702192
Short name T1089
Test name
Test status
Simulation time 48318798 ps
CPU time 2.89 seconds
Started Feb 21 12:41:33 PM PST 24
Finished Feb 21 12:41:36 PM PST 24
Peak memory 206992 kb
Host smart-0f8302a4-2948-48a7-ad5b-a9d463763b32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574702192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.574702192
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1724192778
Short name T74
Test name
Test status
Simulation time 409619987 ps
CPU time 7.22 seconds
Started Feb 21 12:41:46 PM PST 24
Finished Feb 21 12:41:54 PM PST 24
Peak memory 215040 kb
Host smart-d90acc3f-0274-4eba-a83f-ecbe2a1e7ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724192778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1724192778
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3131165819
Short name T1087
Test name
Test status
Simulation time 3891927389 ps
CPU time 5.1 seconds
Started Feb 21 12:41:45 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 217908 kb
Host smart-9586d145-b727-4e74-9c6d-72eca2885dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131165819 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3131165819
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.803575016
Short name T1098
Test name
Test status
Simulation time 413713640 ps
CPU time 2.69 seconds
Started Feb 21 12:41:33 PM PST 24
Finished Feb 21 12:41:36 PM PST 24
Peak memory 214976 kb
Host smart-4d404f9d-d183-4907-abc5-62ed4baf0371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803575016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.803575016
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2830850764
Short name T1064
Test name
Test status
Simulation time 14210988 ps
CPU time 0.72 seconds
Started Feb 21 12:41:53 PM PST 24
Finished Feb 21 12:41:54 PM PST 24
Peak memory 202956 kb
Host smart-0cc2e7b0-27bf-436e-aa18-52b43a535c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830850764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2830850764
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4215731498
Short name T134
Test name
Test status
Simulation time 128184198 ps
CPU time 2.98 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 206932 kb
Host smart-fd2de9bf-9125-4f1f-af52-0057bd2bc1ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215731498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4215731498
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2701849832
Short name T1094
Test name
Test status
Simulation time 102088426 ps
CPU time 1.76 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 215212 kb
Host smart-c358592c-50e9-40f9-a9d9-42f20b96f3d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701849832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2701849832
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1113140995
Short name T135
Test name
Test status
Simulation time 1211705753 ps
CPU time 14.17 seconds
Started Feb 21 12:41:33 PM PST 24
Finished Feb 21 12:41:48 PM PST 24
Peak memory 215112 kb
Host smart-85b83c91-f47c-4160-a31b-9b99da351180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113140995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1113140995
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4024815176
Short name T1095
Test name
Test status
Simulation time 213231625 ps
CPU time 3.92 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 216388 kb
Host smart-a7b15aae-882a-44fc-96c3-540e53bb24af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024815176 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4024815176
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1108709825
Short name T111
Test name
Test status
Simulation time 118823874 ps
CPU time 2.02 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:50 PM PST 24
Peak memory 214908 kb
Host smart-e3acf776-7704-4624-b139-57965d0f06e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108709825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1108709825
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1685327227
Short name T1001
Test name
Test status
Simulation time 19511202 ps
CPU time 0.71 seconds
Started Feb 21 12:43:49 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 202680 kb
Host smart-a1c6951c-2f09-44c2-aa38-91b92547f7d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685327227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1685327227
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4075221379
Short name T1096
Test name
Test status
Simulation time 47644324 ps
CPU time 3.09 seconds
Started Feb 21 12:41:45 PM PST 24
Finished Feb 21 12:41:49 PM PST 24
Peak memory 206964 kb
Host smart-891900fb-aa1f-4ec1-9a92-513b2ed8bc4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075221379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4075221379
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2081514736
Short name T78
Test name
Test status
Simulation time 180767950 ps
CPU time 2.64 seconds
Started Feb 21 12:41:35 PM PST 24
Finished Feb 21 12:41:38 PM PST 24
Peak memory 215280 kb
Host smart-a36494bd-485d-41bd-aa7c-80c1e236ffd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081514736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2081514736
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2815539858
Short name T136
Test name
Test status
Simulation time 2170835879 ps
CPU time 24.63 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:46 PM PST 24
Peak memory 206876 kb
Host smart-c393d3db-4f98-470c-a612-d5ce7ad404a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815539858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2815539858
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3724451015
Short name T105
Test name
Test status
Simulation time 38242082 ps
CPU time 1.21 seconds
Started Feb 21 12:41:15 PM PST 24
Finished Feb 21 12:41:18 PM PST 24
Peak memory 206660 kb
Host smart-cae5023d-ab50-4725-8fc2-52c682ea6e96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724451015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3724451015
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.663123765
Short name T81
Test name
Test status
Simulation time 701859440 ps
CPU time 2.43 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:30 PM PST 24
Peak memory 216268 kb
Host smart-cae79a03-30fe-4e1f-8db2-27c74ab68e42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663123765 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.663123765
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2294727832
Short name T106
Test name
Test status
Simulation time 391863592 ps
CPU time 2.72 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 214900 kb
Host smart-f0ffe6f1-7b0b-44ac-bfc2-ffd783059655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294727832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
294727832
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2181852933
Short name T987
Test name
Test status
Simulation time 12578409 ps
CPU time 0.68 seconds
Started Feb 21 12:41:03 PM PST 24
Finished Feb 21 12:41:04 PM PST 24
Peak memory 202860 kb
Host smart-dcf58151-4ddd-4491-9d47-a47701598074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181852933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
181852933
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1282153529
Short name T1078
Test name
Test status
Simulation time 204869491 ps
CPU time 1.68 seconds
Started Feb 21 12:41:03 PM PST 24
Finished Feb 21 12:41:05 PM PST 24
Peak memory 215048 kb
Host smart-b10b1fa9-7b00-4701-bc5b-678ced732df0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282153529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1282153529
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2796042940
Short name T1072
Test name
Test status
Simulation time 24943835 ps
CPU time 0.66 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 202820 kb
Host smart-2d517010-2a2d-4102-a45a-7e83fd826b0e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796042940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2796042940
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2372198691
Short name T1082
Test name
Test status
Simulation time 918329878 ps
CPU time 2.71 seconds
Started Feb 21 12:41:08 PM PST 24
Finished Feb 21 12:41:11 PM PST 24
Peak memory 207024 kb
Host smart-222645cb-83ab-458c-ad8d-7598e043de6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372198691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2372198691
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.338503168
Short name T82
Test name
Test status
Simulation time 501815129 ps
CPU time 3.66 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:29 PM PST 24
Peak memory 215220 kb
Host smart-5c746ef9-4432-467d-84d2-14dcc3fc4d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338503168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.338503168
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3622050024
Short name T163
Test name
Test status
Simulation time 2809766490 ps
CPU time 14.64 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:39 PM PST 24
Peak memory 215080 kb
Host smart-ca5c3fe1-526c-4b18-a801-e2fe3859e183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622050024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3622050024
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.884326969
Short name T1058
Test name
Test status
Simulation time 29120197 ps
CPU time 0.74 seconds
Started Feb 21 12:42:13 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 202944 kb
Host smart-39902f16-0be9-41b6-8357-9b0b0ab36d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884326969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.884326969
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2187868044
Short name T1012
Test name
Test status
Simulation time 28331279 ps
CPU time 0.72 seconds
Started Feb 21 12:41:57 PM PST 24
Finished Feb 21 12:41:59 PM PST 24
Peak memory 202856 kb
Host smart-a6698e5e-ed32-4324-803b-4391fe067015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187868044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2187868044
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4135755055
Short name T1055
Test name
Test status
Simulation time 17998697 ps
CPU time 0.73 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 202996 kb
Host smart-e36b14bc-72df-47c6-a6ba-53d10d320624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135755055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4135755055
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3273773746
Short name T1090
Test name
Test status
Simulation time 14668970 ps
CPU time 0.74 seconds
Started Feb 21 12:41:33 PM PST 24
Finished Feb 21 12:41:34 PM PST 24
Peak memory 202956 kb
Host smart-e98f2ec7-9f68-454d-ada5-1bf7c6f5ca24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273773746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3273773746
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1518064151
Short name T1021
Test name
Test status
Simulation time 44003816 ps
CPU time 0.72 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 202888 kb
Host smart-8ae53328-9e4a-40a4-9db8-3c37586e7185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518064151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1518064151
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1747451268
Short name T1003
Test name
Test status
Simulation time 50049103 ps
CPU time 0.67 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:43:52 PM PST 24
Peak memory 202680 kb
Host smart-be53deb0-1752-4ecb-af96-f2c302b0f790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747451268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1747451268
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4154005642
Short name T993
Test name
Test status
Simulation time 47586280 ps
CPU time 0.7 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 202892 kb
Host smart-9459cba6-cb47-4928-b479-e7686d770a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154005642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4154005642
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2890648436
Short name T1044
Test name
Test status
Simulation time 14800908 ps
CPU time 0.76 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:06 PM PST 24
Peak memory 202896 kb
Host smart-a5021302-81d5-49ca-9fcd-1652b9747691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890648436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2890648436
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1526227891
Short name T1079
Test name
Test status
Simulation time 15031112 ps
CPU time 0.78 seconds
Started Feb 21 12:41:45 PM PST 24
Finished Feb 21 12:41:46 PM PST 24
Peak memory 202960 kb
Host smart-dbc0aa7f-1350-462e-b01b-15e2755dcdf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526227891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1526227891
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2593932173
Short name T1039
Test name
Test status
Simulation time 17484753 ps
CPU time 0.73 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:42:01 PM PST 24
Peak memory 202952 kb
Host smart-a173f106-1ba8-4cbf-9a92-f8df562f54c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593932173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2593932173
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1546957023
Short name T133
Test name
Test status
Simulation time 6903201975 ps
CPU time 16.75 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:44 PM PST 24
Peak memory 206808 kb
Host smart-f7394b16-1a08-4edf-accd-1f33e68f5df1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546957023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1546957023
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2978066626
Short name T108
Test name
Test status
Simulation time 549076262 ps
CPU time 34.15 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 206892 kb
Host smart-a0620e85-0bc8-4265-95c6-002fc80c252b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978066626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2978066626
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1240112617
Short name T60
Test name
Test status
Simulation time 154151961 ps
CPU time 1.43 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:29 PM PST 24
Peak memory 215108 kb
Host smart-5140a8aa-8d98-4bc3-8051-e9c7c59a1040
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240112617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1240112617
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2735232893
Short name T1031
Test name
Test status
Simulation time 284128506 ps
CPU time 3.63 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 216132 kb
Host smart-54617c35-e52b-4368-88ee-7a05dbfbc399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735232893 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2735232893
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3316537389
Short name T1061
Test name
Test status
Simulation time 86987887 ps
CPU time 2.39 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 206724 kb
Host smart-441515d9-ee6f-4031-9cd2-674a6321d405
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316537389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
316537389
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1556422141
Short name T984
Test name
Test status
Simulation time 48795876 ps
CPU time 0.73 seconds
Started Feb 21 12:41:10 PM PST 24
Finished Feb 21 12:41:12 PM PST 24
Peak memory 202916 kb
Host smart-c889e63a-cd35-41e1-93f6-07f640cd5d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556422141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
556422141
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1189957771
Short name T1050
Test name
Test status
Simulation time 65089831 ps
CPU time 2.07 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:29 PM PST 24
Peak memory 214912 kb
Host smart-64f8a043-f031-4e16-983b-060ca7e447f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189957771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1189957771
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4108157935
Short name T1000
Test name
Test status
Simulation time 14250952 ps
CPU time 0.67 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 202652 kb
Host smart-2cdcb5cb-9f04-44ed-b8c0-25a53b882401
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108157935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4108157935
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.672761412
Short name T1043
Test name
Test status
Simulation time 763321480 ps
CPU time 3.47 seconds
Started Feb 21 12:41:02 PM PST 24
Finished Feb 21 12:41:06 PM PST 24
Peak memory 215136 kb
Host smart-ee7b79e6-a47e-420b-b6c4-b70860b378cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672761412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.672761412
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3367289614
Short name T87
Test name
Test status
Simulation time 126703604 ps
CPU time 2.53 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:26 PM PST 24
Peak memory 215268 kb
Host smart-8bc0f6fd-e72f-460b-a26b-e9625fc25f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367289614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
367289614
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2157448733
Short name T164
Test name
Test status
Simulation time 533992283 ps
CPU time 14.38 seconds
Started Feb 21 12:41:04 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 214972 kb
Host smart-15a6dc9e-1bde-466a-a22b-46e2a23eae66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157448733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2157448733
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1802274047
Short name T1032
Test name
Test status
Simulation time 57467803 ps
CPU time 0.74 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 202856 kb
Host smart-46aa7ee8-d445-4d98-9e56-e2f8d0bafc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802274047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1802274047
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4187256805
Short name T1020
Test name
Test status
Simulation time 52056048 ps
CPU time 0.75 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:35 PM PST 24
Peak memory 202936 kb
Host smart-31e3f41e-bcf3-4d04-b4ff-7b81094709b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187256805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4187256805
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3641270410
Short name T1011
Test name
Test status
Simulation time 15712658 ps
CPU time 0.73 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 202884 kb
Host smart-b3f4e449-8b15-4f4c-af8c-a9e8a50bae54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641270410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3641270410
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.9827993
Short name T1018
Test name
Test status
Simulation time 142312315 ps
CPU time 0.65 seconds
Started Feb 21 12:43:51 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 202672 kb
Host smart-b0cc562b-c483-4cca-b5ec-552058caa2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9827993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.9827993
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2545626658
Short name T1025
Test name
Test status
Simulation time 26505713 ps
CPU time 0.71 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:56 PM PST 24
Peak memory 202864 kb
Host smart-27237cd3-1c09-4ccc-ace1-6f43f6f45b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545626658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2545626658
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.450960671
Short name T1059
Test name
Test status
Simulation time 37197709 ps
CPU time 0.68 seconds
Started Feb 21 12:41:40 PM PST 24
Finished Feb 21 12:41:52 PM PST 24
Peak memory 202892 kb
Host smart-ddde4f5d-9f34-4346-b3eb-9c159c9c507a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450960671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.450960671
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2249349605
Short name T1027
Test name
Test status
Simulation time 15504546 ps
CPU time 0.69 seconds
Started Feb 21 12:43:46 PM PST 24
Finished Feb 21 12:43:50 PM PST 24
Peak memory 202680 kb
Host smart-343dc7bc-9064-466c-9f6d-6c53b9529170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249349605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2249349605
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2631115768
Short name T997
Test name
Test status
Simulation time 11737154 ps
CPU time 0.71 seconds
Started Feb 21 12:41:46 PM PST 24
Finished Feb 21 12:41:48 PM PST 24
Peak memory 202948 kb
Host smart-df2c8244-d061-406a-96de-6ecf7f035060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631115768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2631115768
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1929669121
Short name T1009
Test name
Test status
Simulation time 20319010 ps
CPU time 0.7 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:06 PM PST 24
Peak memory 202892 kb
Host smart-534020ba-864a-41ef-83c8-c1cc430f956a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929669121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1929669121
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3061744877
Short name T1057
Test name
Test status
Simulation time 39089324 ps
CPU time 0.72 seconds
Started Feb 21 12:41:58 PM PST 24
Finished Feb 21 12:42:00 PM PST 24
Peak memory 202848 kb
Host smart-484e1cd0-d46d-45ea-8761-9a24d0d74e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061744877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3061744877
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1189031918
Short name T1035
Test name
Test status
Simulation time 1891825749 ps
CPU time 7.88 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:32 PM PST 24
Peak memory 206796 kb
Host smart-e25bb6bc-474c-4964-9ba1-2c5dc4a55594
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189031918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1189031918
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.583531195
Short name T1017
Test name
Test status
Simulation time 6719040337 ps
CPU time 31.49 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:55 PM PST 24
Peak memory 206792 kb
Host smart-6e19185f-f0d8-49c0-b7f5-b7f56027389e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583531195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.583531195
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.96668484
Short name T1022
Test name
Test status
Simulation time 168106384 ps
CPU time 1.42 seconds
Started Feb 21 12:41:16 PM PST 24
Finished Feb 21 12:41:18 PM PST 24
Peak memory 206892 kb
Host smart-9ba8d6a8-c8c6-4c98-9031-6a1be42e6b3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96668484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
hw_reset.96668484
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1614420187
Short name T1084
Test name
Test status
Simulation time 165042267 ps
CPU time 2.86 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:26 PM PST 24
Peak memory 216328 kb
Host smart-8dac2af4-293a-4abe-9c68-2a134cc9f31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614420187 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1614420187
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.115291026
Short name T138
Test name
Test status
Simulation time 127997730 ps
CPU time 1.68 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:23 PM PST 24
Peak memory 214980 kb
Host smart-8afb1800-0455-4568-a5fd-54a984ea63e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115291026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.115291026
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1927434313
Short name T1102
Test name
Test status
Simulation time 13198543 ps
CPU time 0.7 seconds
Started Feb 21 12:41:32 PM PST 24
Finished Feb 21 12:41:33 PM PST 24
Peak memory 203252 kb
Host smart-a8e1ddcb-7904-4233-a735-9d4583d6cb46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927434313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
927434313
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1947867408
Short name T112
Test name
Test status
Simulation time 68309617 ps
CPU time 2.2 seconds
Started Feb 21 12:41:34 PM PST 24
Finished Feb 21 12:41:37 PM PST 24
Peak memory 215156 kb
Host smart-2e1d3320-fedc-4043-a754-55696d338243
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947867408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1947867408
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.548370617
Short name T996
Test name
Test status
Simulation time 13899043 ps
CPU time 0.65 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 203180 kb
Host smart-321291ae-3cff-436d-a998-290e1bd88958
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548370617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.548370617
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3140601438
Short name T1088
Test name
Test status
Simulation time 79092048 ps
CPU time 2.79 seconds
Started Feb 21 12:41:14 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 214140 kb
Host smart-09b732fa-1900-4a34-b4c8-39df6a596798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140601438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3140601438
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2888593382
Short name T89
Test name
Test status
Simulation time 80905497 ps
CPU time 2.14 seconds
Started Feb 21 12:41:32 PM PST 24
Finished Feb 21 12:41:35 PM PST 24
Peak memory 216372 kb
Host smart-4fc7bef4-1064-4aa1-a570-12bf61c271cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888593382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
888593382
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1306955175
Short name T1086
Test name
Test status
Simulation time 332951511 ps
CPU time 7.54 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:31 PM PST 24
Peak memory 215244 kb
Host smart-54f77407-8c66-424e-8ef7-c4bfac353102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306955175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1306955175
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1368771873
Short name T1056
Test name
Test status
Simulation time 31212211 ps
CPU time 0.7 seconds
Started Feb 21 12:43:19 PM PST 24
Finished Feb 21 12:43:20 PM PST 24
Peak memory 202296 kb
Host smart-c7cb75be-0487-41d3-a4cf-3373b8812867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368771873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1368771873
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3534092925
Short name T1026
Test name
Test status
Simulation time 15837695 ps
CPU time 0.74 seconds
Started Feb 21 12:41:46 PM PST 24
Finished Feb 21 12:41:47 PM PST 24
Peak memory 202888 kb
Host smart-7c5470b7-94c0-4bda-9963-52ab14c0ba67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534092925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3534092925
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.360714587
Short name T995
Test name
Test status
Simulation time 42236884 ps
CPU time 0.69 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:06 PM PST 24
Peak memory 202884 kb
Host smart-083c7c0a-b7c6-4c2c-b88e-6d9009f8f2ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360714587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.360714587
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2149883084
Short name T1023
Test name
Test status
Simulation time 15151158 ps
CPU time 0.71 seconds
Started Feb 21 12:41:59 PM PST 24
Finished Feb 21 12:42:01 PM PST 24
Peak memory 202864 kb
Host smart-2295d655-7cbd-4857-b7df-56bb0cd94e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149883084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2149883084
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3563912707
Short name T1099
Test name
Test status
Simulation time 11968761 ps
CPU time 0.7 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:56 PM PST 24
Peak memory 203180 kb
Host smart-107b0902-929e-4228-ba63-9fe55afb6cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563912707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3563912707
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.273590851
Short name T1013
Test name
Test status
Simulation time 34763977 ps
CPU time 0.71 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:56 PM PST 24
Peak memory 202864 kb
Host smart-1c66471f-6e3b-4dda-9700-ee6e98f2114d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273590851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.273590851
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.265353852
Short name T1060
Test name
Test status
Simulation time 31056949 ps
CPU time 0.71 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 202856 kb
Host smart-294a8435-0210-4ecf-aa8b-376be4d26fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265353852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.265353852
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.307663567
Short name T994
Test name
Test status
Simulation time 42924250 ps
CPU time 0.69 seconds
Started Feb 21 12:41:45 PM PST 24
Finished Feb 21 12:41:46 PM PST 24
Peak memory 202892 kb
Host smart-692406b2-d366-4f7c-b760-42f4f98d1c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307663567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.307663567
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1992926972
Short name T1075
Test name
Test status
Simulation time 14957922 ps
CPU time 0.67 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:55 PM PST 24
Peak memory 202804 kb
Host smart-20d8ba1a-5610-4e95-b8a5-a0a9f1560aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992926972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1992926972
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2879962649
Short name T1097
Test name
Test status
Simulation time 15860683 ps
CPU time 0.74 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 202892 kb
Host smart-23e66492-5e91-47c9-8d6a-cbeafdf989a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879962649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2879962649
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2742838470
Short name T77
Test name
Test status
Simulation time 356124796 ps
CPU time 2.95 seconds
Started Feb 21 12:41:02 PM PST 24
Finished Feb 21 12:41:06 PM PST 24
Peak memory 216152 kb
Host smart-ada78211-b698-425b-82e7-7ae928964937
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742838470 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2742838470
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1190779842
Short name T1071
Test name
Test status
Simulation time 34798676 ps
CPU time 1.22 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 206936 kb
Host smart-0dc525a3-66e1-49da-9ba3-0c5ad28546c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190779842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
190779842
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2308908043
Short name T985
Test name
Test status
Simulation time 76161705 ps
CPU time 0.66 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 202956 kb
Host smart-ab3a27ca-5eee-4d2f-a470-1cc167fc5c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308908043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
308908043
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3458847044
Short name T1085
Test name
Test status
Simulation time 1202560148 ps
CPU time 4.54 seconds
Started Feb 21 12:41:09 PM PST 24
Finished Feb 21 12:41:15 PM PST 24
Peak memory 206952 kb
Host smart-aaaa1c2f-65ee-46f7-af7e-58cedadb613e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458847044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3458847044
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1768531910
Short name T1063
Test name
Test status
Simulation time 1238603666 ps
CPU time 7.47 seconds
Started Feb 21 12:41:11 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 215124 kb
Host smart-b7b70144-2713-46ac-b141-278347147121
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768531910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1768531910
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3359964214
Short name T1077
Test name
Test status
Simulation time 108264011 ps
CPU time 4.22 seconds
Started Feb 21 12:41:20 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 218044 kb
Host smart-862f8146-e5cb-423f-b51d-f374250be139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359964214 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3359964214
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2295871633
Short name T1103
Test name
Test status
Simulation time 23084930 ps
CPU time 1.35 seconds
Started Feb 21 12:41:22 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 206900 kb
Host smart-81185a3a-0847-493b-8e39-646d42ce9726
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295871633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
295871633
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4182266006
Short name T992
Test name
Test status
Simulation time 14859370 ps
CPU time 0.77 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 202980 kb
Host smart-62b9cb31-1018-4bb6-8f35-f6c0651b010f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182266006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
182266006
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1365235541
Short name T1062
Test name
Test status
Simulation time 655242624 ps
CPU time 4.34 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:31 PM PST 24
Peak memory 206808 kb
Host smart-b40ceb15-7b7f-44ea-8af3-7a190810096d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365235541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1365235541
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2255570598
Short name T1076
Test name
Test status
Simulation time 211467875 ps
CPU time 4.96 seconds
Started Feb 21 12:41:27 PM PST 24
Finished Feb 21 12:41:32 PM PST 24
Peak memory 215328 kb
Host smart-904e9611-297f-4142-9f4e-1ac801e092c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255570598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
255570598
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.636866311
Short name T100
Test name
Test status
Simulation time 590527872 ps
CPU time 12.33 seconds
Started Feb 21 12:41:07 PM PST 24
Finished Feb 21 12:41:20 PM PST 24
Peak memory 215288 kb
Host smart-0faa8b51-bb68-46c6-9240-f560a09dc8db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636866311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.636866311
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1385297502
Short name T1042
Test name
Test status
Simulation time 92599603 ps
CPU time 1.82 seconds
Started Feb 21 12:41:05 PM PST 24
Finished Feb 21 12:41:07 PM PST 24
Peak memory 215180 kb
Host smart-f61f7fe6-59ff-4bc9-a839-01dc7871f149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385297502 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1385297502
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1434580068
Short name T986
Test name
Test status
Simulation time 28457051 ps
CPU time 1.86 seconds
Started Feb 21 12:41:02 PM PST 24
Finished Feb 21 12:41:05 PM PST 24
Peak memory 215024 kb
Host smart-8d564e84-d167-4a5c-ab01-f8e54ab2f83d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434580068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
434580068
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1348613585
Short name T1030
Test name
Test status
Simulation time 37172563 ps
CPU time 0.7 seconds
Started Feb 21 12:41:24 PM PST 24
Finished Feb 21 12:41:25 PM PST 24
Peak memory 203132 kb
Host smart-810d9b57-d7e8-4e83-9521-c656fb47cbdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348613585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
348613585
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.556190033
Short name T999
Test name
Test status
Simulation time 158312968 ps
CPU time 3.91 seconds
Started Feb 21 12:41:28 PM PST 24
Finished Feb 21 12:41:33 PM PST 24
Peak memory 206820 kb
Host smart-88632c15-e55e-434c-a4d0-86ed5782efa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556190033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.556190033
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1152432787
Short name T1092
Test name
Test status
Simulation time 27895422 ps
CPU time 2.02 seconds
Started Feb 21 12:41:19 PM PST 24
Finished Feb 21 12:41:22 PM PST 24
Peak memory 215212 kb
Host smart-59ef6d09-6362-4c44-b952-e1605ab88afb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152432787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
152432787
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.23116700
Short name T102
Test name
Test status
Simulation time 2535931010 ps
CPU time 15.79 seconds
Started Feb 21 12:41:26 PM PST 24
Finished Feb 21 12:41:42 PM PST 24
Peak memory 215152 kb
Host smart-d31a148e-67ce-4cdf-92c1-48fab1513112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23116700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_t
l_intg_err.23116700
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.251728513
Short name T1052
Test name
Test status
Simulation time 238810755 ps
CPU time 6.95 seconds
Started Feb 21 12:41:29 PM PST 24
Finished Feb 21 12:41:37 PM PST 24
Peak memory 217196 kb
Host smart-1d525ab5-6a83-4088-bdb3-d4858544082c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251728513 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.251728513
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1036932544
Short name T116
Test name
Test status
Simulation time 42970989 ps
CPU time 1.38 seconds
Started Feb 21 12:41:05 PM PST 24
Finished Feb 21 12:41:07 PM PST 24
Peak memory 206856 kb
Host smart-5349f254-fd0e-4a89-afe0-12616b7c82ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036932544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
036932544
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3496530854
Short name T1028
Test name
Test status
Simulation time 15281395 ps
CPU time 0.72 seconds
Started Feb 21 12:41:18 PM PST 24
Finished Feb 21 12:41:19 PM PST 24
Peak memory 202748 kb
Host smart-465aca5c-77e9-45ad-9e7b-17fe65d6b41b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496530854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
496530854
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.702715361
Short name T1038
Test name
Test status
Simulation time 107411186 ps
CPU time 1.73 seconds
Started Feb 21 12:41:25 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 206716 kb
Host smart-c48e0229-6a1c-4ca9-95ea-dc93008bfa5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702715361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.702715361
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.223143649
Short name T90
Test name
Test status
Simulation time 382287411 ps
CPU time 2.77 seconds
Started Feb 21 12:41:04 PM PST 24
Finished Feb 21 12:41:07 PM PST 24
Peak memory 215380 kb
Host smart-a09a30a0-bf4e-4462-aa22-f29654e5ee96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223143649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.223143649
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1050781091
Short name T86
Test name
Test status
Simulation time 192385123 ps
CPU time 3.73 seconds
Started Feb 21 12:41:03 PM PST 24
Finished Feb 21 12:41:07 PM PST 24
Peak memory 217028 kb
Host smart-4d607f85-8b31-4ade-a0d1-dd8eeeb250b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050781091 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1050781091
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.891971926
Short name T1054
Test name
Test status
Simulation time 146317280 ps
CPU time 2.39 seconds
Started Feb 21 12:41:21 PM PST 24
Finished Feb 21 12:41:24 PM PST 24
Peak memory 206756 kb
Host smart-331b699d-185d-4b0f-81c7-1b175b777db6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891971926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.891971926
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3011589729
Short name T991
Test name
Test status
Simulation time 54678795 ps
CPU time 0.74 seconds
Started Feb 21 12:41:08 PM PST 24
Finished Feb 21 12:41:10 PM PST 24
Peak memory 202764 kb
Host smart-4210800a-1f35-47c9-b6ab-3b22d771eec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011589729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
011589729
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3633147508
Short name T1100
Test name
Test status
Simulation time 185716906 ps
CPU time 3.83 seconds
Started Feb 21 12:41:23 PM PST 24
Finished Feb 21 12:41:28 PM PST 24
Peak memory 215132 kb
Host smart-98188819-eaa4-49d4-bf15-580e2ce3924e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633147508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3633147508
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1225298356
Short name T91
Test name
Test status
Simulation time 2483802720 ps
CPU time 3.72 seconds
Started Feb 21 12:41:22 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 216400 kb
Host smart-31a243d4-8cd0-42d8-a32c-027a856b04b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225298356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
225298356
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1167982631
Short name T79
Test name
Test status
Simulation time 2178129239 ps
CPU time 14.03 seconds
Started Feb 21 12:41:11 PM PST 24
Finished Feb 21 12:41:26 PM PST 24
Peak memory 215188 kb
Host smart-a4686cad-8900-4c1e-8079-a68327ae6ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167982631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1167982631
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3250126128
Short name T365
Test name
Test status
Simulation time 14389064 ps
CPU time 0.72 seconds
Started Feb 21 02:21:12 PM PST 24
Finished Feb 21 02:21:13 PM PST 24
Peak memory 204404 kb
Host smart-e42206ef-f62e-4d59-a8d4-2217a1f2885f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250126128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
250126128
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2699135019
Short name T911
Test name
Test status
Simulation time 1491164163 ps
CPU time 4.4 seconds
Started Feb 21 02:20:57 PM PST 24
Finished Feb 21 02:21:02 PM PST 24
Peak memory 232872 kb
Host smart-25ddc40f-43d4-4854-90b2-e843247e9a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699135019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2699135019
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2773300903
Short name T394
Test name
Test status
Simulation time 36868065 ps
CPU time 0.71 seconds
Started Feb 21 02:20:40 PM PST 24
Finished Feb 21 02:20:41 PM PST 24
Peak memory 205488 kb
Host smart-23f08a8d-7bb0-400f-9a63-4deee5d9418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773300903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2773300903
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4090948747
Short name T557
Test name
Test status
Simulation time 28514758501 ps
CPU time 141.19 seconds
Started Feb 21 02:20:58 PM PST 24
Finished Feb 21 02:23:20 PM PST 24
Peak memory 252220 kb
Host smart-79fbc50e-d25c-49a1-b4af-71d0844ce22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090948747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4090948747
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1612046968
Short name T561
Test name
Test status
Simulation time 8412971654 ps
CPU time 106.86 seconds
Started Feb 21 02:20:59 PM PST 24
Finished Feb 21 02:22:47 PM PST 24
Peak memory 254352 kb
Host smart-26006983-b756-47de-aca3-ea120851c99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612046968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1612046968
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.806538645
Short name T739
Test name
Test status
Simulation time 258889580252 ps
CPU time 223.52 seconds
Started Feb 21 02:20:59 PM PST 24
Finished Feb 21 02:24:43 PM PST 24
Peak memory 236136 kb
Host smart-a2a68cdc-3d4c-4f49-b8bf-3aabd490fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806538645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
806538645
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3450870009
Short name T862
Test name
Test status
Simulation time 5393356137 ps
CPU time 21.32 seconds
Started Feb 21 02:20:59 PM PST 24
Finished Feb 21 02:21:21 PM PST 24
Peak memory 224716 kb
Host smart-2b98e7b2-6bb2-4366-a2ac-02d904701869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450870009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3450870009
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2856779284
Short name T477
Test name
Test status
Simulation time 59515621 ps
CPU time 2.56 seconds
Started Feb 21 02:20:57 PM PST 24
Finished Feb 21 02:21:00 PM PST 24
Peak memory 232744 kb
Host smart-4d0de975-bcb8-48e8-9ece-763c9602f461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856779284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2856779284
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1278723210
Short name T218
Test name
Test status
Simulation time 4723064614 ps
CPU time 14.95 seconds
Started Feb 21 02:21:01 PM PST 24
Finished Feb 21 02:21:17 PM PST 24
Peak memory 238044 kb
Host smart-b3b38561-5834-41f2-bdf4-eb0eba2129ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278723210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1278723210
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2394281556
Short name T686
Test name
Test status
Simulation time 10161474165 ps
CPU time 9.61 seconds
Started Feb 21 02:20:58 PM PST 24
Finished Feb 21 02:21:08 PM PST 24
Peak memory 233524 kb
Host smart-bb365042-f25a-427d-ae6e-5c9f4bbfe2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394281556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2394281556
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3782477581
Short name T103
Test name
Test status
Simulation time 4257103673 ps
CPU time 14.09 seconds
Started Feb 21 02:20:54 PM PST 24
Finished Feb 21 02:21:08 PM PST 24
Peak memory 233584 kb
Host smart-07b2b1ee-bb97-461e-87ff-9be07bf749c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782477581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3782477581
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3931709862
Short name T571
Test name
Test status
Simulation time 44899103 ps
CPU time 0.74 seconds
Started Feb 21 02:20:59 PM PST 24
Finished Feb 21 02:21:00 PM PST 24
Peak memory 216348 kb
Host smart-4ba8c038-dfbd-49b5-9292-52c87d64579b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931709862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3931709862
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3307818652
Short name T379
Test name
Test status
Simulation time 1927624635 ps
CPU time 3.81 seconds
Started Feb 21 02:21:12 PM PST 24
Finished Feb 21 02:21:16 PM PST 24
Peak memory 216652 kb
Host smart-55df7401-8e6d-43cd-86ba-b4f1881531f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3307818652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3307818652
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.647122537
Short name T48
Test name
Test status
Simulation time 440376029 ps
CPU time 1.11 seconds
Started Feb 21 02:21:11 PM PST 24
Finished Feb 21 02:21:13 PM PST 24
Peak memory 235432 kb
Host smart-e2091876-eff1-4cb5-8cae-ea4430b7b233
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647122537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.647122537
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3216549587
Short name T437
Test name
Test status
Simulation time 30841322853 ps
CPU time 108.05 seconds
Started Feb 21 02:20:57 PM PST 24
Finished Feb 21 02:22:46 PM PST 24
Peak memory 216532 kb
Host smart-81cf6047-9338-419e-a78f-5eeaf700c20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216549587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3216549587
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.666268113
Short name T427
Test name
Test status
Simulation time 580953014 ps
CPU time 4.53 seconds
Started Feb 21 02:20:53 PM PST 24
Finished Feb 21 02:20:58 PM PST 24
Peak memory 216316 kb
Host smart-47484fa5-681e-4e6f-945f-f04d6814f396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666268113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.666268113
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3346058203
Short name T324
Test name
Test status
Simulation time 422270399 ps
CPU time 1.52 seconds
Started Feb 21 02:20:59 PM PST 24
Finished Feb 21 02:21:01 PM PST 24
Peak memory 216832 kb
Host smart-d9623e86-4929-45bf-bdb2-7e3364ef02fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346058203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3346058203
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.667279523
Short name T746
Test name
Test status
Simulation time 116481869 ps
CPU time 0.91 seconds
Started Feb 21 02:20:56 PM PST 24
Finished Feb 21 02:20:58 PM PST 24
Peak memory 205480 kb
Host smart-8a46cce0-dc87-4738-8008-45bf2602a447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667279523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.667279523
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1328353937
Short name T354
Test name
Test status
Simulation time 13624186208 ps
CPU time 45.3 seconds
Started Feb 21 02:20:58 PM PST 24
Finished Feb 21 02:21:44 PM PST 24
Peak memory 248656 kb
Host smart-8117a944-7621-44d3-b3b9-42219d938ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328353937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1328353937
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2953688756
Short name T727
Test name
Test status
Simulation time 75611322 ps
CPU time 0.67 seconds
Started Feb 21 02:21:31 PM PST 24
Finished Feb 21 02:21:32 PM PST 24
Peak memory 204364 kb
Host smart-dbccd303-d847-49c0-a1d9-801f507ec0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953688756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
953688756
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2649130467
Short name T654
Test name
Test status
Simulation time 227061316 ps
CPU time 2.55 seconds
Started Feb 21 02:21:22 PM PST 24
Finished Feb 21 02:21:25 PM PST 24
Peak memory 224560 kb
Host smart-33b4a6d6-3da1-4ad7-ba6d-36a38838603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649130467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2649130467
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.855137236
Short name T693
Test name
Test status
Simulation time 42530704 ps
CPU time 0.73 seconds
Started Feb 21 02:21:11 PM PST 24
Finished Feb 21 02:21:12 PM PST 24
Peak memory 205500 kb
Host smart-db829f0e-e6d5-4c26-b4d2-bd93a9495352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855137236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.855137236
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2514410339
Short name T271
Test name
Test status
Simulation time 41773308493 ps
CPU time 354.24 seconds
Started Feb 21 02:21:20 PM PST 24
Finished Feb 21 02:27:15 PM PST 24
Peak memory 273272 kb
Host smart-2aa20321-8045-49b6-8276-ad86625acdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514410339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2514410339
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.284763066
Short name T469
Test name
Test status
Simulation time 48843316564 ps
CPU time 124.37 seconds
Started Feb 21 02:21:22 PM PST 24
Finished Feb 21 02:23:27 PM PST 24
Peak memory 250308 kb
Host smart-87ccc85a-471b-4293-a326-512feab8e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284763066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
284763066
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3908095825
Short name T764
Test name
Test status
Simulation time 1340338434 ps
CPU time 12.95 seconds
Started Feb 21 02:21:21 PM PST 24
Finished Feb 21 02:21:35 PM PST 24
Peak memory 241168 kb
Host smart-5aafbab9-c3e3-41f5-bc9b-8e6f1d54ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908095825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3908095825
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.407483740
Short name T842
Test name
Test status
Simulation time 358258231 ps
CPU time 3.15 seconds
Started Feb 21 02:21:23 PM PST 24
Finished Feb 21 02:21:26 PM PST 24
Peak memory 216504 kb
Host smart-692f076f-043e-4bf9-882b-d4e93794bb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407483740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.407483740
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2632314186
Short name T410
Test name
Test status
Simulation time 11307625339 ps
CPU time 19.48 seconds
Started Feb 21 02:21:20 PM PST 24
Finished Feb 21 02:21:40 PM PST 24
Peak memory 251192 kb
Host smart-ccc344ea-0357-4172-9a46-98ab82fa2b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632314186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2632314186
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.273896494
Short name T296
Test name
Test status
Simulation time 25278937 ps
CPU time 0.96 seconds
Started Feb 21 02:21:14 PM PST 24
Finished Feb 21 02:21:15 PM PST 24
Peak memory 217876 kb
Host smart-d1b8ec1e-0001-4f37-82af-977924ec7afa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273896494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.273896494
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2624963949
Short name T534
Test name
Test status
Simulation time 665446469 ps
CPU time 8.43 seconds
Started Feb 21 02:21:20 PM PST 24
Finished Feb 21 02:21:29 PM PST 24
Peak memory 217080 kb
Host smart-59d42cd4-4b9f-4eeb-a7d2-81c99c9c14e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624963949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2624963949
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4085188345
Short name T823
Test name
Test status
Simulation time 13862973462 ps
CPU time 28.61 seconds
Started Feb 21 02:21:19 PM PST 24
Finished Feb 21 02:21:49 PM PST 24
Peak memory 240224 kb
Host smart-4a6fb922-7c5f-475f-97dc-2b714fd72959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085188345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4085188345
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3172165237
Short name T316
Test name
Test status
Simulation time 693139930 ps
CPU time 4.05 seconds
Started Feb 21 02:21:19 PM PST 24
Finished Feb 21 02:21:24 PM PST 24
Peak memory 220240 kb
Host smart-ffc1ff27-2c83-4009-8297-33c988b713df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3172165237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3172165237
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1677744593
Short name T47
Test name
Test status
Simulation time 109573581 ps
CPU time 0.94 seconds
Started Feb 21 02:21:35 PM PST 24
Finished Feb 21 02:21:36 PM PST 24
Peak memory 234360 kb
Host smart-a128c474-7e3d-449d-832a-0ed4e50ffa04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677744593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1677744593
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.617342359
Short name T40
Test name
Test status
Simulation time 190191419 ps
CPU time 0.99 seconds
Started Feb 21 02:21:34 PM PST 24
Finished Feb 21 02:21:36 PM PST 24
Peak memory 206184 kb
Host smart-a6792f06-d651-413b-b0dc-630f8b9b1528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617342359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.617342359
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2975916045
Short name T436
Test name
Test status
Simulation time 16212123770 ps
CPU time 46.16 seconds
Started Feb 21 02:21:12 PM PST 24
Finished Feb 21 02:21:59 PM PST 24
Peak memory 216468 kb
Host smart-f0950a6c-6e7e-405a-b0c5-ee466363146d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975916045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2975916045
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3015006780
Short name T389
Test name
Test status
Simulation time 36468140036 ps
CPU time 23.03 seconds
Started Feb 21 02:21:12 PM PST 24
Finished Feb 21 02:21:35 PM PST 24
Peak memory 216516 kb
Host smart-0f7ae175-566d-43f5-96c7-6fe5d3880bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015006780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3015006780
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2679758600
Short name T690
Test name
Test status
Simulation time 372222264 ps
CPU time 9.54 seconds
Started Feb 21 02:21:13 PM PST 24
Finished Feb 21 02:21:23 PM PST 24
Peak memory 209416 kb
Host smart-3d85ac85-8d5c-426e-be72-6ed0096a94a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679758600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2679758600
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_upload.3399318197
Short name T408
Test name
Test status
Simulation time 2652681409 ps
CPU time 6.24 seconds
Started Feb 21 02:21:19 PM PST 24
Finished Feb 21 02:21:26 PM PST 24
Peak memory 224652 kb
Host smart-e521cafa-682a-476b-a3d4-c318c3aff2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399318197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3399318197
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2480818330
Short name T683
Test name
Test status
Simulation time 12053819 ps
CPU time 0.75 seconds
Started Feb 21 02:23:42 PM PST 24
Finished Feb 21 02:23:43 PM PST 24
Peak memory 204720 kb
Host smart-27329971-aeaf-49b4-a022-5d7cbc852882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480818330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2480818330
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2220421694
Short name T963
Test name
Test status
Simulation time 407974835 ps
CPU time 3.99 seconds
Started Feb 21 02:23:42 PM PST 24
Finished Feb 21 02:23:47 PM PST 24
Peak memory 218800 kb
Host smart-ed90f284-1d6f-45f6-9cd1-793c77a5d9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220421694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2220421694
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4277733198
Short name T341
Test name
Test status
Simulation time 47031095 ps
CPU time 0.77 seconds
Started Feb 21 02:23:13 PM PST 24
Finished Feb 21 02:23:14 PM PST 24
Peak memory 206200 kb
Host smart-b10475f5-29a9-495c-b6ee-2230f4701cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277733198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4277733198
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3081433394
Short name T387
Test name
Test status
Simulation time 4366860868 ps
CPU time 36.86 seconds
Started Feb 21 02:23:40 PM PST 24
Finished Feb 21 02:24:18 PM PST 24
Peak memory 256052 kb
Host smart-aa94d1cc-97ad-4c60-a28b-989504aece95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081433394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3081433394
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.178477426
Short name T900
Test name
Test status
Simulation time 27449709114 ps
CPU time 166.56 seconds
Started Feb 21 02:23:35 PM PST 24
Finished Feb 21 02:26:22 PM PST 24
Peak memory 249596 kb
Host smart-7a933c8d-2771-4680-8548-dfead21238d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178477426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.178477426
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2445834227
Short name T673
Test name
Test status
Simulation time 20394275594 ps
CPU time 96.07 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:25:20 PM PST 24
Peak memory 238688 kb
Host smart-aecb8a65-2a06-4667-a1c9-22b4f1eb4d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445834227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2445834227
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3301398651
Short name T633
Test name
Test status
Simulation time 13508535745 ps
CPU time 20.25 seconds
Started Feb 21 02:23:36 PM PST 24
Finished Feb 21 02:23:57 PM PST 24
Peak memory 232956 kb
Host smart-60a15344-cee2-4f66-89e1-16a0d99caaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301398651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3301398651
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2383754498
Short name T226
Test name
Test status
Simulation time 137351888 ps
CPU time 3.35 seconds
Started Feb 21 02:23:31 PM PST 24
Finished Feb 21 02:23:35 PM PST 24
Peak memory 232976 kb
Host smart-a8295a3c-5a6f-4365-9b7c-e1a7f10afa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383754498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2383754498
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3220918597
Short name T170
Test name
Test status
Simulation time 3560454697 ps
CPU time 6.4 seconds
Started Feb 21 02:23:27 PM PST 24
Finished Feb 21 02:23:34 PM PST 24
Peak memory 233560 kb
Host smart-58e2e38b-6d53-45ac-9a99-3689b4640955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220918597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3220918597
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.917945584
Short name T972
Test name
Test status
Simulation time 81337371 ps
CPU time 1.05 seconds
Started Feb 21 02:23:18 PM PST 24
Finished Feb 21 02:23:19 PM PST 24
Peak memory 216652 kb
Host smart-c66d7faa-24ad-4612-9b4d-243a804211c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917945584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.917945584
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.608992411
Short name T779
Test name
Test status
Simulation time 587215916 ps
CPU time 7.64 seconds
Started Feb 21 02:23:33 PM PST 24
Finished Feb 21 02:23:41 PM PST 24
Peak memory 228988 kb
Host smart-a8135d1f-62b0-4a65-b6c2-07dac9ecb991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608992411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.608992411
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3202548857
Short name T973
Test name
Test status
Simulation time 6160686353 ps
CPU time 7.75 seconds
Started Feb 21 02:23:27 PM PST 24
Finished Feb 21 02:23:36 PM PST 24
Peak memory 223644 kb
Host smart-30e25971-28a7-4d1b-b06a-876b9c13253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202548857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3202548857
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1561979110
Short name T975
Test name
Test status
Simulation time 17707247 ps
CPU time 0.74 seconds
Started Feb 21 02:23:25 PM PST 24
Finished Feb 21 02:23:27 PM PST 24
Peak memory 216364 kb
Host smart-2d3fe9d6-e2bf-401e-bcff-7c6506650bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561979110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1561979110
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2751031604
Short name T368
Test name
Test status
Simulation time 5319558841 ps
CPU time 6.73 seconds
Started Feb 21 02:23:42 PM PST 24
Finished Feb 21 02:23:50 PM PST 24
Peak memory 216456 kb
Host smart-6e85748c-a33a-4263-af93-a737912f272a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2751031604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2751031604
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.539065930
Short name T283
Test name
Test status
Simulation time 10274357237 ps
CPU time 41.26 seconds
Started Feb 21 02:23:26 PM PST 24
Finished Feb 21 02:24:08 PM PST 24
Peak memory 216508 kb
Host smart-57854f3d-d1e4-4bb1-934d-703affdf4c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539065930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.539065930
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4142294320
Short name T735
Test name
Test status
Simulation time 862273249 ps
CPU time 3.08 seconds
Started Feb 21 02:23:27 PM PST 24
Finished Feb 21 02:23:31 PM PST 24
Peak memory 208028 kb
Host smart-76254834-ff10-4e90-86ca-ae1f17b2f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142294320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4142294320
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1368534503
Short name T898
Test name
Test status
Simulation time 1712062596 ps
CPU time 7.59 seconds
Started Feb 21 02:23:39 PM PST 24
Finished Feb 21 02:23:47 PM PST 24
Peak memory 216552 kb
Host smart-6aaef9a2-9fbc-4064-9e33-bcf2f9bfe8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368534503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1368534503
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1681588565
Short name T769
Test name
Test status
Simulation time 319835758 ps
CPU time 0.76 seconds
Started Feb 21 02:23:39 PM PST 24
Finished Feb 21 02:23:41 PM PST 24
Peak memory 205496 kb
Host smart-06e10d76-ba52-45a0-93af-d821d97ecccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681588565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1681588565
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3763241386
Short name T887
Test name
Test status
Simulation time 2398283650 ps
CPU time 6.26 seconds
Started Feb 21 02:23:27 PM PST 24
Finished Feb 21 02:23:34 PM PST 24
Peak memory 234836 kb
Host smart-5be64924-5d03-482c-bdcb-5bbd32b72eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763241386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3763241386
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1304283688
Short name T507
Test name
Test status
Simulation time 487724106 ps
CPU time 3.43 seconds
Started Feb 21 02:23:40 PM PST 24
Finished Feb 21 02:23:44 PM PST 24
Peak memory 234644 kb
Host smart-f310f448-5df9-4ab5-bbf7-f797d929cd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304283688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1304283688
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.344290372
Short name T810
Test name
Test status
Simulation time 18895548 ps
CPU time 0.76 seconds
Started Feb 21 02:23:36 PM PST 24
Finished Feb 21 02:23:38 PM PST 24
Peak memory 205540 kb
Host smart-c07444c7-0bd0-42d7-8f18-52fb251f08ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344290372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.344290372
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1626509162
Short name T916
Test name
Test status
Simulation time 41762924400 ps
CPU time 87.27 seconds
Started Feb 21 02:23:35 PM PST 24
Finished Feb 21 02:25:03 PM PST 24
Peak memory 249276 kb
Host smart-810580b3-ce4e-4585-bc01-3f59fd863a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626509162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1626509162
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.363969085
Short name T266
Test name
Test status
Simulation time 15340158376 ps
CPU time 120.83 seconds
Started Feb 21 02:23:33 PM PST 24
Finished Feb 21 02:25:34 PM PST 24
Peak memory 256040 kb
Host smart-a7e71dc7-6212-4a59-812c-04f15cbf512e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363969085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.363969085
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.21561988
Short name T360
Test name
Test status
Simulation time 414095229 ps
CPU time 12.72 seconds
Started Feb 21 02:23:33 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 232836 kb
Host smart-44b4a0ac-fdbe-45f1-8e56-e3714f9bf368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21561988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.21561988
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1961649233
Short name T905
Test name
Test status
Simulation time 2953727384 ps
CPU time 5.24 seconds
Started Feb 21 02:23:39 PM PST 24
Finished Feb 21 02:23:45 PM PST 24
Peak memory 219064 kb
Host smart-e6b6b789-d0f3-46d4-b223-68261ff00082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961649233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1961649233
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4243050006
Short name T72
Test name
Test status
Simulation time 157532115098 ps
CPU time 26.71 seconds
Started Feb 21 02:23:31 PM PST 24
Finished Feb 21 02:23:59 PM PST 24
Peak memory 233340 kb
Host smart-0132e55b-da97-4b6d-b2c6-1ec26d2bfebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243050006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4243050006
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2147723162
Short name T22
Test name
Test status
Simulation time 178267750 ps
CPU time 1.06 seconds
Started Feb 21 02:23:46 PM PST 24
Finished Feb 21 02:23:48 PM PST 24
Peak memory 216636 kb
Host smart-6c3b645a-d61f-4282-bfbc-9013f1f0bda4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147723162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2147723162
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3086584990
Short name T235
Test name
Test status
Simulation time 233553717344 ps
CPU time 29.72 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:24:14 PM PST 24
Peak memory 218660 kb
Host smart-0179a67f-e61c-4d8f-bcf7-83f45c0dad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086584990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3086584990
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1313763849
Short name T396
Test name
Test status
Simulation time 1261253542 ps
CPU time 5.48 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:50 PM PST 24
Peak memory 233520 kb
Host smart-3c481f2a-296b-4e6f-997d-8d7c0abe6b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313763849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1313763849
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3293304495
Short name T917
Test name
Test status
Simulation time 17243554 ps
CPU time 0.74 seconds
Started Feb 21 02:23:48 PM PST 24
Finished Feb 21 02:23:50 PM PST 24
Peak memory 216348 kb
Host smart-6cec46d5-57fb-4d3e-b030-2e1686e8d7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293304495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3293304495
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.969877062
Short name T504
Test name
Test status
Simulation time 1036527264 ps
CPU time 4.03 seconds
Started Feb 21 02:23:34 PM PST 24
Finished Feb 21 02:23:39 PM PST 24
Peak memory 220240 kb
Host smart-3362eff7-b1eb-4067-b385-0e28d0392493
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=969877062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.969877062
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3023506829
Short name T679
Test name
Test status
Simulation time 2695929441 ps
CPU time 9.59 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:23:53 PM PST 24
Peak memory 216540 kb
Host smart-9528f030-e1ca-4a7f-92c3-eb7cffdb76fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023506829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3023506829
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1901544089
Short name T65
Test name
Test status
Simulation time 5956115430 ps
CPU time 6.07 seconds
Started Feb 21 02:23:41 PM PST 24
Finished Feb 21 02:23:48 PM PST 24
Peak memory 216492 kb
Host smart-cc1118de-3ccd-418c-8e39-1bbe14381038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901544089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1901544089
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3126317292
Short name T288
Test name
Test status
Simulation time 51402872 ps
CPU time 1.89 seconds
Started Feb 21 02:23:39 PM PST 24
Finished Feb 21 02:23:41 PM PST 24
Peak memory 216744 kb
Host smart-f6b78fb2-f961-4849-ac55-c869fd91d1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126317292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3126317292
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1658283864
Short name T346
Test name
Test status
Simulation time 37819751 ps
CPU time 0.89 seconds
Started Feb 21 02:23:42 PM PST 24
Finished Feb 21 02:23:44 PM PST 24
Peak memory 206496 kb
Host smart-81e36e31-7c6e-4953-ae0e-a570d2dcc60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658283864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1658283864
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1656127943
Short name T826
Test name
Test status
Simulation time 3178151718 ps
CPU time 12.3 seconds
Started Feb 21 02:23:34 PM PST 24
Finished Feb 21 02:23:47 PM PST 24
Peak memory 223764 kb
Host smart-3c26d78d-1d45-458b-bc75-a6ed5e6765f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656127943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1656127943
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3738269834
Short name T653
Test name
Test status
Simulation time 25122720 ps
CPU time 0.72 seconds
Started Feb 21 02:23:49 PM PST 24
Finished Feb 21 02:23:50 PM PST 24
Peak memory 204992 kb
Host smart-e20cc4e3-c258-4bb5-87b6-d2d526f9f81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738269834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3738269834
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3945299866
Short name T229
Test name
Test status
Simulation time 1208011088 ps
CPU time 5.49 seconds
Started Feb 21 02:23:42 PM PST 24
Finished Feb 21 02:23:48 PM PST 24
Peak memory 232960 kb
Host smart-ef5a9893-851a-4e30-bd14-b21814147362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945299866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3945299866
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.394013983
Short name T934
Test name
Test status
Simulation time 34336364 ps
CPU time 0.78 seconds
Started Feb 21 02:23:42 PM PST 24
Finished Feb 21 02:23:44 PM PST 24
Peak memory 206188 kb
Host smart-5f3685c3-7448-417c-b1c7-1d5c32968ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394013983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.394013983
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4091983092
Short name T855
Test name
Test status
Simulation time 16985183482 ps
CPU time 56.64 seconds
Started Feb 21 02:23:49 PM PST 24
Finished Feb 21 02:24:46 PM PST 24
Peak memory 252500 kb
Host smart-1d502d6e-2162-43a1-9314-b31ddecd0220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091983092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4091983092
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2784017361
Short name T594
Test name
Test status
Simulation time 154818108 ps
CPU time 2.54 seconds
Started Feb 21 02:23:47 PM PST 24
Finished Feb 21 02:23:50 PM PST 24
Peak memory 232840 kb
Host smart-1bf30974-ea73-4dff-8175-23d52ff319db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784017361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2784017361
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.626456775
Short name T666
Test name
Test status
Simulation time 3349423630 ps
CPU time 8.39 seconds
Started Feb 21 02:23:39 PM PST 24
Finished Feb 21 02:23:48 PM PST 24
Peak memory 233756 kb
Host smart-afe93439-3f8a-4bf1-937a-eeda0a4bb75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626456775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.626456775
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1373349605
Short name T366
Test name
Test status
Simulation time 105118752 ps
CPU time 1.03 seconds
Started Feb 21 02:23:32 PM PST 24
Finished Feb 21 02:23:34 PM PST 24
Peak memory 217900 kb
Host smart-b4a8cbfb-f058-4a8f-9ffd-c65850aeaa39
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373349605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1373349605
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2618140300
Short name T187
Test name
Test status
Simulation time 8996170095 ps
CPU time 11.9 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:23:56 PM PST 24
Peak memory 223460 kb
Host smart-1dad5a0c-73d1-4633-ae12-427068426220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618140300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2618140300
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.464455424
Short name T641
Test name
Test status
Simulation time 1490246365 ps
CPU time 5.18 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:51 PM PST 24
Peak memory 217824 kb
Host smart-50390a63-59bd-4f90-87bc-e0ad8e8049ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464455424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.464455424
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.2371025430
Short name T414
Test name
Test status
Simulation time 38892492 ps
CPU time 0.73 seconds
Started Feb 21 02:23:33 PM PST 24
Finished Feb 21 02:23:34 PM PST 24
Peak memory 216316 kb
Host smart-d0eb3c55-9b23-4b48-ade9-99c7757130e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371025430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.2371025430
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3391489383
Short name T124
Test name
Test status
Simulation time 173416531 ps
CPU time 3.54 seconds
Started Feb 21 02:23:32 PM PST 24
Finished Feb 21 02:23:37 PM PST 24
Peak memory 221484 kb
Host smart-a105ccce-01ef-41e6-8cd9-b161bfbe646f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3391489383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3391489383
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1442149169
Short name T39
Test name
Test status
Simulation time 252406842 ps
CPU time 1.16 seconds
Started Feb 21 02:23:33 PM PST 24
Finished Feb 21 02:23:36 PM PST 24
Peak memory 206800 kb
Host smart-b89875c4-535b-4761-9abd-1277ab3b789e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442149169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1442149169
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1832887935
Short name T336
Test name
Test status
Simulation time 11654527047 ps
CPU time 46.19 seconds
Started Feb 21 02:23:47 PM PST 24
Finished Feb 21 02:24:34 PM PST 24
Peak memory 216476 kb
Host smart-061d8e94-1ca1-4bee-aff2-14777526888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832887935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1832887935
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1884738491
Short name T801
Test name
Test status
Simulation time 1150345988 ps
CPU time 3.44 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:23:48 PM PST 24
Peak memory 216380 kb
Host smart-fe0340ce-2e5c-4e02-8393-75e33b087472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884738491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1884738491
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.106048971
Short name T515
Test name
Test status
Simulation time 483478187 ps
CPU time 5.97 seconds
Started Feb 21 02:23:34 PM PST 24
Finished Feb 21 02:23:41 PM PST 24
Peak memory 216456 kb
Host smart-fb9b467b-fcab-46bd-9ade-4b5a2f6cd025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106048971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.106048971
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2917214426
Short name T904
Test name
Test status
Simulation time 460333433 ps
CPU time 1.15 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:23:45 PM PST 24
Peak memory 206512 kb
Host smart-012b09e3-fe32-4f6c-a5be-8083ff4219d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917214426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2917214426
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1977183299
Short name T230
Test name
Test status
Simulation time 12839222814 ps
CPU time 22.22 seconds
Started Feb 21 02:23:39 PM PST 24
Finished Feb 21 02:24:02 PM PST 24
Peak memory 227268 kb
Host smart-537e7c1b-6717-450c-8250-b926acadf266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977183299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1977183299
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2060177356
Short name T712
Test name
Test status
Simulation time 14818618 ps
CPU time 0.7 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 204400 kb
Host smart-4f78f3a4-b13e-4551-a10c-d6c4bfe9fb3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060177356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2060177356
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.75762139
Short name T819
Test name
Test status
Simulation time 2089901739 ps
CPU time 2.54 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:47 PM PST 24
Peak memory 224636 kb
Host smart-d0d052bf-7337-4a74-894b-406ccc31cf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75762139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.75762139
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.567746102
Short name T554
Test name
Test status
Simulation time 34701847 ps
CPU time 0.81 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 206352 kb
Host smart-76c90d90-5d7a-474d-bff9-b8719e04ed89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567746102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.567746102
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2144697031
Short name T586
Test name
Test status
Simulation time 280751933857 ps
CPU time 151.58 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:26:16 PM PST 24
Peak memory 249280 kb
Host smart-7e530871-2e35-454f-8cc3-6b8b8fc8b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144697031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2144697031
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1883393337
Short name T894
Test name
Test status
Simulation time 13536561680 ps
CPU time 154.48 seconds
Started Feb 21 02:23:41 PM PST 24
Finished Feb 21 02:26:16 PM PST 24
Peak memory 257548 kb
Host smart-6181c648-aacf-4de6-a9cd-52b44977e6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883393337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1883393337
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1790616746
Short name T185
Test name
Test status
Simulation time 28703949437 ps
CPU time 65.38 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:24:50 PM PST 24
Peak memory 249464 kb
Host smart-9a26f9a3-6310-47c7-9069-f27d32703c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790616746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1790616746
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.950012246
Short name T941
Test name
Test status
Simulation time 4036808681 ps
CPU time 16.91 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:24:01 PM PST 24
Peak memory 224592 kb
Host smart-a9e157ae-7afd-4a11-b792-93d8e0f80688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950012246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.950012246
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3133594959
Short name T483
Test name
Test status
Simulation time 415649944 ps
CPU time 3.67 seconds
Started Feb 21 02:23:41 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 217748 kb
Host smart-57931a75-e175-4453-8320-2d8dc2439b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133594959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3133594959
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2107825600
Short name T209
Test name
Test status
Simulation time 954650346 ps
CPU time 5.45 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:23:49 PM PST 24
Peak memory 220388 kb
Host smart-51666807-cca7-492f-b2ad-feb80e442610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107825600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2107825600
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3245643054
Short name T528
Test name
Test status
Simulation time 88519376 ps
CPU time 1.15 seconds
Started Feb 21 02:23:42 PM PST 24
Finished Feb 21 02:23:43 PM PST 24
Peak memory 216636 kb
Host smart-525f08ef-986e-4b5d-8890-faef97aa5e4e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245643054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3245643054
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2114508847
Short name T891
Test name
Test status
Simulation time 2466054482 ps
CPU time 4.85 seconds
Started Feb 21 02:23:37 PM PST 24
Finished Feb 21 02:23:42 PM PST 24
Peak memory 216672 kb
Host smart-d0c5c7fc-f785-4cee-8327-14666af40998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114508847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2114508847
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.257320357
Short name T221
Test name
Test status
Simulation time 7042880769 ps
CPU time 18.07 seconds
Started Feb 21 02:23:41 PM PST 24
Finished Feb 21 02:24:00 PM PST 24
Peak memory 233584 kb
Host smart-7e4f617e-a088-49b2-9abb-0b8cb297a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257320357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.257320357
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.3178880691
Short name T530
Test name
Test status
Simulation time 86381083 ps
CPU time 0.72 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 216508 kb
Host smart-86536e46-cfb8-46a3-8588-7aa0ef5bf845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178880691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.3178880691
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1772399934
Short name T125
Test name
Test status
Simulation time 3560451590 ps
CPU time 5.51 seconds
Started Feb 21 02:23:39 PM PST 24
Finished Feb 21 02:23:45 PM PST 24
Peak memory 220060 kb
Host smart-ddf2c99b-bed9-447a-956b-1c1946445b69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772399934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1772399934
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3891405295
Short name T914
Test name
Test status
Simulation time 10857566864 ps
CPU time 44.54 seconds
Started Feb 21 02:23:54 PM PST 24
Finished Feb 21 02:24:40 PM PST 24
Peak memory 239424 kb
Host smart-52c82ea4-ab74-403e-8bbd-7872481b1898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891405295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3891405295
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2211676398
Short name T62
Test name
Test status
Simulation time 65896627284 ps
CPU time 68.61 seconds
Started Feb 21 02:23:42 PM PST 24
Finished Feb 21 02:24:51 PM PST 24
Peak memory 216484 kb
Host smart-88017f28-0510-4361-b625-f31986b5f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211676398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2211676398
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2458796322
Short name T803
Test name
Test status
Simulation time 1199095162 ps
CPU time 3.75 seconds
Started Feb 21 02:23:41 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 208248 kb
Host smart-6e622dc9-5eec-4c2c-867a-76b938e87412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458796322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2458796322
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4157056135
Short name T872
Test name
Test status
Simulation time 215879399 ps
CPU time 11.59 seconds
Started Feb 21 02:23:35 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 216448 kb
Host smart-ae88aad5-ccc3-4f02-a81f-df53e6e8d0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157056135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4157056135
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2548948642
Short name T840
Test name
Test status
Simulation time 200458719 ps
CPU time 1.2 seconds
Started Feb 21 02:23:43 PM PST 24
Finished Feb 21 02:23:44 PM PST 24
Peak memory 206436 kb
Host smart-187ba4d8-7db7-472e-bbf9-ff6c2ac8c21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548948642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2548948642
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.217321389
Short name T694
Test name
Test status
Simulation time 726761198 ps
CPU time 9.73 seconds
Started Feb 21 02:23:51 PM PST 24
Finished Feb 21 02:24:01 PM PST 24
Peak memory 226100 kb
Host smart-4ec7d1e9-2ce2-4ba1-89e3-a0d71ceda746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217321389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.217321389
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2078684427
Short name T775
Test name
Test status
Simulation time 11778094 ps
CPU time 0.67 seconds
Started Feb 21 02:23:54 PM PST 24
Finished Feb 21 02:23:56 PM PST 24
Peak memory 205008 kb
Host smart-3e5c6efe-0d89-4450-9261-b0d2395eb998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078684427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2078684427
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2409376123
Short name T446
Test name
Test status
Simulation time 3684842851 ps
CPU time 8.32 seconds
Started Feb 21 02:23:53 PM PST 24
Finished Feb 21 02:24:03 PM PST 24
Peak memory 224668 kb
Host smart-b66ca199-09fc-412a-9fb5-7a2932480b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409376123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2409376123
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3113511568
Short name T613
Test name
Test status
Simulation time 17655887 ps
CPU time 0.77 seconds
Started Feb 21 02:23:54 PM PST 24
Finished Feb 21 02:23:56 PM PST 24
Peak memory 205368 kb
Host smart-53e9957c-4c02-4993-af25-3ec6f829e5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113511568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3113511568
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3417790528
Short name T578
Test name
Test status
Simulation time 1963792103 ps
CPU time 39.07 seconds
Started Feb 21 02:23:53 PM PST 24
Finished Feb 21 02:24:33 PM PST 24
Peak memory 249216 kb
Host smart-c976a87d-2184-49d4-b55c-e060c41fb112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417790528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3417790528
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3826379109
Short name T966
Test name
Test status
Simulation time 51182467681 ps
CPU time 265.43 seconds
Started Feb 21 02:24:00 PM PST 24
Finished Feb 21 02:28:26 PM PST 24
Peak memory 265760 kb
Host smart-a290f60f-d181-431c-b9bd-93194128398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826379109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3826379109
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2761966801
Short name T945
Test name
Test status
Simulation time 33510606823 ps
CPU time 34.67 seconds
Started Feb 21 02:23:58 PM PST 24
Finished Feb 21 02:24:33 PM PST 24
Peak memory 249196 kb
Host smart-fc3e2b5f-7442-438a-9af3-afd5d112342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761966801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2761966801
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3367452868
Short name T338
Test name
Test status
Simulation time 2635734463 ps
CPU time 3.56 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:48 PM PST 24
Peak memory 233892 kb
Host smart-c9304e75-6160-4dd4-ada6-746c815bd30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367452868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3367452868
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2996255722
Short name T723
Test name
Test status
Simulation time 5736400547 ps
CPU time 13.06 seconds
Started Feb 21 02:23:45 PM PST 24
Finished Feb 21 02:23:59 PM PST 24
Peak memory 234492 kb
Host smart-8200e96d-daeb-498e-92e3-662730c06006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996255722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2996255722
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2157470392
Short name T901
Test name
Test status
Simulation time 24849332 ps
CPU time 1.09 seconds
Started Feb 21 02:23:45 PM PST 24
Finished Feb 21 02:23:47 PM PST 24
Peak memory 216648 kb
Host smart-5236ce12-dcf2-42a5-ba63-971d3492dca1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157470392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2157470392
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1831468590
Short name T537
Test name
Test status
Simulation time 3063771197 ps
CPU time 3.38 seconds
Started Feb 21 02:23:52 PM PST 24
Finished Feb 21 02:23:56 PM PST 24
Peak memory 218012 kb
Host smart-b1241e74-edac-4677-8aed-d17b5db062d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831468590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1831468590
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3907957310
Short name T344
Test name
Test status
Simulation time 1065842677 ps
CPU time 3.98 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:50 PM PST 24
Peak memory 234708 kb
Host smart-6941d098-39c0-4997-a7b0-dde9ad434771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907957310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3907957310
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1623899683
Short name T701
Test name
Test status
Simulation time 23284082 ps
CPU time 0.75 seconds
Started Feb 21 02:23:48 PM PST 24
Finished Feb 21 02:23:49 PM PST 24
Peak memory 216356 kb
Host smart-e2f79ed9-8254-49d9-ae8a-4e08067448db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623899683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1623899683
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2226417016
Short name T395
Test name
Test status
Simulation time 931972968 ps
CPU time 4.76 seconds
Started Feb 21 02:23:55 PM PST 24
Finished Feb 21 02:24:00 PM PST 24
Peak memory 221508 kb
Host smart-a4e9e3c4-f3a6-4fa3-838b-1113f98662de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2226417016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2226417016
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3265070433
Short name T250
Test name
Test status
Simulation time 15575810809 ps
CPU time 192.4 seconds
Started Feb 21 02:23:56 PM PST 24
Finished Feb 21 02:27:10 PM PST 24
Peak memory 264216 kb
Host smart-2703d4f7-d9c2-4dcf-85c0-13a493634679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265070433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3265070433
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2324052603
Short name T284
Test name
Test status
Simulation time 6027312172 ps
CPU time 42.96 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:24:28 PM PST 24
Peak memory 216516 kb
Host smart-8d1088c3-56fa-423e-9049-f1ee283ce6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324052603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2324052603
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2909205688
Short name T556
Test name
Test status
Simulation time 2273046374 ps
CPU time 6.27 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:51 PM PST 24
Peak memory 216432 kb
Host smart-1579ea2b-0e13-4b2a-8522-97beedf28db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909205688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2909205688
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2559912365
Short name T738
Test name
Test status
Simulation time 1398600952 ps
CPU time 4.93 seconds
Started Feb 21 02:23:44 PM PST 24
Finished Feb 21 02:23:49 PM PST 24
Peak memory 216668 kb
Host smart-3bc83af4-9f57-4c84-8b84-8677f0e66200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559912365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2559912365
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2775254331
Short name T2
Test name
Test status
Simulation time 391663855 ps
CPU time 0.91 seconds
Started Feb 21 02:23:54 PM PST 24
Finished Feb 21 02:23:56 PM PST 24
Peak memory 205692 kb
Host smart-c1fb7a20-2551-4fb1-9d95-8738b7db2ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775254331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2775254331
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2544259233
Short name T486
Test name
Test status
Simulation time 490981490 ps
CPU time 2.16 seconds
Started Feb 21 02:23:54 PM PST 24
Finished Feb 21 02:23:57 PM PST 24
Peak memory 224624 kb
Host smart-a9d5b7a6-ee13-4261-96bc-5604aad3a73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544259233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2544259233
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1429876631
Short name T521
Test name
Test status
Simulation time 31450169 ps
CPU time 0.72 seconds
Started Feb 21 02:24:16 PM PST 24
Finished Feb 21 02:24:18 PM PST 24
Peak memory 205032 kb
Host smart-cf2c00ce-c3db-4741-ad2b-95281ef921ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429876631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1429876631
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.40162152
Short name T848
Test name
Test status
Simulation time 276829801 ps
CPU time 2.65 seconds
Started Feb 21 02:24:04 PM PST 24
Finished Feb 21 02:24:07 PM PST 24
Peak memory 219080 kb
Host smart-0690f7ff-77e5-4c93-9f33-7845c7771f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40162152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.40162152
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4202106236
Short name T55
Test name
Test status
Simulation time 29392216 ps
CPU time 0.79 seconds
Started Feb 21 02:23:58 PM PST 24
Finished Feb 21 02:23:59 PM PST 24
Peak memory 206468 kb
Host smart-81d2645c-5b24-413f-9b2b-0cc543446b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202106236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4202106236
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1016039409
Short name T25
Test name
Test status
Simulation time 26830509280 ps
CPU time 177.33 seconds
Started Feb 21 02:24:12 PM PST 24
Finished Feb 21 02:27:10 PM PST 24
Peak memory 257076 kb
Host smart-8bfdf463-6297-455d-82f5-25981e235ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016039409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1016039409
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2961742395
Short name T261
Test name
Test status
Simulation time 15547738700 ps
CPU time 70.72 seconds
Started Feb 21 02:24:15 PM PST 24
Finished Feb 21 02:25:26 PM PST 24
Peak memory 252464 kb
Host smart-9ce82699-8ca9-4b8a-a82b-7df371223df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961742395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2961742395
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3063368441
Short name T508
Test name
Test status
Simulation time 27171118030 ps
CPU time 41.07 seconds
Started Feb 21 02:24:15 PM PST 24
Finished Feb 21 02:24:56 PM PST 24
Peak memory 236792 kb
Host smart-c0b2a442-b0a9-4e20-aa43-7741f99b88c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063368441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3063368441
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.146533872
Short name T927
Test name
Test status
Simulation time 508253745 ps
CPU time 3.47 seconds
Started Feb 21 02:24:02 PM PST 24
Finished Feb 21 02:24:06 PM PST 24
Peak memory 232924 kb
Host smart-5440fa3c-b904-409f-8a10-05d0c95ec278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146533872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.146533872
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2533843245
Short name T415
Test name
Test status
Simulation time 19107863521 ps
CPU time 52.7 seconds
Started Feb 21 02:24:12 PM PST 24
Finished Feb 21 02:25:05 PM PST 24
Peak memory 232920 kb
Host smart-f50442f3-e97b-40fe-8e77-ad26fc9bfef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533843245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2533843245
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1804797305
Short name T460
Test name
Test status
Simulation time 146229981 ps
CPU time 1.02 seconds
Started Feb 21 02:24:00 PM PST 24
Finished Feb 21 02:24:02 PM PST 24
Peak memory 216640 kb
Host smart-0f80ddb8-a60f-49f9-aa85-86dab3d70110
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804797305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1804797305
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.277972482
Short name T525
Test name
Test status
Simulation time 85841919 ps
CPU time 2.53 seconds
Started Feb 21 02:24:06 PM PST 24
Finished Feb 21 02:24:09 PM PST 24
Peak memory 217028 kb
Host smart-031b31c0-a531-40f5-abb8-a072a33624aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277972482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.277972482
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1336768291
Short name T774
Test name
Test status
Simulation time 17135331192 ps
CPU time 11.72 seconds
Started Feb 21 02:24:11 PM PST 24
Finished Feb 21 02:24:23 PM PST 24
Peak memory 233428 kb
Host smart-859b5f15-f65b-45a3-b71c-4caccf77d449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336768291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1336768291
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2454741208
Short name T355
Test name
Test status
Simulation time 17849732 ps
CPU time 0.73 seconds
Started Feb 21 02:23:55 PM PST 24
Finished Feb 21 02:23:57 PM PST 24
Peak memory 216320 kb
Host smart-75093898-324e-4b30-871b-1db23591a803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454741208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2454741208
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.403433181
Short name T128
Test name
Test status
Simulation time 142263875 ps
CPU time 3.69 seconds
Started Feb 21 02:24:03 PM PST 24
Finished Feb 21 02:24:07 PM PST 24
Peak memory 222612 kb
Host smart-85e1de52-52ea-4653-b8cf-526632e75bb3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=403433181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.403433181
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.792802261
Short name T860
Test name
Test status
Simulation time 3959814456 ps
CPU time 37.55 seconds
Started Feb 21 02:24:05 PM PST 24
Finished Feb 21 02:24:43 PM PST 24
Peak memory 216404 kb
Host smart-00b31679-a1c5-4acb-8043-6dae09dc9148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792802261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.792802261
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.235170690
Short name T564
Test name
Test status
Simulation time 985402558 ps
CPU time 4.49 seconds
Started Feb 21 02:23:54 PM PST 24
Finished Feb 21 02:23:59 PM PST 24
Peak memory 216264 kb
Host smart-54a81b65-1b23-4289-8c8b-66b5fbab06ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235170690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.235170690
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3513164882
Short name T475
Test name
Test status
Simulation time 112838737 ps
CPU time 1.49 seconds
Started Feb 21 02:24:09 PM PST 24
Finished Feb 21 02:24:12 PM PST 24
Peak memory 216904 kb
Host smart-aa2a108a-fc6a-4362-8e1f-2d79010f44bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513164882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3513164882
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.643253247
Short name T929
Test name
Test status
Simulation time 73449906 ps
CPU time 0.9 seconds
Started Feb 21 02:24:02 PM PST 24
Finished Feb 21 02:24:03 PM PST 24
Peak memory 205480 kb
Host smart-3d3789bc-ba8b-40be-b2b8-b3076b4d9a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643253247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.643253247
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.821865926
Short name T946
Test name
Test status
Simulation time 495437809 ps
CPU time 4.26 seconds
Started Feb 21 02:24:08 PM PST 24
Finished Feb 21 02:24:13 PM PST 24
Peak memory 216892 kb
Host smart-4a21d9f9-8982-4950-a425-7530aacfddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821865926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.821865926
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.230302278
Short name T977
Test name
Test status
Simulation time 23654999 ps
CPU time 0.7 seconds
Started Feb 21 02:24:22 PM PST 24
Finished Feb 21 02:24:23 PM PST 24
Peak memory 204964 kb
Host smart-f80618d1-5516-41c4-9766-54ba577c46bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230302278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.230302278
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4128892404
Short name T428
Test name
Test status
Simulation time 10438958591 ps
CPU time 5.05 seconds
Started Feb 21 02:24:21 PM PST 24
Finished Feb 21 02:24:27 PM PST 24
Peak memory 219088 kb
Host smart-558adfa0-a3aa-48d7-88de-a88f347d319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128892404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4128892404
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2859030912
Short name T870
Test name
Test status
Simulation time 23296622 ps
CPU time 0.73 seconds
Started Feb 21 02:24:17 PM PST 24
Finished Feb 21 02:24:18 PM PST 24
Peak memory 205520 kb
Host smart-b1071d1e-b564-4382-8b2d-f365be3e2394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859030912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2859030912
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3802618776
Short name T193
Test name
Test status
Simulation time 22347781193 ps
CPU time 71.51 seconds
Started Feb 21 02:24:26 PM PST 24
Finished Feb 21 02:25:38 PM PST 24
Peak memory 249296 kb
Host smart-bc3599e5-3097-4705-b05b-8c8e052846c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802618776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3802618776
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.811162099
Short name T494
Test name
Test status
Simulation time 213236794347 ps
CPU time 291.7 seconds
Started Feb 21 02:24:24 PM PST 24
Finished Feb 21 02:29:16 PM PST 24
Peak memory 253280 kb
Host smart-662df38c-753b-4100-a4ca-2f47c9677e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811162099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.811162099
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4161980061
Short name T923
Test name
Test status
Simulation time 51611937381 ps
CPU time 67.26 seconds
Started Feb 21 02:24:25 PM PST 24
Finished Feb 21 02:25:33 PM PST 24
Peak memory 255232 kb
Host smart-5810c3ea-a5a3-4ced-bd8d-48523b643482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161980061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4161980061
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1376005950
Short name T785
Test name
Test status
Simulation time 4462823844 ps
CPU time 6.73 seconds
Started Feb 21 02:24:18 PM PST 24
Finished Feb 21 02:24:25 PM PST 24
Peak memory 234012 kb
Host smart-0329d854-46a0-4569-81f0-46cfe425a92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376005950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1376005950
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.88850062
Short name T317
Test name
Test status
Simulation time 5154024366 ps
CPU time 15.37 seconds
Started Feb 21 02:24:19 PM PST 24
Finished Feb 21 02:24:35 PM PST 24
Peak memory 240336 kb
Host smart-d98e9624-24e9-4f1a-8616-f3de63685861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88850062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.88850062
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3412799333
Short name T730
Test name
Test status
Simulation time 44729921 ps
CPU time 1.08 seconds
Started Feb 21 02:24:22 PM PST 24
Finished Feb 21 02:24:24 PM PST 24
Peak memory 216644 kb
Host smart-872bb02f-5af5-4d5f-a171-07c3ec69eca2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412799333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3412799333
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3243451329
Short name T233
Test name
Test status
Simulation time 17697244546 ps
CPU time 49.19 seconds
Started Feb 21 02:24:18 PM PST 24
Finished Feb 21 02:25:09 PM PST 24
Peak memory 248532 kb
Host smart-df6b4737-9f7b-4205-b2b2-39595dba2f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243451329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3243451329
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4083713978
Short name T513
Test name
Test status
Simulation time 294497422 ps
CPU time 2.63 seconds
Started Feb 21 02:24:17 PM PST 24
Finished Feb 21 02:24:20 PM PST 24
Peak memory 216952 kb
Host smart-8072ca77-2dad-4ff8-8385-99cb320c7820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083713978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4083713978
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.3018143650
Short name T449
Test name
Test status
Simulation time 18368972 ps
CPU time 0.74 seconds
Started Feb 21 02:24:15 PM PST 24
Finished Feb 21 02:24:16 PM PST 24
Peak memory 216340 kb
Host smart-48d80bd3-4e9f-4803-983e-25fbd42d0738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018143650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.3018143650
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1756477627
Short name T847
Test name
Test status
Simulation time 292494419 ps
CPU time 4.02 seconds
Started Feb 21 02:24:22 PM PST 24
Finished Feb 21 02:24:27 PM PST 24
Peak memory 219068 kb
Host smart-a7ca22af-ebec-457f-a7d5-7ca633a0a413
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1756477627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1756477627
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2748769656
Short name T982
Test name
Test status
Simulation time 168159395 ps
CPU time 1.03 seconds
Started Feb 21 02:24:25 PM PST 24
Finished Feb 21 02:24:27 PM PST 24
Peak memory 207864 kb
Host smart-7b42e5a7-d3ec-45e7-a54c-2ac764847952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748769656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2748769656
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1395395448
Short name T392
Test name
Test status
Simulation time 3417504245 ps
CPU time 4.68 seconds
Started Feb 21 02:24:16 PM PST 24
Finished Feb 21 02:24:22 PM PST 24
Peak memory 216520 kb
Host smart-0b762fa3-1e2c-41bb-bdc6-3dbc3c27b52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395395448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1395395448
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3913230017
Short name T330
Test name
Test status
Simulation time 20577461570 ps
CPU time 9.67 seconds
Started Feb 21 02:24:18 PM PST 24
Finished Feb 21 02:24:29 PM PST 24
Peak memory 216500 kb
Host smart-572a5e4d-223e-4114-a2a4-c3ffea6a6ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913230017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3913230017
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.836592371
Short name T598
Test name
Test status
Simulation time 759249483 ps
CPU time 1.95 seconds
Started Feb 21 02:24:16 PM PST 24
Finished Feb 21 02:24:19 PM PST 24
Peak memory 208376 kb
Host smart-f0e6e6db-a8f8-4e12-9b85-d830e134452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836592371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.836592371
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3796627690
Short name T793
Test name
Test status
Simulation time 621591057 ps
CPU time 1.06 seconds
Started Feb 21 02:24:18 PM PST 24
Finished Feb 21 02:24:19 PM PST 24
Peak memory 206528 kb
Host smart-8e517cc3-ac79-48b2-9be1-345822828b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796627690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3796627690
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2484358202
Short name T570
Test name
Test status
Simulation time 1366280453 ps
CPU time 10.69 seconds
Started Feb 21 02:24:26 PM PST 24
Finished Feb 21 02:24:37 PM PST 24
Peak memory 228028 kb
Host smart-2a5700bc-0b32-49bc-a463-c8e0007651e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484358202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2484358202
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.120363063
Short name T699
Test name
Test status
Simulation time 23141248 ps
CPU time 0.69 seconds
Started Feb 21 02:24:29 PM PST 24
Finished Feb 21 02:24:31 PM PST 24
Peak memory 205324 kb
Host smart-35e47a93-2534-4055-8d8e-13e95b2f6d52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120363063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.120363063
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.357288994
Short name T576
Test name
Test status
Simulation time 1936535972 ps
CPU time 2.75 seconds
Started Feb 21 02:24:29 PM PST 24
Finished Feb 21 02:24:33 PM PST 24
Peak memory 218056 kb
Host smart-95573960-4ced-45ee-9255-1c2e9176192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357288994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.357288994
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1821422730
Short name T703
Test name
Test status
Simulation time 23003533 ps
CPU time 0.82 seconds
Started Feb 21 02:24:23 PM PST 24
Finished Feb 21 02:24:24 PM PST 24
Peak memory 206172 kb
Host smart-94deb9de-0ef1-4a96-b6fc-add4fc5834a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821422730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1821422730
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.584581792
Short name T322
Test name
Test status
Simulation time 113747842547 ps
CPU time 271.31 seconds
Started Feb 21 02:24:27 PM PST 24
Finished Feb 21 02:28:59 PM PST 24
Peak memory 254800 kb
Host smart-522076be-741a-4f57-8960-837425ce716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584581792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.584581792
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2131681416
Short name T795
Test name
Test status
Simulation time 61663855396 ps
CPU time 51.93 seconds
Started Feb 21 02:24:28 PM PST 24
Finished Feb 21 02:25:21 PM PST 24
Peak memory 241148 kb
Host smart-e0f0b48b-7e85-40d4-b79f-81450a20dab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131681416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2131681416
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1062118827
Short name T249
Test name
Test status
Simulation time 27426377818 ps
CPU time 256.89 seconds
Started Feb 21 02:24:29 PM PST 24
Finished Feb 21 02:28:47 PM PST 24
Peak memory 273148 kb
Host smart-996b1412-ae03-435a-9bcd-9ff0ec17a6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062118827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1062118827
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2538524700
Short name T400
Test name
Test status
Simulation time 1391500856 ps
CPU time 12.83 seconds
Started Feb 21 02:24:30 PM PST 24
Finished Feb 21 02:24:43 PM PST 24
Peak memory 236256 kb
Host smart-662d851f-84e1-4ac5-9cc7-ac6b97237d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538524700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2538524700
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4035010671
Short name T456
Test name
Test status
Simulation time 2215723256 ps
CPU time 4.68 seconds
Started Feb 21 02:24:28 PM PST 24
Finished Feb 21 02:24:34 PM PST 24
Peak memory 218608 kb
Host smart-831e8c09-e4b9-4b47-9e9e-5dcbdc9d5997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035010671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4035010671
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1574376040
Short name T890
Test name
Test status
Simulation time 4725619751 ps
CPU time 17.62 seconds
Started Feb 21 02:24:27 PM PST 24
Finished Feb 21 02:24:45 PM PST 24
Peak memory 232856 kb
Host smart-d6892fdd-4ed2-4eac-9b6a-e8b55850d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574376040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1574376040
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1851106120
Short name T888
Test name
Test status
Simulation time 14770210 ps
CPU time 0.98 seconds
Started Feb 21 02:24:27 PM PST 24
Finished Feb 21 02:24:28 PM PST 24
Peak memory 217848 kb
Host smart-2a1b68a9-5dd7-4cfa-974a-aaedf8188fc3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851106120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1851106120
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.931274279
Short name T268
Test name
Test status
Simulation time 4129743272 ps
CPU time 12.69 seconds
Started Feb 21 02:24:30 PM PST 24
Finished Feb 21 02:24:43 PM PST 24
Peak memory 233944 kb
Host smart-4b2e2821-f4d0-40ae-967c-094853a26677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931274279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.931274279
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1928825790
Short name T240
Test name
Test status
Simulation time 1552976383 ps
CPU time 3.61 seconds
Started Feb 21 02:24:22 PM PST 24
Finished Feb 21 02:24:26 PM PST 24
Peak memory 224636 kb
Host smart-f0194093-55c8-40d0-8f77-28cb26aa5ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928825790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1928825790
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.792877185
Short name T897
Test name
Test status
Simulation time 16955493 ps
CPU time 0.76 seconds
Started Feb 21 02:24:24 PM PST 24
Finished Feb 21 02:24:25 PM PST 24
Peak memory 216328 kb
Host smart-c94fc0ab-c9cc-4597-975e-b73d45b66683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792877185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.792877185
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4267364957
Short name T924
Test name
Test status
Simulation time 3886541105 ps
CPU time 4.57 seconds
Started Feb 21 02:24:28 PM PST 24
Finished Feb 21 02:24:34 PM PST 24
Peak memory 218960 kb
Host smart-6655a604-c540-4568-8a7b-40f1c4dfeac9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4267364957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4267364957
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3877228071
Short name T267
Test name
Test status
Simulation time 255806343269 ps
CPU time 437.98 seconds
Started Feb 21 02:24:27 PM PST 24
Finished Feb 21 02:31:45 PM PST 24
Peak memory 266812 kb
Host smart-983feb73-a7e4-440c-a7b5-ddcfea195dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877228071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3877228071
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.843792855
Short name T583
Test name
Test status
Simulation time 1506676240 ps
CPU time 11.67 seconds
Started Feb 21 02:24:22 PM PST 24
Finished Feb 21 02:24:35 PM PST 24
Peak memory 216492 kb
Host smart-10038a57-58d5-47a1-9d9b-62e03d272776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843792855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.843792855
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2108248487
Short name T321
Test name
Test status
Simulation time 1895874870 ps
CPU time 10.35 seconds
Started Feb 21 02:24:20 PM PST 24
Finished Feb 21 02:24:31 PM PST 24
Peak memory 216424 kb
Host smart-7ced6258-435e-4ddd-9a39-23c86ad57a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108248487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2108248487
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2670863904
Short name T627
Test name
Test status
Simulation time 56998100 ps
CPU time 3.13 seconds
Started Feb 21 02:24:25 PM PST 24
Finished Feb 21 02:24:28 PM PST 24
Peak memory 208092 kb
Host smart-4bc6d3d6-622e-4747-8e27-93d104cefc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670863904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2670863904
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1205768240
Short name T907
Test name
Test status
Simulation time 117651064 ps
CPU time 0.85 seconds
Started Feb 21 02:24:25 PM PST 24
Finished Feb 21 02:24:26 PM PST 24
Peak memory 205460 kb
Host smart-6354d274-35a1-4bc0-8e6a-5fd30f8ae364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205768240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1205768240
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.952620966
Short name T757
Test name
Test status
Simulation time 362008410 ps
CPU time 6.22 seconds
Started Feb 21 02:24:28 PM PST 24
Finished Feb 21 02:24:36 PM PST 24
Peak memory 237276 kb
Host smart-09afb0c2-fd71-48e1-a037-cfbc4d96bf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952620966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.952620966
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3161699296
Short name T691
Test name
Test status
Simulation time 49533753 ps
CPU time 0.72 seconds
Started Feb 21 02:24:32 PM PST 24
Finished Feb 21 02:24:34 PM PST 24
Peak memory 205324 kb
Host smart-99f2227c-5020-403b-9790-9fd48c57f1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161699296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3161699296
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1046689551
Short name T484
Test name
Test status
Simulation time 208936243 ps
CPU time 2.95 seconds
Started Feb 21 02:24:31 PM PST 24
Finished Feb 21 02:24:35 PM PST 24
Peak memory 224752 kb
Host smart-60bbe838-61be-4c24-b76d-c51c082b1092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046689551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1046689551
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3776415637
Short name T51
Test name
Test status
Simulation time 46817828 ps
CPU time 0.78 seconds
Started Feb 21 02:24:29 PM PST 24
Finished Feb 21 02:24:31 PM PST 24
Peak memory 206500 kb
Host smart-f87fbe8e-2071-4a6f-ba40-2da8ef38ac5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776415637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3776415637
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.205045995
Short name T154
Test name
Test status
Simulation time 716754892 ps
CPU time 6.2 seconds
Started Feb 21 02:24:32 PM PST 24
Finished Feb 21 02:24:39 PM PST 24
Peak memory 233888 kb
Host smart-78e00785-6756-416d-8895-672cf25d9b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205045995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.205045995
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1386164335
Short name T326
Test name
Test status
Simulation time 8529015031 ps
CPU time 75.57 seconds
Started Feb 21 02:24:31 PM PST 24
Finished Feb 21 02:25:48 PM PST 24
Peak memory 234420 kb
Host smart-9c11d351-8829-4ee3-b1f7-c33277c62b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386164335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1386164335
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4205945523
Short name T397
Test name
Test status
Simulation time 8432937923 ps
CPU time 63.36 seconds
Started Feb 21 02:24:34 PM PST 24
Finished Feb 21 02:25:38 PM PST 24
Peak memory 222928 kb
Host smart-e5f90873-eb89-4a17-9675-edc56d92105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205945523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4205945523
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2929303565
Short name T839
Test name
Test status
Simulation time 34286998750 ps
CPU time 39 seconds
Started Feb 21 02:24:35 PM PST 24
Finished Feb 21 02:25:14 PM PST 24
Peak memory 241064 kb
Host smart-5ecec8cf-f76b-4cce-a685-f938dc5a67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929303565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2929303565
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.809657692
Short name T442
Test name
Test status
Simulation time 479958446 ps
CPU time 5.58 seconds
Started Feb 21 02:24:29 PM PST 24
Finished Feb 21 02:24:36 PM PST 24
Peak memory 234540 kb
Host smart-a45fb3ab-ba65-4c46-8b88-e7d360c9f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809657692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.809657692
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4221678383
Short name T195
Test name
Test status
Simulation time 4104039475 ps
CPU time 17.24 seconds
Started Feb 21 02:24:32 PM PST 24
Finished Feb 21 02:24:51 PM PST 24
Peak memory 233852 kb
Host smart-1143d7ce-5c61-4882-86d2-c5ab2d43fbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221678383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4221678383
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1759057411
Short name T299
Test name
Test status
Simulation time 41225120 ps
CPU time 1.06 seconds
Started Feb 21 02:24:30 PM PST 24
Finished Feb 21 02:24:32 PM PST 24
Peak memory 217748 kb
Host smart-ff3e5e86-e9e9-4158-afe1-6021bc86eda8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759057411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1759057411
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.53578324
Short name T352
Test name
Test status
Simulation time 929583107 ps
CPU time 5.45 seconds
Started Feb 21 02:24:34 PM PST 24
Finished Feb 21 02:24:41 PM PST 24
Peak memory 233468 kb
Host smart-8135609b-19fd-426c-b971-5e43b67cc371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53578324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.53578324
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.996499688
Short name T960
Test name
Test status
Simulation time 1396041933 ps
CPU time 3.65 seconds
Started Feb 21 02:24:27 PM PST 24
Finished Feb 21 02:24:31 PM PST 24
Peak memory 216980 kb
Host smart-6639cea8-4c5b-4b31-86eb-d52e4f51b7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996499688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.996499688
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2133845775
Short name T645
Test name
Test status
Simulation time 23585167 ps
CPU time 0.74 seconds
Started Feb 21 02:24:28 PM PST 24
Finished Feb 21 02:24:30 PM PST 24
Peak memory 216356 kb
Host smart-0db9e4b5-eebd-451a-9aaf-0d9249e75e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133845775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2133845775
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.66837913
Short name T722
Test name
Test status
Simulation time 214591738 ps
CPU time 3.56 seconds
Started Feb 21 02:24:34 PM PST 24
Finished Feb 21 02:24:39 PM PST 24
Peak memory 216600 kb
Host smart-2c8cd11c-1398-4860-affa-10c28a441c89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=66837913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direc
t.66837913
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.163546665
Short name T647
Test name
Test status
Simulation time 692845444 ps
CPU time 8 seconds
Started Feb 21 02:24:28 PM PST 24
Finished Feb 21 02:24:38 PM PST 24
Peak memory 216448 kb
Host smart-a28ce958-0817-4dd9-b409-d65d2752dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163546665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.163546665
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3411617271
Short name T742
Test name
Test status
Simulation time 1288709042 ps
CPU time 8.61 seconds
Started Feb 21 02:24:28 PM PST 24
Finished Feb 21 02:24:38 PM PST 24
Peak memory 216444 kb
Host smart-8a016359-7a2e-4eaa-be21-d8c88373bc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411617271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3411617271
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.882752497
Short name T885
Test name
Test status
Simulation time 809585793 ps
CPU time 3.58 seconds
Started Feb 21 02:24:30 PM PST 24
Finished Feb 21 02:24:35 PM PST 24
Peak memory 216372 kb
Host smart-4f0bed77-aa53-4f73-a4c0-d17def6351de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882752497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.882752497
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.885367290
Short name T68
Test name
Test status
Simulation time 174054986 ps
CPU time 0.83 seconds
Started Feb 21 02:24:28 PM PST 24
Finished Feb 21 02:24:30 PM PST 24
Peak memory 205524 kb
Host smart-d401c007-7004-4f9e-9e13-737c1fb94a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885367290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.885367290
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.541885908
Short name T560
Test name
Test status
Simulation time 9829910200 ps
CPU time 9.83 seconds
Started Feb 21 02:24:30 PM PST 24
Finished Feb 21 02:24:41 PM PST 24
Peak memory 224676 kb
Host smart-4e83aa07-cd84-45f1-af73-0c0496f2e565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541885908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.541885908
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1997977921
Short name T660
Test name
Test status
Simulation time 13797660 ps
CPU time 0.72 seconds
Started Feb 21 02:24:42 PM PST 24
Finished Feb 21 02:24:43 PM PST 24
Peak memory 204976 kb
Host smart-d30765ab-4216-4ae2-ac79-4cd48be96146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997977921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1997977921
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.853687059
Short name T983
Test name
Test status
Simulation time 200046740 ps
CPU time 3.64 seconds
Started Feb 21 02:24:34 PM PST 24
Finished Feb 21 02:24:38 PM PST 24
Peak memory 219412 kb
Host smart-90eafbc9-a491-4e0c-af89-885ff6d778cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853687059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.853687059
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1380249901
Short name T928
Test name
Test status
Simulation time 32004214 ps
CPU time 0.8 seconds
Started Feb 21 02:24:31 PM PST 24
Finished Feb 21 02:24:33 PM PST 24
Peak memory 205492 kb
Host smart-be1a7ee0-d747-4237-a3c1-e28b313e5553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380249901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1380249901
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2932291138
Short name T709
Test name
Test status
Simulation time 10576954270 ps
CPU time 42.2 seconds
Started Feb 21 02:24:39 PM PST 24
Finished Feb 21 02:25:21 PM PST 24
Peak memory 249236 kb
Host smart-9bab2eba-f0c5-46dd-a85d-ab3e38bab0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932291138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2932291138
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2778797860
Short name T369
Test name
Test status
Simulation time 1662674034 ps
CPU time 16.09 seconds
Started Feb 21 02:24:39 PM PST 24
Finished Feb 21 02:24:55 PM PST 24
Peak memory 234148 kb
Host smart-423b24fd-f0f7-4ff4-84fb-91a978410b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778797860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2778797860
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.46760569
Short name T878
Test name
Test status
Simulation time 33021031769 ps
CPU time 229.24 seconds
Started Feb 21 02:24:38 PM PST 24
Finished Feb 21 02:28:28 PM PST 24
Peak memory 256804 kb
Host smart-279c35bb-bc7e-4fa8-973f-ff231c3482b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46760569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.46760569
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2900357823
Short name T875
Test name
Test status
Simulation time 3296581893 ps
CPU time 6.52 seconds
Started Feb 21 02:24:39 PM PST 24
Finished Feb 21 02:24:46 PM PST 24
Peak memory 238008 kb
Host smart-302265e4-6f9b-438e-94d1-136c37a09cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900357823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2900357823
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4259127521
Short name T445
Test name
Test status
Simulation time 7122808354 ps
CPU time 6.9 seconds
Started Feb 21 02:24:31 PM PST 24
Finished Feb 21 02:24:40 PM PST 24
Peak memory 217960 kb
Host smart-c92223b2-3096-44a8-a763-a7f928319671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259127521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4259127521
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2367728379
Short name T302
Test name
Test status
Simulation time 12557373355 ps
CPU time 10.05 seconds
Started Feb 21 02:24:32 PM PST 24
Finished Feb 21 02:24:43 PM PST 24
Peak memory 233688 kb
Host smart-7fd7bfbe-01fb-42f0-ab7f-19265d0c510a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367728379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2367728379
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.877412632
Short name T590
Test name
Test status
Simulation time 89828899 ps
CPU time 1.07 seconds
Started Feb 21 02:24:31 PM PST 24
Finished Feb 21 02:24:33 PM PST 24
Peak memory 216644 kb
Host smart-6a5f26c5-2831-4159-89dd-6b5db5a1957c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877412632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.877412632
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1183174487
Short name T719
Test name
Test status
Simulation time 479469530 ps
CPU time 4.31 seconds
Started Feb 21 02:24:34 PM PST 24
Finished Feb 21 02:24:39 PM PST 24
Peak memory 224668 kb
Host smart-73c4ca4a-eb56-41c3-8d55-b39eb2107b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183174487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1183174487
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3287014973
Short name T337
Test name
Test status
Simulation time 282501154 ps
CPU time 2.75 seconds
Started Feb 21 02:24:33 PM PST 24
Finished Feb 21 02:24:37 PM PST 24
Peak memory 224600 kb
Host smart-3facd293-9eeb-4e2b-990d-b20b38e9ecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287014973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3287014973
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3544217983
Short name T642
Test name
Test status
Simulation time 23516522 ps
CPU time 0.74 seconds
Started Feb 21 02:24:31 PM PST 24
Finished Feb 21 02:24:33 PM PST 24
Peak memory 216316 kb
Host smart-ab8e16d5-6959-4a28-b542-86edd58f0d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544217983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3544217983
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3871834818
Short name T406
Test name
Test status
Simulation time 10215292419 ps
CPU time 5.73 seconds
Started Feb 21 02:24:39 PM PST 24
Finished Feb 21 02:24:45 PM PST 24
Peak memory 219060 kb
Host smart-8b409b77-25b0-4e17-8aeb-d14b110acae5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3871834818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3871834818
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.517970013
Short name T514
Test name
Test status
Simulation time 8000767978 ps
CPU time 38.16 seconds
Started Feb 21 02:24:32 PM PST 24
Finished Feb 21 02:25:11 PM PST 24
Peak memory 216560 kb
Host smart-2e75965e-2016-46ce-aa9e-688b97fd2efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517970013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.517970013
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3955923184
Short name T937
Test name
Test status
Simulation time 126965230 ps
CPU time 1.7 seconds
Started Feb 21 02:24:32 PM PST 24
Finished Feb 21 02:24:35 PM PST 24
Peak memory 206880 kb
Host smart-520f9b37-86af-48c3-a876-76de37ce57da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955923184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3955923184
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.31627393
Short name T615
Test name
Test status
Simulation time 159582214 ps
CPU time 4.11 seconds
Started Feb 21 02:24:32 PM PST 24
Finished Feb 21 02:24:37 PM PST 24
Peak memory 216484 kb
Host smart-a61bf87e-1df8-4bbd-9220-94fae97b69ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31627393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.31627393
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.862239059
Short name T577
Test name
Test status
Simulation time 238207385 ps
CPU time 0.84 seconds
Started Feb 21 02:24:32 PM PST 24
Finished Feb 21 02:24:34 PM PST 24
Peak memory 205512 kb
Host smart-00f6de6f-f7da-4173-9cb3-2254900a37dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862239059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.862239059
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2485581919
Short name T10
Test name
Test status
Simulation time 18715101339 ps
CPU time 26.93 seconds
Started Feb 21 02:24:33 PM PST 24
Finished Feb 21 02:25:01 PM PST 24
Peak memory 224696 kb
Host smart-4a2e05bb-06ab-44f6-ac1e-078f548906b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485581919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2485581919
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2799633623
Short name T572
Test name
Test status
Simulation time 30182410 ps
CPU time 0.67 seconds
Started Feb 21 02:21:50 PM PST 24
Finished Feb 21 02:21:51 PM PST 24
Peak memory 204420 kb
Host smart-a5174aa3-bcbb-4a8c-8799-eb68fe879146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799633623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
799633623
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.521318681
Short name T236
Test name
Test status
Simulation time 3696554847 ps
CPU time 5.62 seconds
Started Feb 21 02:21:40 PM PST 24
Finished Feb 21 02:21:46 PM PST 24
Peak memory 219944 kb
Host smart-fdc1c1ee-2cad-4917-864f-3ea99d686a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521318681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.521318681
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1544752331
Short name T922
Test name
Test status
Simulation time 99559269 ps
CPU time 0.79 seconds
Started Feb 21 02:21:30 PM PST 24
Finished Feb 21 02:21:31 PM PST 24
Peak memory 205680 kb
Host smart-f7b7c969-d69b-4955-b9a9-a3c55594a73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544752331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1544752331
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2031181679
Short name T54
Test name
Test status
Simulation time 6129404299 ps
CPU time 38.76 seconds
Started Feb 21 02:21:48 PM PST 24
Finished Feb 21 02:22:28 PM PST 24
Peak memory 249312 kb
Host smart-40d1bed4-22a2-4ce0-a4b2-52c309d8caff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031181679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2031181679
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1144917357
Short name T28
Test name
Test status
Simulation time 317888682437 ps
CPU time 511.21 seconds
Started Feb 21 02:21:50 PM PST 24
Finished Feb 21 02:30:21 PM PST 24
Peak memory 273608 kb
Host smart-58657176-f298-4ec8-9726-f4c1de8f22c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144917357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1144917357
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.760903101
Short name T26
Test name
Test status
Simulation time 66744935520 ps
CPU time 257.03 seconds
Started Feb 21 02:21:56 PM PST 24
Finished Feb 21 02:26:14 PM PST 24
Peak memory 240800 kb
Host smart-69196fa4-9238-40f6-9fa7-6556e2cb3252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760903101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
760903101
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2374931372
Short name T1
Test name
Test status
Simulation time 330208851 ps
CPU time 7.65 seconds
Started Feb 21 02:21:42 PM PST 24
Finished Feb 21 02:21:50 PM PST 24
Peak memory 247108 kb
Host smart-8b90bddb-5df4-4828-9afc-f84249330636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374931372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2374931372
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.830430500
Short name T611
Test name
Test status
Simulation time 564159402 ps
CPU time 3.29 seconds
Started Feb 21 02:21:40 PM PST 24
Finished Feb 21 02:21:44 PM PST 24
Peak memory 216456 kb
Host smart-48a53918-48df-46e7-a393-2a242bb8c82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830430500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.830430500
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.297913935
Short name T519
Test name
Test status
Simulation time 2029187605 ps
CPU time 6.74 seconds
Started Feb 21 02:21:42 PM PST 24
Finished Feb 21 02:21:49 PM PST 24
Peak memory 236212 kb
Host smart-b4ad41e3-4ea6-43b5-a50b-37990e32a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297913935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.297913935
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1197085495
Short name T503
Test name
Test status
Simulation time 45462067 ps
CPU time 1 seconds
Started Feb 21 02:21:31 PM PST 24
Finished Feb 21 02:21:32 PM PST 24
Peak memory 216652 kb
Host smart-5b46de5e-fdda-4eeb-b79c-d621d87045da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197085495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1197085495
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1063476827
Short name T546
Test name
Test status
Simulation time 1449590134 ps
CPU time 11.93 seconds
Started Feb 21 02:21:40 PM PST 24
Finished Feb 21 02:21:52 PM PST 24
Peak memory 246152 kb
Host smart-210d6776-edfd-41a8-acbf-d6199422ac21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063476827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1063476827
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2789550284
Short name T376
Test name
Test status
Simulation time 17443687660 ps
CPU time 37.77 seconds
Started Feb 21 02:21:39 PM PST 24
Finished Feb 21 02:22:17 PM PST 24
Peak memory 224596 kb
Host smart-20c528e6-6057-4a89-b65b-0a57c2699fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789550284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2789550284
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.940193921
Short name T42
Test name
Test status
Simulation time 34229349 ps
CPU time 0.73 seconds
Started Feb 21 02:21:40 PM PST 24
Finished Feb 21 02:21:41 PM PST 24
Peak memory 216336 kb
Host smart-7be09ff4-9e37-478d-b645-752661dd26e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940193921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.940193921
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3657878621
Short name T71
Test name
Test status
Simulation time 9779191852 ps
CPU time 4.81 seconds
Started Feb 21 02:21:48 PM PST 24
Finished Feb 21 02:21:53 PM PST 24
Peak memory 216608 kb
Host smart-3060b68e-582c-425d-8d5e-325d37547d57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3657878621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3657878621
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2348413298
Short name T453
Test name
Test status
Simulation time 394657057051 ps
CPU time 746 seconds
Started Feb 21 02:21:51 PM PST 24
Finished Feb 21 02:34:17 PM PST 24
Peak memory 273788 kb
Host smart-fd89716f-c6aa-4021-aa61-11ebad9b461d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348413298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2348413298
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1835078018
Short name T452
Test name
Test status
Simulation time 1291830431 ps
CPU time 14.54 seconds
Started Feb 21 02:21:41 PM PST 24
Finished Feb 21 02:21:56 PM PST 24
Peak memory 216452 kb
Host smart-9044eae9-615d-40b3-a158-ea29f504b62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835078018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1835078018
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1028482362
Short name T867
Test name
Test status
Simulation time 3281193917 ps
CPU time 3.56 seconds
Started Feb 21 02:21:43 PM PST 24
Finished Feb 21 02:21:46 PM PST 24
Peak memory 216304 kb
Host smart-449b2df8-fb29-4143-b365-f79c2da261df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028482362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1028482362
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3784083405
Short name T682
Test name
Test status
Simulation time 64895940 ps
CPU time 0.87 seconds
Started Feb 21 02:21:42 PM PST 24
Finished Feb 21 02:21:43 PM PST 24
Peak memory 206620 kb
Host smart-9669e554-ba63-48df-89d9-3b613c0fa834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784083405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3784083405
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1705482242
Short name T802
Test name
Test status
Simulation time 250882876 ps
CPU time 0.81 seconds
Started Feb 21 02:21:43 PM PST 24
Finished Feb 21 02:21:44 PM PST 24
Peak memory 205488 kb
Host smart-ee5fc219-0d46-4948-be8f-942dec6a2ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705482242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1705482242
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1938837881
Short name T804
Test name
Test status
Simulation time 17771298134 ps
CPU time 16.11 seconds
Started Feb 21 02:21:41 PM PST 24
Finished Feb 21 02:21:57 PM PST 24
Peak memory 233252 kb
Host smart-a950dfad-15e2-4604-a9f9-137f8a7e3212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938837881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1938837881
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1324531431
Short name T600
Test name
Test status
Simulation time 28829996 ps
CPU time 0.69 seconds
Started Feb 21 02:24:51 PM PST 24
Finished Feb 21 02:24:52 PM PST 24
Peak memory 204420 kb
Host smart-2d4d6416-79d3-4bad-be73-2e8e15f5f688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324531431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1324531431
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1907127418
Short name T373
Test name
Test status
Simulation time 359980381 ps
CPU time 3.8 seconds
Started Feb 21 02:24:38 PM PST 24
Finished Feb 21 02:24:43 PM PST 24
Peak memory 221040 kb
Host smart-3092e83d-3d3c-452b-af93-e0b9e8c04997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907127418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1907127418
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3748909123
Short name T309
Test name
Test status
Simulation time 13533701 ps
CPU time 0.76 seconds
Started Feb 21 02:24:41 PM PST 24
Finished Feb 21 02:24:42 PM PST 24
Peak memory 206112 kb
Host smart-8192b7ee-0e21-42e6-b31d-42f396ba07e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748909123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3748909123
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3270603384
Short name T824
Test name
Test status
Simulation time 21245789465 ps
CPU time 52.12 seconds
Started Feb 21 02:24:42 PM PST 24
Finished Feb 21 02:25:34 PM PST 24
Peak memory 236764 kb
Host smart-48428ffa-6f7e-49fd-b6c2-ea4fe29b7903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270603384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3270603384
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3610724507
Short name T264
Test name
Test status
Simulation time 181987999989 ps
CPU time 108.62 seconds
Started Feb 21 02:24:41 PM PST 24
Finished Feb 21 02:26:29 PM PST 24
Peak memory 263136 kb
Host smart-84ef25d7-4f3a-4bd1-952b-3e9de76f019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610724507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3610724507
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2382535471
Short name T720
Test name
Test status
Simulation time 66439010631 ps
CPU time 125.28 seconds
Started Feb 21 02:24:39 PM PST 24
Finished Feb 21 02:26:45 PM PST 24
Peak memory 256928 kb
Host smart-1996664c-afb2-41b3-b1d4-2ede12789435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382535471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2382535471
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4249109077
Short name T217
Test name
Test status
Simulation time 276466766 ps
CPU time 4.47 seconds
Started Feb 21 02:24:39 PM PST 24
Finished Feb 21 02:24:44 PM PST 24
Peak memory 224592 kb
Host smart-0fb3f419-cd69-45ea-a5c8-83167595c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249109077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4249109077
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.521632564
Short name T454
Test name
Test status
Simulation time 66016598 ps
CPU time 2.58 seconds
Started Feb 21 02:24:42 PM PST 24
Finished Feb 21 02:24:45 PM PST 24
Peak memory 224636 kb
Host smart-0454856b-13ce-4beb-9f53-7ab971f15e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521632564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.521632564
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2765663861
Short name T273
Test name
Test status
Simulation time 76130956109 ps
CPU time 20.45 seconds
Started Feb 21 02:24:36 PM PST 24
Finished Feb 21 02:24:57 PM PST 24
Peak memory 233528 kb
Host smart-1d0665d8-52a6-4a41-a581-6ed04f2a0909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765663861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2765663861
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3433753195
Short name T179
Test name
Test status
Simulation time 2966285914 ps
CPU time 5.67 seconds
Started Feb 21 02:24:39 PM PST 24
Finished Feb 21 02:24:45 PM PST 24
Peak memory 219300 kb
Host smart-d38484cd-535d-4b38-b4c2-00bd54e828f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433753195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3433753195
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.14339111
Short name T978
Test name
Test status
Simulation time 2167113556 ps
CPU time 5.87 seconds
Started Feb 21 02:24:41 PM PST 24
Finished Feb 21 02:24:47 PM PST 24
Peak memory 222620 kb
Host smart-b13cd23b-4192-4df4-b3c5-4eda2b18131b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=14339111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direc
t.14339111
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2242418053
Short name T497
Test name
Test status
Simulation time 365440007 ps
CPU time 6.83 seconds
Started Feb 21 02:24:40 PM PST 24
Finished Feb 21 02:24:47 PM PST 24
Peak memory 216456 kb
Host smart-bb5212a5-5949-4657-8bef-ae2958aaadd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242418053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2242418053
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3173934296
Short name T357
Test name
Test status
Simulation time 15673018588 ps
CPU time 14.65 seconds
Started Feb 21 02:24:38 PM PST 24
Finished Feb 21 02:24:53 PM PST 24
Peak memory 216480 kb
Host smart-92da827c-10c7-48bf-9a26-5414034b67ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173934296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3173934296
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2626552651
Short name T398
Test name
Test status
Simulation time 167127923 ps
CPU time 1.76 seconds
Started Feb 21 02:24:38 PM PST 24
Finished Feb 21 02:24:40 PM PST 24
Peak memory 216760 kb
Host smart-85605d47-5e99-4729-aaf6-850b81034fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626552651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2626552651
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.724738680
Short name T970
Test name
Test status
Simulation time 121968927 ps
CPU time 0.85 seconds
Started Feb 21 02:24:38 PM PST 24
Finished Feb 21 02:24:40 PM PST 24
Peak memory 205516 kb
Host smart-63011a66-74fa-45bc-9008-c56aca051dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724738680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.724738680
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1193154156
Short name T805
Test name
Test status
Simulation time 635555227 ps
CPU time 7.45 seconds
Started Feb 21 02:24:42 PM PST 24
Finished Feb 21 02:24:50 PM PST 24
Peak memory 239616 kb
Host smart-cdff8840-6e7a-413e-8844-ba424e8c2176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193154156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1193154156
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1347317677
Short name T685
Test name
Test status
Simulation time 15825608 ps
CPU time 0.73 seconds
Started Feb 21 02:25:07 PM PST 24
Finished Feb 21 02:25:08 PM PST 24
Peak memory 204992 kb
Host smart-37526b22-cd1f-4bcd-84aa-a667a6f15fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347317677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1347317677
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.225698421
Short name T892
Test name
Test status
Simulation time 143151042 ps
CPU time 2.35 seconds
Started Feb 21 02:25:00 PM PST 24
Finished Feb 21 02:25:02 PM PST 24
Peak memory 233716 kb
Host smart-4f54247b-491d-4588-8101-d3246ea0ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225698421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.225698421
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2334008366
Short name T933
Test name
Test status
Simulation time 15874299 ps
CPU time 0.78 seconds
Started Feb 21 02:24:55 PM PST 24
Finished Feb 21 02:24:56 PM PST 24
Peak memory 206208 kb
Host smart-f67d0b87-312a-4145-95bf-c16ec46cb866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334008366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2334008366
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3455321832
Short name T954
Test name
Test status
Simulation time 3378319780 ps
CPU time 51.62 seconds
Started Feb 21 02:24:50 PM PST 24
Finished Feb 21 02:25:42 PM PST 24
Peak memory 255824 kb
Host smart-a8624442-26b4-431f-ad35-d8fe3272ae01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455321832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3455321832
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3968118454
Short name T792
Test name
Test status
Simulation time 34016367101 ps
CPU time 80.41 seconds
Started Feb 21 02:24:49 PM PST 24
Finished Feb 21 02:26:10 PM PST 24
Peak memory 224892 kb
Host smart-e6ee066e-c61c-493f-8ecb-3dd25a813dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968118454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3968118454
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3127329823
Short name T684
Test name
Test status
Simulation time 4490571377 ps
CPU time 19.73 seconds
Started Feb 21 02:24:50 PM PST 24
Finished Feb 21 02:25:10 PM PST 24
Peak memory 233032 kb
Host smart-3a100d9b-aeaa-4e1c-9a16-78a1fad9d899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127329823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3127329823
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2973144241
Short name T630
Test name
Test status
Simulation time 51734180966 ps
CPU time 42.75 seconds
Started Feb 21 02:24:49 PM PST 24
Finished Feb 21 02:25:33 PM PST 24
Peak memory 250648 kb
Host smart-f116ef5b-c58d-44f7-add7-2fe20e3bec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973144241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2973144241
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1246473575
Short name T393
Test name
Test status
Simulation time 6288281277 ps
CPU time 9.61 seconds
Started Feb 21 02:24:49 PM PST 24
Finished Feb 21 02:24:59 PM PST 24
Peak memory 219476 kb
Host smart-7b1fa71d-a131-490d-9d3c-9e59e92dceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246473575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1246473575
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.463223009
Short name T416
Test name
Test status
Simulation time 718071489 ps
CPU time 12.38 seconds
Started Feb 21 02:24:53 PM PST 24
Finished Feb 21 02:25:06 PM PST 24
Peak memory 248588 kb
Host smart-3938f22a-bc34-48e2-a286-bae3e0e2bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463223009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.463223009
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2560493689
Short name T895
Test name
Test status
Simulation time 3148046490 ps
CPU time 8.34 seconds
Started Feb 21 02:24:51 PM PST 24
Finished Feb 21 02:24:59 PM PST 24
Peak memory 224672 kb
Host smart-fcd5c542-26df-478b-bf88-3b04e9465f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560493689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2560493689
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3688553113
Short name T198
Test name
Test status
Simulation time 884334761 ps
CPU time 8.14 seconds
Started Feb 21 02:24:47 PM PST 24
Finished Feb 21 02:24:56 PM PST 24
Peak memory 218768 kb
Host smart-7410f11d-4851-4e55-ac1d-e84bf81a275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688553113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3688553113
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2753405878
Short name T329
Test name
Test status
Simulation time 641705197 ps
CPU time 5.51 seconds
Started Feb 21 02:24:56 PM PST 24
Finished Feb 21 02:25:01 PM PST 24
Peak memory 222588 kb
Host smart-2cdb671d-5efd-4bd3-83b7-87b210f9a555
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2753405878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2753405878
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.34419354
Short name T144
Test name
Test status
Simulation time 261973175907 ps
CPU time 563.74 seconds
Started Feb 21 02:24:49 PM PST 24
Finished Feb 21 02:34:13 PM PST 24
Peak memory 289416 kb
Host smart-a0056289-1989-4de7-815e-7552016563fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34419354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress
_all.34419354
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3123754584
Short name T465
Test name
Test status
Simulation time 314704755 ps
CPU time 2.68 seconds
Started Feb 21 02:24:50 PM PST 24
Finished Feb 21 02:24:53 PM PST 24
Peak memory 208056 kb
Host smart-d201f76e-1481-4d63-974b-ff6a27ea2661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123754584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3123754584
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2651774219
Short name T429
Test name
Test status
Simulation time 563282579 ps
CPU time 2.2 seconds
Started Feb 21 02:24:48 PM PST 24
Finished Feb 21 02:24:51 PM PST 24
Peak memory 217800 kb
Host smart-e698288c-ff4c-4dee-930b-08e785e9e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651774219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2651774219
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3036896330
Short name T69
Test name
Test status
Simulation time 177471334 ps
CPU time 0.72 seconds
Started Feb 21 02:24:59 PM PST 24
Finished Feb 21 02:25:00 PM PST 24
Peak memory 205504 kb
Host smart-a2860036-efe5-4beb-bc5a-fd5668e76551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036896330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3036896330
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1240148247
Short name T180
Test name
Test status
Simulation time 4839149819 ps
CPU time 9.6 seconds
Started Feb 21 02:24:50 PM PST 24
Finished Feb 21 02:25:00 PM PST 24
Peak memory 228792 kb
Host smart-52e6598e-2653-4e5b-bf3b-2b79b5e1431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240148247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1240148247
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.395197501
Short name T542
Test name
Test status
Simulation time 19004715 ps
CPU time 0.74 seconds
Started Feb 21 02:25:08 PM PST 24
Finished Feb 21 02:25:09 PM PST 24
Peak memory 205324 kb
Host smart-ee76bc66-7cbf-4443-b080-7f0958025a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395197501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.395197501
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2094001890
Short name T225
Test name
Test status
Simulation time 149636530 ps
CPU time 2.28 seconds
Started Feb 21 02:24:59 PM PST 24
Finished Feb 21 02:25:01 PM PST 24
Peak memory 217484 kb
Host smart-795e6d02-1976-47c7-98f9-f2e8d652fce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094001890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2094001890
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1557376628
Short name T375
Test name
Test status
Simulation time 18113242 ps
CPU time 0.79 seconds
Started Feb 21 02:24:54 PM PST 24
Finished Feb 21 02:24:55 PM PST 24
Peak memory 206536 kb
Host smart-7c14b1a4-f173-4c00-89e8-b84195b0d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557376628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1557376628
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1949009135
Short name T256
Test name
Test status
Simulation time 404859620215 ps
CPU time 501.05 seconds
Started Feb 21 02:25:07 PM PST 24
Finished Feb 21 02:33:29 PM PST 24
Peak memory 250272 kb
Host smart-16545c58-9c60-4097-82f0-0c8f1ef3be96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949009135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1949009135
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.642940014
Short name T122
Test name
Test status
Simulation time 121611402904 ps
CPU time 907.71 seconds
Started Feb 21 02:25:08 PM PST 24
Finished Feb 21 02:40:17 PM PST 24
Peak memory 266908 kb
Host smart-7d924b77-b68e-42c1-9bd8-50492808510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642940014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.642940014
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3137694811
Short name T678
Test name
Test status
Simulation time 5808352927 ps
CPU time 10.29 seconds
Started Feb 21 02:24:51 PM PST 24
Finished Feb 21 02:25:02 PM PST 24
Peak memory 224708 kb
Host smart-6843a1f4-206d-4774-b466-3cf9dd3e85ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137694811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3137694811
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3559280657
Short name T952
Test name
Test status
Simulation time 8883783573 ps
CPU time 10.5 seconds
Started Feb 21 02:25:00 PM PST 24
Finished Feb 21 02:25:10 PM PST 24
Peak memory 233316 kb
Host smart-e0261c7c-bd02-4eb5-9a86-5a607126ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559280657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3559280657
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.473243050
Short name T815
Test name
Test status
Simulation time 3725498012 ps
CPU time 7.31 seconds
Started Feb 21 02:25:01 PM PST 24
Finished Feb 21 02:25:08 PM PST 24
Peak memory 224632 kb
Host smart-7cac80dc-8f71-4fd0-9528-c973151aabe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473243050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.473243050
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1403006496
Short name T544
Test name
Test status
Simulation time 1057553020 ps
CPU time 13.88 seconds
Started Feb 21 02:25:00 PM PST 24
Finished Feb 21 02:25:14 PM PST 24
Peak memory 238644 kb
Host smart-402d758a-3ffb-412c-855d-e12f8b5ec698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403006496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1403006496
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4030117287
Short name T698
Test name
Test status
Simulation time 1079256473 ps
CPU time 7.91 seconds
Started Feb 21 02:24:54 PM PST 24
Finished Feb 21 02:25:02 PM PST 24
Peak memory 223064 kb
Host smart-f143b555-cfa2-4f7d-8c5b-a1bb4ce18b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030117287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4030117287
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4156580806
Short name T511
Test name
Test status
Simulation time 218774472 ps
CPU time 3.97 seconds
Started Feb 21 02:25:08 PM PST 24
Finished Feb 21 02:25:13 PM PST 24
Peak memory 219744 kb
Host smart-2ddae41d-40a3-43ef-9dfc-e30c6a2250b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4156580806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4156580806
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.799434362
Short name T822
Test name
Test status
Simulation time 53283620 ps
CPU time 0.95 seconds
Started Feb 21 02:25:08 PM PST 24
Finished Feb 21 02:25:10 PM PST 24
Peak memory 206576 kb
Host smart-4c63c10c-8a23-494b-9d6b-da635ccda4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799434362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.799434362
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3292987378
Short name T573
Test name
Test status
Simulation time 10035228573 ps
CPU time 41.1 seconds
Started Feb 21 02:24:59 PM PST 24
Finished Feb 21 02:25:40 PM PST 24
Peak memory 216512 kb
Host smart-ceb2fa81-3845-4bbb-8fd3-cd9694cad8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292987378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3292987378
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1372739085
Short name T550
Test name
Test status
Simulation time 2016584259 ps
CPU time 8.19 seconds
Started Feb 21 02:25:01 PM PST 24
Finished Feb 21 02:25:09 PM PST 24
Peak memory 216456 kb
Host smart-2466e3c2-ad3e-4b56-8d9c-df5d40f4f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372739085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1372739085
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1129951263
Short name T298
Test name
Test status
Simulation time 903532335 ps
CPU time 3.36 seconds
Started Feb 21 02:24:54 PM PST 24
Finished Feb 21 02:24:58 PM PST 24
Peak memory 208996 kb
Host smart-18e1de67-1c79-4eec-9c34-c6917b8b5aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129951263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1129951263
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3374895712
Short name T651
Test name
Test status
Simulation time 20111575 ps
CPU time 0.7 seconds
Started Feb 21 02:24:58 PM PST 24
Finished Feb 21 02:24:59 PM PST 24
Peak memory 205496 kb
Host smart-eb930d69-2158-4816-90a4-e66e1842c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374895712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3374895712
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4088684144
Short name T335
Test name
Test status
Simulation time 24003134385 ps
CPU time 18.03 seconds
Started Feb 21 02:25:01 PM PST 24
Finished Feb 21 02:25:20 PM PST 24
Peak memory 247708 kb
Host smart-bff60033-289e-41d7-9a00-910719e0ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088684144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4088684144
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3583368463
Short name T3
Test name
Test status
Simulation time 19286271 ps
CPU time 0.72 seconds
Started Feb 21 02:25:13 PM PST 24
Finished Feb 21 02:25:14 PM PST 24
Peak memory 204428 kb
Host smart-ce402268-21a8-4092-a4f4-48c6f2e8ad0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583368463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3583368463
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2781642628
Short name T752
Test name
Test status
Simulation time 3953526025 ps
CPU time 14.72 seconds
Started Feb 21 02:25:13 PM PST 24
Finished Feb 21 02:25:28 PM PST 24
Peak memory 233852 kb
Host smart-93e49afc-8f4a-48a6-a56a-27a11bd9584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781642628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2781642628
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1168331868
Short name T717
Test name
Test status
Simulation time 73878371 ps
CPU time 0.79 seconds
Started Feb 21 02:25:08 PM PST 24
Finished Feb 21 02:25:10 PM PST 24
Peak memory 206152 kb
Host smart-c1c49e44-4d83-4d7e-92bf-fecb88d53689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168331868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1168331868
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1276268842
Short name T714
Test name
Test status
Simulation time 3003147726 ps
CPU time 15.36 seconds
Started Feb 21 02:25:16 PM PST 24
Finished Feb 21 02:25:33 PM PST 24
Peak memory 241132 kb
Host smart-971af71c-7414-4dff-88e7-538ac85b4be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276268842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1276268842
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2103223898
Short name T857
Test name
Test status
Simulation time 6104703999 ps
CPU time 48.55 seconds
Started Feb 21 02:25:16 PM PST 24
Finished Feb 21 02:26:06 PM PST 24
Peak memory 249368 kb
Host smart-264bf858-65e2-45de-88d2-dcbb9bf4ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103223898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2103223898
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1604849421
Short name T778
Test name
Test status
Simulation time 4921986138 ps
CPU time 11.03 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:25:26 PM PST 24
Peak memory 238056 kb
Host smart-fef40d84-720e-4191-b701-339c6a6519ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604849421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1604849421
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2873171020
Short name T130
Test name
Test status
Simulation time 4563656039 ps
CPU time 5.65 seconds
Started Feb 21 02:25:20 PM PST 24
Finished Feb 21 02:25:26 PM PST 24
Peak memory 219096 kb
Host smart-af20d221-4c29-4530-829c-487fa64cb1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873171020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2873171020
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2584976157
Short name T643
Test name
Test status
Simulation time 21096943480 ps
CPU time 22.44 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:25:38 PM PST 24
Peak memory 238120 kb
Host smart-7c46a667-c77c-46be-95f8-d9cfe86fba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584976157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2584976157
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.764551962
Short name T9
Test name
Test status
Simulation time 92865770 ps
CPU time 2.97 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:25:18 PM PST 24
Peak memory 232844 kb
Host smart-94908aed-6df9-4751-b7b2-c93df86d0199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764551962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.764551962
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3637966577
Short name T655
Test name
Test status
Simulation time 16084462455 ps
CPU time 42.1 seconds
Started Feb 21 02:25:06 PM PST 24
Finished Feb 21 02:25:48 PM PST 24
Peak memory 240320 kb
Host smart-25d4e7f0-584a-448f-afd7-d0a37173ebbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637966577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3637966577
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2005242044
Short name T559
Test name
Test status
Simulation time 3154882828 ps
CPU time 3.95 seconds
Started Feb 21 02:25:13 PM PST 24
Finished Feb 21 02:25:17 PM PST 24
Peak memory 223148 kb
Host smart-fada85a3-70e7-4c51-8f55-c35a6aade085
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2005242044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2005242044
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1059323119
Short name T282
Test name
Test status
Simulation time 8240203353 ps
CPU time 24.63 seconds
Started Feb 21 02:25:08 PM PST 24
Finished Feb 21 02:25:33 PM PST 24
Peak memory 219332 kb
Host smart-d462aa72-aea2-4289-99c3-0ad2d2a162d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059323119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1059323119
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2459993224
Short name T517
Test name
Test status
Simulation time 801867444 ps
CPU time 6.93 seconds
Started Feb 21 02:25:04 PM PST 24
Finished Feb 21 02:25:12 PM PST 24
Peak memory 216396 kb
Host smart-a15dd18e-032a-4f7c-9d5a-e05b347349fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459993224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2459993224
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1272049511
Short name T940
Test name
Test status
Simulation time 225777801 ps
CPU time 1.64 seconds
Started Feb 21 02:25:07 PM PST 24
Finished Feb 21 02:25:09 PM PST 24
Peak memory 216716 kb
Host smart-cd737d97-9d2e-462c-a21a-2b06e7f8e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272049511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1272049511
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.119047256
Short name T656
Test name
Test status
Simulation time 98428483 ps
CPU time 0.92 seconds
Started Feb 21 02:25:06 PM PST 24
Finished Feb 21 02:25:08 PM PST 24
Peak memory 205500 kb
Host smart-d24a264a-fc17-4b89-8f9f-7cf54fd31a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119047256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.119047256
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1237536202
Short name T580
Test name
Test status
Simulation time 361992523 ps
CPU time 5.72 seconds
Started Feb 21 02:25:15 PM PST 24
Finished Feb 21 02:25:21 PM PST 24
Peak memory 232704 kb
Host smart-6f81ae2b-fe3a-4c19-863a-6b57110cc5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237536202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1237536202
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.11540404
Short name T487
Test name
Test status
Simulation time 27364714 ps
CPU time 0.71 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:25:16 PM PST 24
Peak memory 204984 kb
Host smart-2870af51-b3d9-499b-8f2f-70fbecfbd693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11540404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.11540404
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2479405852
Short name T634
Test name
Test status
Simulation time 5945042984 ps
CPU time 6.88 seconds
Started Feb 21 02:25:19 PM PST 24
Finished Feb 21 02:25:27 PM PST 24
Peak memory 224704 kb
Host smart-62834915-1ec8-41d3-a635-465bd4aae02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479405852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2479405852
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3126002226
Short name T444
Test name
Test status
Simulation time 38623844 ps
CPU time 0.78 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:25:16 PM PST 24
Peak memory 206176 kb
Host smart-68e7d0ea-dbe7-4d7c-bc9e-2d749680821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126002226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3126002226
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3955817824
Short name T200
Test name
Test status
Simulation time 60104202909 ps
CPU time 114.12 seconds
Started Feb 21 02:25:20 PM PST 24
Finished Feb 21 02:27:14 PM PST 24
Peak memory 257420 kb
Host smart-209a71b1-fb84-4ad7-8c46-6159c5b766df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955817824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3955817824
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2929550467
Short name T173
Test name
Test status
Simulation time 92872887822 ps
CPU time 149.97 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:27:45 PM PST 24
Peak memory 239964 kb
Host smart-767fff38-47fb-4c85-afe5-2971dd86631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929550467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2929550467
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.968321435
Short name T813
Test name
Test status
Simulation time 10387572151 ps
CPU time 14.02 seconds
Started Feb 21 02:25:16 PM PST 24
Finished Feb 21 02:25:32 PM PST 24
Peak memory 224832 kb
Host smart-27ddd284-ee4e-4344-b610-6a0697b5ea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968321435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.968321435
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3245393193
Short name T362
Test name
Test status
Simulation time 15062119755 ps
CPU time 5.97 seconds
Started Feb 21 02:25:22 PM PST 24
Finished Feb 21 02:25:28 PM PST 24
Peak memory 233896 kb
Host smart-acaea5ed-86bb-4dc1-8cb4-868ed8b61521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245393193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3245393193
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.61289489
Short name T188
Test name
Test status
Simulation time 1767304502 ps
CPU time 12.1 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:25:27 PM PST 24
Peak memory 240912 kb
Host smart-92dde791-ccc0-41ed-a2dc-0c688384beca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61289489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.61289489
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1688575081
Short name T926
Test name
Test status
Simulation time 1259533429 ps
CPU time 7.43 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:25:23 PM PST 24
Peak memory 232776 kb
Host smart-2de1b5bc-8f44-470d-887a-bf3c93a89eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688575081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1688575081
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.313054554
Short name T345
Test name
Test status
Simulation time 1026564239 ps
CPU time 6.23 seconds
Started Feb 21 02:25:16 PM PST 24
Finished Feb 21 02:25:22 PM PST 24
Peak memory 217208 kb
Host smart-deed524d-30e9-45d5-ad54-47b0a3642446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313054554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.313054554
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3714866415
Short name T632
Test name
Test status
Simulation time 1275348230 ps
CPU time 3.61 seconds
Started Feb 21 02:25:22 PM PST 24
Finished Feb 21 02:25:25 PM PST 24
Peak memory 219744 kb
Host smart-9a3771c6-c19d-42d0-9c8e-6cd0e694295c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3714866415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3714866415
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4068756078
Short name T140
Test name
Test status
Simulation time 5700482572 ps
CPU time 99.81 seconds
Started Feb 21 02:25:17 PM PST 24
Finished Feb 21 02:26:58 PM PST 24
Peak memory 267224 kb
Host smart-673acfc4-a311-4f85-8134-11574bf44cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068756078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4068756078
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3607898013
Short name T287
Test name
Test status
Simulation time 948979125 ps
CPU time 17.06 seconds
Started Feb 21 02:25:17 PM PST 24
Finished Feb 21 02:25:36 PM PST 24
Peak memory 216428 kb
Host smart-1c9f4dc0-11d6-480b-a212-9e516c12227f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607898013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3607898013
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2662088292
Short name T856
Test name
Test status
Simulation time 7269504199 ps
CPU time 23.4 seconds
Started Feb 21 02:25:15 PM PST 24
Finished Feb 21 02:25:39 PM PST 24
Peak memory 216456 kb
Host smart-b63bf3cb-04bc-4070-b337-d576651229b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662088292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2662088292
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.258999404
Short name T430
Test name
Test status
Simulation time 689477722 ps
CPU time 2.27 seconds
Started Feb 21 02:25:16 PM PST 24
Finished Feb 21 02:25:19 PM PST 24
Peak memory 216568 kb
Host smart-ceef971f-5c03-42b6-889b-b4175b8b4d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258999404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.258999404
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2021668440
Short name T755
Test name
Test status
Simulation time 94065114 ps
CPU time 0.8 seconds
Started Feb 21 02:25:14 PM PST 24
Finished Feb 21 02:25:16 PM PST 24
Peak memory 205500 kb
Host smart-6e28db1b-5548-48cc-8428-47a07246f4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021668440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2021668440
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1922910188
Short name T478
Test name
Test status
Simulation time 58603755419 ps
CPU time 28.84 seconds
Started Feb 21 02:25:19 PM PST 24
Finished Feb 21 02:25:49 PM PST 24
Peak memory 233872 kb
Host smart-0cc6b4f8-b93a-4a3f-ae6c-38d0db4599b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922910188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1922910188
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.746344455
Short name T858
Test name
Test status
Simulation time 22013120 ps
CPU time 0.71 seconds
Started Feb 21 02:25:35 PM PST 24
Finished Feb 21 02:25:36 PM PST 24
Peak memory 204976 kb
Host smart-8c7aef88-28f2-453f-a8cb-743805f64a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746344455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.746344455
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2205752604
Short name T882
Test name
Test status
Simulation time 1025868206 ps
CPU time 2.98 seconds
Started Feb 21 02:25:27 PM PST 24
Finished Feb 21 02:25:30 PM PST 24
Peak memory 235936 kb
Host smart-d9a55b94-901f-49c9-8da8-4fc011002fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205752604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2205752604
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4109247806
Short name T290
Test name
Test status
Simulation time 40661447 ps
CPU time 0.76 seconds
Started Feb 21 02:25:15 PM PST 24
Finished Feb 21 02:25:16 PM PST 24
Peak memory 205176 kb
Host smart-6de213ad-da45-417c-9fae-0e2485cac637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109247806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4109247806
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2759295766
Short name T818
Test name
Test status
Simulation time 69377513058 ps
CPU time 136.53 seconds
Started Feb 21 02:25:27 PM PST 24
Finished Feb 21 02:27:45 PM PST 24
Peak memory 255820 kb
Host smart-f681d322-57f1-489b-8b37-c51f694373dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759295766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2759295766
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.474318630
Short name T648
Test name
Test status
Simulation time 3021581559 ps
CPU time 72.3 seconds
Started Feb 21 02:25:27 PM PST 24
Finished Feb 21 02:26:40 PM PST 24
Peak memory 256880 kb
Host smart-0d2ae376-a61c-4840-884f-b8293c7c486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474318630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.474318630
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3936393
Short name T244
Test name
Test status
Simulation time 23668214484 ps
CPU time 49.85 seconds
Started Feb 21 02:25:27 PM PST 24
Finished Feb 21 02:26:17 PM PST 24
Peak memory 234124 kb
Host smart-9927c5cb-f54a-482f-a247-fbac48b9fce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.3936393
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1911485799
Short name T275
Test name
Test status
Simulation time 300830070 ps
CPU time 7.71 seconds
Started Feb 21 02:25:36 PM PST 24
Finished Feb 21 02:25:44 PM PST 24
Peak memory 232788 kb
Host smart-08215355-e85a-4a95-9881-b35d94ed3d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911485799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1911485799
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2974940369
Short name T84
Test name
Test status
Simulation time 90944538 ps
CPU time 2.44 seconds
Started Feb 21 02:25:28 PM PST 24
Finished Feb 21 02:25:31 PM PST 24
Peak memory 232796 kb
Host smart-9d689d05-c3ca-4ce9-8f9b-ba4cb9ea1ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974940369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2974940369
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2449265338
Short name T219
Test name
Test status
Simulation time 2756420832 ps
CPU time 11.5 seconds
Started Feb 21 02:25:36 PM PST 24
Finished Feb 21 02:25:47 PM PST 24
Peak memory 232920 kb
Host smart-4ccffb61-533d-463a-884b-f48cddb678b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449265338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2449265338
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.910108233
Short name T883
Test name
Test status
Simulation time 3004507427 ps
CPU time 10.67 seconds
Started Feb 21 02:25:34 PM PST 24
Finished Feb 21 02:25:45 PM PST 24
Peak memory 216976 kb
Host smart-1064a76d-df7c-43c7-b6d1-ab5b3e3400c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910108233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.910108233
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.870157324
Short name T646
Test name
Test status
Simulation time 1899720089 ps
CPU time 6.05 seconds
Started Feb 21 02:25:20 PM PST 24
Finished Feb 21 02:25:26 PM PST 24
Peak memory 218800 kb
Host smart-b28172de-e657-45a0-b445-0e2857bb713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870157324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.870157324
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2815438055
Short name T35
Test name
Test status
Simulation time 509095954 ps
CPU time 3.73 seconds
Started Feb 21 02:25:38 PM PST 24
Finished Feb 21 02:25:42 PM PST 24
Peak memory 222704 kb
Host smart-21a15c8c-a9d3-49ae-8f74-4a1189dd01ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2815438055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2815438055
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4250654205
Short name T237
Test name
Test status
Simulation time 17568378826 ps
CPU time 188.34 seconds
Started Feb 21 02:25:41 PM PST 24
Finished Feb 21 02:28:50 PM PST 24
Peak memory 256716 kb
Host smart-80b3a89e-ddc7-4bdf-8a6c-ef2bbc0694bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250654205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4250654205
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3089549832
Short name T820
Test name
Test status
Simulation time 46924174246 ps
CPU time 100.68 seconds
Started Feb 21 02:25:20 PM PST 24
Finished Feb 21 02:27:01 PM PST 24
Peak memory 216524 kb
Host smart-610eca8a-1f2c-4315-897a-8e4b3af8a169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089549832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3089549832
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.907237114
Short name T968
Test name
Test status
Simulation time 7623421991 ps
CPU time 22.26 seconds
Started Feb 21 02:25:17 PM PST 24
Finished Feb 21 02:25:40 PM PST 24
Peak memory 217356 kb
Host smart-d552d1a2-5c41-490f-b8fa-85fdabbbe01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907237114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.907237114
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3714958562
Short name T942
Test name
Test status
Simulation time 85244054 ps
CPU time 1.04 seconds
Started Feb 21 02:25:16 PM PST 24
Finished Feb 21 02:25:18 PM PST 24
Peak memory 206900 kb
Host smart-f07bb062-dd9d-4ee0-81b8-a5b35aea8b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714958562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3714958562
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3089016595
Short name T548
Test name
Test status
Simulation time 179585371 ps
CPU time 0.84 seconds
Started Feb 21 02:25:16 PM PST 24
Finished Feb 21 02:25:19 PM PST 24
Peak memory 205520 kb
Host smart-1b8ae62f-a5d3-4e7c-9d4c-06d8c2ac1a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089016595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3089016595
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3998350301
Short name T340
Test name
Test status
Simulation time 680002121 ps
CPU time 4.88 seconds
Started Feb 21 02:25:36 PM PST 24
Finished Feb 21 02:25:42 PM PST 24
Peak memory 233396 kb
Host smart-d3633c67-3749-4e53-9d05-dea2c3bf7149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998350301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3998350301
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.18648318
Short name T625
Test name
Test status
Simulation time 27325159 ps
CPU time 0.66 seconds
Started Feb 21 02:25:34 PM PST 24
Finished Feb 21 02:25:35 PM PST 24
Peak memory 204440 kb
Host smart-379893e1-dc19-46be-837b-b64d94a0d6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.18648318
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3223413370
Short name T371
Test name
Test status
Simulation time 345219845 ps
CPU time 3.37 seconds
Started Feb 21 02:25:34 PM PST 24
Finished Feb 21 02:25:38 PM PST 24
Peak memory 217356 kb
Host smart-46484201-a1d9-407e-98c3-e9b39efeb6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223413370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3223413370
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.17276503
Short name T944
Test name
Test status
Simulation time 13640487 ps
CPU time 0.78 seconds
Started Feb 21 02:25:30 PM PST 24
Finished Feb 21 02:25:31 PM PST 24
Peak memory 205152 kb
Host smart-9bb6e37a-1e9f-4d30-b460-8c796f55e602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17276503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.17276503
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4015144632
Short name T896
Test name
Test status
Simulation time 106883625248 ps
CPU time 44.54 seconds
Started Feb 21 02:25:29 PM PST 24
Finished Feb 21 02:26:14 PM PST 24
Peak memory 224880 kb
Host smart-a2471a56-2236-406b-9dd2-668d6e19dbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015144632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4015144632
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3728041870
Short name T251
Test name
Test status
Simulation time 64223403101 ps
CPU time 298.21 seconds
Started Feb 21 02:25:29 PM PST 24
Finished Feb 21 02:30:27 PM PST 24
Peak memory 270020 kb
Host smart-ec9a2dc1-3c38-4b02-9d47-f57905ded1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728041870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3728041870
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1964048785
Short name T242
Test name
Test status
Simulation time 66957682012 ps
CPU time 167.28 seconds
Started Feb 21 02:25:42 PM PST 24
Finished Feb 21 02:28:29 PM PST 24
Peak memory 254556 kb
Host smart-76f3ba83-115f-4b0a-adf9-00dfd36a88c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964048785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1964048785
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3733855608
Short name T644
Test name
Test status
Simulation time 11277432805 ps
CPU time 48.86 seconds
Started Feb 21 02:25:34 PM PST 24
Finished Feb 21 02:26:23 PM PST 24
Peak memory 249280 kb
Host smart-5249bb6a-3344-47c8-80df-76b2c292b6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733855608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3733855608
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1550040994
Short name T958
Test name
Test status
Simulation time 644727251 ps
CPU time 4.21 seconds
Started Feb 21 02:25:34 PM PST 24
Finished Feb 21 02:25:39 PM PST 24
Peak memory 216940 kb
Host smart-66a52699-49d6-4d1a-bc27-09b3043d26e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550040994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1550040994
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2792208201
Short name T425
Test name
Test status
Simulation time 2726969482 ps
CPU time 5.02 seconds
Started Feb 21 02:25:26 PM PST 24
Finished Feb 21 02:25:32 PM PST 24
Peak memory 233980 kb
Host smart-6651836d-e400-485a-99f3-94ab88c116d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792208201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2792208201
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1738822
Short name T617
Test name
Test status
Simulation time 10255294610 ps
CPU time 10.55 seconds
Started Feb 21 02:25:35 PM PST 24
Finished Feb 21 02:25:46 PM PST 24
Peak memory 236596 kb
Host smart-d41324ef-33d3-478f-bff2-2f02487dd700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.1738822
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.948546053
Short name T485
Test name
Test status
Simulation time 255157400 ps
CPU time 4.53 seconds
Started Feb 21 02:25:25 PM PST 24
Finished Feb 21 02:25:31 PM PST 24
Peak memory 220996 kb
Host smart-e7d6b1b3-d0de-4020-8fdc-9be9666f7bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948546053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.948546053
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2424797587
Short name T306
Test name
Test status
Simulation time 555635434 ps
CPU time 3.71 seconds
Started Feb 21 02:25:34 PM PST 24
Finished Feb 21 02:25:38 PM PST 24
Peak memory 222552 kb
Host smart-e4440f10-9ce7-47c3-aeef-68cf9eb03884
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2424797587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2424797587
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3388048083
Short name T551
Test name
Test status
Simulation time 92457593999 ps
CPU time 97.18 seconds
Started Feb 21 02:25:35 PM PST 24
Finished Feb 21 02:27:13 PM PST 24
Peak memory 216488 kb
Host smart-2dd10665-deae-4ded-9c91-ca29927918eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388048083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3388048083
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1235890328
Short name T915
Test name
Test status
Simulation time 1474751237 ps
CPU time 4.71 seconds
Started Feb 21 02:25:36 PM PST 24
Finished Feb 21 02:25:41 PM PST 24
Peak memory 216300 kb
Host smart-bba97c84-c36e-4485-8bb5-b5fc4687b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235890328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1235890328
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3346421442
Short name T57
Test name
Test status
Simulation time 47714035 ps
CPU time 0.87 seconds
Started Feb 21 02:25:35 PM PST 24
Finished Feb 21 02:25:36 PM PST 24
Peak memory 206532 kb
Host smart-1908f1b7-6feb-4547-bb00-e1c02122af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346421442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3346421442
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2915252115
Short name T447
Test name
Test status
Simulation time 120714594 ps
CPU time 0.81 seconds
Started Feb 21 02:25:26 PM PST 24
Finished Feb 21 02:25:28 PM PST 24
Peak memory 205500 kb
Host smart-27c234ed-de9c-4445-9d82-ce468db9adcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915252115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2915252115
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1666521514
Short name T85
Test name
Test status
Simulation time 1785491603 ps
CPU time 12.39 seconds
Started Feb 21 02:25:35 PM PST 24
Finished Feb 21 02:25:48 PM PST 24
Peak memory 228264 kb
Host smart-93664133-2d5b-473e-80e2-c013aace1ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666521514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1666521514
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.228793268
Short name T293
Test name
Test status
Simulation time 24250112 ps
CPU time 0.71 seconds
Started Feb 21 02:25:44 PM PST 24
Finished Feb 21 02:25:45 PM PST 24
Peak memory 204992 kb
Host smart-8f979e76-2536-4ae9-99c1-b8de5a9e3e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228793268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.228793268
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.596757344
Short name T212
Test name
Test status
Simulation time 121354046 ps
CPU time 2.04 seconds
Started Feb 21 02:25:50 PM PST 24
Finished Feb 21 02:25:52 PM PST 24
Peak memory 216792 kb
Host smart-fde64009-4e9e-4dec-a452-d9f3858e8d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596757344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.596757344
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3002679417
Short name T509
Test name
Test status
Simulation time 35569183 ps
CPU time 0.77 seconds
Started Feb 21 02:25:34 PM PST 24
Finished Feb 21 02:25:36 PM PST 24
Peak memory 206132 kb
Host smart-0efb35d0-2c49-4415-8c8c-71efbdd9f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002679417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3002679417
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.446611682
Short name T782
Test name
Test status
Simulation time 586310745465 ps
CPU time 348.96 seconds
Started Feb 21 02:25:53 PM PST 24
Finished Feb 21 02:31:43 PM PST 24
Peak memory 271296 kb
Host smart-5e9647f2-585b-4056-8ab6-a60159417ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446611682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.446611682
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.706263786
Short name T119
Test name
Test status
Simulation time 10516129173 ps
CPU time 99.28 seconds
Started Feb 21 02:25:51 PM PST 24
Finished Feb 21 02:27:31 PM PST 24
Peak memory 251412 kb
Host smart-22401e61-84f9-4b64-b0b8-5ddb589e69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706263786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.706263786
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1513787308
Short name T175
Test name
Test status
Simulation time 232255261622 ps
CPU time 191.72 seconds
Started Feb 21 02:25:53 PM PST 24
Finished Feb 21 02:29:05 PM PST 24
Peak memory 257052 kb
Host smart-34b354d5-2540-4f8d-92e2-0544f02b5991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513787308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1513787308
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1855750518
Short name T969
Test name
Test status
Simulation time 995002861 ps
CPU time 10.27 seconds
Started Feb 21 02:25:58 PM PST 24
Finished Feb 21 02:26:09 PM PST 24
Peak memory 230120 kb
Host smart-fcd54b43-d62a-49a2-bb15-3a5e885cf754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855750518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1855750518
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2243428595
Short name T461
Test name
Test status
Simulation time 1458919046 ps
CPU time 7 seconds
Started Feb 21 02:26:00 PM PST 24
Finished Feb 21 02:26:07 PM PST 24
Peak memory 233516 kb
Host smart-c5823b2e-23ae-48a5-a6fd-be9cb578e4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243428595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2243428595
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2084600185
Short name T575
Test name
Test status
Simulation time 2821457217 ps
CPU time 18.05 seconds
Started Feb 21 02:26:05 PM PST 24
Finished Feb 21 02:26:23 PM PST 24
Peak memory 248736 kb
Host smart-c38b1f83-8c8e-4200-acdf-213ca1f075a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084600185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2084600185
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1545522319
Short name T174
Test name
Test status
Simulation time 3473004866 ps
CPU time 5.65 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:15 PM PST 24
Peak memory 232928 kb
Host smart-9a6489ef-d0dc-482d-9f22-397e7948250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545522319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1545522319
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2208444442
Short name T902
Test name
Test status
Simulation time 17873280898 ps
CPU time 8.38 seconds
Started Feb 21 02:26:02 PM PST 24
Finished Feb 21 02:26:11 PM PST 24
Peak memory 217992 kb
Host smart-42bfddde-b8f4-42e9-acad-5b67fe2cabff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208444442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2208444442
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1235600566
Short name T313
Test name
Test status
Simulation time 146221208 ps
CPU time 3.3 seconds
Started Feb 21 02:25:47 PM PST 24
Finished Feb 21 02:25:52 PM PST 24
Peak memory 220728 kb
Host smart-aa9239d9-7e70-40ff-954e-c81a6cc454c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1235600566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1235600566
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3271480063
Short name T626
Test name
Test status
Simulation time 31538496526 ps
CPU time 37.23 seconds
Started Feb 21 02:25:33 PM PST 24
Finished Feb 21 02:26:11 PM PST 24
Peak memory 216540 kb
Host smart-15384bff-8a56-4740-9163-9d6cdc4e52d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271480063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3271480063
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.236929731
Short name T705
Test name
Test status
Simulation time 1843002964 ps
CPU time 4.95 seconds
Started Feb 21 02:25:32 PM PST 24
Finished Feb 21 02:25:37 PM PST 24
Peak memory 208060 kb
Host smart-54f0d9c7-7cbb-4685-aafd-61e24cb22f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236929731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.236929731
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3285716211
Short name T563
Test name
Test status
Simulation time 669449473 ps
CPU time 1.83 seconds
Started Feb 21 02:25:33 PM PST 24
Finished Feb 21 02:25:36 PM PST 24
Peak memory 208300 kb
Host smart-1b7623ab-bbb0-4fd3-a436-142bc795d7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285716211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3285716211
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.201279339
Short name T496
Test name
Test status
Simulation time 168573971 ps
CPU time 0.9 seconds
Started Feb 21 02:25:38 PM PST 24
Finished Feb 21 02:25:39 PM PST 24
Peak memory 206480 kb
Host smart-6cb871db-af3b-439c-b47f-3694a4b920ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201279339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.201279339
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1313674773
Short name T893
Test name
Test status
Simulation time 5702963558 ps
CPU time 12.8 seconds
Started Feb 21 02:26:03 PM PST 24
Finished Feb 21 02:26:17 PM PST 24
Peak memory 237976 kb
Host smart-92b79fdc-57b1-4365-86c3-309591a25a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313674773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1313674773
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2313192219
Short name T420
Test name
Test status
Simulation time 42996297 ps
CPU time 0.73 seconds
Started Feb 21 02:25:53 PM PST 24
Finished Feb 21 02:25:54 PM PST 24
Peak memory 204988 kb
Host smart-9803e868-bc9f-4b31-a5a5-547542043720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313192219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2313192219
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1480819024
Short name T726
Test name
Test status
Simulation time 686456201 ps
CPU time 3.09 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:13 PM PST 24
Peak memory 224596 kb
Host smart-fe746e26-c935-474d-91d0-f5c9f71646db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480819024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1480819024
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.646608398
Short name T628
Test name
Test status
Simulation time 17074438 ps
CPU time 0.8 seconds
Started Feb 21 02:25:53 PM PST 24
Finished Feb 21 02:25:55 PM PST 24
Peak memory 206168 kb
Host smart-2d96497f-4406-43f5-9020-dab3366e1357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646608398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.646608398
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.287062577
Short name T177
Test name
Test status
Simulation time 40299434342 ps
CPU time 127.46 seconds
Started Feb 21 02:26:01 PM PST 24
Finished Feb 21 02:28:09 PM PST 24
Peak memory 265668 kb
Host smart-5daf0909-8db6-489c-94f8-46b36523c8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287062577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.287062577
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3673004731
Short name T772
Test name
Test status
Simulation time 9844043313 ps
CPU time 91.97 seconds
Started Feb 21 02:25:49 PM PST 24
Finished Feb 21 02:27:22 PM PST 24
Peak memory 254096 kb
Host smart-ab0a1ec4-96d0-45fc-817f-d01f77c4f924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673004731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3673004731
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.829613194
Short name T278
Test name
Test status
Simulation time 51807725483 ps
CPU time 39.86 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:49 PM PST 24
Peak memory 248744 kb
Host smart-7674e4c2-34d8-47cf-9c3d-d88017885e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829613194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.829613194
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2720378640
Short name T853
Test name
Test status
Simulation time 11081021494 ps
CPU time 12.45 seconds
Started Feb 21 02:25:45 PM PST 24
Finished Feb 21 02:25:59 PM PST 24
Peak memory 234908 kb
Host smart-de86bbda-5132-4166-a7d2-199e32e9b3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720378640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2720378640
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2885104798
Short name T231
Test name
Test status
Simulation time 876667334 ps
CPU time 5.91 seconds
Started Feb 21 02:25:47 PM PST 24
Finished Feb 21 02:25:54 PM PST 24
Peak memory 233804 kb
Host smart-3ee20d7f-ad0e-44f8-a4f2-53ed5d9da774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885104798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2885104798
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3505209904
Short name T171
Test name
Test status
Simulation time 41666217790 ps
CPU time 21.94 seconds
Started Feb 21 02:25:47 PM PST 24
Finished Feb 21 02:26:10 PM PST 24
Peak memory 227244 kb
Host smart-4c2e19b2-6bf0-4809-a2ad-bee2ae67cc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505209904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3505209904
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.909019495
Short name T149
Test name
Test status
Simulation time 50639726996 ps
CPU time 21.5 seconds
Started Feb 21 02:25:53 PM PST 24
Finished Feb 21 02:26:15 PM PST 24
Peak memory 238060 kb
Host smart-ebf9331a-3d93-49ef-ad67-622e4009a3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909019495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.909019495
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3600598148
Short name T52
Test name
Test status
Simulation time 627914779 ps
CPU time 4.51 seconds
Started Feb 21 02:26:00 PM PST 24
Finished Feb 21 02:26:05 PM PST 24
Peak memory 220216 kb
Host smart-e551f242-6dff-47e3-9a6d-45c70eb9b106
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3600598148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3600598148
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4131213092
Short name T949
Test name
Test status
Simulation time 272662625 ps
CPU time 0.97 seconds
Started Feb 21 02:26:03 PM PST 24
Finished Feb 21 02:26:05 PM PST 24
Peak memory 205388 kb
Host smart-89eaa404-118b-4f8c-b10b-de59dfa9b9ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131213092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4131213092
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3222121126
Short name T66
Test name
Test status
Simulation time 1570449171 ps
CPU time 18.02 seconds
Started Feb 21 02:25:53 PM PST 24
Finished Feb 21 02:26:12 PM PST 24
Peak memory 216440 kb
Host smart-1f32e5ea-ab13-4058-9c90-612f95f9d4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222121126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3222121126
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1516488288
Short name T467
Test name
Test status
Simulation time 82124487293 ps
CPU time 17.51 seconds
Started Feb 21 02:25:52 PM PST 24
Finished Feb 21 02:26:10 PM PST 24
Peak memory 216476 kb
Host smart-b1976acd-142b-4778-b7dd-28962915df3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516488288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1516488288
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1529054981
Short name T547
Test name
Test status
Simulation time 113053692 ps
CPU time 2.13 seconds
Started Feb 21 02:25:52 PM PST 24
Finished Feb 21 02:25:55 PM PST 24
Peak memory 208448 kb
Host smart-5964d7a4-6e9d-4918-b131-b515781df627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529054981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1529054981
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.438527172
Short name T435
Test name
Test status
Simulation time 137366983 ps
CPU time 1.05 seconds
Started Feb 21 02:25:51 PM PST 24
Finished Feb 21 02:25:52 PM PST 24
Peak memory 206520 kb
Host smart-e460bc92-03f8-4317-95ca-27d5af056f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438527172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.438527172
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.982146081
Short name T943
Test name
Test status
Simulation time 884633507 ps
CPU time 5.58 seconds
Started Feb 21 02:26:06 PM PST 24
Finished Feb 21 02:26:12 PM PST 24
Peak memory 218248 kb
Host smart-d7d1fc93-539b-4212-9998-51b2dbe0f133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982146081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.982146081
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3485995621
Short name T339
Test name
Test status
Simulation time 49281157 ps
CPU time 0.75 seconds
Started Feb 21 02:26:02 PM PST 24
Finished Feb 21 02:26:03 PM PST 24
Peak memory 204432 kb
Host smart-fd0c5916-ead0-4500-83c6-ad4a1a1a0344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485995621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3485995621
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.551511855
Short name T640
Test name
Test status
Simulation time 1993725424 ps
CPU time 3.62 seconds
Started Feb 21 02:26:05 PM PST 24
Finished Feb 21 02:26:09 PM PST 24
Peak memory 224608 kb
Host smart-94393b88-75d6-4291-bc88-ce633b39d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551511855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.551511855
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.704278303
Short name T920
Test name
Test status
Simulation time 44847483 ps
CPU time 0.74 seconds
Started Feb 21 02:25:46 PM PST 24
Finished Feb 21 02:25:48 PM PST 24
Peak memory 205168 kb
Host smart-4a815221-4486-4a4c-8e47-b220b25578d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704278303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.704278303
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2205668133
Short name T260
Test name
Test status
Simulation time 61795175491 ps
CPU time 164.98 seconds
Started Feb 21 02:26:02 PM PST 24
Finished Feb 21 02:28:48 PM PST 24
Peak memory 250804 kb
Host smart-4b8a0994-47b5-45ea-9722-195de9c0c20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205668133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2205668133
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1385376166
Short name T121
Test name
Test status
Simulation time 72935677450 ps
CPU time 483.08 seconds
Started Feb 21 02:26:00 PM PST 24
Finished Feb 21 02:34:03 PM PST 24
Peak memory 258228 kb
Host smart-d1b53b7c-6f1f-4590-b3fa-f8b60e6f193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385376166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1385376166
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2343428722
Short name T64
Test name
Test status
Simulation time 433242102070 ps
CPU time 268.75 seconds
Started Feb 21 02:26:07 PM PST 24
Finished Feb 21 02:30:36 PM PST 24
Peak memory 251096 kb
Host smart-75285c18-fd76-45d0-9056-67c46c877767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343428722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2343428722
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_intercept.130799469
Short name T207
Test name
Test status
Simulation time 1949947380 ps
CPU time 4.78 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:13 PM PST 24
Peak memory 233584 kb
Host smart-039ccc91-6d0d-4c1a-abb6-5abb2f2de894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130799469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.130799469
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2293283537
Short name T348
Test name
Test status
Simulation time 3948115200 ps
CPU time 20.77 seconds
Started Feb 21 02:26:05 PM PST 24
Finished Feb 21 02:26:26 PM PST 24
Peak memory 247608 kb
Host smart-5e211e37-c685-4f01-8f07-9f9f1b5566b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293283537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2293283537
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1237880314
Short name T380
Test name
Test status
Simulation time 556375218 ps
CPU time 3.94 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:26:18 PM PST 24
Peak memory 233464 kb
Host smart-26757e52-fbe0-460d-ac64-549a9f55b1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237880314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1237880314
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1784191763
Short name T754
Test name
Test status
Simulation time 25432812073 ps
CPU time 9.55 seconds
Started Feb 21 02:26:03 PM PST 24
Finished Feb 21 02:26:13 PM PST 24
Peak memory 233120 kb
Host smart-bc70b9de-0717-4187-9d6d-e97b6e34fcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784191763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1784191763
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2461190838
Short name T126
Test name
Test status
Simulation time 616191936 ps
CPU time 4.78 seconds
Started Feb 21 02:26:06 PM PST 24
Finished Feb 21 02:26:12 PM PST 24
Peak memory 220032 kb
Host smart-7f81b8c1-fab3-4d97-a806-cc7cef4c9ee1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2461190838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2461190838
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.646178030
Short name T832
Test name
Test status
Simulation time 58230007587 ps
CPU time 288.14 seconds
Started Feb 21 02:26:05 PM PST 24
Finished Feb 21 02:30:54 PM PST 24
Peak memory 250412 kb
Host smart-12b18cc1-1725-420e-818f-032c9c1a654f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646178030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.646178030
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4281464668
Short name T377
Test name
Test status
Simulation time 17996184279 ps
CPU time 32.21 seconds
Started Feb 21 02:26:05 PM PST 24
Finished Feb 21 02:26:38 PM PST 24
Peak memory 216464 kb
Host smart-1a7358b8-eccf-4bbb-924b-decbdb220da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281464668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4281464668
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1073247776
Short name T358
Test name
Test status
Simulation time 2691626651 ps
CPU time 9.79 seconds
Started Feb 21 02:25:47 PM PST 24
Finished Feb 21 02:25:58 PM PST 24
Peak memory 216432 kb
Host smart-a17b065e-651d-4869-9912-1bb6f04b2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073247776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1073247776
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3392787749
Short name T850
Test name
Test status
Simulation time 126959708 ps
CPU time 0.88 seconds
Started Feb 21 02:25:51 PM PST 24
Finished Feb 21 02:25:53 PM PST 24
Peak memory 206080 kb
Host smart-5cea3061-939d-4237-892e-94a605f8e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392787749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3392787749
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.763619949
Short name T931
Test name
Test status
Simulation time 83893790 ps
CPU time 1.05 seconds
Started Feb 21 02:26:00 PM PST 24
Finished Feb 21 02:26:02 PM PST 24
Peak memory 206432 kb
Host smart-937f4f6e-5c5b-4ddf-acb2-ac626fcec4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763619949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.763619949
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2712653611
Short name T869
Test name
Test status
Simulation time 39589638815 ps
CPU time 21.14 seconds
Started Feb 21 02:26:06 PM PST 24
Finished Feb 21 02:26:28 PM PST 24
Peak memory 248880 kb
Host smart-8c3875cc-771c-49c4-a258-cf7e0928ff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712653611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2712653611
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3689626077
Short name T129
Test name
Test status
Simulation time 11651954 ps
CPU time 0.73 seconds
Started Feb 21 02:22:07 PM PST 24
Finished Feb 21 02:22:08 PM PST 24
Peak memory 204440 kb
Host smart-2952a64a-8527-47a3-9380-45fa0837fd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689626077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
689626077
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2326603693
Short name T732
Test name
Test status
Simulation time 524323612 ps
CPU time 3.71 seconds
Started Feb 21 02:21:59 PM PST 24
Finished Feb 21 02:22:03 PM PST 24
Peak memory 234384 kb
Host smart-f26326ba-df6a-4406-a66a-636beeab91e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326603693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2326603693
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1044201473
Short name T676
Test name
Test status
Simulation time 45842791 ps
CPU time 0.75 seconds
Started Feb 21 02:21:50 PM PST 24
Finished Feb 21 02:21:51 PM PST 24
Peak memory 205512 kb
Host smart-442a1a70-a00c-46ee-bba3-5998a7f3998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044201473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1044201473
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1873948639
Short name T272
Test name
Test status
Simulation time 11234056883 ps
CPU time 81.29 seconds
Started Feb 21 02:22:00 PM PST 24
Finished Feb 21 02:23:21 PM PST 24
Peak memory 267576 kb
Host smart-2bdf8a8a-c73e-423e-a66a-019572fdfc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873948639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1873948639
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1392164802
Short name T253
Test name
Test status
Simulation time 9919227738 ps
CPU time 93.28 seconds
Started Feb 21 02:21:57 PM PST 24
Finished Feb 21 02:23:31 PM PST 24
Peak memory 253304 kb
Host smart-8a8f8d35-67bb-4925-b924-ec3b366f1786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392164802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1392164802
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2218413646
Short name T156
Test name
Test status
Simulation time 692603815 ps
CPU time 11.18 seconds
Started Feb 21 02:22:00 PM PST 24
Finished Feb 21 02:22:11 PM PST 24
Peak memory 238792 kb
Host smart-6c4fe83c-3c73-4c8e-8b91-c29649707182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218413646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2218413646
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1218148821
Short name T913
Test name
Test status
Simulation time 5588591213 ps
CPU time 8.05 seconds
Started Feb 21 02:21:58 PM PST 24
Finished Feb 21 02:22:07 PM PST 24
Peak memory 233600 kb
Host smart-83d77d1c-af27-4f89-8186-e991a14f3477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218148821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1218148821
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1291403995
Short name T401
Test name
Test status
Simulation time 21235962724 ps
CPU time 44.9 seconds
Started Feb 21 02:22:00 PM PST 24
Finished Feb 21 02:22:45 PM PST 24
Peak memory 223916 kb
Host smart-9f55057d-31c8-4c05-8fcb-328eef7ed202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291403995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1291403995
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1487806510
Short name T618
Test name
Test status
Simulation time 15079841 ps
CPU time 0.97 seconds
Started Feb 21 02:22:00 PM PST 24
Finished Feb 21 02:22:01 PM PST 24
Peak memory 217868 kb
Host smart-6b8f4d0a-b703-41f4-a5ef-d73023780731
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487806510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1487806510
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2084259381
Short name T672
Test name
Test status
Simulation time 13474528687 ps
CPU time 24.41 seconds
Started Feb 21 02:21:58 PM PST 24
Finished Feb 21 02:22:23 PM PST 24
Peak memory 233048 kb
Host smart-4285e2e7-0339-4014-a276-f3b364a2579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084259381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2084259381
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1291429076
Short name T347
Test name
Test status
Simulation time 2024759988 ps
CPU time 9.13 seconds
Started Feb 21 02:22:00 PM PST 24
Finished Feb 21 02:22:10 PM PST 24
Peak memory 236600 kb
Host smart-7c3edfeb-1cef-44ed-906c-7f3dbee5c16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291429076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1291429076
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.377145404
Short name T43
Test name
Test status
Simulation time 72562032 ps
CPU time 0.7 seconds
Started Feb 21 02:22:03 PM PST 24
Finished Feb 21 02:22:05 PM PST 24
Peak memory 216328 kb
Host smart-125c43c2-f21f-43de-a444-c00d24ec7de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377145404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.377145404
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2620999845
Short name T36
Test name
Test status
Simulation time 666791699 ps
CPU time 4.02 seconds
Started Feb 21 02:21:58 PM PST 24
Finished Feb 21 02:22:03 PM PST 24
Peak memory 216484 kb
Host smart-5bbd63dd-4881-4403-8469-4640e4af3b03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2620999845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2620999845
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2296649233
Short name T49
Test name
Test status
Simulation time 218389245 ps
CPU time 1.07 seconds
Started Feb 21 02:22:08 PM PST 24
Finished Feb 21 02:22:10 PM PST 24
Peak memory 235468 kb
Host smart-5cbb0cba-fe78-49e8-b76a-5628d4703e15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296649233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2296649233
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3597151649
Short name T743
Test name
Test status
Simulation time 18399863935 ps
CPU time 58.59 seconds
Started Feb 21 02:21:59 PM PST 24
Finished Feb 21 02:22:58 PM PST 24
Peak memory 216620 kb
Host smart-8ca37039-3cc3-4c50-b2b3-8e0cde40676d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597151649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3597151649
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1603562158
Short name T19
Test name
Test status
Simulation time 7544133072 ps
CPU time 9.09 seconds
Started Feb 21 02:21:58 PM PST 24
Finished Feb 21 02:22:07 PM PST 24
Peak memory 216492 kb
Host smart-1a2f0ce1-044f-4dfb-bccb-aa3d3b732886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603562158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1603562158
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.99353607
Short name T524
Test name
Test status
Simulation time 147071469 ps
CPU time 1.03 seconds
Started Feb 21 02:21:59 PM PST 24
Finished Feb 21 02:22:00 PM PST 24
Peak memory 206768 kb
Host smart-27fb83a2-345b-46a1-ba4f-55531a710852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99353607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.99353607
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2111310865
Short name T482
Test name
Test status
Simulation time 76578162 ps
CPU time 0.95 seconds
Started Feb 21 02:21:59 PM PST 24
Finished Feb 21 02:22:01 PM PST 24
Peak memory 205520 kb
Host smart-3a8b94ca-4c99-4754-a596-039bc58b6d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111310865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2111310865
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4289020700
Short name T426
Test name
Test status
Simulation time 349846955 ps
CPU time 5.17 seconds
Started Feb 21 02:22:00 PM PST 24
Finished Feb 21 02:22:06 PM PST 24
Peak memory 240988 kb
Host smart-05255179-c727-41d9-ac3b-23b8d308aec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289020700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4289020700
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2146317514
Short name T4
Test name
Test status
Simulation time 11490574 ps
CPU time 0.77 seconds
Started Feb 21 02:26:03 PM PST 24
Finished Feb 21 02:26:04 PM PST 24
Peak memory 204980 kb
Host smart-71f9a788-e6c1-45e2-939b-1324045b536d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146317514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2146317514
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2041574886
Short name T657
Test name
Test status
Simulation time 627075916 ps
CPU time 2.76 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:11 PM PST 24
Peak memory 218988 kb
Host smart-8ac63705-d997-485c-a4d5-40f14b1b49e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041574886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2041574886
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.677467241
Short name T806
Test name
Test status
Simulation time 38210338 ps
CPU time 0.77 seconds
Started Feb 21 02:26:12 PM PST 24
Finished Feb 21 02:26:13 PM PST 24
Peak memory 206200 kb
Host smart-eab3c2b3-e61b-4b6f-9027-b6fc8d8c5f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677467241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.677467241
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3378588479
Short name T859
Test name
Test status
Simulation time 22430429746 ps
CPU time 85.99 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:27:36 PM PST 24
Peak memory 241048 kb
Host smart-6e13dac1-283e-42e9-bd4e-124cd7c5855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378588479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3378588479
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3870308237
Short name T595
Test name
Test status
Simulation time 71195365047 ps
CPU time 142.91 seconds
Started Feb 21 02:26:07 PM PST 24
Finished Feb 21 02:28:31 PM PST 24
Peak memory 256448 kb
Host smart-4cd58d70-3c28-4534-b4f8-4a3b2105a72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870308237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3870308237
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2700361818
Short name T243
Test name
Test status
Simulation time 684941402574 ps
CPU time 461.79 seconds
Started Feb 21 02:26:04 PM PST 24
Finished Feb 21 02:33:47 PM PST 24
Peak memory 273104 kb
Host smart-89cac1dd-c177-473f-adbe-5e8445e37b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700361818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2700361818
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3876908597
Short name T505
Test name
Test status
Simulation time 1967158137 ps
CPU time 14.51 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:24 PM PST 24
Peak memory 245628 kb
Host smart-1ecbaac3-fb62-4b12-81a7-cd883d7e249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876908597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3876908597
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3339768727
Short name T53
Test name
Test status
Simulation time 183628346 ps
CPU time 3.95 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:12 PM PST 24
Peak memory 219536 kb
Host smart-3ffbfeae-b389-4539-b4d4-48ea0b93a641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339768727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3339768727
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1661107277
Short name T241
Test name
Test status
Simulation time 941699220 ps
CPU time 5 seconds
Started Feb 21 02:26:10 PM PST 24
Finished Feb 21 02:26:15 PM PST 24
Peak memory 218016 kb
Host smart-9e63b82f-558e-42b6-8312-56c7b3f199ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661107277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1661107277
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2807335488
Short name T956
Test name
Test status
Simulation time 35577790707 ps
CPU time 20.13 seconds
Started Feb 21 02:26:07 PM PST 24
Finished Feb 21 02:26:28 PM PST 24
Peak memory 233776 kb
Host smart-317f80e0-6b93-405c-9e86-16ee4475f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807335488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2807335488
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.158590341
Short name T936
Test name
Test status
Simulation time 2110522330 ps
CPU time 5.52 seconds
Started Feb 21 02:26:05 PM PST 24
Finished Feb 21 02:26:11 PM PST 24
Peak memory 224596 kb
Host smart-13283e1e-0088-430a-a5c9-1921e333ef2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158590341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.158590341
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2950867729
Short name T422
Test name
Test status
Simulation time 1535365203 ps
CPU time 7.11 seconds
Started Feb 21 02:26:10 PM PST 24
Finished Feb 21 02:26:17 PM PST 24
Peak memory 221540 kb
Host smart-728a99dd-30ca-4e09-b635-85106c067fbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2950867729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2950867729
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.165371417
Short name T680
Test name
Test status
Simulation time 48017658523 ps
CPU time 42.93 seconds
Started Feb 21 02:26:05 PM PST 24
Finished Feb 21 02:26:48 PM PST 24
Peak memory 216484 kb
Host smart-d38339da-7c55-4df5-8c04-65b1dc077c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165371417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.165371417
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.158736855
Short name T619
Test name
Test status
Simulation time 15116655946 ps
CPU time 7.54 seconds
Started Feb 21 02:26:04 PM PST 24
Finished Feb 21 02:26:12 PM PST 24
Peak memory 216520 kb
Host smart-b87dbac0-5f26-43ba-b6b8-16d108258740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158736855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.158736855
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3290570393
Short name T768
Test name
Test status
Simulation time 90983983 ps
CPU time 1.16 seconds
Started Feb 21 02:26:04 PM PST 24
Finished Feb 21 02:26:06 PM PST 24
Peak memory 207644 kb
Host smart-089ee187-9c98-462a-8a2b-b9c1b075b03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290570393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3290570393
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.369891969
Short name T481
Test name
Test status
Simulation time 1328719715 ps
CPU time 0.87 seconds
Started Feb 21 02:26:06 PM PST 24
Finished Feb 21 02:26:08 PM PST 24
Peak memory 205524 kb
Host smart-81aba31e-b043-43de-a9a3-7ef2ef168ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369891969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.369891969
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4282258679
Short name T539
Test name
Test status
Simulation time 740217535 ps
CPU time 9.01 seconds
Started Feb 21 02:26:06 PM PST 24
Finished Feb 21 02:26:16 PM PST 24
Peak memory 218020 kb
Host smart-ddcc6b8c-da7a-4c40-ad7e-ffb3d7fc41e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282258679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4282258679
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1591075602
Short name T388
Test name
Test status
Simulation time 25467092 ps
CPU time 0.77 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:26:15 PM PST 24
Peak memory 204620 kb
Host smart-dffeede5-da9e-4020-b892-5a8abefa003c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591075602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1591075602
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3153250412
Short name T763
Test name
Test status
Simulation time 12447278219 ps
CPU time 11.72 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:21 PM PST 24
Peak memory 233968 kb
Host smart-5049bcfe-314a-45b4-91f0-920574775885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153250412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3153250412
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2646801108
Short name T386
Test name
Test status
Simulation time 13441929 ps
CPU time 0.82 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:10 PM PST 24
Peak memory 205532 kb
Host smart-0dab565d-5c51-4440-ae95-bd3d4398d0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646801108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2646801108
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1007728679
Short name T255
Test name
Test status
Simulation time 285336308173 ps
CPU time 503.7 seconds
Started Feb 21 02:26:06 PM PST 24
Finished Feb 21 02:34:30 PM PST 24
Peak memory 265592 kb
Host smart-dcb6f7ea-8492-4f58-9a5b-68cc57484250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007728679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1007728679
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4067673706
Short name T620
Test name
Test status
Simulation time 354247932159 ps
CPU time 658.6 seconds
Started Feb 21 02:26:11 PM PST 24
Finished Feb 21 02:37:10 PM PST 24
Peak memory 250400 kb
Host smart-08c5d5b3-9832-41d8-9604-31a534fa974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067673706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4067673706
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2311306657
Short name T636
Test name
Test status
Simulation time 55459284029 ps
CPU time 117.87 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:28:12 PM PST 24
Peak memory 237432 kb
Host smart-b0672882-0a7e-410d-8699-89130ccb03e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311306657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2311306657
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.555459258
Short name T538
Test name
Test status
Simulation time 338068980 ps
CPU time 7.63 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:17 PM PST 24
Peak memory 235956 kb
Host smart-e3aa97ac-a2a6-499c-b706-24d78ff93f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555459258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.555459258
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.262687788
Short name T203
Test name
Test status
Simulation time 1801416681 ps
CPU time 8.12 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:17 PM PST 24
Peak memory 219528 kb
Host smart-92c88978-e2f4-4a4e-b24b-0924838e0318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262687788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.262687788
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3420986686
Short name T523
Test name
Test status
Simulation time 1021947146 ps
CPU time 8.15 seconds
Started Feb 21 02:26:11 PM PST 24
Finished Feb 21 02:26:19 PM PST 24
Peak memory 222048 kb
Host smart-bfa39456-e140-4fc9-a4fd-990e5ea1ae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420986686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3420986686
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.38057705
Short name T749
Test name
Test status
Simulation time 10177194815 ps
CPU time 12.79 seconds
Started Feb 21 02:26:10 PM PST 24
Finished Feb 21 02:26:23 PM PST 24
Peak memory 233020 kb
Host smart-43c60527-85bd-418c-a8f6-5a464268f115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38057705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.38057705
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.731684028
Short name T585
Test name
Test status
Simulation time 2507391437 ps
CPU time 3.55 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:12 PM PST 24
Peak memory 233420 kb
Host smart-413d425c-bd40-42f4-be55-2c638d72aaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731684028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.731684028
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.231336706
Short name T596
Test name
Test status
Simulation time 2169525415 ps
CPU time 5.68 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:15 PM PST 24
Peak memory 218992 kb
Host smart-daef7b82-ebc0-4d25-a646-04129b79a524
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=231336706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.231336706
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2731671195
Short name T964
Test name
Test status
Simulation time 73067993 ps
CPU time 1.23 seconds
Started Feb 21 02:26:11 PM PST 24
Finished Feb 21 02:26:12 PM PST 24
Peak memory 206588 kb
Host smart-f71f4867-b143-45ad-9b42-5f3b6d4c41c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731671195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2731671195
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.648890061
Short name T558
Test name
Test status
Simulation time 12779093561 ps
CPU time 50.63 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:59 PM PST 24
Peak memory 220732 kb
Host smart-5e554a64-3086-471f-9272-283278ed789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648890061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.648890061
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3723438965
Short name T489
Test name
Test status
Simulation time 11871097275 ps
CPU time 8.85 seconds
Started Feb 21 02:26:12 PM PST 24
Finished Feb 21 02:26:21 PM PST 24
Peak memory 216492 kb
Host smart-edee2935-a809-4646-9794-f424faff00fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723438965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3723438965
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.843526943
Short name T925
Test name
Test status
Simulation time 62728033 ps
CPU time 1.48 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:10 PM PST 24
Peak memory 208424 kb
Host smart-ed1c55b4-999e-4658-837a-8286e70cf0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843526943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.843526943
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1412428222
Short name T784
Test name
Test status
Simulation time 48239689 ps
CPU time 0.84 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:09 PM PST 24
Peak memory 205492 kb
Host smart-70b141e4-9aab-4494-ad4a-847a4f5d5546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412428222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1412428222
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.792381284
Short name T332
Test name
Test status
Simulation time 45928515397 ps
CPU time 10.66 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:19 PM PST 24
Peak memory 218428 kb
Host smart-032bc54c-6723-47ce-ab6b-32abcc619f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792381284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.792381284
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3843194830
Short name T522
Test name
Test status
Simulation time 88698583 ps
CPU time 0.7 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:09 PM PST 24
Peak memory 205020 kb
Host smart-13f6316c-e544-47ad-b47e-63d512c507fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843194830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3843194830
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1706159090
Short name T13
Test name
Test status
Simulation time 376723923 ps
CPU time 3.84 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:26:18 PM PST 24
Peak memory 223624 kb
Host smart-6fb6f7b4-c761-4adc-a306-88e1cb1606ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706159090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1706159090
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.680619936
Short name T871
Test name
Test status
Simulation time 89597198 ps
CPU time 0.75 seconds
Started Feb 21 02:26:10 PM PST 24
Finished Feb 21 02:26:11 PM PST 24
Peak memory 205152 kb
Host smart-1c08d735-f994-492c-991e-656158ddc06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680619936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.680619936
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2840357345
Short name T165
Test name
Test status
Simulation time 17252417758 ps
CPU time 26.81 seconds
Started Feb 21 02:26:10 PM PST 24
Finished Feb 21 02:26:37 PM PST 24
Peak memory 233900 kb
Host smart-f82944d4-48bc-4815-bfc8-c8ae478088e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840357345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2840357345
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2189560813
Short name T909
Test name
Test status
Simulation time 22674301683 ps
CPU time 99.35 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:27:49 PM PST 24
Peak memory 250412 kb
Host smart-cdccf6e4-76b9-48c0-8fe8-97c4bc41a376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189560813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2189560813
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.529021485
Short name T681
Test name
Test status
Simulation time 21897388807 ps
CPU time 66.23 seconds
Started Feb 21 02:26:07 PM PST 24
Finished Feb 21 02:27:13 PM PST 24
Peak memory 234132 kb
Host smart-a9925f82-cc19-45ad-a259-3ac0a6fe2537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529021485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.529021485
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1659462443
Short name T279
Test name
Test status
Simulation time 26142104400 ps
CPU time 34.06 seconds
Started Feb 21 02:26:10 PM PST 24
Finished Feb 21 02:26:44 PM PST 24
Peak memory 247172 kb
Host smart-eda33fa6-49fc-4a2e-bc3b-a30c8be06feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659462443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1659462443
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.328756373
Short name T623
Test name
Test status
Simulation time 629972274 ps
CPU time 5.94 seconds
Started Feb 21 02:26:10 PM PST 24
Finished Feb 21 02:26:16 PM PST 24
Peak memory 237524 kb
Host smart-6e321bfd-5db5-43f4-8075-6f7db78d5d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328756373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.328756373
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4038015752
Short name T965
Test name
Test status
Simulation time 42176506499 ps
CPU time 44.46 seconds
Started Feb 21 02:26:11 PM PST 24
Finished Feb 21 02:26:56 PM PST 24
Peak memory 218236 kb
Host smart-92df1f1b-0667-4b84-9001-14f6b4a40fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038015752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4038015752
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2454092997
Short name T616
Test name
Test status
Simulation time 161515172145 ps
CPU time 20.04 seconds
Started Feb 21 02:26:11 PM PST 24
Finished Feb 21 02:26:32 PM PST 24
Peak memory 220768 kb
Host smart-3efd0730-d0c5-4c05-8bf8-e9de9248b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454092997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2454092997
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.90759824
Short name T305
Test name
Test status
Simulation time 7170633611 ps
CPU time 5.9 seconds
Started Feb 21 02:26:11 PM PST 24
Finished Feb 21 02:26:17 PM PST 24
Peak memory 216500 kb
Host smart-001ed391-9aa3-42f8-99a9-53c72aab9a24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90759824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.90759824
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.865549674
Short name T910
Test name
Test status
Simulation time 10138686150 ps
CPU time 34.92 seconds
Started Feb 21 02:26:12 PM PST 24
Finished Feb 21 02:26:47 PM PST 24
Peak memory 216496 kb
Host smart-9435df5f-c948-41b2-9c7f-04b5522b53e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865549674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.865549674
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2151549989
Short name T404
Test name
Test status
Simulation time 884836082 ps
CPU time 6.13 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:14 PM PST 24
Peak memory 216516 kb
Host smart-7d3e8662-f75a-4083-8471-2fbb66108df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151549989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2151549989
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.521555608
Short name T605
Test name
Test status
Simulation time 77594930 ps
CPU time 1.25 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:09 PM PST 24
Peak memory 208164 kb
Host smart-163140fd-addf-411f-a82f-e3dcfe433237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521555608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.521555608
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3513381960
Short name T756
Test name
Test status
Simulation time 115688369 ps
CPU time 1.06 seconds
Started Feb 21 02:26:09 PM PST 24
Finished Feb 21 02:26:10 PM PST 24
Peak memory 206520 kb
Host smart-6bee5d7e-80f2-44dc-ac25-1522bf934184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513381960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3513381960
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.756715621
Short name T228
Test name
Test status
Simulation time 2353339228 ps
CPU time 15.54 seconds
Started Feb 21 02:26:10 PM PST 24
Finished Feb 21 02:26:26 PM PST 24
Peak memory 233916 kb
Host smart-89592473-cca6-44ad-b443-e94a467f6882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756715621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.756715621
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.957928150
Short name T631
Test name
Test status
Simulation time 13493759 ps
CPU time 0.7 seconds
Started Feb 21 02:26:19 PM PST 24
Finished Feb 21 02:26:20 PM PST 24
Peak memory 204972 kb
Host smart-e9a6d297-9a65-44dd-8943-cb132041a6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957928150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.957928150
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2485783069
Short name T462
Test name
Test status
Simulation time 209493899 ps
CPU time 3.97 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:26:18 PM PST 24
Peak memory 235788 kb
Host smart-8ee8af18-06d9-4abc-86bc-7bfe8157b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485783069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2485783069
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1942998223
Short name T304
Test name
Test status
Simulation time 45703303 ps
CPU time 0.75 seconds
Started Feb 21 02:26:08 PM PST 24
Finished Feb 21 02:26:09 PM PST 24
Peak memory 205148 kb
Host smart-0b99801f-0ac5-4e5e-9754-e24268967537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942998223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1942998223
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.876582040
Short name T599
Test name
Test status
Simulation time 1159796128 ps
CPU time 6.11 seconds
Started Feb 21 02:26:21 PM PST 24
Finished Feb 21 02:26:28 PM PST 24
Peak memory 233856 kb
Host smart-69d6a1a3-d477-4a52-a9be-dc92640633db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876582040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.876582040
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4178679183
Short name T675
Test name
Test status
Simulation time 15064563464 ps
CPU time 55.14 seconds
Started Feb 21 02:26:13 PM PST 24
Finished Feb 21 02:27:09 PM PST 24
Peak memory 237176 kb
Host smart-58a17b6a-4b1e-439b-8382-ce7ac40e6c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178679183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4178679183
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.670383994
Short name T692
Test name
Test status
Simulation time 588661759028 ps
CPU time 358.23 seconds
Started Feb 21 02:26:17 PM PST 24
Finished Feb 21 02:32:16 PM PST 24
Peak memory 267652 kb
Host smart-411bdba4-1f41-46d4-9766-737fa71aa351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670383994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.670383994
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2393057339
Short name T274
Test name
Test status
Simulation time 7431753217 ps
CPU time 26.96 seconds
Started Feb 21 02:26:12 PM PST 24
Finished Feb 21 02:26:39 PM PST 24
Peak memory 249700 kb
Host smart-0ab061b8-9d7b-410e-ba0d-0216ee8209ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393057339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2393057339
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2982560262
Short name T403
Test name
Test status
Simulation time 1598790095 ps
CPU time 7.31 seconds
Started Feb 21 02:26:19 PM PST 24
Finished Feb 21 02:26:26 PM PST 24
Peak memory 217612 kb
Host smart-8e4d8a32-57cc-477f-a886-1ea647bb3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982560262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2982560262
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1499164696
Short name T189
Test name
Test status
Simulation time 493523721 ps
CPU time 6.18 seconds
Started Feb 21 02:26:17 PM PST 24
Finished Feb 21 02:26:23 PM PST 24
Peak memory 238048 kb
Host smart-35b7ca99-802c-4242-a44a-5f7ebdf8db6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499164696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1499164696
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3603950775
Short name T421
Test name
Test status
Simulation time 454885360 ps
CPU time 2.64 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:26:17 PM PST 24
Peak memory 218488 kb
Host smart-591d1997-e83a-46a7-84b3-bd955cffb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603950775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3603950775
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.215894702
Short name T533
Test name
Test status
Simulation time 404136442 ps
CPU time 6.62 seconds
Started Feb 21 02:26:17 PM PST 24
Finished Feb 21 02:26:24 PM PST 24
Peak memory 225872 kb
Host smart-d5bcae03-0134-406d-8bff-629fc657a5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215894702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.215894702
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3931414016
Short name T725
Test name
Test status
Simulation time 1070068484 ps
CPU time 4.43 seconds
Started Feb 21 02:26:17 PM PST 24
Finished Feb 21 02:26:22 PM PST 24
Peak memory 219072 kb
Host smart-20fdb7f6-6268-426e-b85e-18e7a705e01d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3931414016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3931414016
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3832077106
Short name T41
Test name
Test status
Simulation time 6168070691 ps
CPU time 32.95 seconds
Started Feb 21 02:26:23 PM PST 24
Finished Feb 21 02:26:56 PM PST 24
Peak memory 224764 kb
Host smart-b7041066-921d-4755-a763-8120c7ad82a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832077106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3832077106
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2760140968
Short name T610
Test name
Test status
Simulation time 19296370064 ps
CPU time 79.64 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:27:34 PM PST 24
Peak memory 216484 kb
Host smart-752ca140-67dc-4c97-ac32-baf464561c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760140968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2760140968
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2453391190
Short name T948
Test name
Test status
Simulation time 12824108463 ps
CPU time 11.92 seconds
Started Feb 21 02:26:17 PM PST 24
Finished Feb 21 02:26:29 PM PST 24
Peak memory 216504 kb
Host smart-91bc97d2-0b01-4b3f-8cd6-9a963778f491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453391190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2453391190
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4184531217
Short name T450
Test name
Test status
Simulation time 526186447 ps
CPU time 10.02 seconds
Started Feb 21 02:26:13 PM PST 24
Finished Feb 21 02:26:24 PM PST 24
Peak memory 216420 kb
Host smart-1d8578d2-fef0-4022-9bfb-f70b784d5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184531217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4184531217
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.448218531
Short name T300
Test name
Test status
Simulation time 33997338 ps
CPU time 0.88 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:26:15 PM PST 24
Peak memory 206528 kb
Host smart-2ca4189e-ab3e-4926-b6c5-8ff61c006f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448218531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.448218531
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3855354855
Short name T828
Test name
Test status
Simulation time 2869074299 ps
CPU time 5.96 seconds
Started Feb 21 02:26:14 PM PST 24
Finished Feb 21 02:26:20 PM PST 24
Peak memory 233684 kb
Host smart-c46762fc-ce85-4c7b-a4cc-f57223905ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855354855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3855354855
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2386577177
Short name T612
Test name
Test status
Simulation time 37446193 ps
CPU time 0.71 seconds
Started Feb 21 02:26:15 PM PST 24
Finished Feb 21 02:26:16 PM PST 24
Peak memory 205300 kb
Host smart-2499c6e9-dcda-4a6d-95a0-455bb55727c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386577177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2386577177
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3550936588
Short name T555
Test name
Test status
Simulation time 12081911703 ps
CPU time 5.25 seconds
Started Feb 21 02:26:17 PM PST 24
Finished Feb 21 02:26:22 PM PST 24
Peak memory 224660 kb
Host smart-83c6b63b-a438-4c91-be4b-27bb0ac94192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550936588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3550936588
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2867097630
Short name T492
Test name
Test status
Simulation time 14436543 ps
CPU time 0.75 seconds
Started Feb 21 02:26:22 PM PST 24
Finished Feb 21 02:26:23 PM PST 24
Peak memory 205468 kb
Host smart-7ec09d9c-5600-4996-80d1-6385928fd7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867097630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2867097630
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1584837011
Short name T638
Test name
Test status
Simulation time 28747191491 ps
CPU time 74.82 seconds
Started Feb 21 02:26:22 PM PST 24
Finished Feb 21 02:27:37 PM PST 24
Peak memory 255872 kb
Host smart-1ea2d0ea-de27-4e41-83f8-156df788106c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584837011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1584837011
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2142916451
Short name T258
Test name
Test status
Simulation time 114594969447 ps
CPU time 228.29 seconds
Started Feb 21 02:26:22 PM PST 24
Finished Feb 21 02:30:10 PM PST 24
Peak memory 251512 kb
Host smart-77941129-0b15-4cdd-b293-628930da0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142916451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2142916451
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3534097376
Short name T205
Test name
Test status
Simulation time 3332411233 ps
CPU time 72.74 seconds
Started Feb 21 02:26:18 PM PST 24
Finished Feb 21 02:27:31 PM PST 24
Peak memory 252236 kb
Host smart-41af03c5-bf87-47b7-84c4-645468afb51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534097376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3534097376
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_intercept.7630644
Short name T83
Test name
Test status
Simulation time 3717061040 ps
CPU time 11.12 seconds
Started Feb 21 02:26:12 PM PST 24
Finished Feb 21 02:26:24 PM PST 24
Peak memory 224668 kb
Host smart-4d4bd5c8-a858-437c-b33a-1c275b2fdb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7630644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.7630644
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4129489467
Short name T821
Test name
Test status
Simulation time 3270039759 ps
CPU time 11.63 seconds
Started Feb 21 02:26:21 PM PST 24
Finished Feb 21 02:26:33 PM PST 24
Peak memory 224596 kb
Host smart-3b29e4e1-6055-4aa1-ba2b-bf199101ce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129489467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4129489467
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1070992533
Short name T474
Test name
Test status
Simulation time 13071926295 ps
CPU time 34.44 seconds
Started Feb 21 02:26:17 PM PST 24
Finished Feb 21 02:26:51 PM PST 24
Peak memory 236892 kb
Host smart-c40b0479-5515-4434-942d-2c5d6d036545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070992533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1070992533
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4289467601
Short name T34
Test name
Test status
Simulation time 275353313 ps
CPU time 2.67 seconds
Started Feb 21 02:26:15 PM PST 24
Finished Feb 21 02:26:18 PM PST 24
Peak memory 233540 kb
Host smart-7805a07c-b453-423a-87fc-61af75a49afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289467601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4289467601
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3453715391
Short name T464
Test name
Test status
Simulation time 1279871655 ps
CPU time 4.88 seconds
Started Feb 21 02:26:22 PM PST 24
Finished Feb 21 02:26:27 PM PST 24
Peak memory 221564 kb
Host smart-c9ff66b0-5d94-4c6e-8cc2-0fef26ce9404
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3453715391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3453715391
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.50081485
Short name T884
Test name
Test status
Simulation time 774954358 ps
CPU time 13.81 seconds
Started Feb 21 02:26:22 PM PST 24
Finished Feb 21 02:26:36 PM PST 24
Peak memory 216444 kb
Host smart-73f3d3b9-6c53-4f0b-9961-e74e34051241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50081485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.50081485
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.541551357
Short name T830
Test name
Test status
Simulation time 1787310083 ps
CPU time 7.87 seconds
Started Feb 21 02:26:19 PM PST 24
Finished Feb 21 02:26:27 PM PST 24
Peak memory 216412 kb
Host smart-939423b0-b464-43ac-9905-f9cb1b900c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541551357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.541551357
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1297228184
Short name T677
Test name
Test status
Simulation time 1329840995 ps
CPU time 3.18 seconds
Started Feb 21 02:26:13 PM PST 24
Finished Feb 21 02:26:17 PM PST 24
Peak memory 216644 kb
Host smart-ae64fc97-5602-40a5-b2ec-76e170b29c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297228184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1297228184
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1388012328
Short name T708
Test name
Test status
Simulation time 50859386 ps
CPU time 0.71 seconds
Started Feb 21 02:26:18 PM PST 24
Finished Feb 21 02:26:19 PM PST 24
Peak memory 205452 kb
Host smart-9cf19501-3336-42fe-896c-60b40ff87f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388012328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1388012328
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3430576719
Short name T787
Test name
Test status
Simulation time 50625961538 ps
CPU time 16.04 seconds
Started Feb 21 02:26:23 PM PST 24
Finished Feb 21 02:26:39 PM PST 24
Peak memory 217512 kb
Host smart-6a805a72-e8a8-4cf5-a467-cb63e1afc8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430576719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3430576719
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1814554925
Short name T689
Test name
Test status
Simulation time 14459561 ps
CPU time 0.76 seconds
Started Feb 21 02:26:27 PM PST 24
Finished Feb 21 02:26:28 PM PST 24
Peak memory 204980 kb
Host smart-768fd78a-67d3-49cf-924d-10994f01bb40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814554925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1814554925
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2334870024
Short name T407
Test name
Test status
Simulation time 5529461677 ps
CPU time 6.75 seconds
Started Feb 21 02:26:27 PM PST 24
Finished Feb 21 02:26:34 PM PST 24
Peak memory 233884 kb
Host smart-e7ade0c6-0bcd-413a-86fc-57fec868b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334870024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2334870024
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2267856279
Short name T294
Test name
Test status
Simulation time 72697252 ps
CPU time 0.78 seconds
Started Feb 21 02:26:22 PM PST 24
Finished Feb 21 02:26:23 PM PST 24
Peak memory 206168 kb
Host smart-b221ae4a-2dec-49f7-8868-7a2ddd2ab35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267856279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2267856279
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1686469294
Short name T153
Test name
Test status
Simulation time 34066141293 ps
CPU time 86.03 seconds
Started Feb 21 02:26:24 PM PST 24
Finished Feb 21 02:27:50 PM PST 24
Peak memory 240684 kb
Host smart-206ed9d8-ef71-485f-bc8f-b633bdb6741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686469294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1686469294
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3482974973
Short name T349
Test name
Test status
Simulation time 2890729094 ps
CPU time 48.97 seconds
Started Feb 21 02:26:26 PM PST 24
Finished Feb 21 02:27:16 PM PST 24
Peak memory 256576 kb
Host smart-6ca1185d-e1bb-43cd-a851-04eddae5444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482974973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3482974973
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1008531291
Short name T466
Test name
Test status
Simulation time 23514252212 ps
CPU time 21.87 seconds
Started Feb 21 02:26:25 PM PST 24
Finished Feb 21 02:26:48 PM PST 24
Peak memory 240932 kb
Host smart-6de50173-cb85-4a38-a656-f40f76d75a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008531291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1008531291
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1866643406
Short name T721
Test name
Test status
Simulation time 110612351 ps
CPU time 2.54 seconds
Started Feb 21 02:26:23 PM PST 24
Finished Feb 21 02:26:26 PM PST 24
Peak memory 224484 kb
Host smart-a12d2f22-2052-464c-bb76-8220e88e23e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866643406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1866643406
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4059992750
Short name T378
Test name
Test status
Simulation time 89137185332 ps
CPU time 21.9 seconds
Started Feb 21 02:26:23 PM PST 24
Finished Feb 21 02:26:45 PM PST 24
Peak memory 230392 kb
Host smart-4bae7253-005e-4914-9684-5df496d08c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059992750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4059992750
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1872040684
Short name T516
Test name
Test status
Simulation time 1388127387 ps
CPU time 7.76 seconds
Started Feb 21 02:26:30 PM PST 24
Finished Feb 21 02:26:38 PM PST 24
Peak memory 235588 kb
Host smart-1a286700-8e8b-45a0-9e45-bd4bfc858468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872040684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1872040684
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1211919419
Short name T609
Test name
Test status
Simulation time 379135693 ps
CPU time 2.79 seconds
Started Feb 21 02:26:29 PM PST 24
Finished Feb 21 02:26:32 PM PST 24
Peak memory 216980 kb
Host smart-45189a92-e616-477d-ad92-4da0b5f86926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211919419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1211919419
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.553056044
Short name T411
Test name
Test status
Simulation time 325769006 ps
CPU time 3.84 seconds
Started Feb 21 02:26:25 PM PST 24
Finished Feb 21 02:26:29 PM PST 24
Peak memory 216624 kb
Host smart-1756262c-b133-4936-bbd5-d7d9c6e290f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=553056044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.553056044
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3974075353
Short name T257
Test name
Test status
Simulation time 544965700937 ps
CPU time 721 seconds
Started Feb 21 02:26:26 PM PST 24
Finished Feb 21 02:38:27 PM PST 24
Peak memory 273952 kb
Host smart-af7c1bb1-baf9-4420-9dd5-9fc64d5404a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974075353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3974075353
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.493930543
Short name T520
Test name
Test status
Simulation time 24920791448 ps
CPU time 95.23 seconds
Started Feb 21 02:26:28 PM PST 24
Finished Feb 21 02:28:04 PM PST 24
Peak memory 216500 kb
Host smart-41919026-72be-47a7-bb18-ea34c90263a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493930543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.493930543
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2196880420
Short name T399
Test name
Test status
Simulation time 929161386 ps
CPU time 6.42 seconds
Started Feb 21 02:26:22 PM PST 24
Finished Feb 21 02:26:29 PM PST 24
Peak memory 216440 kb
Host smart-dfe280f0-2e77-46e9-8516-a62c2c30c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196880420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2196880420
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3789812868
Short name T979
Test name
Test status
Simulation time 14273272 ps
CPU time 0.73 seconds
Started Feb 21 02:26:26 PM PST 24
Finished Feb 21 02:26:27 PM PST 24
Peak memory 205488 kb
Host smart-ed78315a-6723-4ffd-860f-dc20823ccefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789812868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3789812868
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1833128263
Short name T479
Test name
Test status
Simulation time 258976137 ps
CPU time 1.16 seconds
Started Feb 21 02:26:29 PM PST 24
Finished Feb 21 02:26:31 PM PST 24
Peak memory 206496 kb
Host smart-0440b074-8e00-4eb6-9b9f-897b673b52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833128263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1833128263
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2688938088
Short name T166
Test name
Test status
Simulation time 4916442235 ps
CPU time 6.9 seconds
Started Feb 21 02:26:23 PM PST 24
Finished Feb 21 02:26:30 PM PST 24
Peak memory 233304 kb
Host smart-fd0cf870-ef74-441b-ace6-92880d648c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688938088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2688938088
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4213137725
Short name T440
Test name
Test status
Simulation time 14729152 ps
CPU time 0.75 seconds
Started Feb 21 02:26:42 PM PST 24
Finished Feb 21 02:26:44 PM PST 24
Peak memory 204380 kb
Host smart-126bfb9b-0f0e-478b-99e1-97194d10f031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213137725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4213137725
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3305153013
Short name T297
Test name
Test status
Simulation time 737320178 ps
CPU time 4.53 seconds
Started Feb 21 02:26:42 PM PST 24
Finished Feb 21 02:26:47 PM PST 24
Peak memory 234872 kb
Host smart-205ac1cb-08c1-4560-9334-07c23b58212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305153013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3305153013
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4219202055
Short name T480
Test name
Test status
Simulation time 76416927 ps
CPU time 0.85 seconds
Started Feb 21 02:26:24 PM PST 24
Finished Feb 21 02:26:25 PM PST 24
Peak memory 206204 kb
Host smart-afb2d983-b4f4-4243-92f4-9dd147f75089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219202055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4219202055
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3277353152
Short name T381
Test name
Test status
Simulation time 26686402501 ps
CPU time 105.74 seconds
Started Feb 21 02:26:45 PM PST 24
Finished Feb 21 02:28:31 PM PST 24
Peak memory 253236 kb
Host smart-b121b53a-f56f-410f-9b6d-6911332a3cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277353152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3277353152
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1201861552
Short name T874
Test name
Test status
Simulation time 213316181958 ps
CPU time 412.6 seconds
Started Feb 21 02:26:42 PM PST 24
Finished Feb 21 02:33:35 PM PST 24
Peak memory 250552 kb
Host smart-ce2adee1-6259-490e-95e9-9d73cb369713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201861552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1201861552
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2423555291
Short name T637
Test name
Test status
Simulation time 11315971318 ps
CPU time 42.19 seconds
Started Feb 21 02:26:44 PM PST 24
Finished Feb 21 02:27:27 PM PST 24
Peak memory 253376 kb
Host smart-b3349e9e-88a7-48d6-9695-deed2a0e8f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423555291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2423555291
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.84078990
Short name T765
Test name
Test status
Simulation time 8881418461 ps
CPU time 44.41 seconds
Started Feb 21 02:26:44 PM PST 24
Finished Feb 21 02:27:29 PM PST 24
Peak memory 249248 kb
Host smart-58cfffac-0427-4834-9327-923c68534cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84078990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.84078990
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.625123518
Short name T798
Test name
Test status
Simulation time 714585793 ps
CPU time 4.56 seconds
Started Feb 21 02:26:40 PM PST 24
Finished Feb 21 02:26:45 PM PST 24
Peak memory 224620 kb
Host smart-9b01fbd0-c2f2-4778-9fa9-e2c9c6fd723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625123518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.625123518
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2449363239
Short name T131
Test name
Test status
Simulation time 114381172 ps
CPU time 4.01 seconds
Started Feb 21 02:26:42 PM PST 24
Finished Feb 21 02:26:47 PM PST 24
Peak memory 233692 kb
Host smart-ebfa1fa1-16ea-4eb7-a384-db055543006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449363239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2449363239
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.96908422
Short name T208
Test name
Test status
Simulation time 7561332452 ps
CPU time 25.66 seconds
Started Feb 21 02:26:45 PM PST 24
Finished Feb 21 02:27:11 PM PST 24
Peak memory 238036 kb
Host smart-3c2e6f69-b20b-40ea-91ab-dfb8d96c82ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96908422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.96908422
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1757371697
Short name T216
Test name
Test status
Simulation time 909936293 ps
CPU time 3.46 seconds
Started Feb 21 02:26:42 PM PST 24
Finished Feb 21 02:26:46 PM PST 24
Peak memory 216652 kb
Host smart-a7d63ccd-c801-4c88-8211-be84311502d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757371697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1757371697
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2585449556
Short name T959
Test name
Test status
Simulation time 6112710109 ps
CPU time 5.78 seconds
Started Feb 21 02:26:55 PM PST 24
Finished Feb 21 02:27:01 PM PST 24
Peak memory 216780 kb
Host smart-1829479e-74ca-4f02-80d1-fdb916b94b8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2585449556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2585449556
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.857941984
Short name T718
Test name
Test status
Simulation time 145894648257 ps
CPU time 359.47 seconds
Started Feb 21 02:26:41 PM PST 24
Finished Feb 21 02:32:42 PM PST 24
Peak memory 250348 kb
Host smart-fde55830-ee69-4b46-9c2c-e96b41f683fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857941984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.857941984
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4042170532
Short name T372
Test name
Test status
Simulation time 2037379609 ps
CPU time 26.29 seconds
Started Feb 21 02:26:24 PM PST 24
Finished Feb 21 02:26:50 PM PST 24
Peak memory 216456 kb
Host smart-711cdbdc-0c4f-455a-aafb-c3d7bced356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042170532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4042170532
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.836616508
Short name T845
Test name
Test status
Simulation time 514423555 ps
CPU time 4 seconds
Started Feb 21 02:26:27 PM PST 24
Finished Feb 21 02:26:32 PM PST 24
Peak memory 208192 kb
Host smart-0173345b-bf60-4635-95b3-1d78313b2d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836616508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.836616508
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.894354819
Short name T588
Test name
Test status
Simulation time 244374565 ps
CPU time 1.33 seconds
Started Feb 21 02:26:48 PM PST 24
Finished Feb 21 02:26:50 PM PST 24
Peak memory 207720 kb
Host smart-21f2182e-8249-4e2d-b883-c35e7468a479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894354819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.894354819
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1976006236
Short name T424
Test name
Test status
Simulation time 117091124 ps
CPU time 1.07 seconds
Started Feb 21 02:26:30 PM PST 24
Finished Feb 21 02:26:32 PM PST 24
Peak memory 205492 kb
Host smart-033a9a11-0632-47bb-9ded-4ba975f2fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976006236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1976006236
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3517349462
Short name T980
Test name
Test status
Simulation time 5758917844 ps
CPU time 10.39 seconds
Started Feb 21 02:26:42 PM PST 24
Finished Feb 21 02:26:53 PM PST 24
Peak memory 235316 kb
Host smart-e894777c-c902-4a2b-8750-a2591e13682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517349462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3517349462
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1862170042
Short name T510
Test name
Test status
Simulation time 196834323 ps
CPU time 0.78 seconds
Started Feb 21 02:26:51 PM PST 24
Finished Feb 21 02:26:53 PM PST 24
Peak memory 204976 kb
Host smart-e10d9c0f-ce8f-41e6-82de-11c96560ca96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862170042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1862170042
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3191440213
Short name T224
Test name
Test status
Simulation time 450714103 ps
CPU time 2.3 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:26:56 PM PST 24
Peak memory 224508 kb
Host smart-d10edb30-cd43-48d1-a78a-da7572d3ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191440213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3191440213
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1290788739
Short name T319
Test name
Test status
Simulation time 37531483 ps
CPU time 0.8 seconds
Started Feb 21 02:26:44 PM PST 24
Finished Feb 21 02:26:46 PM PST 24
Peak memory 206512 kb
Host smart-e69d600a-8196-4ede-891d-98a3333364cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290788739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1290788739
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3727601842
Short name T950
Test name
Test status
Simulation time 13870364912 ps
CPU time 58.34 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:27:51 PM PST 24
Peak memory 266424 kb
Host smart-79b0e9e7-1086-418f-bdc6-4d55bccdbc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727601842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3727601842
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3924370271
Short name T191
Test name
Test status
Simulation time 14068839403 ps
CPU time 22.7 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:27:15 PM PST 24
Peak memory 250676 kb
Host smart-ee38e3a3-314e-449f-bd27-eb4bfea24228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924370271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3924370271
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3823981206
Short name T736
Test name
Test status
Simulation time 7151165612 ps
CPU time 61.41 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:27:55 PM PST 24
Peak memory 237956 kb
Host smart-bcd21c48-7360-4007-8a20-944b48868102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823981206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3823981206
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2174615404
Short name T391
Test name
Test status
Simulation time 36547033141 ps
CPU time 18.1 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:27:12 PM PST 24
Peak memory 236212 kb
Host smart-31248870-9744-486c-ba79-f6d9a139ba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174615404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2174615404
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.376255837
Short name T587
Test name
Test status
Simulation time 112836946 ps
CPU time 3.18 seconds
Started Feb 21 02:26:42 PM PST 24
Finished Feb 21 02:26:47 PM PST 24
Peak memory 235316 kb
Host smart-06c85c56-a5b4-4df2-98cc-3986a9514490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376255837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.376255837
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4053885797
Short name T220
Test name
Test status
Simulation time 36556112065 ps
CPU time 27.39 seconds
Started Feb 21 02:26:51 PM PST 24
Finished Feb 21 02:27:20 PM PST 24
Peak memory 237236 kb
Host smart-9afaa499-5068-47dc-a002-43203d3e172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053885797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4053885797
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.93423944
Short name T932
Test name
Test status
Simulation time 43226424746 ps
CPU time 20.98 seconds
Started Feb 21 02:26:42 PM PST 24
Finished Feb 21 02:27:04 PM PST 24
Peak memory 240048 kb
Host smart-8b71a985-c9d0-4bcc-88de-f2a312b61c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93423944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.93423944
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1081815922
Short name T535
Test name
Test status
Simulation time 1351600973 ps
CPU time 5.19 seconds
Started Feb 21 02:26:40 PM PST 24
Finished Feb 21 02:26:46 PM PST 24
Peak memory 216468 kb
Host smart-f5b08e01-9fed-4e63-8c25-5ea653ba2be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081815922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1081815922
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2046434774
Short name T903
Test name
Test status
Simulation time 1065170751 ps
CPU time 5.86 seconds
Started Feb 21 02:26:51 PM PST 24
Finished Feb 21 02:26:58 PM PST 24
Peak memory 218864 kb
Host smart-56ba20cf-f8b0-4acb-ae2b-7c16a0489a22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2046434774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2046434774
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4208733916
Short name T145
Test name
Test status
Simulation time 52600310868 ps
CPU time 203.21 seconds
Started Feb 21 02:26:50 PM PST 24
Finished Feb 21 02:30:14 PM PST 24
Peak memory 239408 kb
Host smart-d901db7b-6cd1-4756-be47-0db624d5408c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208733916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4208733916
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1320524735
Short name T356
Test name
Test status
Simulation time 23097628702 ps
CPU time 123.15 seconds
Started Feb 21 02:26:41 PM PST 24
Finished Feb 21 02:28:45 PM PST 24
Peak memory 216480 kb
Host smart-e87e2579-cf83-4bfc-8295-868afca560b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320524735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1320524735
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1893039883
Short name T788
Test name
Test status
Simulation time 4472747896 ps
CPU time 12.3 seconds
Started Feb 21 02:26:41 PM PST 24
Finished Feb 21 02:26:54 PM PST 24
Peak memory 216524 kb
Host smart-47b2d451-8c0f-4796-a87c-4264ab1ae39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893039883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1893039883
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3380734358
Short name T791
Test name
Test status
Simulation time 22444910 ps
CPU time 1.25 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:26:55 PM PST 24
Peak memory 207968 kb
Host smart-286c78e2-8430-4d1d-8175-0357bb5a4603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380734358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3380734358
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1972736073
Short name T320
Test name
Test status
Simulation time 69108425 ps
CPU time 0.8 seconds
Started Feb 21 02:26:49 PM PST 24
Finished Feb 21 02:26:51 PM PST 24
Peak memory 205500 kb
Host smart-2ef85a8a-0bf4-4148-82f4-8841bdfb4ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972736073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1972736073
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3237697291
Short name T194
Test name
Test status
Simulation time 423580181 ps
CPU time 6.95 seconds
Started Feb 21 02:26:50 PM PST 24
Finished Feb 21 02:26:58 PM PST 24
Peak memory 233016 kb
Host smart-5a979faf-b1a7-4e76-a9ff-10e458533f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237697291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3237697291
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2122952059
Short name T490
Test name
Test status
Simulation time 21816472 ps
CPU time 0.73 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:26:54 PM PST 24
Peak memory 204408 kb
Host smart-fa7e73ae-7d86-4f38-94af-a8bafd9acda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122952059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2122952059
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1216251093
Short name T740
Test name
Test status
Simulation time 462208730 ps
CPU time 2.36 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:26:56 PM PST 24
Peak memory 224620 kb
Host smart-bd4c1548-1221-45cc-b0bb-f30bcba4778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216251093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1216251093
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3064357163
Short name T582
Test name
Test status
Simulation time 20892575 ps
CPU time 0.77 seconds
Started Feb 21 02:26:50 PM PST 24
Finished Feb 21 02:26:52 PM PST 24
Peak memory 206168 kb
Host smart-1b7b58d8-390e-43ba-a353-43cbe9f9eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064357163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3064357163
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3863590257
Short name T540
Test name
Test status
Simulation time 35427935316 ps
CPU time 113 seconds
Started Feb 21 02:26:55 PM PST 24
Finished Feb 21 02:28:48 PM PST 24
Peak memory 249280 kb
Host smart-bb616fa7-d162-408f-bdba-cabdd7f408dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863590257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3863590257
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3401370374
Short name T607
Test name
Test status
Simulation time 119612252615 ps
CPU time 198.17 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:30:11 PM PST 24
Peak memory 235464 kb
Host smart-a3ba1e93-505e-4118-8ee4-e5bb1fe283a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401370374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3401370374
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.272965765
Short name T597
Test name
Test status
Simulation time 229819521162 ps
CPU time 489.86 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:35:03 PM PST 24
Peak memory 253996 kb
Host smart-1fb7c266-a3da-4215-a5a6-09172f9570b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272965765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.272965765
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1092603759
Short name T518
Test name
Test status
Simulation time 14236986591 ps
CPU time 10.78 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:27:05 PM PST 24
Peak memory 247680 kb
Host smart-080f1c2b-9f6c-459b-a26d-4154a6432416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092603759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1092603759
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3136996867
Short name T471
Test name
Test status
Simulation time 2601917267 ps
CPU time 4.81 seconds
Started Feb 21 02:26:51 PM PST 24
Finished Feb 21 02:26:57 PM PST 24
Peak memory 219140 kb
Host smart-6ded1065-6de0-4f5f-a1a0-bd7722201004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136996867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3136996867
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.702831548
Short name T602
Test name
Test status
Simulation time 1733158723 ps
CPU time 10.95 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:27:04 PM PST 24
Peak memory 239640 kb
Host smart-e9de9415-b7e5-4b7d-8804-255975a36f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702831548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.702831548
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4250713576
Short name T687
Test name
Test status
Simulation time 497220220 ps
CPU time 4.2 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:26:57 PM PST 24
Peak memory 216960 kb
Host smart-3a46167a-5e31-4e24-9841-7af1e85d10eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250713576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4250713576
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1540683842
Short name T182
Test name
Test status
Simulation time 2990457097 ps
CPU time 15.99 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:27:08 PM PST 24
Peak memory 227128 kb
Host smart-c03a379e-62d1-452a-9fe2-5e982ae5a336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540683842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1540683842
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.542188941
Short name T591
Test name
Test status
Simulation time 3177176767 ps
CPU time 6.74 seconds
Started Feb 21 02:27:00 PM PST 24
Finished Feb 21 02:27:07 PM PST 24
Peak memory 222136 kb
Host smart-1e37b417-c311-480c-9f95-cb9c45626842
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=542188941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.542188941
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2527866517
Short name T767
Test name
Test status
Simulation time 3734771735 ps
CPU time 53.07 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:27:47 PM PST 24
Peak memory 224732 kb
Host smart-7bc4ada0-e174-4d3b-adc3-0a8b9567cfe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527866517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2527866517
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.552863036
Short name T459
Test name
Test status
Simulation time 59160160268 ps
CPU time 100.34 seconds
Started Feb 21 02:26:49 PM PST 24
Finished Feb 21 02:28:30 PM PST 24
Peak memory 216492 kb
Host smart-1569d9b6-f8c9-4d2a-a39d-12eae4a00ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552863036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.552863036
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3210138984
Short name T621
Test name
Test status
Simulation time 193964279 ps
CPU time 1.36 seconds
Started Feb 21 02:26:51 PM PST 24
Finished Feb 21 02:26:53 PM PST 24
Peak memory 206816 kb
Host smart-c4d5a874-81f1-48a1-b6dd-12141dd13929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210138984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3210138984
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3094723429
Short name T359
Test name
Test status
Simulation time 202805174 ps
CPU time 1.61 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:26:55 PM PST 24
Peak memory 217660 kb
Host smart-d0a35470-bc20-49d5-85f0-cd45b7d02f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094723429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3094723429
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2517633014
Short name T312
Test name
Test status
Simulation time 118181966 ps
CPU time 0.8 seconds
Started Feb 21 02:26:49 PM PST 24
Finished Feb 21 02:26:50 PM PST 24
Peak memory 205472 kb
Host smart-aefa221e-8765-4e41-906c-a90f8e13e1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517633014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2517633014
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3744580602
Short name T367
Test name
Test status
Simulation time 1286870898 ps
CPU time 4.78 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:26:59 PM PST 24
Peak memory 224608 kb
Host smart-9cde7302-ea33-4fc1-a9c3-bec9337f9025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744580602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3744580602
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2626642541
Short name T737
Test name
Test status
Simulation time 24490548 ps
CPU time 0.69 seconds
Started Feb 21 02:26:55 PM PST 24
Finished Feb 21 02:26:56 PM PST 24
Peak memory 204424 kb
Host smart-29fa8962-8297-4ebb-bde3-6f67593fa20c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626642541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2626642541
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3740471019
Short name T790
Test name
Test status
Simulation time 7276854985 ps
CPU time 8.03 seconds
Started Feb 21 02:26:55 PM PST 24
Finished Feb 21 02:27:03 PM PST 24
Peak memory 232920 kb
Host smart-110ac39f-dfdf-4ed5-885d-5de91ad78e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740471019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3740471019
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.927927103
Short name T796
Test name
Test status
Simulation time 19882237 ps
CPU time 0.74 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:26:54 PM PST 24
Peak memory 205156 kb
Host smart-2ba530d9-7c5b-42e3-9ecf-af356e5b5718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927927103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.927927103
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1509210165
Short name T259
Test name
Test status
Simulation time 118592653627 ps
CPU time 276.56 seconds
Started Feb 21 02:26:57 PM PST 24
Finished Feb 21 02:31:34 PM PST 24
Peak memory 250800 kb
Host smart-c1ee850e-de64-4c67-9236-451c0507c1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509210165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1509210165
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3879039321
Short name T715
Test name
Test status
Simulation time 43525311640 ps
CPU time 125.49 seconds
Started Feb 21 02:26:57 PM PST 24
Finished Feb 21 02:29:03 PM PST 24
Peak memory 249380 kb
Host smart-36e8547e-d9b5-4e72-a658-18c8cc3992c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879039321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3879039321
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1937153056
Short name T157
Test name
Test status
Simulation time 13838027092 ps
CPU time 32.21 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:27:27 PM PST 24
Peak memory 238732 kb
Host smart-19ff0a99-1c55-4865-b86c-9b6e761fcdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937153056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1937153056
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.958857312
Short name T817
Test name
Test status
Simulation time 6022317568 ps
CPU time 8.08 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:27:02 PM PST 24
Peak memory 237796 kb
Host smart-8d26fc8c-12d0-4d9d-af19-e73f6d982a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958857312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.958857312
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3551911554
Short name T204
Test name
Test status
Simulation time 1608477353 ps
CPU time 8.14 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:27:02 PM PST 24
Peak memory 236384 kb
Host smart-adf37d65-f9ef-415d-b6a3-a3ece3ad7c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551911554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3551911554
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3706625985
Short name T639
Test name
Test status
Simulation time 42955717853 ps
CPU time 27.83 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:27:21 PM PST 24
Peak memory 233352 kb
Host smart-597abee2-cbaf-4369-a4e2-a08958575010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706625985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3706625985
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.297862439
Short name T827
Test name
Test status
Simulation time 938951519 ps
CPU time 6.07 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:26:59 PM PST 24
Peak memory 217648 kb
Host smart-090e6f75-c88b-4f13-b126-9fdaca1a7e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297862439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.297862439
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1097534289
Short name T674
Test name
Test status
Simulation time 539172879 ps
CPU time 4.93 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:26:59 PM PST 24
Peak memory 222608 kb
Host smart-020702e3-0733-4139-aeff-5ea5b10b89f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1097534289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1097534289
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2647205454
Short name T766
Test name
Test status
Simulation time 23658515137 ps
CPU time 188.55 seconds
Started Feb 21 02:27:01 PM PST 24
Finished Feb 21 02:30:10 PM PST 24
Peak memory 264852 kb
Host smart-32b3ebac-ec52-4761-9f07-69d385e9a059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647205454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2647205454
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4206189109
Short name T886
Test name
Test status
Simulation time 4095709940 ps
CPU time 31.9 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:27:25 PM PST 24
Peak memory 216476 kb
Host smart-2fc23a70-46ff-4973-a90d-06572866a423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206189109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4206189109
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4110642435
Short name T967
Test name
Test status
Simulation time 2375038766 ps
CPU time 1.89 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:26:56 PM PST 24
Peak memory 206932 kb
Host smart-db95a581-1219-4808-920a-a045aebb873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110642435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4110642435
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3427959596
Short name T589
Test name
Test status
Simulation time 1053918944 ps
CPU time 9.58 seconds
Started Feb 21 02:26:52 PM PST 24
Finished Feb 21 02:27:02 PM PST 24
Peak memory 216636 kb
Host smart-c9a85e7c-0dfc-4080-ac99-858addd6ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427959596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3427959596
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1864580834
Short name T405
Test name
Test status
Simulation time 60967910 ps
CPU time 0.87 seconds
Started Feb 21 02:26:53 PM PST 24
Finished Feb 21 02:26:55 PM PST 24
Peak memory 205512 kb
Host smart-6f1dfb02-4e2c-4b84-afe0-a5901c399a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864580834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1864580834
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1969300219
Short name T499
Test name
Test status
Simulation time 1935535228 ps
CPU time 8.74 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:27:03 PM PST 24
Peak memory 216636 kb
Host smart-d534fc1f-0aaf-4fba-b6b1-d36b6ce2b7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969300219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1969300219
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3419929384
Short name T843
Test name
Test status
Simulation time 30521002 ps
CPU time 0.73 seconds
Started Feb 21 02:22:26 PM PST 24
Finished Feb 21 02:22:27 PM PST 24
Peak memory 204444 kb
Host smart-4ce879aa-1e0c-42ec-a95f-d32e4f6c11ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419929384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
419929384
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3961601468
Short name T527
Test name
Test status
Simulation time 393403976 ps
CPU time 2.38 seconds
Started Feb 21 02:22:07 PM PST 24
Finished Feb 21 02:22:10 PM PST 24
Peak memory 217892 kb
Host smart-4644459a-7615-43d9-94d9-1a74b82b9db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961601468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3961601468
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4104826580
Short name T873
Test name
Test status
Simulation time 76010705 ps
CPU time 0.9 seconds
Started Feb 21 02:22:09 PM PST 24
Finished Feb 21 02:22:10 PM PST 24
Peak memory 206216 kb
Host smart-a5d7c5c8-8782-4c0a-a1b9-70335ff5a8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104826580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4104826580
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.943609164
Short name T234
Test name
Test status
Simulation time 3966148412 ps
CPU time 74.39 seconds
Started Feb 21 02:22:09 PM PST 24
Finished Feb 21 02:23:24 PM PST 24
Peak memory 257452 kb
Host smart-ac1a6f2a-098c-43e5-8efe-ea0bbb404585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943609164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.943609164
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1336272903
Short name T758
Test name
Test status
Simulation time 208319457478 ps
CPU time 592.62 seconds
Started Feb 21 02:22:25 PM PST 24
Finished Feb 21 02:32:18 PM PST 24
Peak memory 265780 kb
Host smart-757503fa-72f1-4b57-b4cd-8ab82ad915a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336272903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1336272903
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2093675320
Short name T58
Test name
Test status
Simulation time 3077520225 ps
CPU time 20.65 seconds
Started Feb 21 02:22:10 PM PST 24
Finished Feb 21 02:22:31 PM PST 24
Peak memory 249620 kb
Host smart-87b1c7ba-2f32-49b7-825f-f8ae635c6053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093675320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2093675320
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1036359510
Short name T786
Test name
Test status
Simulation time 241772987 ps
CPU time 4.44 seconds
Started Feb 21 02:22:09 PM PST 24
Finished Feb 21 02:22:14 PM PST 24
Peak memory 220256 kb
Host smart-058b649f-043b-46bd-91e0-8f8da91e3fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036359510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1036359510
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1149087800
Short name T433
Test name
Test status
Simulation time 11245654351 ps
CPU time 39.52 seconds
Started Feb 21 02:22:07 PM PST 24
Finished Feb 21 02:22:48 PM PST 24
Peak memory 249232 kb
Host smart-f2bf2160-5ffd-4e71-be33-1838305d910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149087800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1149087800
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.505823562
Short name T838
Test name
Test status
Simulation time 27311234 ps
CPU time 1.03 seconds
Started Feb 21 02:22:08 PM PST 24
Finished Feb 21 02:22:09 PM PST 24
Peak memory 216584 kb
Host smart-d45bdbbb-6153-4854-85b2-346a2346a1b8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505823562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.505823562
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.310884441
Short name T773
Test name
Test status
Simulation time 5441523589 ps
CPU time 19.24 seconds
Started Feb 21 02:22:07 PM PST 24
Finished Feb 21 02:22:27 PM PST 24
Peak memory 239380 kb
Host smart-38c3e39f-e82f-44ca-a4d7-c9c7f19833ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310884441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
310884441
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2825070019
Short name T553
Test name
Test status
Simulation time 145724735 ps
CPU time 2.6 seconds
Started Feb 21 02:22:10 PM PST 24
Finished Feb 21 02:22:13 PM PST 24
Peak memory 233324 kb
Host smart-9aab48fc-2c21-4df7-bc0c-6cd4bdd2195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825070019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2825070019
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2126772389
Short name T384
Test name
Test status
Simulation time 17538244 ps
CPU time 0.74 seconds
Started Feb 21 02:22:08 PM PST 24
Finished Feb 21 02:22:09 PM PST 24
Peak memory 216344 kb
Host smart-0c806e50-acc3-4f33-bc82-5673c6f08398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126772389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2126772389
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.367109974
Short name T831
Test name
Test status
Simulation time 4749449495 ps
CPU time 5.26 seconds
Started Feb 21 02:22:07 PM PST 24
Finished Feb 21 02:22:13 PM PST 24
Peak memory 218816 kb
Host smart-8cd060ea-1669-4804-a22d-a5a83ff4ba6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=367109974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.367109974
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1935937956
Short name T46
Test name
Test status
Simulation time 627679233 ps
CPU time 1.21 seconds
Started Feb 21 02:22:25 PM PST 24
Finished Feb 21 02:22:27 PM PST 24
Peak memory 234960 kb
Host smart-f9368a74-b6ee-4f66-8385-fd7a1c5d1b4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935937956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1935937956
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.833224491
Short name T248
Test name
Test status
Simulation time 97317487659 ps
CPU time 821.74 seconds
Started Feb 21 02:22:23 PM PST 24
Finished Feb 21 02:36:05 PM PST 24
Peak memory 270708 kb
Host smart-484ab4c1-322d-41f3-b80f-9b3c2a914cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833224491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.833224491
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.527755447
Short name T526
Test name
Test status
Simulation time 2683128951 ps
CPU time 21.9 seconds
Started Feb 21 02:22:07 PM PST 24
Finished Feb 21 02:22:30 PM PST 24
Peak memory 216556 kb
Host smart-2b98675f-a915-432f-b699-ddd3205b2d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527755447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.527755447
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1106353601
Short name T846
Test name
Test status
Simulation time 164449441 ps
CPU time 1.29 seconds
Started Feb 21 02:22:08 PM PST 24
Finished Feb 21 02:22:10 PM PST 24
Peak memory 206680 kb
Host smart-3109a9ea-ca72-46ed-bea0-131a0469cca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106353601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1106353601
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.524172097
Short name T794
Test name
Test status
Simulation time 101379430 ps
CPU time 0.93 seconds
Started Feb 21 02:22:07 PM PST 24
Finished Feb 21 02:22:09 PM PST 24
Peak memory 206720 kb
Host smart-389eb508-1caf-4b64-84b8-237bf668051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524172097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.524172097
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2593136311
Short name T753
Test name
Test status
Simulation time 43592239 ps
CPU time 0.84 seconds
Started Feb 21 02:22:07 PM PST 24
Finished Feb 21 02:22:09 PM PST 24
Peak memory 205476 kb
Host smart-623c6d95-fc17-4eab-a6b8-08391d6e5f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593136311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2593136311
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.467484123
Short name T593
Test name
Test status
Simulation time 3892228473 ps
CPU time 6.16 seconds
Started Feb 21 02:22:06 PM PST 24
Finished Feb 21 02:22:14 PM PST 24
Peak memory 221720 kb
Host smart-bdd845b8-fc00-43ce-873e-c748ce4eaa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467484123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.467484123
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1439106389
Short name T906
Test name
Test status
Simulation time 28458736 ps
CPU time 0.77 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:03 PM PST 24
Peak memory 204968 kb
Host smart-b599285e-ffa0-42a3-838e-23e5cdac5ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439106389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1439106389
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.864216082
Short name T807
Test name
Test status
Simulation time 274043073 ps
CPU time 4.01 seconds
Started Feb 21 02:26:58 PM PST 24
Finished Feb 21 02:27:02 PM PST 24
Peak memory 219176 kb
Host smart-4e818705-9cce-4663-bf49-e758d67cf0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864216082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.864216082
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2903816309
Short name T864
Test name
Test status
Simulation time 16791727 ps
CPU time 0.77 seconds
Started Feb 21 02:26:55 PM PST 24
Finished Feb 21 02:26:57 PM PST 24
Peak memory 206100 kb
Host smart-e660ed66-ba6b-4407-9491-abda08838974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903816309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2903816309
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1177068561
Short name T190
Test name
Test status
Simulation time 64678601997 ps
CPU time 281.14 seconds
Started Feb 21 02:27:01 PM PST 24
Finished Feb 21 02:31:42 PM PST 24
Peak memory 255780 kb
Host smart-7b4530b0-ec89-468e-973c-e802f25adea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177068561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1177068561
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.491326883
Short name T196
Test name
Test status
Simulation time 14149281132 ps
CPU time 47.81 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:50 PM PST 24
Peak memory 237816 kb
Host smart-dbaf7f61-c699-4db0-8d72-d7e452be915f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491326883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.491326883
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2412816145
Short name T908
Test name
Test status
Simulation time 6680689272 ps
CPU time 41.32 seconds
Started Feb 21 02:27:00 PM PST 24
Finished Feb 21 02:27:42 PM PST 24
Peak memory 232896 kb
Host smart-8f9d90ff-d720-49f5-a81c-f69ac04ca023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412816145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2412816145
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2065642278
Short name T912
Test name
Test status
Simulation time 2659435854 ps
CPU time 4.09 seconds
Started Feb 21 02:26:57 PM PST 24
Finished Feb 21 02:27:01 PM PST 24
Peak memory 217440 kb
Host smart-fba09410-6045-4b39-b36f-3866f873bda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065642278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2065642278
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.92919755
Short name T659
Test name
Test status
Simulation time 15584415868 ps
CPU time 12.07 seconds
Started Feb 21 02:26:56 PM PST 24
Finished Feb 21 02:27:09 PM PST 24
Peak memory 219720 kb
Host smart-9aedef49-286f-4c0b-95fe-cbabbfad9a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92919755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.92919755
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1347745890
Short name T863
Test name
Test status
Simulation time 2687910888 ps
CPU time 9.62 seconds
Started Feb 21 02:26:58 PM PST 24
Finished Feb 21 02:27:09 PM PST 24
Peak memory 237800 kb
Host smart-43a4551d-39bb-4645-85a1-fac2155f9db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347745890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1347745890
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1417982310
Short name T56
Test name
Test status
Simulation time 902264093 ps
CPU time 6.94 seconds
Started Feb 21 02:26:56 PM PST 24
Finished Feb 21 02:27:03 PM PST 24
Peak memory 221836 kb
Host smart-3bc902ef-9523-4bd2-a706-29bd95f03e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417982310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1417982310
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3190136325
Short name T303
Test name
Test status
Simulation time 592714470 ps
CPU time 4.05 seconds
Started Feb 21 02:27:03 PM PST 24
Finished Feb 21 02:27:07 PM PST 24
Peak memory 216536 kb
Host smart-4a0f33ea-238d-45f7-8b42-1ec3e1da736a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3190136325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3190136325
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1547466812
Short name T147
Test name
Test status
Simulation time 1464177585 ps
CPU time 12.88 seconds
Started Feb 21 02:27:00 PM PST 24
Finished Feb 21 02:27:13 PM PST 24
Peak memory 221560 kb
Host smart-35052934-a535-4d0c-b892-d4807297dd3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547466812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1547466812
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.571144733
Short name T63
Test name
Test status
Simulation time 576271372 ps
CPU time 9.59 seconds
Started Feb 21 02:26:55 PM PST 24
Finished Feb 21 02:27:05 PM PST 24
Peak memory 216464 kb
Host smart-4c8dc2ca-93e1-4f21-ac9e-9239b9fdd1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571144733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.571144733
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1809978999
Short name T670
Test name
Test status
Simulation time 5233171185 ps
CPU time 19.37 seconds
Started Feb 21 02:26:55 PM PST 24
Finished Feb 21 02:27:15 PM PST 24
Peak memory 216548 kb
Host smart-e6c703be-956f-46d8-bf5e-8b2a79b8f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809978999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1809978999
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1058397979
Short name T472
Test name
Test status
Simulation time 1167382381 ps
CPU time 2.12 seconds
Started Feb 21 02:26:55 PM PST 24
Finished Feb 21 02:26:58 PM PST 24
Peak memory 208588 kb
Host smart-e2a1346f-b365-46d3-b292-f1428ca51655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058397979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1058397979
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2146505015
Short name T841
Test name
Test status
Simulation time 51282347 ps
CPU time 0.95 seconds
Started Feb 21 02:26:54 PM PST 24
Finished Feb 21 02:26:55 PM PST 24
Peak memory 206528 kb
Host smart-ff770379-c8cb-4dd2-b6bc-dd9342d101ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146505015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2146505015
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.464843602
Short name T844
Test name
Test status
Simulation time 231730399 ps
CPU time 4.55 seconds
Started Feb 21 02:26:58 PM PST 24
Finished Feb 21 02:27:03 PM PST 24
Peak memory 234024 kb
Host smart-768f8cfb-601f-4497-beea-1955d6697d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464843602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.464843602
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.456298863
Short name T493
Test name
Test status
Simulation time 45108954 ps
CPU time 0.72 seconds
Started Feb 21 02:27:11 PM PST 24
Finished Feb 21 02:27:12 PM PST 24
Peak memory 205308 kb
Host smart-42d75619-ebf4-45d0-af5a-ecf74c76b758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456298863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.456298863
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2928909557
Short name T308
Test name
Test status
Simulation time 3717441830 ps
CPU time 4.24 seconds
Started Feb 21 02:27:03 PM PST 24
Finished Feb 21 02:27:08 PM PST 24
Peak memory 233632 kb
Host smart-bd98eaa8-b82e-4676-a645-9b48704b0776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928909557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2928909557
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2382660952
Short name T649
Test name
Test status
Simulation time 68365955 ps
CPU time 0.84 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:04 PM PST 24
Peak memory 206496 kb
Host smart-9c295cf4-64f8-4b78-b023-5a03fcdd7f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382660952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2382660952
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1494238423
Short name T713
Test name
Test status
Simulation time 56026201541 ps
CPU time 255.42 seconds
Started Feb 21 02:27:01 PM PST 24
Finished Feb 21 02:31:17 PM PST 24
Peak memory 256552 kb
Host smart-4431844c-f093-4eaa-878d-d4a0e2721ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494238423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1494238423
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2973965104
Short name T710
Test name
Test status
Simulation time 2363646464 ps
CPU time 48.82 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:59 PM PST 24
Peak memory 252444 kb
Host smart-89eecf13-86c7-4785-8692-25b4ba0023e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973965104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2973965104
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.346792116
Short name T183
Test name
Test status
Simulation time 62421579668 ps
CPU time 551.33 seconds
Started Feb 21 02:27:03 PM PST 24
Finished Feb 21 02:36:15 PM PST 24
Peak memory 273948 kb
Host smart-7945a50e-f635-4d31-9599-637b80fd8cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346792116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.346792116
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2861328638
Short name T70
Test name
Test status
Simulation time 1931499213 ps
CPU time 9.78 seconds
Started Feb 21 02:27:00 PM PST 24
Finished Feb 21 02:27:11 PM PST 24
Peak memory 239328 kb
Host smart-4d904ee5-79f0-442c-9dd4-4580305b2e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861328638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2861328638
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.599846344
Short name T745
Test name
Test status
Simulation time 631920809 ps
CPU time 3.77 seconds
Started Feb 21 02:27:03 PM PST 24
Finished Feb 21 02:27:07 PM PST 24
Peak memory 218184 kb
Host smart-38ad50ff-da64-4714-86d4-c78f19f0f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599846344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.599846344
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.235526451
Short name T458
Test name
Test status
Simulation time 1643505402 ps
CPU time 4.92 seconds
Started Feb 21 02:27:05 PM PST 24
Finished Feb 21 02:27:11 PM PST 24
Peak memory 217060 kb
Host smart-7d71b88a-b520-449d-acfb-34634e13a7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235526451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.235526451
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1653198796
Short name T463
Test name
Test status
Simulation time 542835901 ps
CPU time 4.52 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:07 PM PST 24
Peak memory 216568 kb
Host smart-49cb4491-40a5-4984-8f92-812c732a9de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653198796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1653198796
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4105182885
Short name T488
Test name
Test status
Simulation time 7467160727 ps
CPU time 7.37 seconds
Started Feb 21 02:27:00 PM PST 24
Finished Feb 21 02:27:08 PM PST 24
Peak memory 233684 kb
Host smart-3488db5e-f337-40e7-818e-8031dba98d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105182885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4105182885
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.344609058
Short name T543
Test name
Test status
Simulation time 2484988666 ps
CPU time 4.61 seconds
Started Feb 21 02:27:00 PM PST 24
Finished Feb 21 02:27:05 PM PST 24
Peak memory 220300 kb
Host smart-ec816f47-b631-47b1-808a-ac0e5b61664c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=344609058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.344609058
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3725424054
Short name T202
Test name
Test status
Simulation time 170570857294 ps
CPU time 1211.23 seconds
Started Feb 21 02:27:05 PM PST 24
Finished Feb 21 02:47:18 PM PST 24
Peak memory 280880 kb
Host smart-3c18a9a1-ae52-4151-9d5c-30d7af2abc5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725424054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3725424054
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2779377581
Short name T15
Test name
Test status
Simulation time 297150644 ps
CPU time 3.42 seconds
Started Feb 21 02:27:00 PM PST 24
Finished Feb 21 02:27:04 PM PST 24
Peak memory 216440 kb
Host smart-4f3aad45-ed63-458f-b227-40f8b55bb09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779377581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2779377581
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.82233420
Short name T868
Test name
Test status
Simulation time 14230130270 ps
CPU time 20.94 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:24 PM PST 24
Peak memory 216440 kb
Host smart-4a62c90d-aab2-4694-a788-b4089e3da38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82233420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.82233420
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2774340578
Short name T418
Test name
Test status
Simulation time 705810079 ps
CPU time 8.55 seconds
Started Feb 21 02:27:05 PM PST 24
Finished Feb 21 02:27:14 PM PST 24
Peak memory 216604 kb
Host smart-c1c3e1f7-28ee-4227-b22d-27d3b387d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774340578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2774340578
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1987388364
Short name T669
Test name
Test status
Simulation time 98977650 ps
CPU time 0.78 seconds
Started Feb 21 02:27:00 PM PST 24
Finished Feb 21 02:27:01 PM PST 24
Peak memory 205444 kb
Host smart-9174ea10-270e-4bab-87d8-5887c288b169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987388364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1987388364
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2740545937
Short name T334
Test name
Test status
Simulation time 3456268729 ps
CPU time 7.72 seconds
Started Feb 21 02:27:01 PM PST 24
Finished Feb 21 02:27:09 PM PST 24
Peak memory 218188 kb
Host smart-3ad8eeba-cbfc-4171-b678-7d9d0578bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740545937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2740545937
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2744133454
Short name T837
Test name
Test status
Simulation time 60965353 ps
CPU time 0.73 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:11 PM PST 24
Peak memory 205300 kb
Host smart-326eb37a-4b8b-47f6-8a61-9413fb8fc2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744133454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2744133454
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.453759178
Short name T635
Test name
Test status
Simulation time 9605377296 ps
CPU time 8.68 seconds
Started Feb 21 02:27:05 PM PST 24
Finished Feb 21 02:27:15 PM PST 24
Peak memory 219532 kb
Host smart-538d3340-c38c-44c2-b637-8349f610bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453759178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.453759178
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2336006364
Short name T581
Test name
Test status
Simulation time 20743248 ps
CPU time 0.79 seconds
Started Feb 21 02:27:01 PM PST 24
Finished Feb 21 02:27:02 PM PST 24
Peak memory 205144 kb
Host smart-2c98aec6-09b1-4361-93b2-173a461e8300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336006364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2336006364
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1217647912
Short name T151
Test name
Test status
Simulation time 115122210109 ps
CPU time 149.82 seconds
Started Feb 21 02:27:08 PM PST 24
Finished Feb 21 02:29:39 PM PST 24
Peak memory 241024 kb
Host smart-27ac5d36-1de5-4384-a019-2ca1e1f70f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217647912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1217647912
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2845933252
Short name T498
Test name
Test status
Simulation time 2703615563 ps
CPU time 26.37 seconds
Started Feb 21 02:27:09 PM PST 24
Finished Feb 21 02:27:36 PM PST 24
Peak memory 252636 kb
Host smart-642ed2b5-9724-4ff7-a0cf-a0b7e250abb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845933252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2845933252
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3347724520
Short name T328
Test name
Test status
Simulation time 9694564071 ps
CPU time 50.22 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:28:01 PM PST 24
Peak memory 236496 kb
Host smart-c8d55e01-6d64-4261-ad24-3f3a9dceeea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347724520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3347724520
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3495829712
Short name T702
Test name
Test status
Simulation time 3107236959 ps
CPU time 5.07 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:07 PM PST 24
Peak memory 217584 kb
Host smart-3bc77cbe-d277-474e-b3cf-20174c776714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495829712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3495829712
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3419138937
Short name T383
Test name
Test status
Simulation time 3031503801 ps
CPU time 10.38 seconds
Started Feb 21 02:27:05 PM PST 24
Finished Feb 21 02:27:17 PM PST 24
Peak memory 222088 kb
Host smart-38378e43-7d08-4f0a-9ef1-02fae783a0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419138937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3419138937
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.936851468
Short name T247
Test name
Test status
Simulation time 1412464580 ps
CPU time 3.96 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:14 PM PST 24
Peak memory 218108 kb
Host smart-c568b606-07b0-4fdf-ae09-804b4fe9a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936851468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.936851468
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.759510046
Short name T512
Test name
Test status
Simulation time 2485265633 ps
CPU time 9.35 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:12 PM PST 24
Peak memory 233524 kb
Host smart-3ec95614-de43-4951-9129-e939252604c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759510046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.759510046
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.847766905
Short name T814
Test name
Test status
Simulation time 1436582163 ps
CPU time 5.91 seconds
Started Feb 21 02:27:09 PM PST 24
Finished Feb 21 02:27:16 PM PST 24
Peak memory 220108 kb
Host smart-c13e75b3-074b-4b9f-b5af-b38c35cfe3cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=847766905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.847766905
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4286868593
Short name T697
Test name
Test status
Simulation time 44419933250 ps
CPU time 130.63 seconds
Started Feb 21 02:27:09 PM PST 24
Finished Feb 21 02:29:20 PM PST 24
Peak memory 263472 kb
Host smart-cbe0c356-7d0f-414d-91f3-c382e6ba9ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286868593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4286868593
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3339017416
Short name T285
Test name
Test status
Simulation time 4554546751 ps
CPU time 6.07 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:09 PM PST 24
Peak memory 216424 kb
Host smart-ead3266c-3149-433f-b11c-55aa33a7780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339017416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3339017416
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1905029513
Short name T291
Test name
Test status
Simulation time 2259297293 ps
CPU time 5.72 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:16 PM PST 24
Peak memory 216492 kb
Host smart-285a4448-d2a4-4108-ae23-a9830eeb3185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905029513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1905029513
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2579482746
Short name T729
Test name
Test status
Simulation time 283653458 ps
CPU time 10.63 seconds
Started Feb 21 02:27:04 PM PST 24
Finished Feb 21 02:27:15 PM PST 24
Peak memory 216536 kb
Host smart-82014d05-f33a-4784-b226-46285b63b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579482746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2579482746
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1799934374
Short name T797
Test name
Test status
Simulation time 223949619 ps
CPU time 0.96 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:11 PM PST 24
Peak memory 205472 kb
Host smart-1cf3ff08-dd5d-439a-ac80-a16aaa4d5d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799934374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1799934374
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1793349784
Short name T167
Test name
Test status
Simulation time 268885641564 ps
CPU time 46.95 seconds
Started Feb 21 02:27:02 PM PST 24
Finished Feb 21 02:27:50 PM PST 24
Peak memory 236108 kb
Host smart-0371ca5f-ee94-433f-a829-99d9ec9e494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793349784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1793349784
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1695219098
Short name T854
Test name
Test status
Simulation time 209847700 ps
CPU time 0.74 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:11 PM PST 24
Peak memory 204432 kb
Host smart-bb077aef-7d9f-4ea7-96ab-5a011bff9c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695219098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1695219098
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4053372655
Short name T455
Test name
Test status
Simulation time 135817208 ps
CPU time 2.55 seconds
Started Feb 21 02:27:11 PM PST 24
Finished Feb 21 02:27:13 PM PST 24
Peak memory 224616 kb
Host smart-69391fd9-d36c-41c5-8263-eb16388107a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053372655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4053372655
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.111385687
Short name T385
Test name
Test status
Simulation time 16013134 ps
CPU time 0.75 seconds
Started Feb 21 02:27:09 PM PST 24
Finished Feb 21 02:27:10 PM PST 24
Peak memory 205172 kb
Host smart-98f60f3f-3c2a-4376-8f62-444ab971b781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111385687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.111385687
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3902295795
Short name T833
Test name
Test status
Simulation time 23007951542 ps
CPU time 117.02 seconds
Started Feb 21 02:27:11 PM PST 24
Finished Feb 21 02:29:08 PM PST 24
Peak memory 240932 kb
Host smart-dce81e35-2a77-48c9-9150-ed8d3fdc8e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902295795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3902295795
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2833405127
Short name T971
Test name
Test status
Simulation time 28023715735 ps
CPU time 35.58 seconds
Started Feb 21 02:27:08 PM PST 24
Finished Feb 21 02:27:44 PM PST 24
Peak memory 223276 kb
Host smart-19c13dde-eb28-450c-a551-bf14179cf595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833405127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2833405127
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.33967535
Short name T812
Test name
Test status
Simulation time 81650307470 ps
CPU time 92.58 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:28:43 PM PST 24
Peak memory 238156 kb
Host smart-bd63d171-d70f-43b2-ab43-cbc994e49f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33967535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.33967535
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2725508742
Short name T276
Test name
Test status
Simulation time 2648881071 ps
CPU time 15.79 seconds
Started Feb 21 02:27:09 PM PST 24
Finished Feb 21 02:27:26 PM PST 24
Peak memory 240384 kb
Host smart-bd155db8-9a53-4b0c-9fb5-b2e797163b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725508742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2725508742
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3189202881
Short name T759
Test name
Test status
Simulation time 1842639600 ps
CPU time 8.87 seconds
Started Feb 21 02:27:12 PM PST 24
Finished Feb 21 02:27:21 PM PST 24
Peak memory 233336 kb
Host smart-623f5788-d6cd-40c4-aa48-8ee3d5566567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189202881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3189202881
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1407309594
Short name T568
Test name
Test status
Simulation time 13465326435 ps
CPU time 20.57 seconds
Started Feb 21 02:27:11 PM PST 24
Finished Feb 21 02:27:32 PM PST 24
Peak memory 234040 kb
Host smart-42387b6d-d669-4864-83f1-d33859f3ff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407309594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1407309594
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2963016050
Short name T172
Test name
Test status
Simulation time 2820158978 ps
CPU time 9.67 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:20 PM PST 24
Peak memory 238720 kb
Host smart-e01fb13f-7d32-46b9-af8c-f7171cbe3db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963016050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2963016050
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.812613088
Short name T665
Test name
Test status
Simulation time 59685305559 ps
CPU time 41.5 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:52 PM PST 24
Peak memory 234640 kb
Host smart-6c68766b-3af5-4c2a-883e-c11213fa7139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812613088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.812613088
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2766743476
Short name T938
Test name
Test status
Simulation time 1003492386 ps
CPU time 4.1 seconds
Started Feb 21 02:27:12 PM PST 24
Finished Feb 21 02:27:16 PM PST 24
Peak memory 216536 kb
Host smart-dd82a5b2-c606-4355-99ca-10f13bb343e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2766743476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2766743476
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.551331318
Short name T671
Test name
Test status
Simulation time 264092571 ps
CPU time 0.96 seconds
Started Feb 21 02:27:09 PM PST 24
Finished Feb 21 02:27:11 PM PST 24
Peak memory 205184 kb
Host smart-2731896d-8fd3-4dd8-93bd-6ae5364659eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551331318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.551331318
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1218883402
Short name T59
Test name
Test status
Simulation time 8319639007 ps
CPU time 24.1 seconds
Started Feb 21 02:27:09 PM PST 24
Finished Feb 21 02:27:34 PM PST 24
Peak memory 216560 kb
Host smart-119d2a84-6450-4fe7-ae36-f3a8e3cbf1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218883402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1218883402
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2840075664
Short name T852
Test name
Test status
Simulation time 2729454473 ps
CPU time 10.42 seconds
Started Feb 21 02:27:07 PM PST 24
Finished Feb 21 02:27:19 PM PST 24
Peak memory 217136 kb
Host smart-e03dfd95-ce30-46f2-b88a-9896073a6a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840075664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2840075664
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.821538000
Short name T301
Test name
Test status
Simulation time 24455998 ps
CPU time 0.86 seconds
Started Feb 21 02:27:06 PM PST 24
Finished Feb 21 02:27:08 PM PST 24
Peak memory 205448 kb
Host smart-1e605109-c267-4e26-8686-e94a14b980e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821538000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.821538000
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1481558147
Short name T353
Test name
Test status
Simulation time 179767338 ps
CPU time 1.06 seconds
Started Feb 21 02:27:11 PM PST 24
Finished Feb 21 02:27:12 PM PST 24
Peak memory 206528 kb
Host smart-6f01a308-1e6d-438b-b262-525fd48deece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481558147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1481558147
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2022852533
Short name T382
Test name
Test status
Simulation time 17880117514 ps
CPU time 20.3 seconds
Started Feb 21 02:27:12 PM PST 24
Finished Feb 21 02:27:33 PM PST 24
Peak memory 228832 kb
Host smart-23916176-3a4e-4ee5-a481-476b5e557125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022852533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2022852533
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1619640839
Short name T310
Test name
Test status
Simulation time 13089946 ps
CPU time 0.79 seconds
Started Feb 21 02:27:18 PM PST 24
Finished Feb 21 02:27:19 PM PST 24
Peak memory 204916 kb
Host smart-0e62fc98-47f5-4990-a082-ca1395430a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619640839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1619640839
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.808352686
Short name T342
Test name
Test status
Simulation time 456840606 ps
CPU time 2.33 seconds
Started Feb 21 02:27:17 PM PST 24
Finished Feb 21 02:27:20 PM PST 24
Peak memory 216512 kb
Host smart-2bc053cb-3a97-497e-bdc1-b2f5da3361c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808352686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.808352686
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.473798543
Short name T443
Test name
Test status
Simulation time 22839261 ps
CPU time 0.79 seconds
Started Feb 21 02:27:10 PM PST 24
Finished Feb 21 02:27:11 PM PST 24
Peak memory 206204 kb
Host smart-c1dc79d5-fbdf-4954-a5b1-c0ca170466ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473798543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.473798543
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.906373566
Short name T270
Test name
Test status
Simulation time 8904376489 ps
CPU time 64.64 seconds
Started Feb 21 02:27:20 PM PST 24
Finished Feb 21 02:28:26 PM PST 24
Peak memory 267176 kb
Host smart-7583fa27-f8ec-447f-8568-65c37a5f108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906373566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.906373566
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2799344617
Short name T667
Test name
Test status
Simulation time 11690288490 ps
CPU time 50.87 seconds
Started Feb 21 02:27:20 PM PST 24
Finished Feb 21 02:28:12 PM PST 24
Peak memory 237324 kb
Host smart-f57aa6d8-24fa-434c-9885-bcefa026c15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799344617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2799344617
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3706545015
Short name T17
Test name
Test status
Simulation time 5880172685 ps
CPU time 47.11 seconds
Started Feb 21 02:27:20 PM PST 24
Finished Feb 21 02:28:09 PM PST 24
Peak memory 222480 kb
Host smart-ad3bccd3-44f1-4a7c-b993-0d9fd569198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706545015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3706545015
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2789750873
Short name T502
Test name
Test status
Simulation time 399437760 ps
CPU time 3.94 seconds
Started Feb 21 02:27:17 PM PST 24
Finished Feb 21 02:27:22 PM PST 24
Peak memory 217512 kb
Host smart-bf08d062-9a93-406b-a3e6-acacea2505cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789750873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2789750873
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.201796256
Short name T239
Test name
Test status
Simulation time 5179348241 ps
CPU time 18.64 seconds
Started Feb 21 02:27:17 PM PST 24
Finished Feb 21 02:27:37 PM PST 24
Peak memory 224672 kb
Host smart-783886b0-a99e-435f-ace5-4652c162c39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201796256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.201796256
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.215188359
Short name T199
Test name
Test status
Simulation time 788634761 ps
CPU time 3.32 seconds
Started Feb 21 02:27:19 PM PST 24
Finished Feb 21 02:27:24 PM PST 24
Peak memory 233488 kb
Host smart-95e2945c-6570-454f-95dd-fc9973bd2f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215188359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.215188359
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1739658369
Short name T206
Test name
Test status
Simulation time 26921844348 ps
CPU time 11.52 seconds
Started Feb 21 02:27:11 PM PST 24
Finished Feb 21 02:27:23 PM PST 24
Peak memory 240416 kb
Host smart-dbec3c39-6ad5-494d-9d50-d40f16cff564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739658369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1739658369
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3712091069
Short name T731
Test name
Test status
Simulation time 1808454917 ps
CPU time 7.71 seconds
Started Feb 21 02:27:24 PM PST 24
Finished Feb 21 02:27:32 PM PST 24
Peak memory 222548 kb
Host smart-f02b89aa-da5c-461c-af73-85e362bd0ea2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3712091069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3712091069
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.234364699
Short name T935
Test name
Test status
Simulation time 12373546463 ps
CPU time 79.41 seconds
Started Feb 21 02:27:20 PM PST 24
Finished Feb 21 02:28:41 PM PST 24
Peak memory 257256 kb
Host smart-50fc6eb1-e2f3-43a4-a793-619ded0ca5e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234364699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.234364699
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3491095695
Short name T417
Test name
Test status
Simulation time 10802581207 ps
CPU time 91.4 seconds
Started Feb 21 02:27:12 PM PST 24
Finished Feb 21 02:28:44 PM PST 24
Peak memory 216804 kb
Host smart-190b9576-905d-430a-ad7a-27a831230977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491095695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3491095695
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3631585686
Short name T438
Test name
Test status
Simulation time 18346614829 ps
CPU time 15.92 seconds
Started Feb 21 02:27:11 PM PST 24
Finished Feb 21 02:27:28 PM PST 24
Peak memory 216688 kb
Host smart-c08b4c2d-a359-47fb-894e-8cb66f8b1130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631585686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3631585686
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2068162758
Short name T158
Test name
Test status
Simulation time 301177123 ps
CPU time 2.92 seconds
Started Feb 21 02:27:11 PM PST 24
Finished Feb 21 02:27:15 PM PST 24
Peak memory 217920 kb
Host smart-37447141-49a7-4623-8ba4-a070455c0ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068162758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2068162758
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3352671161
Short name T750
Test name
Test status
Simulation time 49465155 ps
CPU time 0.77 seconds
Started Feb 21 02:27:09 PM PST 24
Finished Feb 21 02:27:10 PM PST 24
Peak memory 205500 kb
Host smart-c2b4da2f-cefd-4ee1-915e-bb85fdfa5566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352671161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3352671161
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1954874269
Short name T501
Test name
Test status
Simulation time 895829320 ps
CPU time 7.05 seconds
Started Feb 21 02:27:16 PM PST 24
Finished Feb 21 02:27:24 PM PST 24
Peak memory 216872 kb
Host smart-c4a37cbd-ba6e-49c2-983b-a5d01ccd957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954874269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1954874269
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.53553206
Short name T825
Test name
Test status
Simulation time 11547351 ps
CPU time 0.72 seconds
Started Feb 21 02:27:34 PM PST 24
Finished Feb 21 02:27:35 PM PST 24
Peak memory 204428 kb
Host smart-ed297f9d-706a-43c8-90af-6d557c351fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53553206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.53553206
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3662213101
Short name T981
Test name
Test status
Simulation time 217125275 ps
CPU time 4.61 seconds
Started Feb 21 02:27:36 PM PST 24
Finished Feb 21 02:27:40 PM PST 24
Peak memory 233504 kb
Host smart-6494ab2e-4e7f-425c-a023-37752ea979a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662213101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3662213101
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3522502502
Short name T412
Test name
Test status
Simulation time 56614070 ps
CPU time 0.86 seconds
Started Feb 21 02:27:26 PM PST 24
Finished Feb 21 02:27:27 PM PST 24
Peak memory 206492 kb
Host smart-4e00892d-b0cb-4470-928f-3de8b4532443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522502502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3522502502
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4271483044
Short name T24
Test name
Test status
Simulation time 3570029423 ps
CPU time 48.84 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:28:24 PM PST 24
Peak memory 266400 kb
Host smart-59eb00c6-8678-4127-b703-7fe0fdf610c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271483044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4271483044
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1716611503
Short name T668
Test name
Test status
Simulation time 17921478912 ps
CPU time 133.65 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:29:49 PM PST 24
Peak memory 224144 kb
Host smart-e6155145-f254-429f-950c-0ed0ccee4501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716611503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1716611503
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1862079531
Short name T491
Test name
Test status
Simulation time 6517222847 ps
CPU time 78.21 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:28:54 PM PST 24
Peak memory 237240 kb
Host smart-db3a2717-2027-453a-b56e-78a1818eff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862079531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1862079531
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3235401094
Short name T976
Test name
Test status
Simulation time 2851252328 ps
CPU time 21.12 seconds
Started Feb 21 02:27:36 PM PST 24
Finished Feb 21 02:27:57 PM PST 24
Peak memory 232848 kb
Host smart-1a0c76f4-afc5-498f-ab83-1aaab0f41c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235401094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3235401094
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3694826396
Short name T918
Test name
Test status
Simulation time 2309620841 ps
CPU time 9.28 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:27:44 PM PST 24
Peak memory 233260 kb
Host smart-6aa43de8-3145-447c-856c-6191c8829a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694826396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3694826396
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2638848652
Short name T541
Test name
Test status
Simulation time 2458817872 ps
CPU time 7.29 seconds
Started Feb 21 02:27:34 PM PST 24
Finished Feb 21 02:27:41 PM PST 24
Peak memory 235236 kb
Host smart-aa795acf-f96f-479d-9eee-8ebbc0cba229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638848652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2638848652
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2979328446
Short name T760
Test name
Test status
Simulation time 9454965159 ps
CPU time 14.68 seconds
Started Feb 21 02:27:34 PM PST 24
Finished Feb 21 02:27:49 PM PST 24
Peak memory 217840 kb
Host smart-d9d70613-3b57-4efb-abb0-44f062c6b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979328446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2979328446
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.757889485
Short name T12
Test name
Test status
Simulation time 6032582922 ps
CPU time 7.27 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:27:42 PM PST 24
Peak memory 217716 kb
Host smart-dd0a258b-33f4-4b3a-b5db-a02dd28fc42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757889485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.757889485
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1954332540
Short name T919
Test name
Test status
Simulation time 787225505 ps
CPU time 4.66 seconds
Started Feb 21 02:27:34 PM PST 24
Finished Feb 21 02:27:38 PM PST 24
Peak memory 219900 kb
Host smart-999c3421-1619-4aff-bac4-6d721d9262f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1954332540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1954332540
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3899339709
Short name T783
Test name
Test status
Simulation time 12280554479 ps
CPU time 94.3 seconds
Started Feb 21 02:27:34 PM PST 24
Finished Feb 21 02:29:08 PM PST 24
Peak memory 236232 kb
Host smart-62c91f6c-4138-439d-8b37-bfb2ddade5be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899339709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3899339709
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2952130394
Short name T457
Test name
Test status
Simulation time 28784243629 ps
CPU time 98.65 seconds
Started Feb 21 02:27:20 PM PST 24
Finished Feb 21 02:29:00 PM PST 24
Peak memory 216548 kb
Host smart-71aee255-36fc-458e-b84c-24044077b8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952130394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2952130394
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1562053921
Short name T734
Test name
Test status
Simulation time 3748917907 ps
CPU time 3.07 seconds
Started Feb 21 02:27:24 PM PST 24
Finished Feb 21 02:27:27 PM PST 24
Peak memory 208084 kb
Host smart-1ee524d9-f001-43c2-9d36-c4973e8fb722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562053921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1562053921
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.236649249
Short name T604
Test name
Test status
Simulation time 263319305 ps
CPU time 9.53 seconds
Started Feb 21 02:27:23 PM PST 24
Finished Feb 21 02:27:33 PM PST 24
Peak memory 216428 kb
Host smart-283bc28e-8d7d-4939-b2b4-b3d4010616d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236649249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.236649249
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.562198868
Short name T652
Test name
Test status
Simulation time 67930181 ps
CPU time 0.93 seconds
Started Feb 21 02:27:23 PM PST 24
Finished Feb 21 02:27:25 PM PST 24
Peak memory 205520 kb
Host smart-f6028842-4e68-46a3-9465-0d4a4d9afb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562198868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.562198868
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3898043467
Short name T569
Test name
Test status
Simulation time 776154856 ps
CPU time 8.15 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:27:43 PM PST 24
Peak memory 218720 kb
Host smart-e473a4f5-f22b-4b70-8f10-8672d6a4a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898043467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3898043467
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.110104687
Short name T834
Test name
Test status
Simulation time 57025842 ps
CPU time 0.69 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:27:40 PM PST 24
Peak memory 205328 kb
Host smart-597754b0-ca18-4978-a31d-8c94b77aca7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110104687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.110104687
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3088601076
Short name T132
Test name
Test status
Simulation time 914792097 ps
CPU time 3.12 seconds
Started Feb 21 02:27:37 PM PST 24
Finished Feb 21 02:27:41 PM PST 24
Peak memory 224568 kb
Host smart-cc58f71b-b778-45e2-af27-500fabf5e7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088601076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3088601076
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.806509742
Short name T441
Test name
Test status
Simulation time 43049401 ps
CPU time 0.81 seconds
Started Feb 21 02:27:36 PM PST 24
Finished Feb 21 02:27:37 PM PST 24
Peak memory 206204 kb
Host smart-1ffde511-80aa-4bd6-9478-73c3c87e19ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806509742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.806509742
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1457636095
Short name T879
Test name
Test status
Simulation time 2190690816 ps
CPU time 20.89 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:28:00 PM PST 24
Peak memory 241056 kb
Host smart-5c2029ec-4511-4433-90e7-5a13a70f26bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457636095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1457636095
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2038400441
Short name T957
Test name
Test status
Simulation time 25185368158 ps
CPU time 55.58 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:28:35 PM PST 24
Peak memory 251516 kb
Host smart-71621b49-5c71-4fb3-ade8-a47fe1772f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038400441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2038400441
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1066347784
Short name T661
Test name
Test status
Simulation time 1838958561 ps
CPU time 16.93 seconds
Started Feb 21 02:27:38 PM PST 24
Finished Feb 21 02:27:55 PM PST 24
Peak memory 253376 kb
Host smart-446f6071-9b28-46a4-b6e3-000a4f385279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066347784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1066347784
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.626721219
Short name T214
Test name
Test status
Simulation time 336083166 ps
CPU time 6.16 seconds
Started Feb 21 02:27:38 PM PST 24
Finished Feb 21 02:27:44 PM PST 24
Peak memory 232816 kb
Host smart-a81f8b4a-5015-4c76-8413-97ae3bb6511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626721219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.626721219
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.250049626
Short name T536
Test name
Test status
Simulation time 2840722230 ps
CPU time 11.59 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:27:51 PM PST 24
Peak memory 232752 kb
Host smart-ca5ef594-5753-4998-9c1d-a45a05036a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250049626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.250049626
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3463234763
Short name T716
Test name
Test status
Simulation time 2670736199 ps
CPU time 10.09 seconds
Started Feb 21 02:27:37 PM PST 24
Finished Feb 21 02:27:48 PM PST 24
Peak memory 233760 kb
Host smart-08e32873-cd27-4e53-9ca4-3c7b545454c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463234763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3463234763
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1181216300
Short name T448
Test name
Test status
Simulation time 3582623312 ps
CPU time 12.16 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:27:47 PM PST 24
Peak memory 234304 kb
Host smart-5732c5c9-d35e-492c-9170-17fe15a453a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181216300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1181216300
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2120730169
Short name T761
Test name
Test status
Simulation time 1067152702 ps
CPU time 3.85 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:27:43 PM PST 24
Peak memory 219980 kb
Host smart-3d5f267e-4040-410a-a8d1-b1894413b649
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2120730169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2120730169
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2425003144
Short name T552
Test name
Test status
Simulation time 47743593616 ps
CPU time 107.58 seconds
Started Feb 21 02:27:33 PM PST 24
Finished Feb 21 02:29:21 PM PST 24
Peak memory 216544 kb
Host smart-fcd83d5a-9cdb-4ebe-8f27-08e32367e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425003144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2425003144
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2372275770
Short name T614
Test name
Test status
Simulation time 918271243 ps
CPU time 5.5 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:27:40 PM PST 24
Peak memory 216224 kb
Host smart-d0c437e3-d636-46ce-8c41-494135643c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372275770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2372275770
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.583423176
Short name T574
Test name
Test status
Simulation time 183500874 ps
CPU time 1.35 seconds
Started Feb 21 02:27:36 PM PST 24
Finished Feb 21 02:27:38 PM PST 24
Peak memory 216428 kb
Host smart-85f33cdf-fe22-4fba-9319-939ae38d18d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583423176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.583423176
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.793009303
Short name T545
Test name
Test status
Simulation time 412178848 ps
CPU time 1.07 seconds
Started Feb 21 02:27:35 PM PST 24
Finished Feb 21 02:27:36 PM PST 24
Peak memory 206536 kb
Host smart-e087e439-e643-4c65-a68e-acfb685a7e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793009303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.793009303
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1628819534
Short name T603
Test name
Test status
Simulation time 11256974565 ps
CPU time 13.86 seconds
Started Feb 21 02:27:37 PM PST 24
Finished Feb 21 02:27:51 PM PST 24
Peak memory 224672 kb
Host smart-9493fd07-15d6-44a1-a0b1-02b203fd986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628819534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1628819534
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1825076240
Short name T531
Test name
Test status
Simulation time 14316043 ps
CPU time 0.75 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:27:40 PM PST 24
Peak memory 204992 kb
Host smart-cad1dc14-5947-46b7-a8f8-63a462c5d669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825076240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1825076240
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.425690833
Short name T434
Test name
Test status
Simulation time 225870140 ps
CPU time 3.52 seconds
Started Feb 21 02:27:37 PM PST 24
Finished Feb 21 02:27:40 PM PST 24
Peak memory 233736 kb
Host smart-91f9ad88-8678-483e-a936-acd43394a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425690833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.425690833
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4064269451
Short name T696
Test name
Test status
Simulation time 157486117 ps
CPU time 0.75 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:27:41 PM PST 24
Peak memory 205172 kb
Host smart-5e2cb30b-ac97-4c87-9227-7f6e857ff75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064269451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4064269451
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3098261268
Short name T245
Test name
Test status
Simulation time 2854186606 ps
CPU time 27.57 seconds
Started Feb 21 02:27:40 PM PST 24
Finished Feb 21 02:28:08 PM PST 24
Peak memory 232996 kb
Host smart-1ecff1f9-ab38-4235-a89c-4456e21be46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098261268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3098261268
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2383115866
Short name T181
Test name
Test status
Simulation time 20980410608 ps
CPU time 99.09 seconds
Started Feb 21 02:27:41 PM PST 24
Finished Feb 21 02:29:20 PM PST 24
Peak memory 264168 kb
Host smart-633641d6-49a7-4f11-8ebd-b87807df6341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383115866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2383115866
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4207260078
Short name T314
Test name
Test status
Simulation time 17563570918 ps
CPU time 44.67 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:28:24 PM PST 24
Peak memory 247972 kb
Host smart-e8a97471-5569-4a7c-bb39-2c2c010994bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207260078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4207260078
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3219283643
Short name T184
Test name
Test status
Simulation time 9238843563 ps
CPU time 10.37 seconds
Started Feb 21 02:27:38 PM PST 24
Finished Feb 21 02:27:49 PM PST 24
Peak memory 232976 kb
Host smart-5c02f6c4-d48a-4d2c-a48d-ea0de5733cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219283643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3219283643
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4239241255
Short name T238
Test name
Test status
Simulation time 27443847563 ps
CPU time 41.88 seconds
Started Feb 21 02:27:42 PM PST 24
Finished Feb 21 02:28:25 PM PST 24
Peak memory 240416 kb
Host smart-68f72cd2-bd0d-4574-ab70-3c2b61bf7c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239241255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4239241255
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4185390191
Short name T744
Test name
Test status
Simulation time 1869261127 ps
CPU time 4.81 seconds
Started Feb 21 02:27:43 PM PST 24
Finished Feb 21 02:27:48 PM PST 24
Peak memory 216960 kb
Host smart-0fa29e33-c08c-4632-94fd-2a8b3bb35ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185390191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4185390191
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3189428275
Short name T584
Test name
Test status
Simulation time 158021776 ps
CPU time 3.74 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:27:44 PM PST 24
Peak memory 234336 kb
Host smart-e614bd4d-b15f-401f-a374-9970338deeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189428275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3189428275
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3750420178
Short name T468
Test name
Test status
Simulation time 2495361697 ps
CPU time 4.41 seconds
Started Feb 21 02:27:38 PM PST 24
Finished Feb 21 02:27:44 PM PST 24
Peak memory 216664 kb
Host smart-8fc45e21-c103-4ec6-9d09-b6b68bae8639
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3750420178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3750420178
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1777941513
Short name T629
Test name
Test status
Simulation time 55707289372 ps
CPU time 163.02 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:30:23 PM PST 24
Peak memory 257536 kb
Host smart-2225cfb6-196c-44ed-aa1e-18a14f83f46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777941513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1777941513
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1428110922
Short name T286
Test name
Test status
Simulation time 805723172 ps
CPU time 11.86 seconds
Started Feb 21 02:27:38 PM PST 24
Finished Feb 21 02:27:51 PM PST 24
Peak memory 218480 kb
Host smart-667ab6b7-a224-479c-a95a-40641544390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428110922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1428110922
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.751057572
Short name T311
Test name
Test status
Simulation time 2523636602 ps
CPU time 10.78 seconds
Started Feb 21 02:27:37 PM PST 24
Finished Feb 21 02:27:48 PM PST 24
Peak memory 216564 kb
Host smart-8b3cb779-c260-48a4-a81c-d5ec26c8405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751057572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.751057572
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4129468843
Short name T601
Test name
Test status
Simulation time 273821342 ps
CPU time 1.46 seconds
Started Feb 21 02:27:41 PM PST 24
Finished Feb 21 02:27:43 PM PST 24
Peak memory 208316 kb
Host smart-a82f60ed-09e9-4fed-9ef8-6e0446734fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129468843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4129468843
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1004061748
Short name T947
Test name
Test status
Simulation time 412482243 ps
CPU time 1.03 seconds
Started Feb 21 02:27:42 PM PST 24
Finished Feb 21 02:27:43 PM PST 24
Peak memory 206692 kb
Host smart-b81df930-cf07-4cb3-b305-9c07f57e2094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004061748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1004061748
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.628050317
Short name T470
Test name
Test status
Simulation time 16182994609 ps
CPU time 14.72 seconds
Started Feb 21 02:27:39 PM PST 24
Finished Feb 21 02:27:55 PM PST 24
Peak memory 233832 kb
Host smart-4abcab21-7907-402f-80a4-938764cdfc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628050317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.628050317
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3048200471
Short name T37
Test name
Test status
Simulation time 24505109 ps
CPU time 0.7 seconds
Started Feb 21 02:27:49 PM PST 24
Finished Feb 21 02:27:50 PM PST 24
Peak memory 205328 kb
Host smart-69238214-093f-48fc-9d5b-adeb4962bddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048200471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3048200471
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1082391224
Short name T32
Test name
Test status
Simulation time 184457964 ps
CPU time 3.21 seconds
Started Feb 21 02:27:46 PM PST 24
Finished Feb 21 02:27:49 PM PST 24
Peak memory 217892 kb
Host smart-0cbb65da-6363-4ea1-96f7-a237305b89ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082391224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1082391224
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.508760488
Short name T829
Test name
Test status
Simulation time 14503553 ps
CPU time 0.72 seconds
Started Feb 21 02:27:41 PM PST 24
Finished Feb 21 02:27:43 PM PST 24
Peak memory 205504 kb
Host smart-13a0be26-dd6d-4d5d-941c-c95f5cae5a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508760488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.508760488
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2495466700
Short name T262
Test name
Test status
Simulation time 9939879004 ps
CPU time 127.67 seconds
Started Feb 21 02:27:48 PM PST 24
Finished Feb 21 02:29:56 PM PST 24
Peak memory 251288 kb
Host smart-694f852b-eec0-4d30-9afb-d6961916c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495466700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2495466700
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.994594954
Short name T152
Test name
Test status
Simulation time 102774589953 ps
CPU time 290.19 seconds
Started Feb 21 02:27:49 PM PST 24
Finished Feb 21 02:32:39 PM PST 24
Peak memory 253428 kb
Host smart-9b7dda35-efbf-420e-a069-668feccdbdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994594954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.994594954
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3466091175
Short name T711
Test name
Test status
Simulation time 818125676402 ps
CPU time 337.59 seconds
Started Feb 21 02:27:47 PM PST 24
Finished Feb 21 02:33:25 PM PST 24
Peak memory 255424 kb
Host smart-aaad0515-7eb4-4179-89d5-eea322ed6700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466091175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3466091175
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.86952252
Short name T277
Test name
Test status
Simulation time 1912186320 ps
CPU time 14.32 seconds
Started Feb 21 02:27:47 PM PST 24
Finished Feb 21 02:28:02 PM PST 24
Peak memory 233844 kb
Host smart-b493ba4d-fb5e-405c-a4b8-2e024c698b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86952252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.86952252
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3780805068
Short name T930
Test name
Test status
Simulation time 387851430 ps
CPU time 2.75 seconds
Started Feb 21 02:27:41 PM PST 24
Finished Feb 21 02:27:45 PM PST 24
Peak memory 224588 kb
Host smart-09cd0abd-0841-4b96-8e74-d00be641b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780805068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3780805068
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2317450140
Short name T370
Test name
Test status
Simulation time 27590477930 ps
CPU time 21.21 seconds
Started Feb 21 02:27:40 PM PST 24
Finished Feb 21 02:28:01 PM PST 24
Peak memory 238560 kb
Host smart-b2e3ba87-9e2c-4add-9cb5-9ee518d09217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317450140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2317450140
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4115583994
Short name T728
Test name
Test status
Simulation time 21103150356 ps
CPU time 51.96 seconds
Started Feb 21 02:27:40 PM PST 24
Finished Feb 21 02:28:33 PM PST 24
Peak memory 246600 kb
Host smart-cb870007-bc7c-44a7-8be7-893bab2b051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115583994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4115583994
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2043682780
Short name T169
Test name
Test status
Simulation time 335812515 ps
CPU time 5.99 seconds
Started Feb 21 02:27:40 PM PST 24
Finished Feb 21 02:27:47 PM PST 24
Peak memory 219824 kb
Host smart-00775caa-2809-4722-ae23-acc4e96bfa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043682780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2043682780
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1265477745
Short name T876
Test name
Test status
Simulation time 303179758 ps
CPU time 3.81 seconds
Started Feb 21 02:27:51 PM PST 24
Finished Feb 21 02:27:55 PM PST 24
Peak memory 222708 kb
Host smart-1dab1148-3398-4b03-b77a-8fdbb3639aa1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1265477745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1265477745
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3774497822
Short name T139
Test name
Test status
Simulation time 193414272 ps
CPU time 1.07 seconds
Started Feb 21 02:27:49 PM PST 24
Finished Feb 21 02:27:51 PM PST 24
Peak memory 206668 kb
Host smart-ca18e385-1bb3-4b64-8262-1fdbf4c79a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774497822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3774497822
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.463271741
Short name T663
Test name
Test status
Simulation time 4225280102 ps
CPU time 28.69 seconds
Started Feb 21 02:27:43 PM PST 24
Finished Feb 21 02:28:12 PM PST 24
Peak memory 219152 kb
Host smart-9ea7fe3e-3b28-4d2e-bd0a-3e0e3cb3f44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463271741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.463271741
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.44396654
Short name T451
Test name
Test status
Simulation time 1668852194 ps
CPU time 3.26 seconds
Started Feb 21 02:27:42 PM PST 24
Finished Feb 21 02:27:45 PM PST 24
Peak memory 208240 kb
Host smart-19f8dcc5-c1a4-4f16-8de9-c0c8b93cdcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44396654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.44396654
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2542344106
Short name T776
Test name
Test status
Simulation time 547573271 ps
CPU time 5.61 seconds
Started Feb 21 02:27:40 PM PST 24
Finished Feb 21 02:27:46 PM PST 24
Peak memory 216424 kb
Host smart-bc9ef27f-173d-470a-a9c1-f37df2a252c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542344106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2542344106
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1038832089
Short name T939
Test name
Test status
Simulation time 93486155 ps
CPU time 0.99 seconds
Started Feb 21 02:27:38 PM PST 24
Finished Feb 21 02:27:40 PM PST 24
Peak memory 206500 kb
Host smart-3c483051-8aaa-4e03-9d1e-53a81c1f305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038832089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1038832089
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2465463331
Short name T351
Test name
Test status
Simulation time 51599963 ps
CPU time 2.41 seconds
Started Feb 21 02:27:46 PM PST 24
Finished Feb 21 02:27:49 PM PST 24
Peak memory 218780 kb
Host smart-8055de18-455f-4739-b9c6-07b5b5b1452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465463331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2465463331
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.881328129
Short name T292
Test name
Test status
Simulation time 68429917 ps
CPU time 0.71 seconds
Started Feb 21 02:27:47 PM PST 24
Finished Feb 21 02:27:48 PM PST 24
Peak memory 204920 kb
Host smart-8608521b-a020-46e2-8361-6d88c43b2b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881328129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.881328129
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3940214279
Short name T951
Test name
Test status
Simulation time 1474355331 ps
CPU time 7.06 seconds
Started Feb 21 02:27:46 PM PST 24
Finished Feb 21 02:27:53 PM PST 24
Peak memory 220048 kb
Host smart-00a2a760-f126-4662-9341-17fec41a821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940214279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3940214279
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2423663471
Short name T664
Test name
Test status
Simulation time 61904785 ps
CPU time 0.75 seconds
Started Feb 21 02:27:48 PM PST 24
Finished Feb 21 02:27:49 PM PST 24
Peak memory 205180 kb
Host smart-f274969c-f4cf-4f2c-b669-0cf883706888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423663471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2423663471
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1863743373
Short name T565
Test name
Test status
Simulation time 108366546019 ps
CPU time 57.54 seconds
Started Feb 21 02:27:48 PM PST 24
Finished Feb 21 02:28:46 PM PST 24
Peak memory 256412 kb
Host smart-ff63132d-145e-4129-9ee5-387872e27b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863743373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1863743373
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3955777460
Short name T254
Test name
Test status
Simulation time 31714867057 ps
CPU time 214.67 seconds
Started Feb 21 02:27:51 PM PST 24
Finished Feb 21 02:31:25 PM PST 24
Peak memory 265088 kb
Host smart-93c55bca-d331-46f8-a3b8-4806afaaf27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955777460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3955777460
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1121053319
Short name T439
Test name
Test status
Simulation time 4003515422 ps
CPU time 49.08 seconds
Started Feb 21 02:27:46 PM PST 24
Finished Feb 21 02:28:35 PM PST 24
Peak memory 241176 kb
Host smart-152cc1c9-a539-4284-a6fe-4e15348e4fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121053319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1121053319
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1527490076
Short name T307
Test name
Test status
Simulation time 9369798277 ps
CPU time 42.93 seconds
Started Feb 21 02:27:47 PM PST 24
Finished Feb 21 02:28:31 PM PST 24
Peak memory 238656 kb
Host smart-f810228b-21f9-4499-b646-4958e8ac9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527490076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1527490076
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3208357718
Short name T695
Test name
Test status
Simulation time 1099292776 ps
CPU time 5.31 seconds
Started Feb 21 02:27:48 PM PST 24
Finished Feb 21 02:27:54 PM PST 24
Peak memory 220340 kb
Host smart-cc24713c-01b5-4237-a190-45c3b699a720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208357718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3208357718
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4077343141
Short name T781
Test name
Test status
Simulation time 1133099811 ps
CPU time 5.59 seconds
Started Feb 21 02:27:48 PM PST 24
Finished Feb 21 02:27:54 PM PST 24
Peak memory 217348 kb
Host smart-a478d613-28a8-41d7-8fdd-24e212ffe595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077343141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4077343141
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.10093708
Short name T751
Test name
Test status
Simulation time 225264962356 ps
CPU time 36.02 seconds
Started Feb 21 02:27:49 PM PST 24
Finished Feb 21 02:28:25 PM PST 24
Peak memory 228884 kb
Host smart-dd7ca1b4-7e3a-4c9a-9cb6-42340f9351a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10093708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.10093708
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1788053306
Short name T432
Test name
Test status
Simulation time 18506522982 ps
CPU time 19.77 seconds
Started Feb 21 02:27:48 PM PST 24
Finished Feb 21 02:28:08 PM PST 24
Peak memory 229456 kb
Host smart-cd20251c-4102-4ea0-97d1-ca56061a0b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788053306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1788053306
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2192147269
Short name T323
Test name
Test status
Simulation time 5857142242 ps
CPU time 6.36 seconds
Started Feb 21 02:27:45 PM PST 24
Finished Feb 21 02:27:52 PM PST 24
Peak memory 222640 kb
Host smart-43639f0c-784f-4176-a0ad-85d4d05c186a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2192147269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2192147269
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1415324446
Short name T811
Test name
Test status
Simulation time 7549685318 ps
CPU time 48.11 seconds
Started Feb 21 02:27:48 PM PST 24
Finished Feb 21 02:28:36 PM PST 24
Peak memory 255452 kb
Host smart-b1821c47-0da5-4393-9022-5ebd18222f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415324446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1415324446
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.905586922
Short name T707
Test name
Test status
Simulation time 1907074766 ps
CPU time 31.44 seconds
Started Feb 21 02:27:49 PM PST 24
Finished Feb 21 02:28:21 PM PST 24
Peak memory 216420 kb
Host smart-7c289027-7f4b-4de2-975f-3fd4a71f6830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905586922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.905586922
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2322824846
Short name T780
Test name
Test status
Simulation time 2174526693 ps
CPU time 9.08 seconds
Started Feb 21 02:27:45 PM PST 24
Finished Feb 21 02:27:55 PM PST 24
Peak memory 216472 kb
Host smart-f2d68412-8c3e-4bc8-8620-5af2885d4f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322824846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2322824846
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.969312018
Short name T567
Test name
Test status
Simulation time 216358427 ps
CPU time 2.45 seconds
Started Feb 21 02:27:47 PM PST 24
Finished Feb 21 02:27:49 PM PST 24
Peak memory 216652 kb
Host smart-db5cb75e-52a5-471e-a173-01c3ecdf3ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969312018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.969312018
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3181581408
Short name T333
Test name
Test status
Simulation time 60062871 ps
CPU time 0.8 seconds
Started Feb 21 02:27:45 PM PST 24
Finished Feb 21 02:27:47 PM PST 24
Peak memory 205452 kb
Host smart-4ad30b89-e844-46aa-a91b-212a85931d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181581408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3181581408
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1725015610
Short name T419
Test name
Test status
Simulation time 5418285766 ps
CPU time 11.08 seconds
Started Feb 21 02:27:48 PM PST 24
Finished Feb 21 02:27:59 PM PST 24
Peak memory 240488 kb
Host smart-c45c5d7d-3e0f-4806-92d3-2c15a945707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725015610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1725015610
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1466083459
Short name T789
Test name
Test status
Simulation time 11140772 ps
CPU time 0.72 seconds
Started Feb 21 02:22:33 PM PST 24
Finished Feb 21 02:22:35 PM PST 24
Peak memory 204996 kb
Host smart-aa5b7155-c989-4a0c-989f-548fd4293921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466083459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
466083459
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.100115889
Short name T325
Test name
Test status
Simulation time 114268632 ps
CPU time 2.69 seconds
Started Feb 21 02:22:27 PM PST 24
Finished Feb 21 02:22:30 PM PST 24
Peak memory 224660 kb
Host smart-5eb6765c-d3aa-4cf5-ad64-d6c1cd68bb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100115889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.100115889
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.430700571
Short name T20
Test name
Test status
Simulation time 245604761 ps
CPU time 0.77 seconds
Started Feb 21 02:22:24 PM PST 24
Finished Feb 21 02:22:25 PM PST 24
Peak memory 206204 kb
Host smart-4e149331-7535-47ec-b860-177e17d85369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430700571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.430700571
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1821473807
Short name T889
Test name
Test status
Simulation time 3136368277 ps
CPU time 21 seconds
Started Feb 21 02:22:27 PM PST 24
Finished Feb 21 02:22:48 PM PST 24
Peak memory 238576 kb
Host smart-ea6931e5-f056-4e32-9630-458eaf8d7ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821473807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1821473807
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.800709975
Short name T816
Test name
Test status
Simulation time 6670591826 ps
CPU time 57.2 seconds
Started Feb 21 02:22:34 PM PST 24
Finished Feb 21 02:23:31 PM PST 24
Peak memory 240372 kb
Host smart-40883f48-a4c9-450c-8b4e-d623f78c40fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800709975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.800709975
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.553898999
Short name T608
Test name
Test status
Simulation time 5741986287 ps
CPU time 21.92 seconds
Started Feb 21 02:22:23 PM PST 24
Finished Feb 21 02:22:45 PM PST 24
Peak memory 232856 kb
Host smart-390bd407-f9d8-4dc0-a87f-c6d3ce47f714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553898999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.553898999
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1043655575
Short name T658
Test name
Test status
Simulation time 41057294689 ps
CPU time 14.94 seconds
Started Feb 21 02:22:27 PM PST 24
Finished Feb 21 02:22:42 PM PST 24
Peak memory 224700 kb
Host smart-3341ad8d-c745-4c84-a674-52e4ba380989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043655575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1043655575
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1214493987
Short name T6
Test name
Test status
Simulation time 300335465 ps
CPU time 2.48 seconds
Started Feb 21 02:22:25 PM PST 24
Finished Feb 21 02:22:27 PM PST 24
Peak memory 217724 kb
Host smart-6e12cad6-a808-4ed0-ab35-4a2f9ab69802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214493987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1214493987
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2641070989
Short name T974
Test name
Test status
Simulation time 146838555 ps
CPU time 1.06 seconds
Started Feb 21 02:22:27 PM PST 24
Finished Feb 21 02:22:28 PM PST 24
Peak memory 217780 kb
Host smart-83dde4e9-eda4-419e-a3b5-e41cbdbc700d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641070989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2641070989
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3652736535
Short name T473
Test name
Test status
Simulation time 1038121382 ps
CPU time 4.14 seconds
Started Feb 21 02:22:24 PM PST 24
Finished Feb 21 02:22:29 PM PST 24
Peak memory 233256 kb
Host smart-bdac1dd7-36b6-4807-b0ac-d965451d06e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652736535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3652736535
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1552247462
Short name T215
Test name
Test status
Simulation time 1912210555 ps
CPU time 10.01 seconds
Started Feb 21 02:22:26 PM PST 24
Finished Feb 21 02:22:36 PM PST 24
Peak memory 233488 kb
Host smart-c6d19aef-b6d9-4765-a998-ca67bd54bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552247462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1552247462
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2945686064
Short name T529
Test name
Test status
Simulation time 18200607 ps
CPU time 0.76 seconds
Started Feb 21 02:22:25 PM PST 24
Finished Feb 21 02:22:26 PM PST 24
Peak memory 216344 kb
Host smart-924b758b-13f6-4b8b-a0b5-5afd97efc84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945686064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2945686064
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3586306100
Short name T476
Test name
Test status
Simulation time 5166055376 ps
CPU time 4.36 seconds
Started Feb 21 02:22:26 PM PST 24
Finished Feb 21 02:22:30 PM PST 24
Peak memory 222180 kb
Host smart-5aad748e-63c9-4b2a-9fed-8cbceb1c9dfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3586306100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3586306100
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2861417403
Short name T227
Test name
Test status
Simulation time 74700041658 ps
CPU time 540.53 seconds
Started Feb 21 02:22:32 PM PST 24
Finished Feb 21 02:31:34 PM PST 24
Peak memory 265764 kb
Host smart-3f7b9c93-21b8-4003-ac6e-feafac032ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861417403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2861417403
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1409211988
Short name T865
Test name
Test status
Simulation time 10358711171 ps
CPU time 50.92 seconds
Started Feb 21 02:22:23 PM PST 24
Finished Feb 21 02:23:14 PM PST 24
Peak memory 216540 kb
Host smart-d30f01db-127f-4952-9e76-32273d7d6bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409211988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1409211988
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3080073896
Short name T747
Test name
Test status
Simulation time 1253427843 ps
CPU time 7.72 seconds
Started Feb 21 02:22:24 PM PST 24
Finished Feb 21 02:22:32 PM PST 24
Peak memory 216436 kb
Host smart-36412028-9aa4-42ff-b6e3-aff16cb682c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080073896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3080073896
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3703225060
Short name T364
Test name
Test status
Simulation time 854957038 ps
CPU time 3.93 seconds
Started Feb 21 02:22:24 PM PST 24
Finished Feb 21 02:22:29 PM PST 24
Peak memory 208584 kb
Host smart-e4d79c6e-63f6-4fe7-954d-c81209efe09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703225060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3703225060
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.804731698
Short name T331
Test name
Test status
Simulation time 144378380 ps
CPU time 1 seconds
Started Feb 21 02:22:24 PM PST 24
Finished Feb 21 02:22:25 PM PST 24
Peak memory 206516 kb
Host smart-0cb40c93-6b05-4c95-ba3e-f2c70bbf5e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804731698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.804731698
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3942140015
Short name T148
Test name
Test status
Simulation time 6580460317 ps
CPU time 7.68 seconds
Started Feb 21 02:22:25 PM PST 24
Finished Feb 21 02:22:33 PM PST 24
Peak memory 235780 kb
Host smart-e47dda6f-a542-4ee6-a4b9-8b9f391f3add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942140015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3942140015
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1187507367
Short name T500
Test name
Test status
Simulation time 107619779 ps
CPU time 0.66 seconds
Started Feb 21 02:22:39 PM PST 24
Finished Feb 21 02:22:40 PM PST 24
Peak memory 204620 kb
Host smart-57fbb3ad-bdba-4d72-9ea3-43844a3077be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187507367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
187507367
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2747622698
Short name T799
Test name
Test status
Simulation time 73419884 ps
CPU time 2.31 seconds
Started Feb 21 02:22:40 PM PST 24
Finished Feb 21 02:22:43 PM PST 24
Peak memory 216992 kb
Host smart-b7660ea2-ac16-492f-bdf9-dc825141eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747622698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2747622698
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.874251620
Short name T762
Test name
Test status
Simulation time 70894502 ps
CPU time 0.81 seconds
Started Feb 21 02:22:32 PM PST 24
Finished Feb 21 02:22:34 PM PST 24
Peak memory 206184 kb
Host smart-2853ad5d-c925-4c4f-9dfa-e19daf0c900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874251620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.874251620
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3449975989
Short name T921
Test name
Test status
Simulation time 32409671217 ps
CPU time 38.3 seconds
Started Feb 21 02:22:46 PM PST 24
Finished Feb 21 02:23:24 PM PST 24
Peak memory 249284 kb
Host smart-9a62f723-e6e7-4ded-bb1e-a1f2e979b4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449975989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3449975989
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1321589062
Short name T210
Test name
Test status
Simulation time 11244560716 ps
CPU time 59.12 seconds
Started Feb 21 02:22:46 PM PST 24
Finished Feb 21 02:23:45 PM PST 24
Peak memory 224784 kb
Host smart-5459cb2f-b124-47f3-afa7-4966e9aa908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321589062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1321589062
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2390119206
Short name T280
Test name
Test status
Simulation time 37607065776 ps
CPU time 123.01 seconds
Started Feb 21 02:22:41 PM PST 24
Finished Feb 21 02:24:45 PM PST 24
Peak memory 253036 kb
Host smart-3070c666-d589-4d07-bfb5-0a926978aad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390119206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2390119206
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1570938236
Short name T877
Test name
Test status
Simulation time 16119439321 ps
CPU time 30.14 seconds
Started Feb 21 02:22:42 PM PST 24
Finished Feb 21 02:23:13 PM PST 24
Peak memory 233744 kb
Host smart-23b566a1-f0be-452f-8875-686e34c86655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570938236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1570938236
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.243942983
Short name T809
Test name
Test status
Simulation time 122099254 ps
CPU time 3.63 seconds
Started Feb 21 02:22:35 PM PST 24
Finished Feb 21 02:22:39 PM PST 24
Peak memory 233520 kb
Host smart-149180b2-3cd7-4d08-93e0-9f12e1ac5a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243942983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.243942983
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2808432489
Short name T222
Test name
Test status
Simulation time 1497365895 ps
CPU time 6.55 seconds
Started Feb 21 02:22:33 PM PST 24
Finished Feb 21 02:22:41 PM PST 24
Peak memory 233200 kb
Host smart-3839a416-f85f-4d77-9e10-6567976f23de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808432489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2808432489
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.45457906
Short name T777
Test name
Test status
Simulation time 70430170 ps
CPU time 1 seconds
Started Feb 21 02:22:25 PM PST 24
Finished Feb 21 02:22:27 PM PST 24
Peak memory 217840 kb
Host smart-af2bdfdd-bf0a-4b4e-b20a-6164fd7e9b47
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45457906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.45457906
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3992918610
Short name T748
Test name
Test status
Simulation time 1100144522 ps
CPU time 2.95 seconds
Started Feb 21 02:22:26 PM PST 24
Finished Feb 21 02:22:30 PM PST 24
Peak memory 217448 kb
Host smart-25ff5caf-6175-449b-8a0d-4d1d229f9e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992918610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3992918610
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2047301588
Short name T566
Test name
Test status
Simulation time 825494095 ps
CPU time 4.69 seconds
Started Feb 21 02:22:34 PM PST 24
Finished Feb 21 02:22:39 PM PST 24
Peak memory 233412 kb
Host smart-03c6b950-0025-4e61-8c70-d505f1f40226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047301588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2047301588
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.1831623896
Short name T650
Test name
Test status
Simulation time 78159383 ps
CPU time 0.69 seconds
Started Feb 21 02:22:34 PM PST 24
Finished Feb 21 02:22:35 PM PST 24
Peak memory 216344 kb
Host smart-a86f5721-3cc8-49f1-be59-a9853a3108bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831623896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.1831623896
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3385519032
Short name T506
Test name
Test status
Simulation time 2211317462 ps
CPU time 3.03 seconds
Started Feb 21 02:22:38 PM PST 24
Finished Feb 21 02:22:42 PM PST 24
Peak memory 220204 kb
Host smart-10444e5a-0f4a-461c-8702-ec9b48c28b17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3385519032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3385519032
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3837670513
Short name T688
Test name
Test status
Simulation time 36151765698 ps
CPU time 140.8 seconds
Started Feb 21 02:22:41 PM PST 24
Finished Feb 21 02:25:02 PM PST 24
Peak memory 252988 kb
Host smart-c6424ca1-41f1-4e8f-b768-9b5a47d3772a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837670513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3837670513
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2503185619
Short name T562
Test name
Test status
Simulation time 13168907039 ps
CPU time 33.25 seconds
Started Feb 21 02:22:33 PM PST 24
Finished Feb 21 02:23:07 PM PST 24
Peak memory 216644 kb
Host smart-5a300334-3feb-4887-8649-f9648eaf555b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503185619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2503185619
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1803522559
Short name T361
Test name
Test status
Simulation time 5109752428 ps
CPU time 5.97 seconds
Started Feb 21 02:22:40 PM PST 24
Finished Feb 21 02:22:47 PM PST 24
Peak memory 216488 kb
Host smart-23136f8f-13e3-48a2-bcf8-77cff9670bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803522559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1803522559
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2324678953
Short name T579
Test name
Test status
Simulation time 937041638 ps
CPU time 3.57 seconds
Started Feb 21 02:22:33 PM PST 24
Finished Feb 21 02:22:38 PM PST 24
Peak memory 216588 kb
Host smart-33251f21-8ac2-4348-9abd-f942f3ac8629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324678953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2324678953
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.474929662
Short name T67
Test name
Test status
Simulation time 554512465 ps
CPU time 1.08 seconds
Started Feb 21 02:22:35 PM PST 24
Finished Feb 21 02:22:37 PM PST 24
Peak memory 206204 kb
Host smart-a4b5cf62-95e2-426c-bb96-39a2b2faf854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474929662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.474929662
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3231290574
Short name T7
Test name
Test status
Simulation time 5154542494 ps
CPU time 22.8 seconds
Started Feb 21 02:22:35 PM PST 24
Finished Feb 21 02:22:58 PM PST 24
Peak memory 228552 kb
Host smart-c9089563-1331-4859-985b-918728301847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231290574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3231290574
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.474497727
Short name T318
Test name
Test status
Simulation time 36322075 ps
CPU time 0.72 seconds
Started Feb 21 02:22:47 PM PST 24
Finished Feb 21 02:22:49 PM PST 24
Peak memory 204436 kb
Host smart-43fa793e-650e-4bba-a87b-57ce01b41c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474497727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.474497727
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2798772734
Short name T211
Test name
Test status
Simulation time 243411908 ps
CPU time 3.03 seconds
Started Feb 21 02:22:48 PM PST 24
Finished Feb 21 02:22:51 PM PST 24
Peak memory 218448 kb
Host smart-2eb322e1-8344-43af-b398-296b3cff5647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798772734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2798772734
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.796314886
Short name T315
Test name
Test status
Simulation time 15575746 ps
CPU time 0.76 seconds
Started Feb 21 02:22:39 PM PST 24
Finished Feb 21 02:22:41 PM PST 24
Peak memory 205496 kb
Host smart-700e3913-28bf-4dcb-9462-243f5e593daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796314886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.796314886
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1139485423
Short name T706
Test name
Test status
Simulation time 59111158706 ps
CPU time 156.74 seconds
Started Feb 21 02:22:47 PM PST 24
Finished Feb 21 02:25:24 PM PST 24
Peak memory 249320 kb
Host smart-20641394-8c50-4b6d-979f-c10ba499c4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139485423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1139485423
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1392772053
Short name T881
Test name
Test status
Simulation time 8119850485 ps
CPU time 34.32 seconds
Started Feb 21 02:22:46 PM PST 24
Finished Feb 21 02:23:21 PM PST 24
Peak memory 251360 kb
Host smart-22487ca5-ec7f-4042-bc04-0851329e5ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392772053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1392772053
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.34434608
Short name T252
Test name
Test status
Simulation time 69666838964 ps
CPU time 114.28 seconds
Started Feb 21 02:22:50 PM PST 24
Finished Feb 21 02:24:45 PM PST 24
Peak memory 257332 kb
Host smart-ddf75de7-0bc1-42bf-a343-1e0a1d08109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34434608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.34434608
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1209798327
Short name T201
Test name
Test status
Simulation time 922777263 ps
CPU time 6.67 seconds
Started Feb 21 02:22:50 PM PST 24
Finished Feb 21 02:22:57 PM PST 24
Peak memory 239428 kb
Host smart-b258f8d5-fc01-4a28-87f5-87da725c4746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209798327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1209798327
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.743100270
Short name T724
Test name
Test status
Simulation time 7628592397 ps
CPU time 7.59 seconds
Started Feb 21 02:22:47 PM PST 24
Finished Feb 21 02:22:56 PM PST 24
Peak memory 224672 kb
Host smart-aa3b0a2a-a9b3-45e6-a2ef-736440615230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743100270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.743100270
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2579376534
Short name T955
Test name
Test status
Simulation time 464964017 ps
CPU time 5.4 seconds
Started Feb 21 02:22:48 PM PST 24
Finished Feb 21 02:22:54 PM PST 24
Peak memory 233944 kb
Host smart-c0db9d51-2c1a-4da2-9b31-403e9d691141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579376534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2579376534
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1938549091
Short name T532
Test name
Test status
Simulation time 45715044 ps
CPU time 1.08 seconds
Started Feb 21 02:22:41 PM PST 24
Finished Feb 21 02:22:43 PM PST 24
Peak memory 216648 kb
Host smart-da415a27-4411-4771-938b-7aa4fe78091a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938549091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1938549091
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2380820990
Short name T771
Test name
Test status
Simulation time 748986456 ps
CPU time 6.31 seconds
Started Feb 21 02:22:46 PM PST 24
Finished Feb 21 02:22:52 PM PST 24
Peak memory 233220 kb
Host smart-2ab8fb1d-8b8c-466d-8b3b-cfb9b5efde59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380820990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2380820990
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2654918233
Short name T402
Test name
Test status
Simulation time 12794093272 ps
CPU time 31.12 seconds
Started Feb 21 02:22:41 PM PST 24
Finished Feb 21 02:23:13 PM PST 24
Peak memory 240716 kb
Host smart-05d76b2e-6460-478a-9e8e-8067a4db981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654918233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2654918233
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.1951685956
Short name T409
Test name
Test status
Simulation time 55405753 ps
CPU time 0.71 seconds
Started Feb 21 02:22:42 PM PST 24
Finished Feb 21 02:22:43 PM PST 24
Peak memory 216336 kb
Host smart-782f9e45-7fa8-48cb-b677-8db660f922a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951685956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.1951685956
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1617636443
Short name T327
Test name
Test status
Simulation time 538705750 ps
CPU time 5.02 seconds
Started Feb 21 02:22:47 PM PST 24
Finished Feb 21 02:22:52 PM PST 24
Peak memory 222680 kb
Host smart-955a58fd-ef7e-462e-8424-7f6016075312
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1617636443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1617636443
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3382443175
Short name T120
Test name
Test status
Simulation time 38056723912 ps
CPU time 102.24 seconds
Started Feb 21 02:22:46 PM PST 24
Finished Feb 21 02:24:28 PM PST 24
Peak memory 265740 kb
Host smart-13bd6899-4192-4e50-8bae-c5826eb89a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382443175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3382443175
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3088477612
Short name T741
Test name
Test status
Simulation time 3492792358 ps
CPU time 50.98 seconds
Started Feb 21 02:22:41 PM PST 24
Finished Feb 21 02:23:33 PM PST 24
Peak memory 216468 kb
Host smart-f11886d5-53ce-4d0f-8c12-50344bdcfbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088477612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3088477612
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.183840972
Short name T295
Test name
Test status
Simulation time 3849205275 ps
CPU time 14.96 seconds
Started Feb 21 02:22:41 PM PST 24
Finished Feb 21 02:22:57 PM PST 24
Peak memory 217472 kb
Host smart-4fa1b703-4cb6-4ad1-beaa-200afe5d2a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183840972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.183840972
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4055258137
Short name T423
Test name
Test status
Simulation time 350804808 ps
CPU time 1.44 seconds
Started Feb 21 02:22:40 PM PST 24
Finished Feb 21 02:22:43 PM PST 24
Peak memory 207604 kb
Host smart-d0a44c57-7e98-49a8-ac2f-e07d65e428fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055258137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4055258137
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3199019953
Short name T350
Test name
Test status
Simulation time 53016556 ps
CPU time 0.94 seconds
Started Feb 21 02:22:42 PM PST 24
Finished Feb 21 02:22:44 PM PST 24
Peak memory 206520 kb
Host smart-e8464de4-edb2-4768-ae66-fd6e2dd5a9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199019953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3199019953
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.229848574
Short name T962
Test name
Test status
Simulation time 2402229758 ps
CPU time 8.01 seconds
Started Feb 21 02:22:46 PM PST 24
Finished Feb 21 02:22:54 PM PST 24
Peak memory 233340 kb
Host smart-133390b2-d13c-4e7c-a4c8-edfe676ed6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229848574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.229848574
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2220976765
Short name T374
Test name
Test status
Simulation time 12305403 ps
CPU time 0.77 seconds
Started Feb 21 02:23:06 PM PST 24
Finished Feb 21 02:23:07 PM PST 24
Peak memory 204964 kb
Host smart-450518a1-d37e-4c18-93b7-de63e37675c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220976765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
220976765
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1684191163
Short name T700
Test name
Test status
Simulation time 3454104698 ps
CPU time 3.92 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:23:05 PM PST 24
Peak memory 233936 kb
Host smart-de3544a1-9962-4448-8256-573ce15862f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684191163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1684191163
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3454473937
Short name T606
Test name
Test status
Simulation time 47431528 ps
CPU time 0.71 seconds
Started Feb 21 02:22:50 PM PST 24
Finished Feb 21 02:22:51 PM PST 24
Peak memory 205156 kb
Host smart-b3bea32c-5d5e-46ea-964e-a5f8daff643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454473937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3454473937
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.394596890
Short name T390
Test name
Test status
Simulation time 3322985585 ps
CPU time 18.17 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:23:19 PM PST 24
Peak memory 256676 kb
Host smart-0bc6ae61-0935-445d-ab67-216602a87a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394596890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.394596890
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1062650362
Short name T704
Test name
Test status
Simulation time 29932755409 ps
CPU time 15.8 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:23:17 PM PST 24
Peak memory 235228 kb
Host smart-eb8b1887-6553-4955-b2c9-ab0aee8bc74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062650362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1062650362
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3019062659
Short name T45
Test name
Test status
Simulation time 1628284072 ps
CPU time 9.36 seconds
Started Feb 21 02:23:00 PM PST 24
Finished Feb 21 02:23:09 PM PST 24
Peak memory 239532 kb
Host smart-cd1634d5-186f-4975-b866-31599214756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019062659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3019062659
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.718857671
Short name T836
Test name
Test status
Simulation time 142551283 ps
CPU time 1.11 seconds
Started Feb 21 02:22:50 PM PST 24
Finished Feb 21 02:22:52 PM PST 24
Peak memory 216644 kb
Host smart-4888c9d2-cbbd-4971-8878-c5c176f6830a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718857671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.718857671
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1866050795
Short name T808
Test name
Test status
Simulation time 1880031089 ps
CPU time 9.98 seconds
Started Feb 21 02:23:02 PM PST 24
Finished Feb 21 02:23:12 PM PST 24
Peak memory 233568 kb
Host smart-318fc5bf-e065-4b09-88af-fa1a9de18b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866050795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1866050795
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.857249333
Short name T363
Test name
Test status
Simulation time 500416721 ps
CPU time 3.41 seconds
Started Feb 21 02:22:46 PM PST 24
Finished Feb 21 02:22:50 PM PST 24
Peak memory 216924 kb
Host smart-45ffdb2d-260e-4cad-b82c-3b7f2bf2cf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857249333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.857249333
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.508657247
Short name T431
Test name
Test status
Simulation time 18427883 ps
CPU time 0.7 seconds
Started Feb 21 02:22:47 PM PST 24
Finished Feb 21 02:22:48 PM PST 24
Peak memory 216280 kb
Host smart-8da54e36-d97b-46d4-9f93-b535d60c2f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508657247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.508657247
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.905222765
Short name T662
Test name
Test status
Simulation time 282887433 ps
CPU time 2.98 seconds
Started Feb 21 02:23:06 PM PST 24
Finished Feb 21 02:23:09 PM PST 24
Peak memory 219928 kb
Host smart-a8c96e6a-7f73-4015-8ce9-b7e027fea043
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905222765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.905222765
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4014966270
Short name T265
Test name
Test status
Simulation time 143992719775 ps
CPU time 367.34 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:29:08 PM PST 24
Peak memory 255512 kb
Host smart-1538db50-372e-4f02-ad4d-f72c667bc2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014966270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4014966270
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.711203096
Short name T733
Test name
Test status
Simulation time 51786218320 ps
CPU time 117.52 seconds
Started Feb 21 02:22:47 PM PST 24
Finished Feb 21 02:24:45 PM PST 24
Peak memory 216596 kb
Host smart-9161d0b1-48c3-4677-ac95-93334fe64a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711203096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.711203096
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1026309596
Short name T835
Test name
Test status
Simulation time 1043745392 ps
CPU time 4.27 seconds
Started Feb 21 02:22:47 PM PST 24
Finished Feb 21 02:22:52 PM PST 24
Peak memory 208268 kb
Host smart-3884765e-c13f-44d4-9109-b9b0145928ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026309596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1026309596
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1184055864
Short name T343
Test name
Test status
Simulation time 14155180 ps
CPU time 0.8 seconds
Started Feb 21 02:22:47 PM PST 24
Finished Feb 21 02:22:49 PM PST 24
Peak memory 205476 kb
Host smart-e96d5687-8be9-4da1-b4e8-2cf474cae11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184055864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1184055864
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2361507313
Short name T866
Test name
Test status
Simulation time 41264355 ps
CPU time 0.85 seconds
Started Feb 21 02:22:49 PM PST 24
Finished Feb 21 02:22:50 PM PST 24
Peak memory 205492 kb
Host smart-c210bd4c-4f78-4404-9927-ea4677ebcd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361507313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2361507313
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3032697152
Short name T849
Test name
Test status
Simulation time 761762518 ps
CPU time 2.5 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:23:04 PM PST 24
Peak memory 224588 kb
Host smart-41798e77-ee76-42f5-b301-793d54afd866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032697152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3032697152
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2116790476
Short name T770
Test name
Test status
Simulation time 15499913 ps
CPU time 0.73 seconds
Started Feb 21 02:23:17 PM PST 24
Finished Feb 21 02:23:18 PM PST 24
Peak memory 204996 kb
Host smart-3b8de35e-bd62-4e8c-ae70-207a1839e1b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116790476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
116790476
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1399348688
Short name T413
Test name
Test status
Simulation time 1002122845 ps
CPU time 3.91 seconds
Started Feb 21 02:23:18 PM PST 24
Finished Feb 21 02:23:22 PM PST 24
Peak memory 234104 kb
Host smart-21fe4185-13b7-4788-b3de-de7061a02fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399348688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1399348688
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.601140660
Short name T953
Test name
Test status
Simulation time 16170704 ps
CPU time 0.75 seconds
Started Feb 21 02:23:02 PM PST 24
Finished Feb 21 02:23:03 PM PST 24
Peak memory 205148 kb
Host smart-b9636ae2-7395-4b00-b139-488c2ae36655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601140660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.601140660
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.705049889
Short name T33
Test name
Test status
Simulation time 43820799586 ps
CPU time 126.32 seconds
Started Feb 21 02:23:18 PM PST 24
Finished Feb 21 02:25:25 PM PST 24
Peak memory 251436 kb
Host smart-8b60f741-cda9-426f-8140-3aa444fd82c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705049889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.705049889
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3439076556
Short name T800
Test name
Test status
Simulation time 15329474273 ps
CPU time 57.63 seconds
Started Feb 21 02:23:19 PM PST 24
Finished Feb 21 02:24:17 PM PST 24
Peak memory 252948 kb
Host smart-6c8ecd83-ac93-4e93-909d-08d45d009320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439076556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3439076556
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2749272124
Short name T155
Test name
Test status
Simulation time 202693001121 ps
CPU time 379.55 seconds
Started Feb 21 02:23:17 PM PST 24
Finished Feb 21 02:29:37 PM PST 24
Peak memory 252288 kb
Host smart-35236d07-0c0b-48e0-9072-b35d8e0c46c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749272124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2749272124
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3513064022
Short name T624
Test name
Test status
Simulation time 6890902857 ps
CPU time 22.27 seconds
Started Feb 21 02:23:25 PM PST 24
Finished Feb 21 02:23:48 PM PST 24
Peak memory 239620 kb
Host smart-0407c970-5949-4583-ae0e-c3148ca97ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513064022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3513064022
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3210734423
Short name T851
Test name
Test status
Simulation time 1222651031 ps
CPU time 4.74 seconds
Started Feb 21 02:23:18 PM PST 24
Finished Feb 21 02:23:23 PM PST 24
Peak memory 233528 kb
Host smart-e16ac523-90cc-4be7-9647-0c6012f8024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210734423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3210734423
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1689589300
Short name T880
Test name
Test status
Simulation time 3598646716 ps
CPU time 14.8 seconds
Started Feb 21 02:23:17 PM PST 24
Finished Feb 21 02:23:32 PM PST 24
Peak memory 234768 kb
Host smart-fa65c16c-ea60-4fc2-abf9-148ae5139a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689589300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1689589300
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1261118433
Short name T23
Test name
Test status
Simulation time 52960283 ps
CPU time 1.12 seconds
Started Feb 21 02:23:02 PM PST 24
Finished Feb 21 02:23:03 PM PST 24
Peak memory 216620 kb
Host smart-d66d4cab-2b3c-48e3-ac35-70506710e5bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261118433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1261118433
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.841574263
Short name T592
Test name
Test status
Simulation time 12601267221 ps
CPU time 11.35 seconds
Started Feb 21 02:23:11 PM PST 24
Finished Feb 21 02:23:22 PM PST 24
Peak memory 216584 kb
Host smart-01d661a8-ccfd-4b96-becb-98912961a51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841574263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
841574263
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.696696668
Short name T213
Test name
Test status
Simulation time 4833907288 ps
CPU time 8.14 seconds
Started Feb 21 02:23:17 PM PST 24
Finished Feb 21 02:23:25 PM PST 24
Peak memory 224688 kb
Host smart-3265c747-de26-4e38-b0e9-293593c04569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696696668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.696696668
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1618688799
Short name T549
Test name
Test status
Simulation time 16484676 ps
CPU time 0.78 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:23:02 PM PST 24
Peak memory 216248 kb
Host smart-0c4feb72-cdd1-4f3a-a6aa-dc85a4f0a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618688799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1618688799
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.776389832
Short name T127
Test name
Test status
Simulation time 783184797 ps
CPU time 5.36 seconds
Started Feb 21 02:23:27 PM PST 24
Finished Feb 21 02:23:33 PM PST 24
Peak memory 222596 kb
Host smart-0c160421-16ef-4fbe-91f3-642100774e80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=776389832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.776389832
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2296222808
Short name T143
Test name
Test status
Simulation time 265486114 ps
CPU time 1.16 seconds
Started Feb 21 02:23:17 PM PST 24
Finished Feb 21 02:23:19 PM PST 24
Peak memory 206912 kb
Host smart-705efb82-f670-45f1-8f43-2c183c7b7c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296222808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2296222808
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3758224089
Short name T281
Test name
Test status
Simulation time 5230142937 ps
CPU time 29.87 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:23:31 PM PST 24
Peak memory 216492 kb
Host smart-41af1cf4-831e-49d7-902c-da4b8b2c80d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758224089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3758224089
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3495611148
Short name T622
Test name
Test status
Simulation time 1122280619 ps
CPU time 4.98 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:23:06 PM PST 24
Peak memory 208276 kb
Host smart-629fceef-e815-4348-9fa8-04e0820d53dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495611148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3495611148
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3183073147
Short name T899
Test name
Test status
Simulation time 212586728 ps
CPU time 1.3 seconds
Started Feb 21 02:23:17 PM PST 24
Finished Feb 21 02:23:19 PM PST 24
Peak memory 208160 kb
Host smart-0215c597-42bf-4dd8-ade9-097f1ca93954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183073147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3183073147
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.238606449
Short name T861
Test name
Test status
Simulation time 41768622 ps
CPU time 0.75 seconds
Started Feb 21 02:23:01 PM PST 24
Finished Feb 21 02:23:02 PM PST 24
Peak memory 205512 kb
Host smart-63474aee-3f82-426d-9924-87e3e4070729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238606449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.238606449
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2066827004
Short name T223
Test name
Test status
Simulation time 39739684433 ps
CPU time 27.19 seconds
Started Feb 21 02:23:15 PM PST 24
Finished Feb 21 02:23:43 PM PST 24
Peak memory 232832 kb
Host smart-1c88828b-086e-4de2-9d41-03261846bcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066827004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2066827004
Directory /workspace/9.spi_device_upload/latest
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