Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.22	84.31	96.94		87.50	95.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.22	84.31	96.94		87.50	95.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T8,T11
1	0	Covered	T2,T8,T11
1	1	Covered	T2,T8,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T11
1	0	Covered	T2,T8,T11
1	1	Covered	T2,T8,T11

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1744122450	3250	0	0
SrcPulseCheck_M	536647317	3250	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744122450	3250	0	0
T2	728077	14	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	15	0	0
T9	10757	0	0	0
T10	113094	0	0	0
T11	381827	4	0	0
T12	30028	7	0	0
T13	114524	0	0	0
T14	35774	0	0	0
T15	447484	0	0	0
T16	1140600	20	0	0
T17	448332	0	0	0
T18	1296500	13	0	0
T26	0	2	0	0
T27	0	14	0	0
T55	240152	0	0	0
T56	0	4	0	0
T57	0	17	0	0
T58	0	21	0	0
T70	0	7	0	0
T73	1764082	0	0	0
T74	0	6	0	0
T75	0	7	0	0
T117	154126	0	0	0
T125	0	7	0	0
T126	0	27	0	0
T127	0	7	0	0
T128	0	4	0	0
T129	0	7	0	0
T130	0	7	0	0
T131	0	17	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	536647317	3250	0	0
T2	903562	14	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	15	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	4	0	0
T12	68673	7	0	0
T13	48240	0	0	0
T14	114176	0	0	0
T15	440116	0	0	0
T16	279248	20	0	0
T17	107134	0	0	0
T18	1825726	13	0	0
T26	0	2	0	0
T27	0	14	0	0
T55	93354	0	0	0
T56	0	4	0	0
T57	0	17	0	0
T58	0	21	0	0
T70	0	7	0	0
T73	349482	0	0	0
T74	0	6	0	0
T75	0	7	0	0
T117	20864	0	0	0
T125	0	7	0	0
T126	0	27	0	0
T127	0	7	0	0
T128	0	4	0	0
T129	0	7	0	0
T130	0	7	0	0
T131	0	17	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T12,T74,T75
1	0	Covered	T12,T74,T75
1	1	Covered	T12,T74,T75

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T74,T75
1	0	Covered	T12,T74,T75
1	1	Covered	T12,T74,T75

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	581374150	346	0	0
SrcPulseCheck_M	178882439	346	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	346	0	0
T12	15014	2	0	0
T13	57262	0	0	0
T14	17887	0	0	0
T15	223742	0	0	0
T16	570300	0	0	0
T17	224166	0	0	0
T18	648250	0	0	0
T55	120076	0	0	0
T70	0	2	0	0
T73	882041	0	0	0
T74	0	3	0	0
T75	0	2	0	0
T117	77063	0	0	0
T125	0	2	0	0
T126	0	14	0	0
T127	0	2	0	0
T129	0	2	0	0
T130	0	2	0	0
T131	0	17	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	346	0	0
T12	22891	2	0	0
T13	16080	0	0	0
T14	57088	0	0	0
T15	220058	0	0	0
T16	139624	0	0	0
T17	53567	0	0	0
T18	912863	0	0	0
T55	46677	0	0	0
T70	0	2	0	0
T73	174741	0	0	0
T74	0	3	0	0
T75	0	2	0	0
T117	10432	0	0	0
T125	0	2	0	0
T126	0	14	0	0
T127	0	2	0	0
T129	0	2	0	0
T130	0	2	0	0
T131	0	17	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T12,T74,T75
1	0	Covered	T12,T74,T75
1	1	Covered	T12,T74,T75

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T74,T75
1	0	Covered	T12,T74,T75
1	1	Covered	T12,T74,T75

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	581374150	507	0	0
SrcPulseCheck_M	178882439	507	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	507	0	0
T12	15014	5	0	0
T13	57262	0	0	0
T14	17887	0	0	0
T15	223742	0	0	0
T16	570300	0	0	0
T17	224166	0	0	0
T18	648250	0	0	0
T55	120076	0	0	0
T70	0	5	0	0
T73	882041	0	0	0
T74	0	3	0	0
T75	0	5	0	0
T117	77063	0	0	0
T125	0	5	0	0
T126	0	13	0	0
T127	0	5	0	0
T128	0	4	0	0
T129	0	5	0	0
T130	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	507	0	0
T12	22891	5	0	0
T13	16080	0	0	0
T14	57088	0	0	0
T15	220058	0	0	0
T16	139624	0	0	0
T17	53567	0	0	0
T18	912863	0	0	0
T55	46677	0	0	0
T70	0	5	0	0
T73	174741	0	0	0
T74	0	3	0	0
T75	0	5	0	0
T117	10432	0	0	0
T125	0	5	0	0
T126	0	13	0	0
T127	0	5	0	0
T128	0	4	0	0
T129	0	5	0	0
T130	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T8,T11
1	0	Covered	T2,T8,T11
1	1	Covered	T2,T8,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T11
1	0	Covered	T2,T8,T11
1	1	Covered	T2,T8,T11

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	581374150	2397	0	0
SrcPulseCheck_M	178882439	2397	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2397	0	0
T2	728077	14	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	15	0	0
T9	10757	0	0	0
T10	113094	0	0	0
T11	381827	4	0	0
T16	0	20	0	0
T18	0	13	0	0
T26	0	2	0	0
T27	0	14	0	0
T56	0	4	0	0
T57	0	17	0	0
T58	0	21	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178882439	2397	0	0
T2	903562	14	0	0
T4	96437	0	0	0
T5	1281	0	0	0
T7	144	0	0	0
T8	661675	15	0	0
T9	4376	0	0	0
T10	175030	0	0	0
T11	93952	4	0	0
T12	22891	0	0	0
T13	16080	0	0	0
T16	0	20	0	0
T18	0	13	0	0
T26	0	2	0	0
T27	0	14	0	0
T56	0	4	0	0
T57	0	17	0	0
T58	0	21	0	0