Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.60	94.22	84.31	96.94		87.50	95.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.60	94.22	84.31	96.94		87.50	95.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.60	94.22	84.31	96.94		87.50	95.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.74	98.52	94.56	98.61	89.36	97.29	96.09

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	96.74	100.00	87.80		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	84.73	100.00	71.43			67.50	100.00
u_passthrough	89.66	92.75	89.22		75.00	91.35	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	93.26	97.16	93.19		87.50	88.46	100.00
u_reg	99.64	99.54	99.29	100.00		99.37	100.00
u_s2p	86.75	100.00	78.57			68.42	100.00
u_scanmode_sync	100.00						100.00
u_spi_tpm	92.68	99.29	84.99		91.67	95.32	92.16
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	95.45	100.00	81.82			100.00	100.00
u_spid_status	96.26	100.00	89.13			95.89	100.00
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	88.22	100.00	70.73			96.43	85.71
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.12	81.67	59.07			62.50	81.25
u_tlul2sram_ingress	86.67	87.92	74.68			84.09	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_upload	91.23	98.60	74.15		100.00	94.12	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		225	212	94.22
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
ALWAYS	535	4	4	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
ALWAYS	562	0	0
ALWAYS	562	2	2	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
ALWAYS	576	0	0
ALWAYS	576	12	12	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
ALWAYS	778	3	3	100.00
ALWAYS	784	8	8	100.00
ALWAYS	822	9	9	100.00
ALWAYS	846	24	24	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	914	1	1	100.00
ALWAYS	957	5	3	60.00
ALWAYS	968	13	13	100.00
ALWAYS	1005	3	3	100.00
CONT_ASSIGN	1139	1	1	100.00
CONT_ASSIGN	1142	1	1	100.00
CONT_ASSIGN	1146	1	1	100.00
CONT_ASSIGN	1147	1	1	100.00
CONT_ASSIGN	1148	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1151	1	1	100.00
CONT_ASSIGN	1154	1	1	100.00
CONT_ASSIGN	1200	1	0	0.00
CONT_ASSIGN	1230	1	0	0.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1314	1	1	100.00
CONT_ASSIGN	1315	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1359	1	1	100.00
CONT_ASSIGN	1360	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1500	1	0	0.00
CONT_ASSIGN	1508	1	1	100.00
CONT_ASSIGN	1509	1	1	100.00
CONT_ASSIGN	1510	1	1	100.00
CONT_ASSIGN	1511	1	1	100.00
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1515	1	1	100.00
CONT_ASSIGN	1522	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1532	1	1	100.00
CONT_ASSIGN	1533	1	1	100.00
CONT_ASSIGN	1534	1	1	100.00
CONT_ASSIGN	1535	1	1	100.00
CONT_ASSIGN	1536	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1539	1	1	100.00
CONT_ASSIGN	1543	1	1	100.00
CONT_ASSIGN	1545	1	1	100.00
CONT_ASSIGN	1546	1	1	100.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1555	1	1	100.00
CONT_ASSIGN	1556	1	1	100.00
CONT_ASSIGN	1565	1	1	100.00
CONT_ASSIGN	1566	1	1	100.00
CONT_ASSIGN	1567	1	1	100.00
CONT_ASSIGN	1568	1	1	100.00
CONT_ASSIGN	1621	1	1	100.00
CONT_ASSIGN	1623	1	1	100.00
ALWAYS	1628	4	4	100.00
ALWAYS	1637	0	0
ALWAYS	1637	9	9	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1654	1	1	100.00
CONT_ASSIGN	1655	1	1	100.00
CONT_ASSIGN	1655	1	1	100.00
CONT_ASSIGN	1655	1	0	0.00
CONT_ASSIGN	1655	1	0	0.00
CONT_ASSIGN	1655	1	0	0.00
CONT_ASSIGN	1656	1	1	100.00
CONT_ASSIGN	1656	1	1	100.00
CONT_ASSIGN	1656	1	0	0.00
CONT_ASSIGN	1656	1	0	0.00
CONT_ASSIGN	1656	1	1	100.00
CONT_ASSIGN	1657	1	1	100.00
CONT_ASSIGN	1657	1	1	100.00
CONT_ASSIGN	1657	1	0	0.00
CONT_ASSIGN	1657	1	0	0.00
CONT_ASSIGN	1657	1	0	0.00
CONT_ASSIGN	1659	1	1	100.00
CONT_ASSIGN	1659	1	1	100.00
CONT_ASSIGN	1659	1	1	100.00
CONT_ASSIGN	1659	1	1	100.00
CONT_ASSIGN	1659	1	1	100.00
CONT_ASSIGN	1660	1	1	100.00
CONT_ASSIGN	1660	1	1	100.00
CONT_ASSIGN	1660	1	1	100.00
CONT_ASSIGN	1660	1	1	100.00
CONT_ASSIGN	1660	1	1	100.00
CONT_ASSIGN	1661	1	1	100.00
CONT_ASSIGN	1661	1	1	100.00
CONT_ASSIGN	1661	1	1	100.00
CONT_ASSIGN	1661	1	1	100.00
CONT_ASSIGN	1661	1	1	100.00
CONT_ASSIGN	1706	1	1	100.00
CONT_ASSIGN	1708	1	1	100.00
CONT_ASSIGN	1709	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1711	1	1	100.00
CONT_ASSIGN	1712	1	1	100.00
CONT_ASSIGN	1714	1	1	100.00
CONT_ASSIGN	1715	1	1	100.00
CONT_ASSIGN	1716	1	1	100.00
CONT_ASSIGN	1772	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
173	1	1
305	1	1
368	1	1
369	1	1
372	1	1
373	1	1
375	1	1
390	1	1
523	1	1
530	1	1
532	1	1
535	1	1
536	1	1
537	1	1
538	1	1
			MISSING_ELSE
543	1	1
549	1	1
552	1	1
553	1	1
557	1	1
562	1	1
563	1	1
567	1	1
568	1	1
576	1	1
577	1	1
596	1	1
597	1	1
601	1	1
602	1	1
604	1	1
605	1	1
607	1	1
608	1	1
610	1	1
611	1	1
640	1	1
641	1	1
642	1	1
778	2	2
779	1	1
784	1	1
786	1	1
787	1	1
794	1	1
798	1	1
799	1	1
803	1	1
804	1	1
822	1	1
824	1	1
829	1	1
835	1	1
836	1	1
837	1	1
838	1	1
839	1	1
840	1	1
			MISSING_ELSE
846	1	1
847	1	1
848	1	1
849	1	1
851	1	1
853	1	1
855	1	1
857	1	1
861	1	1
863	1	1
864	1	1
865	1	1
868	1	1
870	1	1
871	1	1
872	1	1
877	1	1
879	1	1
880	1	1
881	1	1
885	1	1
887	1	1
888	1	1
889	1	1
913	1	1
914	1	1
957	1	1
958	0	1
959	0	1
961	1	1
962	1	1
968	1	1
969	1	1
971	1	1
973	1	1
974	1	1
978	1	1
980	1	1
981	1	1
985	1	1
986	1	1
987	1	1
989	1	1
990	1	1
1005	2	2
1006	1	1
1139	1	1
1142	1	1
1146	1	1
1147	1	1
1148	1	1
1150	1	1
1151	1	1
1154	1	1
1200	0	1
1230	0	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1319	1	1
1323	1	1
1330	1	1
1331	1	1
1333	1	1
1337	1	1
1340	1	1
1343	1	1
1346	1	1
1349	1	1
1352	1	1
1359	1	1
1360	1	1
1399	1	1
1500	0	1
1508	1	1
1509	1	1
1510	1	1
1511	1	1
1512	1	1
1515	1	1
1522	1	1
1529	5	5
1532	1	1
1533	1	1
1534	1	1
1535	1	1
1536	1	1
1537	1	1
1539	1	1
1543	1	1
1545	1	1
1546	1	1
1553	1	1
1555	1	1
1556	1	1
1565	1	1
1566	1	1
1567	1	1
1568	1	1
1621	1	1
1623	1	1
1628	1	1
1629	1	1
1630	1	1
1631	1	1
			MISSING_ELSE
1637	1	1
1638	1	1
1640	1	1
1643	1	1
1644	1	1
1645	1	1
1646	1	1
1648	1	1
1649	1	1
1654	5	5
1655	2	5
1656	3	5
1657	2	5
1659	5	5
1660	5	5
1661	5	5
1706	1	1
1708	1	1
1709	1	1
1710	1	1
1711	1	1
1712	1	1
1714	1	1
1715	1	1
1716	1	1
1772	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T11

 LINE       695
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       706
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       808
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T11

 LINE       835
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       835
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T4,T11
1	0	Covered	T1,T2,T3

 LINE       835
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T2,T4,T11
1	Covered	T1,T2,T3

 LINE       835
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T11

 LINE       971
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1139
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T8

 LINE       1150
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T10

 LINE       1151
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T10

 LINE       1359
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T10

 LINE       1360
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T10

 LINE       1522
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

 LINE       1630
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1630
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1630
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1706
 EXPRESSION (tpm_rst_n | rst_spi_n)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       1772
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T34,T35

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	59	54	91.53
Total Bits	458	444	96.94
Total Bits 0->1	229	222	96.94
Total Bits 1->0	229	222	96.94

Ports	59	54	91.53
Port Bits	458	444	96.94
Port Bits 0->1	229	222	96.94
Port Bits 1->0	229	222	96.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T36,T27	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T10,T13	Yes	T1,T10,T13	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T22,T23,T24	Yes	T22,T23,T24	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T4,T8	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	OUTPUT
cio_sck_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
cio_csb_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
cio_sd_o[3:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
cio_tpm_csb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T2,*T4,*T11	Yes	T2,T4,T11	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T2,T11,T16	Yes	T2,T4,T11	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T2,T36,T37	Yes	T2,T36,T37	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T2,T36,T37	Yes	T2,T36,T37	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T2,T36,T27	Yes	T2,T36,T27	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T2,T36,T27	Yes	T2,T36,T27	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T2,T36,T37	Yes	T2,T36,T37	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T2,T36,T27	Yes	T2,T36,T27	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T2,T36,T27	Yes	T2,T36,T27	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T2,T36,T27	Yes	T2,T36,T27	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
sck_monitor_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	28	87.50
IF	535	3	3	100.00
IF	778	2	2	100.00
CASE	794	4	4	100.00
IF	835	3	3	100.00
CASE	851	7	5	71.43
IF	957	2	1	50.00
IF	971	5	4	80.00
IF	1005	2	2	100.00
IF	1630	2	2	100.00
IF	1640	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	535	if ((!rst_ni))
-2-:	537	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	778	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T8

	LineNo.	Expression
-1-:	794	case (cmd_dp_sel)
-2-:	808	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T2,T4,T8
DpUpload	-	Covered	T2,T8,T11
default	1	Covered	T2,T8,T11
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	835	if (((!sck_csb) && ((spi_mode == FlashMode) || (spi_mode == PassThrough))))
-2-:	838	if (cfg_tpm_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	851	case (spi_mode)
-2-:	853	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T2,T4,T8
FlashMode PassThrough	DpReadStatus	Covered	T2,T8,T10
FlashMode PassThrough	DpReadJEDEC	Covered	T2,T8,T10
FlashMode PassThrough	DpUpload	Covered	T2,T8,T11
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	957	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	971	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	978	case (spi_mode)
-3-:	985	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T5
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T2,T11,T13
0	PassThrough	0	Covered	T2,T4,T11
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1005	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T8

	LineNo.	Expression
-1-:	1630	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1640	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	20	20	100.00	19	95.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	20	20	100.00	19	95.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	581374150	581286990	0	0
CioSdoEnOKnown	581374150	581286990	0	0
CioSdoEnOffWhenInactive	581374150	581286990	0	0
FpvSecCmRegWeOnehotCheck_A	581374150	110	0	0
InterceptLevel_M	178883355	0	0	0
IntrReadbufFlipOKnown	581374150	581286990	0	0
IntrReadbufWatermarkOKnown	581374150	581286990	0	0
IntrTpmHeaderNotEmptyOKnown	581374150	581286990	0	0
IntrUploadCmdfifoNotEmptyOKnown	581374150	581286990	0	0
IntrUploadPayloadNotEmptyOKnown	581374150	581286990	0	0
IntrUploadPayloadOverflowOKnown	581374150	581286990	0	0
PayloadStartIdxWidthMatch_A	936	936	0	0
SpiModeKnown_A	581374150	581286990	0	0
TpmEnableWhenTpmCsbIdle_M	581374150	347	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	581374150	2151120	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	581374150	198308	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	581374150	2397	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	581374150	1767	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	581374150	256727	0	0
scanmodeKnown	581374150	581374150	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	110	0	0
T41	8387	30	0	0
T42	0	20	0	0
T43	0	10	0	0
T44	0	30	0	0
T45	0	20	0	0
T46	1340	0	0	0
T47	84429	0	0	0
T48	65855	0	0	0
T49	167090	0	0	0
T50	4667	0	0	0
T51	144750	0	0	0
T52	441928	0	0	0
T53	841832	0	0	0
T54	1032	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178883355	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	936	936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581286990	0	0
T1	3939	3873	0	0
T2	728077	728056	0	0
T3	1076	1003	0	0
T4	52565	52479	0	0
T5	3731	3665	0	0
T6	1332	1272	0	0
T7	2308	2238	0	0
T8	314306	314212	0	0
T9	10757	10678	0	0
T10	113094	113020	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	347	0	0
T1	3939	1	0	0
T2	728077	1	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	1	0	0
T6	1332	0	0	0
T7	2308	1	0	0
T8	314306	1	0	0
T9	10757	1	0	0
T10	113094	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T55	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2151120	0	0
T2	728077	10816	0	0
T3	1076	0	0	0
T4	52565	832	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	12480	0	0
T9	10757	0	0	0
T10	113094	2496	0	0
T11	381827	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	14144	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	198308	0	0
T2	728077	699	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	647	0	0
T9	10757	48	0	0
T10	113094	211	0	0
T11	381827	64	0	0
T16	0	839	0	0
T17	0	312	0	0
T18	0	385	0	0
T25	0	242	0	0
T26	0	555	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	2397	0	0
T2	728077	14	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	15	0	0
T9	10757	0	0	0
T10	113094	0	0	0
T11	381827	4	0	0
T16	0	20	0	0
T18	0	13	0	0
T26	0	2	0	0
T27	0	14	0	0
T56	0	4	0	0
T57	0	17	0	0
T58	0	21	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	1767	0	0
T2	728077	7	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	14	0	0
T9	10757	0	0	0
T10	113094	0	0	0
T11	381827	4	0	0
T16	0	16	0	0
T18	0	8	0	0
T26	0	1	0	0
T27	0	14	0	0
T56	0	4	0	0
T57	0	15	0	0
T58	0	13	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	256727	0	0
T2	728077	700	0	0
T3	1076	0	0	0
T4	52565	0	0	0
T5	3731	0	0	0
T6	1332	0	0	0
T7	2308	0	0	0
T8	314306	583	0	0
T9	10757	57	0	0
T10	113094	335	0	0
T11	381827	0	0	0
T16	0	884	0	0
T17	0	683	0	0
T25	0	422	0	0
T26	0	664	0	0
T59	0	724	0	0
T60	0	2971	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	581374150	581374150	0	0
T1	3939	3939	0	0
T2	728077	728077	0	0
T3	1076	1076	0	0
T4	52565	52565	0	0
T5	3731	3731	0	0
T6	1332	1332	0	0
T7	2308	2308	0	0
T8	314306	314306	0	0
T9	10757	10757	0	0
T10	113094	113094	0	0