Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.25	100.00	75.00			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.30	90.91	42.31			60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.72	85.00	42.31			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.89	77.78				50.00

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.03	100.00	78.12			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.11	95.00	78.12			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.66	99.29	91.20		91.67	96.13	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.85	100.00	65.38			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	100.00	73.08			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.85	95.00	73.08			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	32	24	75.00
Logical	32	24	75.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	172	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183944557	25871877	0	0
DepthKnown_A	183944557	139200466	0	0
RvalidKnown_A	183944557	139200466	0	0
WreadyKnown_A	183944557	139200466	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	183944557	25871877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	25871877	0	0
T2	127633	33580	0	0
T3	222208	0	0	0
T4	791679	55539	0	0
T5	19513	18052	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	164327	0	0
T11	44606	1026	0	0
T12	0	12132	0	0
T13	0	51239	0	0
T14	0	1826	0	0
T28	0	16771	0	0
T46	0	14498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	25871877	0	0
T2	127633	33580	0	0
T3	222208	0	0	0
T4	791679	55539	0	0
T5	19513	18052	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	164327	0	0
T11	44606	1026	0	0
T12	0	12132	0	0
T13	0	51239	0	0
T14	0	1826	0	0
T28	0	16771	0	0
T46	0	14498	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
172	1	1
173	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	32	28	87.50
Logical	32	28	87.50
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	172	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183944557	27169007	0	0
DepthKnown_A	183944557	139200466	0	0
RvalidKnown_A	183944557	139200466	0	0
WreadyKnown_A	183944557	139200466	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	183944557	27169007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	27169007	0	0
T2	127633	35337	0	0
T3	222208	0	0	0
T4	791679	57750	0	0
T5	19513	18948	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	170538	0	0
T11	44606	1084	0	0
T12	0	13620	0	0
T13	0	53059	0	0
T14	0	2076	0	0
T28	0	18142	0	0
T46	0	14952	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	27169007	0	0
T2	127633	35337	0	0
T3	222208	0	0	0
T4	791679	57750	0	0
T5	19513	18948	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	170538	0	0
T11	44606	1084	0	0
T12	0	13620	0	0
T13	0	53059	0	0
T14	0	2076	0	0
T28	0	18142	0	0
T46	0	14952	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	1	50.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	0	1
			MISSING_ELSE
175	0	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	11	42.31
Logical	26	11	42.31
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	88	3	1	33.33
TERNARY	180	2	1	50.00
IF	70	3	3	100.00
IF	165	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183944557	0	0	0
DepthKnown_A	183944557	139200466	0	0
RvalidKnown_A	183944557	139200466	0	0
WreadyKnown_A	183944557	139200466	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	183944557	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	139200466	0	0
T2	127633	127633	0	0
T3	222208	222208	0	0
T4	791679	560060	0	0
T5	19513	19236	0	0
T6	99763	0	0	0
T7	107130	0	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	139990	0	0
T11	44606	44306	0	0
T12	0	146284	0	0
T13	0	472499	0	0
T14	0	65202	0	0
T15	0	15698	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	32	25	78.12
Logical	32	25	78.12
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T10
1	0	1	Covered	T4,T7,T10
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T4,T7,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T10

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	172	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T10
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183944557	8721162	0	0
DepthKnown_A	183944557	42823660	0	0
RvalidKnown_A	183944557	42823660	0	0
WreadyKnown_A	183944557	42823660	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	183944557	8721162	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	8721162	0	0
T4	791679	63834	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	40594	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	96651	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	76645	0	0
T18	0	26530	0	0
T19	0	62994	0	0
T28	0	28154	0	0
T29	0	76842	0	0
T30	0	40733	0	0
T47	0	525	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	8721162	0	0
T4	791679	63834	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	40594	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	96651	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	76645	0	0
T18	0	26530	0	0
T19	0	62994	0	0
T28	0	28154	0	0
T29	0	76842	0	0
T30	0	40733	0	0
T47	0	525	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	17	65.38
Logical	26	17	65.38
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T4,T7,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T7,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T7,T10

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T10

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	183944557	280308	0	0
DepthKnown_A	183944557	42823660	0	0
RvalidKnown_A	183944557	42823660	0	0
WreadyKnown_A	183944557	42823660	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	183944557	280308	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	280308	0	0
T4	791679	2057	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	1304	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	3111	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	2467	0	0
T18	0	854	0	0
T19	0	2013	0	0
T28	0	905	0	0
T29	0	2473	0	0
T30	0	1310	0	0
T47	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	42823660	0	0
T4	791679	219736	0	0
T5	19513	0	0	0
T6	99763	90808	0	0
T7	107130	103792	0	0
T8	144	144	0	0
T9	116799	111831	0	0
T10	176201	338400	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	283632	0	0
T18	0	131928	0	0
T28	0	76280	0	0
T29	0	160816	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	183944557	280308	0	0
T4	791679	2057	0	0
T5	19513	0	0	0
T6	99763	0	0	0
T7	107130	1304	0	0
T8	144	0	0	0
T9	116799	0	0	0
T10	176201	3111	0	0
T11	44606	0	0	0
T12	146284	0	0	0
T13	474332	0	0	0
T16	0	2467	0	0
T18	0	854	0	0
T19	0	2013	0	0
T28	0	905	0	0
T29	0	2473	0	0
T30	0	1310	0	0
T47	0	18	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	26	19	73.08
Logical	26	19	73.08
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	563350110	3674213	0	0
DepthKnown_A	563350110	563265295	0	0
RvalidKnown_A	563350110	563265295	0	0
WreadyKnown_A	563350110	563265295	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	563350110	3674213	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	3674213	0	0
T2	75658	4707	0	0
T3	670150	832	0	0
T4	168806	12480	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	0	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	29952	0	0
T11	52621	832	0	0
T12	0	2670	0	0
T13	0	9984	0	0
T14	0	832	0	0
T15	0	840	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	563265295	0	0
T1	1405	1317	0	0
T2	75658	75579	0	0
T3	670150	670084	0	0
T4	168806	168799	0	0
T5	86010	85950	0	0
T6	641971	641914	0	0
T7	633748	633694	0	0
T8	1331	1269	0	0
T9	245284	245225	0	0
T10	504120	504082	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	563265295	0	0
T1	1405	1317	0	0
T2	75658	75579	0	0
T3	670150	670084	0	0
T4	168806	168799	0	0
T5	86010	85950	0	0
T6	641971	641914	0	0
T7	633748	633694	0	0
T8	1331	1269	0	0
T9	245284	245225	0	0
T10	504120	504082	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	563265295	0	0
T1	1405	1317	0	0
T2	75658	75579	0	0
T3	670150	670084	0	0
T4	168806	168799	0	0
T5	86010	85950	0	0
T6	641971	641914	0	0
T7	633748	633694	0	0
T8	1331	1269	0	0
T9	245284	245225	0	0
T10	504120	504082	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	563350110	3674213	0	0
T2	75658	4707	0	0
T3	670150	832	0	0
T4	168806	12480	0	0
T5	86010	832	0	0
T6	641971	0	0	0
T7	633748	0	0	0
T8	1331	0	0	0
T9	245284	0	0	0
T10	504120	29952	0	0
T11	52621	832	0	0
T12	0	2670	0	0
T13	0	9984	0	0
T14	0	832	0	0
T15	0	840	0	0