Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7110190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7419700

1

T1

929

T3

887

T4

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9467589	1			T1	50		T2	75		T3	12
values[0x0]	2531045	1			T1	445		T3	435		T4	15
values[0x1]	2531256	1			T1	478		T3	452		T4	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5154223	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9375667

1

T1

943

T2

27

T3

892

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55281	1			T1	11		T6	1		T9	3
valid_sources[0x01]	56246	1			T1	17		T4	1		T9	7
valid_sources[0x02]	56378	1			T6	1		T9	5		T15	4
valid_sources[0x03]	54481	1			T1	5		T9	6		T15	1
valid_sources[0x04]	57371	1			T1	11		T2	4		T9	6
valid_sources[0x05]	54293	1			T1	1		T6	1		T9	1
valid_sources[0x06]	56544	1			T1	41		T6	1		T9	6
valid_sources[0x07]	55388	1			T15	3		T18	4		T19	1
valid_sources[0x08]	55771	1			T1	4		T9	2		T18	5
valid_sources[0x09]	57518	1			T9	9		T15	4		T13	7
valid_sources[0x0a]	51676	1			T9	1		T15	5		T18	5
valid_sources[0x0b]	55181	1			T1	3		T9	3		T15	4
valid_sources[0x0c]	56538	1			T1	3		T9	1		T15	2
valid_sources[0x0d]	58548	1			T6	1		T9	5		T15	1
valid_sources[0x0e]	58783	1			T1	5		T6	1		T9	4
valid_sources[0x0f]	56268	1			T1	1		T6	1		T9	5
valid_sources[0x10]	56350	1			T4	8		T9	5		T15	1
valid_sources[0x11]	62589	1			T1	18		T9	4		T15	8
valid_sources[0x12]	57005	1			T6	1		T9	2		T15	4
valid_sources[0x13]	58927	1			T1	11		T6	2		T9	3
valid_sources[0x14]	55185	1			T1	5		T9	4		T15	5
valid_sources[0x15]	56447	1			T9	1		T15	4		T18	3
valid_sources[0x16]	58002	1			T1	11		T2	10		T6	1
valid_sources[0x17]	54324	1			T2	13		T6	2		T9	6
valid_sources[0x18]	58396	1			T9	2		T15	6		T18	3
valid_sources[0x19]	60007	1			T1	11		T9	2		T15	5
valid_sources[0x1a]	57550	1			T1	2		T9	5		T15	2
valid_sources[0x1b]	55695	1			T1	2		T2	6		T6	1
valid_sources[0x1c]	52608	1			T1	7		T2	2		T9	7
valid_sources[0x1d]	54816	1			T1	4		T6	2		T9	2
valid_sources[0x1e]	58136	1			T2	5		T9	5		T15	1
valid_sources[0x1f]	56067	1			T6	1		T9	6		T15	5
valid_sources[0x20]	59768	1			T6	2		T9	4		T15	1
valid_sources[0x21]	53377	1			T2	2		T9	2		T15	2
valid_sources[0x22]	56611	1			T1	37		T4	2		T6	1
valid_sources[0x23]	62387	1			T8	2		T9	10		T15	5
valid_sources[0x24]	61131	1			T6	2		T9	3		T10	948
valid_sources[0x25]	56387	1			T6	1		T9	2		T15	3
valid_sources[0x26]	57004	1			T6	2		T9	3		T15	6
valid_sources[0x27]	57665	1			T1	1		T6	1		T9	3
valid_sources[0x28]	52839	1			T6	1		T9	6		T15	1
valid_sources[0x29]	56890	1			T1	24		T6	1		T9	2
valid_sources[0x2a]	53303	1			T9	5		T15	1		T18	4
valid_sources[0x2b]	56069	1			T9	6		T15	3		T18	4
valid_sources[0x2c]	56850	1			T6	1		T9	3		T15	4
valid_sources[0x2d]	54700	1			T9	4		T15	3		T18	1
valid_sources[0x2e]	60007	1			T15	3		T19	1		T13	3
valid_sources[0x2f]	55067	1			T1	1		T9	2		T15	7
valid_sources[0x30]	55241	1			T9	4		T15	7		T18	1
valid_sources[0x31]	53927	1			T6	1		T9	4		T15	6
valid_sources[0x32]	58083	1			T6	3		T9	3		T15	7
valid_sources[0x33]	57019	1			T9	6		T15	4		T18	7
valid_sources[0x34]	55354	1			T9	3		T18	5		T13	4
valid_sources[0x35]	54675	1			T1	5		T9	2		T15	3
valid_sources[0x36]	54071	1			T9	7		T15	3		T18	5
valid_sources[0x37]	54555	1			T1	5		T6	3		T9	5
valid_sources[0x38]	56810	1			T9	5		T15	1		T20	1
valid_sources[0x39]	55683	1			T1	13		T6	1		T9	2
valid_sources[0x3a]	58333	1			T1	7		T9	3		T15	3
valid_sources[0x3b]	56595	1			T1	4		T6	2		T9	5
valid_sources[0x3c]	56749	1			T9	1		T15	3		T18	3
valid_sources[0x3d]	58774	1			T1	5		T7	1		T9	3
valid_sources[0x3e]	58287	1			T2	2		T9	8		T18	6
valid_sources[0x3f]	54217	1			T1	12		T4	10		T6	3
valid_sources[0x40]	57898	1			T9	3		T15	3		T18	5
valid_sources[0x41]	55430	1			T6	1		T9	4		T15	3
valid_sources[0x42]	63514	1			T1	2		T9	2		T15	6
valid_sources[0x43]	56703	1			T9	3		T15	3		T13	1
valid_sources[0x44]	55446	1			T2	7		T6	2		T9	6
valid_sources[0x45]	63281	1			T1	4		T15	1		T18	4
valid_sources[0x46]	57446	1			T9	4		T15	5		T18	4
valid_sources[0x47]	55478	1			T1	10		T9	3		T15	1
valid_sources[0x48]	56177	1			T8	10		T9	5		T15	3
valid_sources[0x49]	55696	1			T9	4		T15	3		T18	2
valid_sources[0x4a]	58225	1			T1	4		T6	1		T9	2
valid_sources[0x4b]	53105	1			T9	1		T15	6		T18	3
valid_sources[0x4c]	55134	1			T8	1		T9	3		T15	4
valid_sources[0x4d]	52510	1			T6	2		T9	2		T15	3
valid_sources[0x4e]	53873	1			T1	2		T9	2		T15	1
valid_sources[0x4f]	58418	1			T1	28		T6	1		T9	3
valid_sources[0x50]	54268	1			T9	3		T15	7		T18	1
valid_sources[0x51]	55876	1			T9	6		T15	4		T18	6
valid_sources[0x52]	62190	1			T6	2		T9	6		T15	7
valid_sources[0x53]	57255	1			T6	2		T9	4		T15	6
valid_sources[0x54]	56794	1			T6	4		T9	4		T18	1
valid_sources[0x55]	56690	1			T1	32		T6	2		T9	10
valid_sources[0x56]	56122	1			T9	5		T15	3		T18	2
valid_sources[0x57]	55467	1			T6	1		T9	3		T15	4
valid_sources[0x58]	56039	1			T6	1		T9	4		T15	3
valid_sources[0x59]	54369	1			T6	1		T9	1		T15	2
valid_sources[0x5a]	54981	1			T9	2		T15	3		T18	3
valid_sources[0x5b]	58985	1			T6	1		T9	3		T15	2
valid_sources[0x5c]	55199	1			T6	1		T15	1		T18	3
valid_sources[0x5d]	52340	1			T5	883		T6	1		T9	4
valid_sources[0x5e]	54849	1			T1	16		T9	6		T15	2
valid_sources[0x5f]	58252	1			T1	3		T9	4		T15	5
valid_sources[0x60]	55568	1			T2	1		T6	1		T9	8
valid_sources[0x61]	58719	1			T1	7		T7	3		T9	6
valid_sources[0x62]	60597	1			T3	899		T9	4		T15	5
valid_sources[0x63]	60066	1			T6	1		T9	3		T15	1
valid_sources[0x64]	59548	1			T4	3		T6	1		T9	2
valid_sources[0x65]	54657	1			T1	5		T9	1		T15	1
valid_sources[0x66]	57347	1			T1	12		T9	2		T15	1
valid_sources[0x67]	54533	1			T1	5		T9	2		T15	3
valid_sources[0x68]	59766	1			T6	1		T9	2		T15	1
valid_sources[0x69]	56179	1			T1	6		T6	1		T9	4
valid_sources[0x6a]	54497	1			T1	9		T8	1		T9	2
valid_sources[0x6b]	56944	1			T1	1		T9	4		T15	2
valid_sources[0x6c]	63975	1			T1	1		T4	1		T9	7
valid_sources[0x6d]	62108	1			T1	8		T6	3		T9	4
valid_sources[0x6e]	63039	1			T8	4		T9	5		T15	4
valid_sources[0x6f]	57900	1			T9	3		T15	8		T18	5
valid_sources[0x70]	59122	1			T4	2		T9	4		T15	3
valid_sources[0x71]	55444	1			T1	1		T6	1		T9	3
valid_sources[0x72]	53851	1			T1	21		T9	3		T15	2
valid_sources[0x73]	52015	1			T1	2		T7	39		T9	4
valid_sources[0x74]	56056	1			T1	5		T6	2		T9	6
valid_sources[0x75]	57992	1			T7	7		T9	5		T15	3
valid_sources[0x76]	53404	1			T6	2		T15	1		T13	4
valid_sources[0x77]	55033	1			T1	2		T9	6		T15	1
valid_sources[0x78]	56960	1			T1	22		T9	4		T15	2
valid_sources[0x79]	56726	1			T1	19		T2	2		T9	3
valid_sources[0x7a]	64866	1			T1	1		T9	4		T18	4
valid_sources[0x7b]	54562	1			T6	2		T9	3		T15	4
valid_sources[0x7c]	54277	1			T1	9		T9	3		T15	1
valid_sources[0x7d]	55128	1			T6	2		T9	6		T18	5
valid_sources[0x7e]	57267	1			T9	7		T15	2		T18	6
valid_sources[0x7f]	59534	1			T6	1		T9	3		T15	5
valid_sources[0x80]	53060	1			T1	9		T6	1		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2890379

1

T1

12

T3

5

T5

1

values[0x0]

all_enables

biggest_size

2282508

1

T1

443

T3

433

T4

13

values[0x1]

all_enables

biggest_size

2246813

1

T1

474

T3

449

T4

16