Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

7128630

1

T1

44

T2

75

T3

12

full_word

7418663

1

T1

929

T3

887

T4

29

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	14546933	1			T1	973		T2	75		T3	899
auto[TlIntgErrCmd]	117	1			T103	6		T106	12		T107	9
auto[TlIntgErrData]	113	1			T103	9		T106	11		T107	6
auto[TlIntgErrBoth]	130	1			T103	5		T106	7		T107	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9469358

1

T1

50

T2

75

T3

12

auto[1]

5077935

1

T1

923

T3

887

T4

36

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6578694	1			T1	38		T2	75		T3	7
auto[TlIntgErrNone]	partial	auto[1]	549608	1			T1	6		T3	5		T4	7
auto[TlIntgErrNone]	full_word	auto[0]	2890504	1			T1	12		T3	5		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	4528127	1			T1	917		T3	882		T4	29
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T103	1		T106	6		T107	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T103	4		T106	5		T107	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T174	1		T175	1		T176	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T103	1		T106	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T103	5		T106	5		T107	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T103	4		T106	3		T107	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T106	1		T171	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T106	2		T107	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T103	1		T106	2		T107	3
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T103	3		T106	3		T107	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T106	1		T121	1		T172	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T103	1		T106	1		T177	2