Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T21,T31
1	0	Covered	T11,T21,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T18
1	0	Unreachable
1	1	Covered	T11,T21,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T21,T23

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T21,T23
1	0	Covered	T11,T21,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T11,T21,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T11,T21

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T11,T21
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1042100279	839432142	0	0
CheckNGreaterZero_A	2814	2814	0	0
GntImpliesReady_A	1042100279	4705389	0	0
GntImpliesValid_A	1042100279	4705389	0	0
GrantKnown_A	1042100279	839432142	0	0
IdxKnown_A	1042100279	839432142	0	0
IndexIsCorrect_A	1042100279	4705389	0	0
LockArbDecision_A	1042100279	0	0	0
NoReadyValidNoGrant_A	1042100279	0	0	0
ReadyAndValidImplyGrant_A	1042100279	4705389	0	0
ReqAndReadyImplyGrant_A	1042100279	4705389	0	0
ReqImpliesValid_A	1042100279	4705389	0	0
ReqStaysHighUntilGranted0_M	1042100279	0	0	0
RoundRobin_A	1042100279	7	0	938
ValidKnown_A	1042100279	839432142	0	0
gen_data_port_assertion.DataFlow_A	1042100279	4705389	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	839432142	0	0
T1	10880	10754	0	0
T2	1598	1519	0	0
T3	35807	35734	0	0
T4	6137	4682	0	0
T5	157024	141525	0	0
T6	1333	1277	0	0
T7	2063	1978	0	0
T8	7922	6356	0	0
T9	431536	247692	0	0
T10	5914	5396	0	0
T11	310255	304005	0	0
T13	485064	242532	0	0
T15	17920	8960	0	0
T16	0	76546	0	0
T18	221832	103744	0	0
T20	68664	65560	0	0
T21	0	183256	0	0
T22	0	576	0	0
T31	0	4248	0	0
T32	0	275408	0	0
T50	0	154320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	4705389	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	620510	11118	0	0
T12	42486	0	0	0
T13	0	832	0	0
T14	272580	0	0	0
T15	0	832	0	0
T16	153780	832	0	0
T17	87420	0	0	0
T21	225600	8331	0	0
T23	1460162	2191	0	0
T29	0	5100	0	0
T30	0	8566	0	0
T31	0	231	0	0
T32	0	22273	0	0
T33	0	102	0	0
T42	192146	0	0	0
T43	89248	0	0	0
T44	452992	0	0	0
T51	0	4093	0	0
T52	0	3	0	0
T53	0	2761	0	0
T54	0	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	4705389	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	620510	11118	0	0
T12	42486	0	0	0
T13	0	832	0	0
T14	272580	0	0	0
T15	0	832	0	0
T16	153780	832	0	0
T17	87420	0	0	0
T21	225600	8331	0	0
T23	1460162	2191	0	0
T29	0	5100	0	0
T30	0	8566	0	0
T31	0	231	0	0
T32	0	22273	0	0
T33	0	102	0	0
T42	192146	0	0	0
T43	89248	0	0	0
T44	452992	0	0	0
T51	0	4093	0	0
T52	0	3	0	0
T53	0	2761	0	0
T54	0	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	839432142	0	0
T1	10880	10754	0	0
T2	1598	1519	0	0
T3	35807	35734	0	0
T4	6137	4682	0	0
T5	157024	141525	0	0
T6	1333	1277	0	0
T7	2063	1978	0	0
T8	7922	6356	0	0
T9	431536	247692	0	0
T10	5914	5396	0	0
T11	310255	304005	0	0
T13	485064	242532	0	0
T15	17920	8960	0	0
T16	0	76546	0	0
T18	221832	103744	0	0
T20	68664	65560	0	0
T21	0	183256	0	0
T22	0	576	0	0
T31	0	4248	0	0
T32	0	275408	0	0
T50	0	154320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	839432142	0	0
T1	10880	10754	0	0
T2	1598	1519	0	0
T3	35807	35734	0	0
T4	6137	4682	0	0
T5	157024	141525	0	0
T6	1333	1277	0	0
T7	2063	1978	0	0
T8	7922	6356	0	0
T9	431536	247692	0	0
T10	5914	5396	0	0
T11	310255	304005	0	0
T13	485064	242532	0	0
T15	17920	8960	0	0
T16	0	76546	0	0
T18	221832	103744	0	0
T20	68664	65560	0	0
T21	0	183256	0	0
T22	0	576	0	0
T31	0	4248	0	0
T32	0	275408	0	0
T50	0	154320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	4705389	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	620510	11118	0	0
T12	42486	0	0	0
T13	0	832	0	0
T14	272580	0	0	0
T15	0	832	0	0
T16	153780	832	0	0
T17	87420	0	0	0
T21	225600	8331	0	0
T23	1460162	2191	0	0
T29	0	5100	0	0
T30	0	8566	0	0
T31	0	231	0	0
T32	0	22273	0	0
T33	0	102	0	0
T42	192146	0	0	0
T43	89248	0	0	0
T44	452992	0	0	0
T51	0	4093	0	0
T52	0	3	0	0
T53	0	2761	0	0
T54	0	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	4705389	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	620510	11118	0	0
T12	42486	0	0	0
T13	0	832	0	0
T14	272580	0	0	0
T15	0	832	0	0
T16	153780	832	0	0
T17	87420	0	0	0
T21	225600	8331	0	0
T23	1460162	2191	0	0
T29	0	5100	0	0
T30	0	8566	0	0
T31	0	231	0	0
T32	0	22273	0	0
T33	0	102	0	0
T42	192146	0	0	0
T43	89248	0	0	0
T44	452992	0	0	0
T51	0	4093	0	0
T52	0	3	0	0
T53	0	2761	0	0
T54	0	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	4705389	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	620510	11118	0	0
T12	42486	0	0	0
T13	0	832	0	0
T14	272580	0	0	0
T15	0	832	0	0
T16	153780	832	0	0
T17	87420	0	0	0
T21	225600	8331	0	0
T23	1460162	2191	0	0
T29	0	5100	0	0
T30	0	8566	0	0
T31	0	231	0	0
T32	0	22273	0	0
T33	0	102	0	0
T42	192146	0	0	0
T43	89248	0	0	0
T44	452992	0	0	0
T51	0	4093	0	0
T52	0	3	0	0
T53	0	2761	0	0
T54	0	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	4705389	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	620510	11118	0	0
T12	42486	0	0	0
T13	0	832	0	0
T14	272580	0	0	0
T15	0	832	0	0
T16	153780	832	0	0
T17	87420	0	0	0
T21	225600	8331	0	0
T23	1460162	2191	0	0
T29	0	5100	0	0
T30	0	8566	0	0
T31	0	231	0	0
T32	0	22273	0	0
T33	0	102	0	0
T42	192146	0	0	0
T43	89248	0	0	0
T44	452992	0	0	0
T51	0	4093	0	0
T52	0	3	0	0
T53	0	2761	0	0
T54	0	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	7	0	938
T38	486568	0	0	1
T39	194685	0	0	1
T55	428495	1	0	1
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	119095	0	0	1
T63	908	0	0	1
T64	1622	0	0	1
T65	1236	0	0	1
T66	862540	0	0	1
T67	36661	0	0	1
T68	108997	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	839432142	0	0
T1	10880	10754	0	0
T2	1598	1519	0	0
T3	35807	35734	0	0
T4	6137	4682	0	0
T5	157024	141525	0	0
T6	1333	1277	0	0
T7	2063	1978	0	0
T8	7922	6356	0	0
T9	431536	247692	0	0
T10	5914	5396	0	0
T11	310255	304005	0	0
T13	485064	242532	0	0
T15	17920	8960	0	0
T16	0	76546	0	0
T18	221832	103744	0	0
T20	68664	65560	0	0
T21	0	183256	0	0
T22	0	576	0	0
T31	0	4248	0	0
T32	0	275408	0	0
T50	0	154320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042100279	4705389	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	620510	11118	0	0
T12	42486	0	0	0
T13	0	832	0	0
T14	272580	0	0	0
T15	0	832	0	0
T16	153780	832	0	0
T17	87420	0	0	0
T21	225600	8331	0	0
T23	1460162	2191	0	0
T29	0	5100	0	0
T30	0	8566	0	0
T31	0	231	0	0
T32	0	22273	0	0
T33	0	102	0	0
T42	192146	0	0	0
T43	89248	0	0	0
T44	452992	0	0	0
T51	0	4093	0	0
T52	0	3	0	0
T53	0	2761	0	0
T54	0	81	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T21,T31
1	0	Covered	T11,T21,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T18
1	0	Unreachable
1	1	Covered	T11,T21,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T21,T31
0	0	1	Unreachable
0	0	0	Covered	T4,T8,T18

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	200649506	41408804	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	200649506	957108	0	0
GntImpliesValid_A	200649506	957108	0	0
GrantKnown_A	200649506	41408804	0	0
IdxKnown_A	200649506	41408804	0	0
IndexIsCorrect_A	200649506	957108	0	0
LockArbDecision_A	200649506	0	0	0
NoReadyValidNoGrant_A	200649506	0	0	0
ReadyAndValidImplyGrant_A	200649506	957108	0	0
ReqAndReadyImplyGrant_A	200649506	957108	0	0
ReqImpliesValid_A	200649506	957108	0	0
ReqStaysHighUntilGranted0_M	200649506	0	0	0
RoundRobin_A	200649506	0	0	0
ValidKnown_A	200649506	41408804	0	0
gen_data_port_assertion.DataFlow_A	200649506	957108	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	41408804	0	0
T4	1129	864	0	0
T5	15401	0	0	0
T8	1471	1440	0	0
T9	183347	0	0	0
T10	305	0	0	0
T11	310255	111144	0	0
T13	242532	0	0	0
T15	8960	0	0	0
T18	110916	103744	0	0
T20	68664	65560	0	0
T21	0	183256	0	0
T22	0	576	0	0
T31	0	4248	0	0
T32	0	275408	0	0
T50	0	154320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	957108	0	0
T11	310255	4247	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	4615	0	0
T23	730081	0	0	0
T29	0	5100	0	0
T30	0	7530	0	0
T31	0	231	0	0
T32	0	10534	0	0
T33	0	102	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T51	0	4093	0	0
T53	0	2211	0	0
T54	0	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	957108	0	0
T11	310255	4247	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	4615	0	0
T23	730081	0	0	0
T29	0	5100	0	0
T30	0	7530	0	0
T31	0	231	0	0
T32	0	10534	0	0
T33	0	102	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T51	0	4093	0	0
T53	0	2211	0	0
T54	0	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	41408804	0	0
T4	1129	864	0	0
T5	15401	0	0	0
T8	1471	1440	0	0
T9	183347	0	0	0
T10	305	0	0	0
T11	310255	111144	0	0
T13	242532	0	0	0
T15	8960	0	0	0
T18	110916	103744	0	0
T20	68664	65560	0	0
T21	0	183256	0	0
T22	0	576	0	0
T31	0	4248	0	0
T32	0	275408	0	0
T50	0	154320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	41408804	0	0
T4	1129	864	0	0
T5	15401	0	0	0
T8	1471	1440	0	0
T9	183347	0	0	0
T10	305	0	0	0
T11	310255	111144	0	0
T13	242532	0	0	0
T15	8960	0	0	0
T18	110916	103744	0	0
T20	68664	65560	0	0
T21	0	183256	0	0
T22	0	576	0	0
T31	0	4248	0	0
T32	0	275408	0	0
T50	0	154320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	957108	0	0
T11	310255	4247	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	4615	0	0
T23	730081	0	0	0
T29	0	5100	0	0
T30	0	7530	0	0
T31	0	231	0	0
T32	0	10534	0	0
T33	0	102	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T51	0	4093	0	0
T53	0	2211	0	0
T54	0	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	957108	0	0
T11	310255	4247	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	4615	0	0
T23	730081	0	0	0
T29	0	5100	0	0
T30	0	7530	0	0
T31	0	231	0	0
T32	0	10534	0	0
T33	0	102	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T51	0	4093	0	0
T53	0	2211	0	0
T54	0	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	957108	0	0
T11	310255	4247	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	4615	0	0
T23	730081	0	0	0
T29	0	5100	0	0
T30	0	7530	0	0
T31	0	231	0	0
T32	0	10534	0	0
T33	0	102	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T51	0	4093	0	0
T53	0	2211	0	0
T54	0	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	957108	0	0
T11	310255	4247	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	4615	0	0
T23	730081	0	0	0
T29	0	5100	0	0
T30	0	7530	0	0
T31	0	231	0	0
T32	0	10534	0	0
T33	0	102	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T51	0	4093	0	0
T53	0	2211	0	0
T54	0	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	41408804	0	0
T4	1129	864	0	0
T5	15401	0	0	0
T8	1471	1440	0	0
T9	183347	0	0	0
T10	305	0	0	0
T11	310255	111144	0	0
T13	242532	0	0	0
T15	8960	0	0	0
T18	110916	103744	0	0
T20	68664	65560	0	0
T21	0	183256	0	0
T22	0	576	0	0
T31	0	4248	0	0
T32	0	275408	0	0
T50	0	154320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	957108	0	0
T11	310255	4247	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	4615	0	0
T23	730081	0	0	0
T29	0	5100	0	0
T30	0	7530	0	0
T31	0	231	0	0
T32	0	10534	0	0
T33	0	102	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T51	0	4093	0	0
T53	0	2211	0	0
T54	0	81	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T21,T23

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T21,T23
1	0	Covered	T11,T21,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T11,T21,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T21,T23
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	200649506	157307086	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	200649506	782568	0	0
GntImpliesValid_A	200649506	782568	0	0
GrantKnown_A	200649506	157307086	0	0
IdxKnown_A	200649506	157307086	0	0
IndexIsCorrect_A	200649506	782568	0	0
LockArbDecision_A	200649506	0	0	0
NoReadyValidNoGrant_A	200649506	0	0	0
ReadyAndValidImplyGrant_A	200649506	782568	0	0
ReqAndReadyImplyGrant_A	200649506	782568	0	0
ReqImpliesValid_A	200649506	782568	0	0
ReqStaysHighUntilGranted0_M	200649506	0	0	0
RoundRobin_A	200649506	0	0	0
ValidKnown_A	200649506	157307086	0	0
gen_data_port_assertion.DataFlow_A	200649506	782568	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	157307086	0	0
T1	275	240	0	0
T3	16720	16720	0	0
T4	1129	0	0	0
T5	15401	15366	0	0
T8	1471	0	0	0
T9	183347	182916	0	0
T10	305	160	0	0
T11	0	192861	0	0
T13	242532	242532	0	0
T15	8960	8960	0	0
T16	0	76546	0	0
T17	0	43428	0	0
T18	110916	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	782568	0	0
T11	310255	2390	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	3716	0	0
T23	730081	2191	0	0
T30	0	1036	0	0
T32	0	11739	0	0
T34	0	260	0	0
T35	0	5891	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T52	0	3	0	0
T53	0	550	0	0
T69	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	782568	0	0
T11	310255	2390	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	3716	0	0
T23	730081	2191	0	0
T30	0	1036	0	0
T32	0	11739	0	0
T34	0	260	0	0
T35	0	5891	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T52	0	3	0	0
T53	0	550	0	0
T69	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	157307086	0	0
T1	275	240	0	0
T3	16720	16720	0	0
T4	1129	0	0	0
T5	15401	15366	0	0
T8	1471	0	0	0
T9	183347	182916	0	0
T10	305	160	0	0
T11	0	192861	0	0
T13	242532	242532	0	0
T15	8960	8960	0	0
T16	0	76546	0	0
T17	0	43428	0	0
T18	110916	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	157307086	0	0
T1	275	240	0	0
T3	16720	16720	0	0
T4	1129	0	0	0
T5	15401	15366	0	0
T8	1471	0	0	0
T9	183347	182916	0	0
T10	305	160	0	0
T11	0	192861	0	0
T13	242532	242532	0	0
T15	8960	8960	0	0
T16	0	76546	0	0
T17	0	43428	0	0
T18	110916	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	782568	0	0
T11	310255	2390	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	3716	0	0
T23	730081	2191	0	0
T30	0	1036	0	0
T32	0	11739	0	0
T34	0	260	0	0
T35	0	5891	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T52	0	3	0	0
T53	0	550	0	0
T69	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	782568	0	0
T11	310255	2390	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	3716	0	0
T23	730081	2191	0	0
T30	0	1036	0	0
T32	0	11739	0	0
T34	0	260	0	0
T35	0	5891	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T52	0	3	0	0
T53	0	550	0	0
T69	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	782568	0	0
T11	310255	2390	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	3716	0	0
T23	730081	2191	0	0
T30	0	1036	0	0
T32	0	11739	0	0
T34	0	260	0	0
T35	0	5891	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T52	0	3	0	0
T53	0	550	0	0
T69	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	782568	0	0
T11	310255	2390	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	3716	0	0
T23	730081	2191	0	0
T30	0	1036	0	0
T32	0	11739	0	0
T34	0	260	0	0
T35	0	5891	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T52	0	3	0	0
T53	0	550	0	0
T69	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	157307086	0	0
T1	275	240	0	0
T3	16720	16720	0	0
T4	1129	0	0	0
T5	15401	15366	0	0
T8	1471	0	0	0
T9	183347	182916	0	0
T10	305	160	0	0
T11	0	192861	0	0
T13	242532	242532	0	0
T15	8960	8960	0	0
T16	0	76546	0	0
T17	0	43428	0	0
T18	110916	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200649506	782568	0	0
T11	310255	2390	0	0
T12	21243	0	0	0
T14	136290	0	0	0
T16	76890	0	0	0
T17	43710	0	0	0
T21	112800	3716	0	0
T23	730081	2191	0	0
T30	0	1036	0	0
T32	0	11739	0	0
T34	0	260	0	0
T35	0	5891	0	0
T42	96073	0	0	0
T43	44624	0	0	0
T44	226496	0	0	0
T52	0	3	0	0
T53	0	550	0	0
T69	0	8	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T11,T21

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T11,T21
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	640801267	640716252	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	640801267	2965713	0	0
GntImpliesValid_A	640801267	2965713	0	0
GrantKnown_A	640801267	640716252	0	0
IdxKnown_A	640801267	640716252	0	0
IndexIsCorrect_A	640801267	2965713	0	0
LockArbDecision_A	640801267	0	0	0
NoReadyValidNoGrant_A	640801267	0	0	0
ReadyAndValidImplyGrant_A	640801267	2965713	0	0
ReqAndReadyImplyGrant_A	640801267	2965713	0	0
ReqImpliesValid_A	640801267	2965713	0	0
ReqStaysHighUntilGranted0_M	640801267	0	0	0
RoundRobin_A	640801267	7	0	938
ValidKnown_A	640801267	640716252	0	0
gen_data_port_assertion.DataFlow_A	640801267	2965713	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	640716252	0	0
T1	10605	10514	0	0
T2	1598	1519	0	0
T3	19087	19014	0	0
T4	3879	3818	0	0
T5	126222	126159	0	0
T6	1333	1277	0	0
T7	2063	1978	0	0
T8	4980	4916	0	0
T9	64842	64776	0	0
T10	5304	5236	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	2965713	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	0	4481	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	2965713	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	0	4481	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	640716252	0	0
T1	10605	10514	0	0
T2	1598	1519	0	0
T3	19087	19014	0	0
T4	3879	3818	0	0
T5	126222	126159	0	0
T6	1333	1277	0	0
T7	2063	1978	0	0
T8	4980	4916	0	0
T9	64842	64776	0	0
T10	5304	5236	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	640716252	0	0
T1	10605	10514	0	0
T2	1598	1519	0	0
T3	19087	19014	0	0
T4	3879	3818	0	0
T5	126222	126159	0	0
T6	1333	1277	0	0
T7	2063	1978	0	0
T8	4980	4916	0	0
T9	64842	64776	0	0
T10	5304	5236	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	2965713	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	0	4481	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	2965713	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	0	4481	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	2965713	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	0	4481	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	2965713	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	0	4481	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	7	0	938
T38	486568	0	0	1
T39	194685	0	0	1
T55	428495	1	0	1
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	119095	0	0	1
T63	908	0	0	1
T64	1622	0	0	1
T65	1236	0	0	1
T66	862540	0	0	1
T67	36661	0	0	1
T68	108997	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	640716252	0	0
T1	10605	10514	0	0
T2	1598	1519	0	0
T3	19087	19014	0	0
T4	3879	3818	0	0
T5	126222	126159	0	0
T6	1333	1277	0	0
T7	2063	1978	0	0
T8	4980	4916	0	0
T9	64842	64776	0	0
T10	5304	5236	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640801267	2965713	0	0
T1	10605	832	0	0
T2	1598	0	0	0
T3	19087	832	0	0
T4	3879	0	0	0
T5	126222	832	0	0
T6	1333	200	0	0
T7	2063	0	0	0
T8	4980	0	0	0
T9	64842	832	0	0
T10	5304	832	0	0
T11	0	4481	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0