Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3355 |
0 |
0 |
T102 |
3893 |
12 |
0 |
0 |
T103 |
54429 |
1 |
0 |
0 |
T104 |
3840 |
34 |
0 |
0 |
T105 |
11362 |
5 |
0 |
0 |
T106 |
29463 |
1 |
0 |
0 |
T107 |
70482 |
1 |
0 |
0 |
T108 |
4283 |
93 |
0 |
0 |
T109 |
4807 |
125 |
0 |
0 |
T115 |
12770 |
185 |
0 |
0 |
T121 |
19121 |
6 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1236 |
0 |
0 |
T105 |
11362 |
15 |
0 |
0 |
T107 |
70482 |
73 |
0 |
0 |
T118 |
103431 |
111 |
0 |
0 |
T133 |
7478 |
7 |
0 |
0 |
T146 |
7280 |
23 |
0 |
0 |
T147 |
84097 |
511 |
0 |
0 |
T148 |
29652 |
27 |
0 |
0 |
T149 |
20378 |
26 |
0 |
0 |
T150 |
14010 |
45 |
0 |
0 |
T151 |
11958 |
32 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1360 |
0 |
0 |
T105 |
11362 |
10 |
0 |
0 |
T107 |
70482 |
66 |
0 |
0 |
T118 |
103431 |
103 |
0 |
0 |
T133 |
7478 |
3 |
0 |
0 |
T146 |
7280 |
43 |
0 |
0 |
T147 |
84097 |
583 |
0 |
0 |
T148 |
29652 |
9 |
0 |
0 |
T149 |
20378 |
74 |
0 |
0 |
T150 |
14010 |
61 |
0 |
0 |
T151 |
11958 |
35 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1696 |
0 |
0 |
T105 |
11362 |
22 |
0 |
0 |
T107 |
70482 |
182 |
0 |
0 |
T118 |
103431 |
153 |
0 |
0 |
T133 |
7478 |
22 |
0 |
0 |
T146 |
7280 |
36 |
0 |
0 |
T147 |
84097 |
536 |
0 |
0 |
T148 |
29652 |
53 |
0 |
0 |
T149 |
20378 |
74 |
0 |
0 |
T150 |
14010 |
78 |
0 |
0 |
T151 |
11958 |
36 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
8441 |
0 |
0 |
T105 |
11362 |
120 |
0 |
0 |
T107 |
70482 |
1764 |
0 |
0 |
T118 |
103431 |
1844 |
0 |
0 |
T133 |
7478 |
8 |
0 |
0 |
T146 |
7280 |
3 |
0 |
0 |
T147 |
84097 |
508 |
0 |
0 |
T148 |
29652 |
227 |
0 |
0 |
T149 |
20378 |
82 |
0 |
0 |
T150 |
14010 |
13 |
0 |
0 |
T151 |
11958 |
18 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
6946 |
0 |
0 |
T105 |
11362 |
148 |
0 |
0 |
T107 |
70482 |
1106 |
0 |
0 |
T118 |
103431 |
1551 |
0 |
0 |
T133 |
7478 |
12 |
0 |
0 |
T146 |
7280 |
47 |
0 |
0 |
T147 |
84097 |
549 |
0 |
0 |
T148 |
29652 |
530 |
0 |
0 |
T149 |
20378 |
52 |
0 |
0 |
T150 |
14010 |
66 |
0 |
0 |
T151 |
11958 |
30 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
6722 |
0 |
0 |
T105 |
11362 |
146 |
0 |
0 |
T107 |
70482 |
1400 |
0 |
0 |
T118 |
103431 |
1628 |
0 |
0 |
T133 |
7478 |
1 |
0 |
0 |
T146 |
7280 |
23 |
0 |
0 |
T147 |
84097 |
509 |
0 |
0 |
T148 |
29652 |
153 |
0 |
0 |
T149 |
20378 |
58 |
0 |
0 |
T150 |
14010 |
68 |
0 |
0 |
T151 |
11958 |
22 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
7328 |
0 |
0 |
T105 |
11362 |
263 |
0 |
0 |
T107 |
70482 |
1131 |
0 |
0 |
T118 |
103431 |
1722 |
0 |
0 |
T133 |
7478 |
119 |
0 |
0 |
T146 |
7280 |
13 |
0 |
0 |
T147 |
84097 |
503 |
0 |
0 |
T148 |
29652 |
510 |
0 |
0 |
T149 |
20378 |
90 |
0 |
0 |
T150 |
14010 |
38 |
0 |
0 |
T151 |
11958 |
18 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
6984 |
0 |
0 |
T105 |
11362 |
267 |
0 |
0 |
T107 |
70482 |
1286 |
0 |
0 |
T118 |
103431 |
1636 |
0 |
0 |
T133 |
7478 |
125 |
0 |
0 |
T146 |
7280 |
33 |
0 |
0 |
T147 |
84097 |
515 |
0 |
0 |
T148 |
29652 |
285 |
0 |
0 |
T149 |
20378 |
75 |
0 |
0 |
T150 |
14010 |
49 |
0 |
0 |
T151 |
11958 |
16 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
7023 |
0 |
0 |
T105 |
11362 |
114 |
0 |
0 |
T107 |
70482 |
1493 |
0 |
0 |
T118 |
103431 |
1366 |
0 |
0 |
T133 |
7478 |
136 |
0 |
0 |
T146 |
7280 |
11 |
0 |
0 |
T147 |
84097 |
532 |
0 |
0 |
T148 |
29652 |
279 |
0 |
0 |
T149 |
20378 |
49 |
0 |
0 |
T150 |
14010 |
20 |
0 |
0 |
T151 |
11958 |
13 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
8236 |
0 |
0 |
T105 |
11362 |
112 |
0 |
0 |
T107 |
70482 |
1398 |
0 |
0 |
T118 |
103431 |
2068 |
0 |
0 |
T133 |
7478 |
277 |
0 |
0 |
T146 |
7280 |
24 |
0 |
0 |
T147 |
84097 |
532 |
0 |
0 |
T148 |
29652 |
253 |
0 |
0 |
T149 |
20378 |
71 |
0 |
0 |
T150 |
14010 |
68 |
0 |
0 |
T151 |
11958 |
5 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
8542 |
0 |
0 |
T105 |
11362 |
230 |
0 |
0 |
T107 |
70482 |
1780 |
0 |
0 |
T118 |
103431 |
2199 |
0 |
0 |
T133 |
7478 |
250 |
0 |
0 |
T146 |
7280 |
6 |
0 |
0 |
T147 |
84097 |
582 |
0 |
0 |
T148 |
29652 |
199 |
0 |
0 |
T149 |
20378 |
52 |
0 |
0 |
T150 |
14010 |
60 |
0 |
0 |
T151 |
11958 |
18 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
4010 |
0 |
0 |
T105 |
11362 |
5 |
0 |
0 |
T107 |
70482 |
659 |
0 |
0 |
T118 |
103431 |
760 |
0 |
0 |
T133 |
7478 |
49 |
0 |
0 |
T147 |
84097 |
576 |
0 |
0 |
T148 |
29652 |
132 |
0 |
0 |
T149 |
20378 |
118 |
0 |
0 |
T150 |
14010 |
20 |
0 |
0 |
T151 |
11958 |
15 |
0 |
0 |
T152 |
6723 |
60 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3655 |
0 |
0 |
T105 |
11362 |
60 |
0 |
0 |
T107 |
70482 |
737 |
0 |
0 |
T118 |
103431 |
840 |
0 |
0 |
T133 |
7478 |
49 |
0 |
0 |
T146 |
7280 |
11 |
0 |
0 |
T147 |
84097 |
516 |
0 |
0 |
T148 |
29652 |
207 |
0 |
0 |
T149 |
20378 |
79 |
0 |
0 |
T150 |
14010 |
79 |
0 |
0 |
T151 |
11958 |
29 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3841 |
0 |
0 |
T105 |
11362 |
100 |
0 |
0 |
T107 |
70482 |
642 |
0 |
0 |
T118 |
103431 |
993 |
0 |
0 |
T133 |
7478 |
79 |
0 |
0 |
T146 |
7280 |
7 |
0 |
0 |
T147 |
84097 |
496 |
0 |
0 |
T148 |
29652 |
186 |
0 |
0 |
T149 |
20378 |
61 |
0 |
0 |
T150 |
14010 |
80 |
0 |
0 |
T151 |
11958 |
18 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3281 |
0 |
0 |
T105 |
11362 |
13 |
0 |
0 |
T107 |
70482 |
768 |
0 |
0 |
T118 |
103431 |
620 |
0 |
0 |
T133 |
7478 |
50 |
0 |
0 |
T146 |
7280 |
31 |
0 |
0 |
T147 |
84097 |
550 |
0 |
0 |
T148 |
29652 |
100 |
0 |
0 |
T149 |
20378 |
89 |
0 |
0 |
T150 |
14010 |
43 |
0 |
0 |
T151 |
11958 |
7 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3998 |
0 |
0 |
T105 |
11362 |
72 |
0 |
0 |
T107 |
70482 |
639 |
0 |
0 |
T118 |
103431 |
832 |
0 |
0 |
T133 |
7478 |
82 |
0 |
0 |
T146 |
7280 |
59 |
0 |
0 |
T147 |
84097 |
496 |
0 |
0 |
T148 |
29652 |
266 |
0 |
0 |
T149 |
20378 |
84 |
0 |
0 |
T150 |
14010 |
44 |
0 |
0 |
T151 |
11958 |
15 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3309 |
0 |
0 |
T105 |
11362 |
82 |
0 |
0 |
T107 |
70482 |
503 |
0 |
0 |
T118 |
103431 |
565 |
0 |
0 |
T133 |
7478 |
50 |
0 |
0 |
T146 |
7280 |
23 |
0 |
0 |
T147 |
84097 |
546 |
0 |
0 |
T148 |
29652 |
134 |
0 |
0 |
T149 |
20378 |
39 |
0 |
0 |
T150 |
14010 |
37 |
0 |
0 |
T151 |
11958 |
32 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3461 |
0 |
0 |
T105 |
11362 |
87 |
0 |
0 |
T107 |
70482 |
535 |
0 |
0 |
T118 |
103431 |
470 |
0 |
0 |
T133 |
7478 |
8 |
0 |
0 |
T146 |
7280 |
4 |
0 |
0 |
T147 |
84097 |
525 |
0 |
0 |
T148 |
29652 |
94 |
0 |
0 |
T149 |
20378 |
41 |
0 |
0 |
T150 |
14010 |
52 |
0 |
0 |
T151 |
11958 |
27 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3708 |
0 |
0 |
T105 |
11362 |
9 |
0 |
0 |
T107 |
70482 |
607 |
0 |
0 |
T118 |
103431 |
792 |
0 |
0 |
T133 |
7478 |
60 |
0 |
0 |
T146 |
7280 |
16 |
0 |
0 |
T147 |
84097 |
480 |
0 |
0 |
T148 |
29652 |
99 |
0 |
0 |
T149 |
20378 |
80 |
0 |
0 |
T150 |
14010 |
33 |
0 |
0 |
T151 |
11958 |
31 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3810 |
0 |
0 |
T105 |
11362 |
15 |
0 |
0 |
T107 |
70482 |
481 |
0 |
0 |
T118 |
103431 |
866 |
0 |
0 |
T133 |
7478 |
6 |
0 |
0 |
T146 |
7280 |
13 |
0 |
0 |
T147 |
84097 |
529 |
0 |
0 |
T148 |
29652 |
188 |
0 |
0 |
T149 |
20378 |
64 |
0 |
0 |
T150 |
14010 |
35 |
0 |
0 |
T151 |
11958 |
11 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3825 |
0 |
0 |
T105 |
11362 |
115 |
0 |
0 |
T107 |
70482 |
686 |
0 |
0 |
T118 |
103431 |
656 |
0 |
0 |
T133 |
7478 |
100 |
0 |
0 |
T146 |
7280 |
22 |
0 |
0 |
T147 |
84097 |
498 |
0 |
0 |
T148 |
29652 |
88 |
0 |
0 |
T149 |
20378 |
53 |
0 |
0 |
T150 |
14010 |
76 |
0 |
0 |
T151 |
11958 |
30 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3587 |
0 |
0 |
T105 |
11362 |
65 |
0 |
0 |
T107 |
70482 |
440 |
0 |
0 |
T118 |
103431 |
830 |
0 |
0 |
T133 |
7478 |
105 |
0 |
0 |
T146 |
7280 |
13 |
0 |
0 |
T147 |
84097 |
537 |
0 |
0 |
T148 |
29652 |
176 |
0 |
0 |
T149 |
20378 |
73 |
0 |
0 |
T150 |
14010 |
44 |
0 |
0 |
T151 |
11958 |
37 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
4182 |
0 |
0 |
T105 |
11362 |
94 |
0 |
0 |
T107 |
70482 |
569 |
0 |
0 |
T118 |
103431 |
807 |
0 |
0 |
T133 |
7478 |
64 |
0 |
0 |
T146 |
7280 |
22 |
0 |
0 |
T147 |
84097 |
519 |
0 |
0 |
T148 |
29652 |
175 |
0 |
0 |
T149 |
20378 |
42 |
0 |
0 |
T150 |
14010 |
54 |
0 |
0 |
T151 |
11958 |
76 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3459 |
0 |
0 |
T105 |
11362 |
20 |
0 |
0 |
T107 |
70482 |
600 |
0 |
0 |
T118 |
103431 |
725 |
0 |
0 |
T133 |
7478 |
92 |
0 |
0 |
T146 |
7280 |
21 |
0 |
0 |
T147 |
84097 |
523 |
0 |
0 |
T148 |
29652 |
120 |
0 |
0 |
T149 |
20378 |
33 |
0 |
0 |
T150 |
14010 |
26 |
0 |
0 |
T151 |
11958 |
29 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3542 |
0 |
0 |
T105 |
11362 |
13 |
0 |
0 |
T107 |
70482 |
535 |
0 |
0 |
T118 |
103431 |
760 |
0 |
0 |
T133 |
7478 |
40 |
0 |
0 |
T146 |
7280 |
24 |
0 |
0 |
T147 |
84097 |
545 |
0 |
0 |
T148 |
29652 |
133 |
0 |
0 |
T149 |
20378 |
80 |
0 |
0 |
T150 |
14010 |
60 |
0 |
0 |
T151 |
11958 |
12 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3994 |
0 |
0 |
T105 |
11362 |
58 |
0 |
0 |
T107 |
70482 |
524 |
0 |
0 |
T118 |
103431 |
1014 |
0 |
0 |
T133 |
7478 |
8 |
0 |
0 |
T146 |
7280 |
20 |
0 |
0 |
T147 |
84097 |
564 |
0 |
0 |
T148 |
29652 |
137 |
0 |
0 |
T149 |
20378 |
62 |
0 |
0 |
T150 |
14010 |
24 |
0 |
0 |
T151 |
11958 |
24 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
4030 |
0 |
0 |
T105 |
11362 |
44 |
0 |
0 |
T107 |
70482 |
618 |
0 |
0 |
T118 |
103431 |
902 |
0 |
0 |
T133 |
7478 |
91 |
0 |
0 |
T146 |
7280 |
44 |
0 |
0 |
T147 |
84097 |
564 |
0 |
0 |
T148 |
29652 |
111 |
0 |
0 |
T149 |
20378 |
113 |
0 |
0 |
T150 |
14010 |
72 |
0 |
0 |
T151 |
11958 |
12 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3638 |
0 |
0 |
T105 |
11362 |
10 |
0 |
0 |
T107 |
70482 |
385 |
0 |
0 |
T118 |
103431 |
800 |
0 |
0 |
T133 |
7478 |
91 |
0 |
0 |
T146 |
7280 |
13 |
0 |
0 |
T147 |
84097 |
506 |
0 |
0 |
T148 |
29652 |
220 |
0 |
0 |
T149 |
20378 |
72 |
0 |
0 |
T150 |
14010 |
55 |
0 |
0 |
T151 |
11958 |
40 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3630 |
0 |
0 |
T105 |
11362 |
21 |
0 |
0 |
T107 |
70482 |
336 |
0 |
0 |
T118 |
103431 |
887 |
0 |
0 |
T133 |
7478 |
39 |
0 |
0 |
T146 |
7280 |
10 |
0 |
0 |
T147 |
84097 |
518 |
0 |
0 |
T148 |
29652 |
230 |
0 |
0 |
T149 |
20378 |
113 |
0 |
0 |
T150 |
14010 |
48 |
0 |
0 |
T152 |
6723 |
5 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3654 |
0 |
0 |
T105 |
11362 |
24 |
0 |
0 |
T107 |
70482 |
570 |
0 |
0 |
T118 |
103431 |
698 |
0 |
0 |
T133 |
7478 |
71 |
0 |
0 |
T146 |
7280 |
32 |
0 |
0 |
T147 |
84097 |
527 |
0 |
0 |
T148 |
29652 |
118 |
0 |
0 |
T149 |
20378 |
83 |
0 |
0 |
T150 |
14010 |
75 |
0 |
0 |
T151 |
11958 |
28 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3870 |
0 |
0 |
T105 |
11362 |
73 |
0 |
0 |
T107 |
70482 |
539 |
0 |
0 |
T118 |
103431 |
964 |
0 |
0 |
T133 |
7478 |
45 |
0 |
0 |
T146 |
7280 |
24 |
0 |
0 |
T147 |
84097 |
522 |
0 |
0 |
T148 |
29652 |
178 |
0 |
0 |
T149 |
20378 |
103 |
0 |
0 |
T150 |
14010 |
15 |
0 |
0 |
T151 |
11958 |
8 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3525 |
0 |
0 |
T105 |
11362 |
110 |
0 |
0 |
T107 |
70482 |
542 |
0 |
0 |
T118 |
103431 |
595 |
0 |
0 |
T133 |
7478 |
39 |
0 |
0 |
T146 |
7280 |
32 |
0 |
0 |
T147 |
84097 |
545 |
0 |
0 |
T148 |
29652 |
100 |
0 |
0 |
T149 |
20378 |
83 |
0 |
0 |
T150 |
14010 |
56 |
0 |
0 |
T151 |
11958 |
16 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3893 |
0 |
0 |
T105 |
11362 |
97 |
0 |
0 |
T107 |
70482 |
666 |
0 |
0 |
T118 |
103431 |
718 |
0 |
0 |
T133 |
7478 |
80 |
0 |
0 |
T146 |
7280 |
23 |
0 |
0 |
T147 |
84097 |
575 |
0 |
0 |
T148 |
29652 |
82 |
0 |
0 |
T149 |
20378 |
61 |
0 |
0 |
T150 |
14010 |
64 |
0 |
0 |
T151 |
11958 |
37 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3736 |
0 |
0 |
T105 |
11362 |
116 |
0 |
0 |
T107 |
70482 |
550 |
0 |
0 |
T118 |
103431 |
727 |
0 |
0 |
T133 |
7478 |
64 |
0 |
0 |
T146 |
7280 |
28 |
0 |
0 |
T147 |
84097 |
500 |
0 |
0 |
T148 |
29652 |
137 |
0 |
0 |
T149 |
20378 |
81 |
0 |
0 |
T150 |
14010 |
22 |
0 |
0 |
T151 |
11958 |
21 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3987 |
0 |
0 |
T105 |
11362 |
55 |
0 |
0 |
T107 |
70482 |
640 |
0 |
0 |
T118 |
103431 |
916 |
0 |
0 |
T133 |
7478 |
56 |
0 |
0 |
T146 |
7280 |
21 |
0 |
0 |
T147 |
84097 |
540 |
0 |
0 |
T148 |
29652 |
94 |
0 |
0 |
T149 |
20378 |
79 |
0 |
0 |
T150 |
14010 |
46 |
0 |
0 |
T151 |
11958 |
29 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1441 |
0 |
0 |
T105 |
11362 |
12 |
0 |
0 |
T107 |
70482 |
126 |
0 |
0 |
T118 |
103431 |
189 |
0 |
0 |
T133 |
7478 |
8 |
0 |
0 |
T146 |
7280 |
9 |
0 |
0 |
T147 |
84097 |
472 |
0 |
0 |
T148 |
29652 |
4 |
0 |
0 |
T149 |
20378 |
84 |
0 |
0 |
T150 |
14010 |
51 |
0 |
0 |
T151 |
11958 |
7 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1400 |
0 |
0 |
T105 |
11362 |
22 |
0 |
0 |
T107 |
70482 |
87 |
0 |
0 |
T118 |
103431 |
119 |
0 |
0 |
T133 |
7478 |
16 |
0 |
0 |
T146 |
7280 |
23 |
0 |
0 |
T147 |
84097 |
489 |
0 |
0 |
T148 |
29652 |
34 |
0 |
0 |
T149 |
20378 |
99 |
0 |
0 |
T150 |
14010 |
42 |
0 |
0 |
T151 |
11958 |
35 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1408 |
0 |
0 |
T105 |
11362 |
16 |
0 |
0 |
T107 |
70482 |
122 |
0 |
0 |
T118 |
103431 |
150 |
0 |
0 |
T133 |
7478 |
6 |
0 |
0 |
T146 |
7280 |
16 |
0 |
0 |
T147 |
84097 |
538 |
0 |
0 |
T148 |
29652 |
17 |
0 |
0 |
T149 |
20378 |
47 |
0 |
0 |
T150 |
14010 |
52 |
0 |
0 |
T151 |
11958 |
21 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1576 |
0 |
0 |
T105 |
11362 |
13 |
0 |
0 |
T107 |
70482 |
136 |
0 |
0 |
T118 |
103431 |
210 |
0 |
0 |
T133 |
7478 |
21 |
0 |
0 |
T146 |
7280 |
29 |
0 |
0 |
T147 |
84097 |
530 |
0 |
0 |
T148 |
29652 |
39 |
0 |
0 |
T149 |
20378 |
117 |
0 |
0 |
T150 |
14010 |
49 |
0 |
0 |
T151 |
11958 |
38 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
2024 |
0 |
0 |
T105 |
11362 |
14 |
0 |
0 |
T107 |
70482 |
235 |
0 |
0 |
T118 |
103431 |
292 |
0 |
0 |
T133 |
7478 |
14 |
0 |
0 |
T146 |
7280 |
39 |
0 |
0 |
T147 |
84097 |
565 |
0 |
0 |
T148 |
29652 |
68 |
0 |
0 |
T149 |
20378 |
75 |
0 |
0 |
T150 |
14010 |
42 |
0 |
0 |
T151 |
11958 |
14 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
3637 |
0 |
0 |
T28 |
1181 |
0 |
0 |
0 |
T53 |
716919 |
39 |
0 |
0 |
T72 |
0 |
5 |
0 |
0 |
T75 |
0 |
16 |
0 |
0 |
T100 |
381211 |
0 |
0 |
0 |
T122 |
206053 |
0 |
0 |
0 |
T123 |
36867 |
0 |
0 |
0 |
T124 |
352719 |
0 |
0 |
0 |
T125 |
701112 |
0 |
0 |
0 |
T153 |
0 |
19 |
0 |
0 |
T154 |
0 |
7 |
0 |
0 |
T155 |
0 |
18 |
0 |
0 |
T156 |
0 |
10 |
0 |
0 |
T157 |
0 |
35 |
0 |
0 |
T158 |
0 |
3 |
0 |
0 |
T159 |
0 |
8 |
0 |
0 |
T160 |
379089 |
0 |
0 |
0 |
T161 |
1303 |
0 |
0 |
0 |
T162 |
399628 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1476 |
0 |
0 |
T105 |
11362 |
19 |
0 |
0 |
T107 |
70482 |
112 |
0 |
0 |
T118 |
103431 |
164 |
0 |
0 |
T133 |
7478 |
8 |
0 |
0 |
T146 |
7280 |
5 |
0 |
0 |
T147 |
84097 |
531 |
0 |
0 |
T148 |
29652 |
16 |
0 |
0 |
T149 |
20378 |
96 |
0 |
0 |
T150 |
14010 |
60 |
0 |
0 |
T151 |
11958 |
14 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1570 |
0 |
0 |
T105 |
11362 |
28 |
0 |
0 |
T107 |
70482 |
131 |
0 |
0 |
T118 |
103431 |
177 |
0 |
0 |
T133 |
7478 |
3 |
0 |
0 |
T146 |
7280 |
41 |
0 |
0 |
T147 |
84097 |
597 |
0 |
0 |
T148 |
29652 |
23 |
0 |
0 |
T149 |
20378 |
109 |
0 |
0 |
T150 |
14010 |
34 |
0 |
0 |
T151 |
11958 |
6 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1261 |
0 |
0 |
T105 |
11362 |
17 |
0 |
0 |
T107 |
70482 |
71 |
0 |
0 |
T118 |
103431 |
122 |
0 |
0 |
T133 |
7478 |
10 |
0 |
0 |
T146 |
7280 |
33 |
0 |
0 |
T147 |
84097 |
546 |
0 |
0 |
T148 |
29652 |
31 |
0 |
0 |
T149 |
20378 |
45 |
0 |
0 |
T150 |
14010 |
76 |
0 |
0 |
T151 |
11958 |
19 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1390 |
0 |
0 |
T105 |
11362 |
25 |
0 |
0 |
T107 |
70482 |
96 |
0 |
0 |
T118 |
103431 |
106 |
0 |
0 |
T133 |
7478 |
12 |
0 |
0 |
T146 |
7280 |
33 |
0 |
0 |
T147 |
84097 |
557 |
0 |
0 |
T148 |
29652 |
21 |
0 |
0 |
T149 |
20378 |
15 |
0 |
0 |
T150 |
14010 |
42 |
0 |
0 |
T151 |
11958 |
28 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1186 |
0 |
0 |
T105 |
11362 |
17 |
0 |
0 |
T107 |
70482 |
74 |
0 |
0 |
T118 |
103431 |
123 |
0 |
0 |
T133 |
7478 |
6 |
0 |
0 |
T146 |
7280 |
10 |
0 |
0 |
T147 |
84097 |
488 |
0 |
0 |
T148 |
29652 |
28 |
0 |
0 |
T149 |
20378 |
13 |
0 |
0 |
T150 |
14010 |
57 |
0 |
0 |
T151 |
11958 |
38 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1234 |
0 |
0 |
T105 |
11362 |
23 |
0 |
0 |
T107 |
70482 |
85 |
0 |
0 |
T118 |
103431 |
124 |
0 |
0 |
T133 |
7478 |
12 |
0 |
0 |
T146 |
7280 |
5 |
0 |
0 |
T147 |
84097 |
530 |
0 |
0 |
T148 |
29652 |
17 |
0 |
0 |
T149 |
20378 |
27 |
0 |
0 |
T150 |
14010 |
37 |
0 |
0 |
T151 |
11958 |
21 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
2034 |
0 |
0 |
T105 |
11362 |
5 |
0 |
0 |
T107 |
70482 |
211 |
0 |
0 |
T118 |
103431 |
247 |
0 |
0 |
T133 |
7478 |
27 |
0 |
0 |
T146 |
7280 |
34 |
0 |
0 |
T147 |
84097 |
530 |
0 |
0 |
T148 |
29652 |
56 |
0 |
0 |
T149 |
20378 |
70 |
0 |
0 |
T150 |
14010 |
21 |
0 |
0 |
T151 |
11958 |
11 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1294 |
0 |
0 |
T105 |
11362 |
22 |
0 |
0 |
T107 |
70482 |
62 |
0 |
0 |
T118 |
103431 |
113 |
0 |
0 |
T133 |
7478 |
1 |
0 |
0 |
T146 |
7280 |
22 |
0 |
0 |
T147 |
84097 |
538 |
0 |
0 |
T148 |
29652 |
24 |
0 |
0 |
T149 |
20378 |
67 |
0 |
0 |
T150 |
14010 |
31 |
0 |
0 |
T151 |
11958 |
9 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
2069 |
0 |
0 |
T105 |
11362 |
41 |
0 |
0 |
T107 |
70482 |
260 |
0 |
0 |
T118 |
103431 |
326 |
0 |
0 |
T133 |
7478 |
42 |
0 |
0 |
T146 |
7280 |
9 |
0 |
0 |
T147 |
84097 |
587 |
0 |
0 |
T148 |
29652 |
47 |
0 |
0 |
T149 |
20378 |
36 |
0 |
0 |
T150 |
14010 |
16 |
0 |
0 |
T152 |
6723 |
27 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1453 |
0 |
0 |
T105 |
11362 |
23 |
0 |
0 |
T107 |
70482 |
107 |
0 |
0 |
T118 |
103431 |
158 |
0 |
0 |
T133 |
7478 |
10 |
0 |
0 |
T146 |
7280 |
28 |
0 |
0 |
T147 |
84097 |
510 |
0 |
0 |
T148 |
29652 |
19 |
0 |
0 |
T149 |
20378 |
82 |
0 |
0 |
T150 |
14010 |
17 |
0 |
0 |
T151 |
11958 |
33 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1373 |
0 |
0 |
T105 |
11362 |
11 |
0 |
0 |
T107 |
70482 |
88 |
0 |
0 |
T118 |
103431 |
104 |
0 |
0 |
T133 |
7478 |
11 |
0 |
0 |
T146 |
7280 |
32 |
0 |
0 |
T147 |
84097 |
517 |
0 |
0 |
T148 |
29652 |
39 |
0 |
0 |
T149 |
20378 |
68 |
0 |
0 |
T150 |
14010 |
110 |
0 |
0 |
T151 |
11958 |
16 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1254 |
0 |
0 |
T105 |
11362 |
9 |
0 |
0 |
T107 |
70482 |
85 |
0 |
0 |
T118 |
103431 |
98 |
0 |
0 |
T133 |
7478 |
4 |
0 |
0 |
T146 |
7280 |
7 |
0 |
0 |
T147 |
84097 |
578 |
0 |
0 |
T148 |
29652 |
12 |
0 |
0 |
T149 |
20378 |
40 |
0 |
0 |
T150 |
14010 |
52 |
0 |
0 |
T151 |
11958 |
12 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1283 |
0 |
0 |
T105 |
11362 |
13 |
0 |
0 |
T107 |
70482 |
81 |
0 |
0 |
T118 |
103431 |
118 |
0 |
0 |
T133 |
7478 |
7 |
0 |
0 |
T146 |
7280 |
8 |
0 |
0 |
T147 |
84097 |
484 |
0 |
0 |
T148 |
29652 |
25 |
0 |
0 |
T149 |
20378 |
54 |
0 |
0 |
T150 |
14010 |
41 |
0 |
0 |
T151 |
11958 |
17 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1259 |
0 |
0 |
T105 |
11362 |
13 |
0 |
0 |
T107 |
70482 |
99 |
0 |
0 |
T118 |
103431 |
108 |
0 |
0 |
T133 |
7478 |
7 |
0 |
0 |
T146 |
7280 |
29 |
0 |
0 |
T147 |
84097 |
494 |
0 |
0 |
T148 |
29652 |
27 |
0 |
0 |
T149 |
20378 |
62 |
0 |
0 |
T150 |
14010 |
63 |
0 |
0 |
T151 |
11958 |
15 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1313 |
0 |
0 |
T105 |
11362 |
7 |
0 |
0 |
T107 |
70482 |
96 |
0 |
0 |
T118 |
103431 |
126 |
0 |
0 |
T133 |
7478 |
4 |
0 |
0 |
T146 |
7280 |
27 |
0 |
0 |
T147 |
84097 |
472 |
0 |
0 |
T148 |
29652 |
27 |
0 |
0 |
T149 |
20378 |
71 |
0 |
0 |
T150 |
14010 |
63 |
0 |
0 |
T151 |
11958 |
36 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
642912828 |
1274 |
0 |
0 |
T105 |
11362 |
9 |
0 |
0 |
T107 |
70482 |
86 |
0 |
0 |
T118 |
103431 |
133 |
0 |
0 |
T133 |
7478 |
11 |
0 |
0 |
T146 |
7280 |
42 |
0 |
0 |
T147 |
84097 |
524 |
0 |
0 |
T148 |
29652 |
25 |
0 |
0 |
T149 |
20378 |
57 |
0 |
0 |
T150 |
14010 |
15 |
0 |
0 |
T151 |
11958 |
27 |
0 |
0 |