T813 |
/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.246041880 |
|
|
Mar 03 02:07:02 PM PST 24 |
Mar 03 02:07:05 PM PST 24 |
1219652987 ps |
T814 |
/workspace/coverage/default/38.spi_device_tpm_sts_read.847344166 |
|
|
Mar 03 02:08:01 PM PST 24 |
Mar 03 02:08:02 PM PST 24 |
247007163 ps |
T815 |
/workspace/coverage/default/17.spi_device_csb_read.2581686649 |
|
|
Mar 03 02:06:46 PM PST 24 |
Mar 03 02:06:47 PM PST 24 |
15740195 ps |
T816 |
/workspace/coverage/default/37.spi_device_alert_test.254308487 |
|
|
Mar 03 02:07:53 PM PST 24 |
Mar 03 02:07:54 PM PST 24 |
16320718 ps |
T817 |
/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1741334900 |
|
|
Mar 03 02:05:58 PM PST 24 |
Mar 03 02:06:07 PM PST 24 |
8557737381 ps |
T818 |
/workspace/coverage/default/29.spi_device_intercept.1842851344 |
|
|
Mar 03 02:07:25 PM PST 24 |
Mar 03 02:07:28 PM PST 24 |
170876357 ps |
T819 |
/workspace/coverage/default/10.spi_device_pass_cmd_filtering.3360952721 |
|
|
Mar 03 02:06:12 PM PST 24 |
Mar 03 02:06:22 PM PST 24 |
1438738648 ps |
T820 |
/workspace/coverage/default/27.spi_device_pass_cmd_filtering.3146860575 |
|
|
Mar 03 02:07:11 PM PST 24 |
Mar 03 02:07:29 PM PST 24 |
63633107521 ps |
T821 |
/workspace/coverage/default/10.spi_device_stress_all.125037258 |
|
|
Mar 03 02:06:14 PM PST 24 |
Mar 03 02:09:41 PM PST 24 |
45584605472 ps |
T822 |
/workspace/coverage/default/42.spi_device_cfg_cmd.866322357 |
|
|
Mar 03 02:08:14 PM PST 24 |
Mar 03 02:08:23 PM PST 24 |
9007160988 ps |
T823 |
/workspace/coverage/default/1.spi_device_mailbox.106974417 |
|
|
Mar 03 02:05:45 PM PST 24 |
Mar 03 02:05:56 PM PST 24 |
3607013933 ps |
T824 |
/workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1731993663 |
|
|
Mar 03 02:06:37 PM PST 24 |
Mar 03 02:06:55 PM PST 24 |
19322083514 ps |
T825 |
/workspace/coverage/default/39.spi_device_csb_read.4104819717 |
|
|
Mar 03 02:08:04 PM PST 24 |
Mar 03 02:08:06 PM PST 24 |
16032211 ps |
T826 |
/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2127796614 |
|
|
Mar 03 02:07:19 PM PST 24 |
Mar 03 02:07:34 PM PST 24 |
3825428277 ps |
T827 |
/workspace/coverage/default/11.spi_device_tpm_all.1042208229 |
|
|
Mar 03 02:06:14 PM PST 24 |
Mar 03 02:06:21 PM PST 24 |
16404373277 ps |
T828 |
/workspace/coverage/default/43.spi_device_upload.3749596992 |
|
|
Mar 03 02:08:24 PM PST 24 |
Mar 03 02:08:38 PM PST 24 |
1605992430 ps |
T256 |
/workspace/coverage/default/42.spi_device_stress_all.4051405397 |
|
|
Mar 03 02:08:16 PM PST 24 |
Mar 03 02:12:20 PM PST 24 |
30068348027 ps |
T829 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1393515263 |
|
|
Mar 03 02:07:11 PM PST 24 |
Mar 03 02:07:32 PM PST 24 |
13845060125 ps |
T830 |
/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3781881818 |
|
|
Mar 03 02:05:50 PM PST 24 |
Mar 03 02:06:06 PM PST 24 |
30958711777 ps |
T831 |
/workspace/coverage/default/41.spi_device_pass_cmd_filtering.2015928326 |
|
|
Mar 03 02:08:08 PM PST 24 |
Mar 03 02:08:17 PM PST 24 |
547789541 ps |
T832 |
/workspace/coverage/default/2.spi_device_ram_cfg.3686225277 |
|
|
Mar 03 02:05:45 PM PST 24 |
Mar 03 02:05:46 PM PST 24 |
52689957 ps |
T833 |
/workspace/coverage/default/3.spi_device_csb_read.3649125886 |
|
|
Mar 03 02:05:49 PM PST 24 |
Mar 03 02:05:50 PM PST 24 |
33597553 ps |
T834 |
/workspace/coverage/default/40.spi_device_tpm_sts_read.494342921 |
|
|
Mar 03 02:08:15 PM PST 24 |
Mar 03 02:08:17 PM PST 24 |
139996234 ps |
T80 |
/workspace/coverage/default/3.spi_device_sec_cm.2376267475 |
|
|
Mar 03 02:05:51 PM PST 24 |
Mar 03 02:05:52 PM PST 24 |
32538057 ps |
T835 |
/workspace/coverage/default/30.spi_device_csb_read.4005514731 |
|
|
Mar 03 02:07:26 PM PST 24 |
Mar 03 02:07:27 PM PST 24 |
16179755 ps |
T836 |
/workspace/coverage/default/46.spi_device_cfg_cmd.2757212276 |
|
|
Mar 03 02:08:36 PM PST 24 |
Mar 03 02:08:39 PM PST 24 |
196532763 ps |
T837 |
/workspace/coverage/default/41.spi_device_tpm_all.1606559713 |
|
|
Mar 03 02:08:18 PM PST 24 |
Mar 03 02:08:35 PM PST 24 |
1066181882 ps |
T838 |
/workspace/coverage/default/47.spi_device_pass_cmd_filtering.2495561600 |
|
|
Mar 03 02:08:35 PM PST 24 |
Mar 03 02:08:44 PM PST 24 |
956203741 ps |
T839 |
/workspace/coverage/default/36.spi_device_csb_read.3249931775 |
|
|
Mar 03 02:07:48 PM PST 24 |
Mar 03 02:07:49 PM PST 24 |
47471360 ps |
T840 |
/workspace/coverage/default/8.spi_device_mem_parity.4124640384 |
|
|
Mar 03 02:06:08 PM PST 24 |
Mar 03 02:06:10 PM PST 24 |
60844679 ps |
T269 |
/workspace/coverage/default/15.spi_device_stress_all.507573451 |
|
|
Mar 03 02:06:40 PM PST 24 |
Mar 03 02:12:03 PM PST 24 |
41058938703 ps |
T267 |
/workspace/coverage/default/27.spi_device_flash_and_tpm.1322000312 |
|
|
Mar 03 02:07:20 PM PST 24 |
Mar 03 02:08:59 PM PST 24 |
31639931488 ps |
T841 |
/workspace/coverage/default/3.spi_device_upload.1598207347 |
|
|
Mar 03 02:05:50 PM PST 24 |
Mar 03 02:06:09 PM PST 24 |
6216269590 ps |
T842 |
/workspace/coverage/default/37.spi_device_intercept.3007330707 |
|
|
Mar 03 02:07:57 PM PST 24 |
Mar 03 02:08:11 PM PST 24 |
4086210655 ps |
T843 |
/workspace/coverage/default/29.spi_device_mailbox.1650827160 |
|
|
Mar 03 02:07:27 PM PST 24 |
Mar 03 02:08:02 PM PST 24 |
10171211844 ps |
T844 |
/workspace/coverage/default/38.spi_device_upload.3963894455 |
|
|
Mar 03 02:08:06 PM PST 24 |
Mar 03 02:08:26 PM PST 24 |
28574892681 ps |
T845 |
/workspace/coverage/default/39.spi_device_pass_cmd_filtering.2231546334 |
|
|
Mar 03 02:08:07 PM PST 24 |
Mar 03 02:08:12 PM PST 24 |
2721910925 ps |
T846 |
/workspace/coverage/default/40.spi_device_cfg_cmd.3828322900 |
|
|
Mar 03 02:08:07 PM PST 24 |
Mar 03 02:08:11 PM PST 24 |
53245973 ps |
T847 |
/workspace/coverage/default/3.spi_device_flash_all.1980368583 |
|
|
Mar 03 02:05:51 PM PST 24 |
Mar 03 02:06:24 PM PST 24 |
14323450313 ps |
T848 |
/workspace/coverage/default/10.spi_device_tpm_sts_read.4102774636 |
|
|
Mar 03 02:06:14 PM PST 24 |
Mar 03 02:06:15 PM PST 24 |
167157570 ps |
T849 |
/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3154707056 |
|
|
Mar 03 02:07:31 PM PST 24 |
Mar 03 02:07:34 PM PST 24 |
172317444 ps |
T850 |
/workspace/coverage/default/7.spi_device_tpm_sts_read.2806732120 |
|
|
Mar 03 02:06:00 PM PST 24 |
Mar 03 02:06:01 PM PST 24 |
91367637 ps |
T851 |
/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.827701206 |
|
|
Mar 03 02:07:53 PM PST 24 |
Mar 03 02:08:16 PM PST 24 |
31291686261 ps |
T852 |
/workspace/coverage/default/10.spi_device_tpm_all.2299882687 |
|
|
Mar 03 02:06:13 PM PST 24 |
Mar 03 02:06:25 PM PST 24 |
4188479256 ps |
T853 |
/workspace/coverage/default/6.spi_device_tpm_all.2617380337 |
|
|
Mar 03 02:06:03 PM PST 24 |
Mar 03 02:06:26 PM PST 24 |
4429457674 ps |
T854 |
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2511971671 |
|
|
Mar 03 02:06:00 PM PST 24 |
Mar 03 02:06:06 PM PST 24 |
1807973872 ps |
T855 |
/workspace/coverage/default/45.spi_device_tpm_rw.1444054074 |
|
|
Mar 03 02:08:27 PM PST 24 |
Mar 03 02:08:28 PM PST 24 |
51733834 ps |
T268 |
/workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.681173279 |
|
|
Mar 03 02:06:22 PM PST 24 |
Mar 03 02:11:06 PM PST 24 |
503364817449 ps |
T856 |
/workspace/coverage/default/42.spi_device_upload.3299838130 |
|
|
Mar 03 02:08:15 PM PST 24 |
Mar 03 02:08:33 PM PST 24 |
4231236377 ps |
T857 |
/workspace/coverage/default/30.spi_device_stress_all.1977637105 |
|
|
Mar 03 02:07:31 PM PST 24 |
Mar 03 02:10:27 PM PST 24 |
58367958476 ps |
T858 |
/workspace/coverage/default/36.spi_device_pass_cmd_filtering.3104858364 |
|
|
Mar 03 02:07:46 PM PST 24 |
Mar 03 02:07:50 PM PST 24 |
736616185 ps |
T859 |
/workspace/coverage/default/39.spi_device_cfg_cmd.1998278394 |
|
|
Mar 03 02:08:03 PM PST 24 |
Mar 03 02:08:06 PM PST 24 |
1504751667 ps |
T860 |
/workspace/coverage/default/22.spi_device_tpm_read_hw_reg.309463680 |
|
|
Mar 03 02:06:53 PM PST 24 |
Mar 03 02:07:11 PM PST 24 |
6076384316 ps |
T861 |
/workspace/coverage/default/34.spi_device_tpm_sts_read.784555320 |
|
|
Mar 03 02:07:38 PM PST 24 |
Mar 03 02:07:39 PM PST 24 |
190059531 ps |
T862 |
/workspace/coverage/default/33.spi_device_tpm_all.763885079 |
|
|
Mar 03 02:07:42 PM PST 24 |
Mar 03 02:08:19 PM PST 24 |
15936084982 ps |
T863 |
/workspace/coverage/default/30.spi_device_flash_and_tpm.2745288459 |
|
|
Mar 03 02:07:33 PM PST 24 |
Mar 03 02:08:09 PM PST 24 |
72917442069 ps |
T864 |
/workspace/coverage/default/8.spi_device_read_buffer_direct.2084216716 |
|
|
Mar 03 02:06:07 PM PST 24 |
Mar 03 02:06:13 PM PST 24 |
415081806 ps |
T865 |
/workspace/coverage/default/11.spi_device_pass_cmd_filtering.1690294824 |
|
|
Mar 03 02:06:18 PM PST 24 |
Mar 03 02:06:36 PM PST 24 |
38677201915 ps |
T866 |
/workspace/coverage/default/49.spi_device_read_buffer_direct.2243363820 |
|
|
Mar 03 02:08:44 PM PST 24 |
Mar 03 02:08:53 PM PST 24 |
7378845339 ps |
T867 |
/workspace/coverage/default/44.spi_device_mailbox.947001365 |
|
|
Mar 03 02:08:24 PM PST 24 |
Mar 03 02:08:51 PM PST 24 |
33972659144 ps |
T868 |
/workspace/coverage/default/18.spi_device_intercept.841571438 |
|
|
Mar 03 02:06:46 PM PST 24 |
Mar 03 02:06:56 PM PST 24 |
5296782295 ps |
T869 |
/workspace/coverage/default/38.spi_device_flash_mode.1400882015 |
|
|
Mar 03 02:08:01 PM PST 24 |
Mar 03 02:08:31 PM PST 24 |
25491039168 ps |
T870 |
/workspace/coverage/default/19.spi_device_tpm_all.594884059 |
|
|
Mar 03 02:06:47 PM PST 24 |
Mar 03 02:07:02 PM PST 24 |
7390918550 ps |
T871 |
/workspace/coverage/default/25.spi_device_read_buffer_direct.2924637505 |
|
|
Mar 03 02:07:06 PM PST 24 |
Mar 03 02:07:11 PM PST 24 |
3159046321 ps |
T872 |
/workspace/coverage/default/10.spi_device_tpm_rw.385390262 |
|
|
Mar 03 02:06:11 PM PST 24 |
Mar 03 02:06:13 PM PST 24 |
48216868 ps |
T873 |
/workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3541283291 |
|
|
Mar 03 02:05:56 PM PST 24 |
Mar 03 02:07:29 PM PST 24 |
34106488583 ps |
T874 |
/workspace/coverage/default/23.spi_device_mailbox.1084480580 |
|
|
Mar 03 02:07:02 PM PST 24 |
Mar 03 02:07:52 PM PST 24 |
15427310992 ps |
T875 |
/workspace/coverage/default/33.spi_device_alert_test.3953147653 |
|
|
Mar 03 02:07:41 PM PST 24 |
Mar 03 02:07:42 PM PST 24 |
11794151 ps |
T876 |
/workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.314322664 |
|
|
Mar 03 02:07:02 PM PST 24 |
Mar 03 02:08:27 PM PST 24 |
29126085146 ps |
T877 |
/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2640456506 |
|
|
Mar 03 02:07:13 PM PST 24 |
Mar 03 02:07:37 PM PST 24 |
23437709636 ps |
T878 |
/workspace/coverage/default/2.spi_device_tpm_rw.3702531175 |
|
|
Mar 03 02:05:47 PM PST 24 |
Mar 03 02:05:50 PM PST 24 |
277749736 ps |
T879 |
/workspace/coverage/default/17.spi_device_pass_cmd_filtering.558219634 |
|
|
Mar 03 02:06:43 PM PST 24 |
Mar 03 02:07:11 PM PST 24 |
9422870404 ps |
T880 |
/workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2848341794 |
|
|
Mar 03 02:06:19 PM PST 24 |
Mar 03 02:07:05 PM PST 24 |
5825662161 ps |
T881 |
/workspace/coverage/default/45.spi_device_flash_mode.1512516553 |
|
|
Mar 03 02:08:28 PM PST 24 |
Mar 03 02:09:22 PM PST 24 |
21163766831 ps |
T882 |
/workspace/coverage/default/9.spi_device_ram_cfg.1441485877 |
|
|
Mar 03 02:06:06 PM PST 24 |
Mar 03 02:06:07 PM PST 24 |
18033171 ps |
T883 |
/workspace/coverage/default/17.spi_device_flash_all.109158595 |
|
|
Mar 03 02:06:43 PM PST 24 |
Mar 03 02:07:08 PM PST 24 |
9915559297 ps |
T884 |
/workspace/coverage/default/31.spi_device_alert_test.4013157183 |
|
|
Mar 03 02:07:34 PM PST 24 |
Mar 03 02:07:35 PM PST 24 |
12073802 ps |
T885 |
/workspace/coverage/default/18.spi_device_read_buffer_direct.341797954 |
|
|
Mar 03 02:06:47 PM PST 24 |
Mar 03 02:06:53 PM PST 24 |
1076688216 ps |
T886 |
/workspace/coverage/default/6.spi_device_mem_parity.1555250071 |
|
|
Mar 03 02:05:58 PM PST 24 |
Mar 03 02:05:59 PM PST 24 |
81814098 ps |
T887 |
/workspace/coverage/default/25.spi_device_tpm_rw.323182325 |
|
|
Mar 03 02:07:06 PM PST 24 |
Mar 03 02:07:08 PM PST 24 |
585908995 ps |
T888 |
/workspace/coverage/default/31.spi_device_intercept.3680965509 |
|
|
Mar 03 02:07:34 PM PST 24 |
Mar 03 02:07:37 PM PST 24 |
381243729 ps |
T889 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.1974273489 |
|
|
Mar 03 02:08:35 PM PST 24 |
Mar 03 02:08:40 PM PST 24 |
917142324 ps |
T890 |
/workspace/coverage/default/16.spi_device_tpm_sts_read.2430658162 |
|
|
Mar 03 02:06:35 PM PST 24 |
Mar 03 02:06:35 PM PST 24 |
60040135 ps |
T891 |
/workspace/coverage/default/14.spi_device_read_buffer_direct.3360805976 |
|
|
Mar 03 02:06:28 PM PST 24 |
Mar 03 02:06:33 PM PST 24 |
954201047 ps |
T892 |
/workspace/coverage/default/28.spi_device_alert_test.94467819 |
|
|
Mar 03 02:07:26 PM PST 24 |
Mar 03 02:07:28 PM PST 24 |
44967472 ps |
T893 |
/workspace/coverage/default/47.spi_device_csb_read.1892278746 |
|
|
Mar 03 02:08:38 PM PST 24 |
Mar 03 02:08:40 PM PST 24 |
20857223 ps |
T894 |
/workspace/coverage/default/41.spi_device_read_buffer_direct.1914827497 |
|
|
Mar 03 02:08:13 PM PST 24 |
Mar 03 02:08:19 PM PST 24 |
1873804282 ps |
T895 |
/workspace/coverage/default/7.spi_device_csb_read.2897503010 |
|
|
Mar 03 02:06:00 PM PST 24 |
Mar 03 02:06:01 PM PST 24 |
57489069 ps |
T896 |
/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.754427437 |
|
|
Mar 03 02:06:20 PM PST 24 |
Mar 03 02:06:27 PM PST 24 |
1086076549 ps |
T897 |
/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2476676987 |
|
|
Mar 03 02:06:44 PM PST 24 |
Mar 03 02:08:37 PM PST 24 |
8972504503 ps |
T898 |
/workspace/coverage/default/1.spi_device_alert_test.2447234753 |
|
|
Mar 03 02:05:46 PM PST 24 |
Mar 03 02:05:48 PM PST 24 |
18080177 ps |
T899 |
/workspace/coverage/default/31.spi_device_pass_cmd_filtering.799997186 |
|
|
Mar 03 02:07:31 PM PST 24 |
Mar 03 02:07:36 PM PST 24 |
1742087320 ps |
T900 |
/workspace/coverage/default/39.spi_device_upload.366516050 |
|
|
Mar 03 02:08:03 PM PST 24 |
Mar 03 02:08:13 PM PST 24 |
1433093802 ps |
T901 |
/workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3357423698 |
|
|
Mar 03 02:08:36 PM PST 24 |
Mar 03 02:09:28 PM PST 24 |
3209859639 ps |
T250 |
/workspace/coverage/default/14.spi_device_flash_all.604431269 |
|
|
Mar 03 02:06:28 PM PST 24 |
Mar 03 02:14:17 PM PST 24 |
351903212142 ps |
T902 |
/workspace/coverage/default/5.spi_device_tpm_all.870220367 |
|
|
Mar 03 02:05:58 PM PST 24 |
Mar 03 02:06:31 PM PST 24 |
28820594476 ps |
T903 |
/workspace/coverage/default/20.spi_device_flash_and_tpm.2578365881 |
|
|
Mar 03 02:06:55 PM PST 24 |
Mar 03 02:13:13 PM PST 24 |
57863026477 ps |
T904 |
/workspace/coverage/default/43.spi_device_csb_read.4160459392 |
|
|
Mar 03 02:08:15 PM PST 24 |
Mar 03 02:08:16 PM PST 24 |
64312777 ps |
T905 |
/workspace/coverage/default/24.spi_device_mailbox.2988237704 |
|
|
Mar 03 02:06:59 PM PST 24 |
Mar 03 02:07:16 PM PST 24 |
1262695194 ps |
T906 |
/workspace/coverage/default/13.spi_device_tpm_all.413804479 |
|
|
Mar 03 02:06:21 PM PST 24 |
Mar 03 02:06:59 PM PST 24 |
9407614362 ps |
T907 |
/workspace/coverage/default/1.spi_device_flash_and_tpm.2992667836 |
|
|
Mar 03 02:05:48 PM PST 24 |
Mar 03 02:14:25 PM PST 24 |
75460441288 ps |
T908 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.246225127 |
|
|
Mar 03 02:06:35 PM PST 24 |
Mar 03 02:06:48 PM PST 24 |
3944659622 ps |
T909 |
/workspace/coverage/default/10.spi_device_flash_all.2282273229 |
|
|
Mar 03 02:06:13 PM PST 24 |
Mar 03 02:07:40 PM PST 24 |
74362333039 ps |
T910 |
/workspace/coverage/default/0.spi_device_alert_test.3837914981 |
|
|
Mar 03 02:05:44 PM PST 24 |
Mar 03 02:05:45 PM PST 24 |
35665558 ps |
T911 |
/workspace/coverage/default/6.spi_device_tpm_rw.3751998367 |
|
|
Mar 03 02:05:59 PM PST 24 |
Mar 03 02:06:00 PM PST 24 |
21810479 ps |
T912 |
/workspace/coverage/default/2.spi_device_tpm_all.1873659034 |
|
|
Mar 03 02:05:46 PM PST 24 |
Mar 03 02:06:54 PM PST 24 |
12727781786 ps |
T913 |
/workspace/coverage/default/14.spi_device_stress_all.1701238618 |
|
|
Mar 03 02:06:27 PM PST 24 |
Mar 03 02:11:51 PM PST 24 |
69268304856 ps |
T914 |
/workspace/coverage/default/43.spi_device_tpm_rw.2047111566 |
|
|
Mar 03 02:08:16 PM PST 24 |
Mar 03 02:08:18 PM PST 24 |
215723996 ps |
T915 |
/workspace/coverage/default/11.spi_device_mailbox.3007481527 |
|
|
Mar 03 02:06:13 PM PST 24 |
Mar 03 02:06:41 PM PST 24 |
13451267492 ps |
T916 |
/workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.168904546 |
|
|
Mar 03 02:07:07 PM PST 24 |
Mar 03 02:08:49 PM PST 24 |
9016337790 ps |
T917 |
/workspace/coverage/default/1.spi_device_flash_all.774462313 |
|
|
Mar 03 02:05:47 PM PST 24 |
Mar 03 02:05:53 PM PST 24 |
1102657155 ps |
T918 |
/workspace/coverage/default/13.spi_device_csb_read.2029927541 |
|
|
Mar 03 02:06:19 PM PST 24 |
Mar 03 02:06:20 PM PST 24 |
20959204 ps |
T919 |
/workspace/coverage/default/35.spi_device_read_buffer_direct.3952169585 |
|
|
Mar 03 02:07:54 PM PST 24 |
Mar 03 02:07:59 PM PST 24 |
158517541 ps |
T81 |
/workspace/coverage/default/0.spi_device_sec_cm.4082878425 |
|
|
Mar 03 02:05:48 PM PST 24 |
Mar 03 02:05:49 PM PST 24 |
168887112 ps |
T920 |
/workspace/coverage/default/44.spi_device_upload.2331557622 |
|
|
Mar 03 02:08:20 PM PST 24 |
Mar 03 02:08:55 PM PST 24 |
67524654383 ps |
T921 |
/workspace/coverage/default/16.spi_device_alert_test.2235218625 |
|
|
Mar 03 02:06:41 PM PST 24 |
Mar 03 02:06:42 PM PST 24 |
92698998 ps |
T922 |
/workspace/coverage/default/23.spi_device_alert_test.3658745939 |
|
|
Mar 03 02:07:00 PM PST 24 |
Mar 03 02:07:01 PM PST 24 |
41367949 ps |
T264 |
/workspace/coverage/default/20.spi_device_stress_all.2006833920 |
|
|
Mar 03 02:06:53 PM PST 24 |
Mar 03 02:29:11 PM PST 24 |
199542850914 ps |
T923 |
/workspace/coverage/default/46.spi_device_stress_all.4012977962 |
|
|
Mar 03 02:08:35 PM PST 24 |
Mar 03 02:11:43 PM PST 24 |
134848414989 ps |
T924 |
/workspace/coverage/default/23.spi_device_stress_all.3180573241 |
|
|
Mar 03 02:06:59 PM PST 24 |
Mar 03 02:07:01 PM PST 24 |
49976796 ps |
T925 |
/workspace/coverage/default/42.spi_device_flash_and_tpm.1882591259 |
|
|
Mar 03 02:08:16 PM PST 24 |
Mar 03 02:09:37 PM PST 24 |
35238823537 ps |
T926 |
/workspace/coverage/default/21.spi_device_flash_and_tpm.236073014 |
|
|
Mar 03 02:06:56 PM PST 24 |
Mar 03 02:14:08 PM PST 24 |
60320516859 ps |
T927 |
/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4089997295 |
|
|
Mar 03 02:07:46 PM PST 24 |
Mar 03 02:10:16 PM PST 24 |
53853009576 ps |
T928 |
/workspace/coverage/default/16.spi_device_tpm_rw.1549923343 |
|
|
Mar 03 02:06:35 PM PST 24 |
Mar 03 02:06:36 PM PST 24 |
32204631 ps |
T929 |
/workspace/coverage/default/14.spi_device_mem_parity.3521817060 |
|
|
Mar 03 02:06:29 PM PST 24 |
Mar 03 02:06:32 PM PST 24 |
35534999 ps |
T273 |
/workspace/coverage/default/4.spi_device_stress_all.2000960018 |
|
|
Mar 03 02:06:04 PM PST 24 |
Mar 03 02:09:59 PM PST 24 |
82439146309 ps |
T930 |
/workspace/coverage/default/15.spi_device_intercept.1539053031 |
|
|
Mar 03 02:06:37 PM PST 24 |
Mar 03 02:06:44 PM PST 24 |
1668222660 ps |
T931 |
/workspace/coverage/default/6.spi_device_cfg_cmd.1182062203 |
|
|
Mar 03 02:05:58 PM PST 24 |
Mar 03 02:06:03 PM PST 24 |
316414993 ps |
T932 |
/workspace/coverage/default/26.spi_device_upload.2999435427 |
|
|
Mar 03 02:07:13 PM PST 24 |
Mar 03 02:07:23 PM PST 24 |
859326231 ps |
T933 |
/workspace/coverage/default/24.spi_device_cfg_cmd.364865990 |
|
|
Mar 03 02:07:01 PM PST 24 |
Mar 03 02:07:06 PM PST 24 |
304002753 ps |
T934 |
/workspace/coverage/default/8.spi_device_flash_and_tpm.151579511 |
|
|
Mar 03 02:06:04 PM PST 24 |
Mar 03 02:06:39 PM PST 24 |
4739519121 ps |
T935 |
/workspace/coverage/default/17.spi_device_tpm_all.4257008583 |
|
|
Mar 03 02:06:40 PM PST 24 |
Mar 03 02:07:27 PM PST 24 |
8016271376 ps |
T936 |
/workspace/coverage/default/7.spi_device_tpm_rw.1271595472 |
|
|
Mar 03 02:06:00 PM PST 24 |
Mar 03 02:06:02 PM PST 24 |
47826250 ps |
T937 |
/workspace/coverage/default/11.spi_device_tpm_sts_read.287334273 |
|
|
Mar 03 02:06:13 PM PST 24 |
Mar 03 02:06:15 PM PST 24 |
521997515 ps |
T938 |
/workspace/coverage/default/0.spi_device_read_buffer_direct.3201589522 |
|
|
Mar 03 02:05:39 PM PST 24 |
Mar 03 02:05:44 PM PST 24 |
2214246816 ps |
T939 |
/workspace/coverage/default/46.spi_device_tpm_all.2168576807 |
|
|
Mar 03 02:08:33 PM PST 24 |
Mar 03 02:08:52 PM PST 24 |
11953195604 ps |
T940 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.3877040045 |
|
|
Mar 03 02:05:52 PM PST 24 |
Mar 03 02:06:05 PM PST 24 |
5340822016 ps |
T941 |
/workspace/coverage/default/42.spi_device_flash_mode.1287033736 |
|
|
Mar 03 02:08:14 PM PST 24 |
Mar 03 02:08:26 PM PST 24 |
743649521 ps |
T942 |
/workspace/coverage/default/26.spi_device_flash_mode.3274380119 |
|
|
Mar 03 02:07:11 PM PST 24 |
Mar 03 02:07:30 PM PST 24 |
2577038723 ps |
T943 |
/workspace/coverage/default/42.spi_device_mailbox.2263665465 |
|
|
Mar 03 02:08:16 PM PST 24 |
Mar 03 02:08:30 PM PST 24 |
9466793906 ps |
T944 |
/workspace/coverage/default/19.spi_device_upload.1918320474 |
|
|
Mar 03 02:06:49 PM PST 24 |
Mar 03 02:06:59 PM PST 24 |
14932597743 ps |
T945 |
/workspace/coverage/default/2.spi_device_mem_parity.3831682608 |
|
|
Mar 03 02:05:44 PM PST 24 |
Mar 03 02:05:45 PM PST 24 |
42289943 ps |
T946 |
/workspace/coverage/default/17.spi_device_mailbox.4189718263 |
|
|
Mar 03 02:06:41 PM PST 24 |
Mar 03 02:07:00 PM PST 24 |
18829942842 ps |
T947 |
/workspace/coverage/default/42.spi_device_tpm_all.302115786 |
|
|
Mar 03 02:08:16 PM PST 24 |
Mar 03 02:08:58 PM PST 24 |
11543292458 ps |
T948 |
/workspace/coverage/default/13.spi_device_flash_all.2286105744 |
|
|
Mar 03 02:06:19 PM PST 24 |
Mar 03 02:09:00 PM PST 24 |
56570333167 ps |
T949 |
/workspace/coverage/default/45.spi_device_tpm_all.3645900163 |
|
|
Mar 03 02:08:28 PM PST 24 |
Mar 03 02:08:33 PM PST 24 |
353409843 ps |
T950 |
/workspace/coverage/default/24.spi_device_flash_mode.3906649723 |
|
|
Mar 03 02:07:07 PM PST 24 |
Mar 03 02:07:46 PM PST 24 |
7896885794 ps |
T951 |
/workspace/coverage/default/17.spi_device_intercept.3486183121 |
|
|
Mar 03 02:06:43 PM PST 24 |
Mar 03 02:06:56 PM PST 24 |
6864739815 ps |
T952 |
/workspace/coverage/default/15.spi_device_alert_test.235260476 |
|
|
Mar 03 02:06:40 PM PST 24 |
Mar 03 02:06:42 PM PST 24 |
11309255 ps |
T953 |
/workspace/coverage/default/10.spi_device_ram_cfg.614195937 |
|
|
Mar 03 02:06:18 PM PST 24 |
Mar 03 02:06:19 PM PST 24 |
66107921 ps |
T82 |
/workspace/coverage/default/1.spi_device_sec_cm.3017202966 |
|
|
Mar 03 02:05:48 PM PST 24 |
Mar 03 02:05:50 PM PST 24 |
124118543 ps |
T954 |
/workspace/coverage/default/30.spi_device_flash_mode.3174713744 |
|
|
Mar 03 02:07:34 PM PST 24 |
Mar 03 02:07:42 PM PST 24 |
295769667 ps |
T955 |
/workspace/coverage/default/38.spi_device_intercept.1225903928 |
|
|
Mar 03 02:08:02 PM PST 24 |
Mar 03 02:08:06 PM PST 24 |
4176384596 ps |
T956 |
/workspace/coverage/default/48.spi_device_alert_test.544457220 |
|
|
Mar 03 02:08:43 PM PST 24 |
Mar 03 02:08:44 PM PST 24 |
34818319 ps |
T957 |
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.225811783 |
|
|
Mar 03 02:06:10 PM PST 24 |
Mar 03 02:06:29 PM PST 24 |
5656240944 ps |
T958 |
/workspace/coverage/default/25.spi_device_flash_and_tpm.2306667390 |
|
|
Mar 03 02:07:05 PM PST 24 |
Mar 03 02:07:52 PM PST 24 |
12197484186 ps |
T959 |
/workspace/coverage/default/12.spi_device_tpm_all.1722878440 |
|
|
Mar 03 02:06:19 PM PST 24 |
Mar 03 02:06:38 PM PST 24 |
11872336533 ps |
T960 |
/workspace/coverage/default/21.spi_device_upload.401271085 |
|
|
Mar 03 02:06:56 PM PST 24 |
Mar 03 02:07:12 PM PST 24 |
14069800948 ps |
T961 |
/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3025777347 |
|
|
Mar 03 02:08:29 PM PST 24 |
Mar 03 02:08:39 PM PST 24 |
1946481312 ps |
T962 |
/workspace/coverage/default/1.spi_device_pass_cmd_filtering.4023915149 |
|
|
Mar 03 02:05:47 PM PST 24 |
Mar 03 02:05:51 PM PST 24 |
762854728 ps |
T963 |
/workspace/coverage/default/36.spi_device_tpm_rw.3553307552 |
|
|
Mar 03 02:07:54 PM PST 24 |
Mar 03 02:07:57 PM PST 24 |
94248108 ps |
T964 |
/workspace/coverage/default/7.spi_device_intercept.2675671505 |
|
|
Mar 03 02:05:58 PM PST 24 |
Mar 03 02:06:07 PM PST 24 |
4196356300 ps |
T965 |
/workspace/coverage/default/32.spi_device_tpm_rw.1606902984 |
|
|
Mar 03 02:07:39 PM PST 24 |
Mar 03 02:07:41 PM PST 24 |
294326478 ps |
T966 |
/workspace/coverage/default/28.spi_device_upload.2114220978 |
|
|
Mar 03 02:07:23 PM PST 24 |
Mar 03 02:07:57 PM PST 24 |
47433926496 ps |
T967 |
/workspace/coverage/default/13.spi_device_cfg_cmd.1500308396 |
|
|
Mar 03 02:06:25 PM PST 24 |
Mar 03 02:06:28 PM PST 24 |
98601933 ps |
T968 |
/workspace/coverage/default/20.spi_device_mailbox.3266945747 |
|
|
Mar 03 02:06:55 PM PST 24 |
Mar 03 02:07:04 PM PST 24 |
1014829136 ps |
T969 |
/workspace/coverage/default/22.spi_device_read_buffer_direct.588033299 |
|
|
Mar 03 02:07:05 PM PST 24 |
Mar 03 02:07:11 PM PST 24 |
4505975084 ps |
T970 |
/workspace/coverage/default/7.spi_device_cfg_cmd.760216706 |
|
|
Mar 03 02:06:11 PM PST 24 |
Mar 03 02:06:20 PM PST 24 |
4895292437 ps |
T971 |
/workspace/coverage/default/32.spi_device_cfg_cmd.2862955665 |
|
|
Mar 03 02:07:44 PM PST 24 |
Mar 03 02:07:47 PM PST 24 |
360458507 ps |
T972 |
/workspace/coverage/default/46.spi_device_alert_test.1671997807 |
|
|
Mar 03 02:08:36 PM PST 24 |
Mar 03 02:08:37 PM PST 24 |
49818267 ps |
T973 |
/workspace/coverage/default/9.spi_device_stress_all.1846224121 |
|
|
Mar 03 02:06:19 PM PST 24 |
Mar 03 02:06:20 PM PST 24 |
37707870 ps |
T974 |
/workspace/coverage/default/23.spi_device_cfg_cmd.456169559 |
|
|
Mar 03 02:06:59 PM PST 24 |
Mar 03 02:07:06 PM PST 24 |
1517068487 ps |
T975 |
/workspace/coverage/default/4.spi_device_ram_cfg.3340018525 |
|
|
Mar 03 02:05:53 PM PST 24 |
Mar 03 02:05:54 PM PST 24 |
19099658 ps |
T270 |
/workspace/coverage/default/38.spi_device_flash_all.2103034207 |
|
|
Mar 03 02:08:01 PM PST 24 |
Mar 03 02:12:12 PM PST 24 |
52420377614 ps |
T976 |
/workspace/coverage/default/32.spi_device_csb_read.3685721314 |
|
|
Mar 03 02:07:31 PM PST 24 |
Mar 03 02:07:33 PM PST 24 |
41109126 ps |
T977 |
/workspace/coverage/default/3.spi_device_ram_cfg.2824702177 |
|
|
Mar 03 02:05:48 PM PST 24 |
Mar 03 02:05:49 PM PST 24 |
33095666 ps |
T978 |
/workspace/coverage/default/33.spi_device_intercept.2250419937 |
|
|
Mar 03 02:07:38 PM PST 24 |
Mar 03 02:07:42 PM PST 24 |
1968448033 ps |
T979 |
/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3168677536 |
|
|
Mar 03 02:05:39 PM PST 24 |
Mar 03 02:05:57 PM PST 24 |
2979175883 ps |
T980 |
/workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1975363459 |
|
|
Mar 03 02:07:02 PM PST 24 |
Mar 03 02:07:09 PM PST 24 |
936459193 ps |
T981 |
/workspace/coverage/default/11.spi_device_alert_test.1076089582 |
|
|
Mar 03 02:06:18 PM PST 24 |
Mar 03 02:06:19 PM PST 24 |
13729403 ps |
T982 |
/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1238024851 |
|
|
Mar 03 02:07:12 PM PST 24 |
Mar 03 02:07:37 PM PST 24 |
12101350755 ps |
T983 |
/workspace/coverage/default/15.spi_device_flash_mode.2843436878 |
|
|
Mar 03 02:06:35 PM PST 24 |
Mar 03 02:06:42 PM PST 24 |
1396378813 ps |
T984 |
/workspace/coverage/default/12.spi_device_mailbox.4256713502 |
|
|
Mar 03 02:06:27 PM PST 24 |
Mar 03 02:06:50 PM PST 24 |
4631981899 ps |
T985 |
/workspace/coverage/default/49.spi_device_upload.1794212887 |
|
|
Mar 03 02:08:44 PM PST 24 |
Mar 03 02:08:53 PM PST 24 |
2204255100 ps |
T986 |
/workspace/coverage/default/27.spi_device_csb_read.3264625793 |
|
|
Mar 03 02:07:14 PM PST 24 |
Mar 03 02:07:17 PM PST 24 |
16815570 ps |
T987 |
/workspace/coverage/default/18.spi_device_mem_parity.2370932150 |
|
|
Mar 03 02:06:42 PM PST 24 |
Mar 03 02:06:44 PM PST 24 |
48055832 ps |
T988 |
/workspace/coverage/default/22.spi_device_upload.3171944359 |
|
|
Mar 03 02:06:59 PM PST 24 |
Mar 03 02:07:06 PM PST 24 |
990257887 ps |
T989 |
/workspace/coverage/default/20.spi_device_cfg_cmd.587482805 |
|
|
Mar 03 02:06:47 PM PST 24 |
Mar 03 02:06:50 PM PST 24 |
869171646 ps |
T102 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3123539228 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:32 PM PST 24 |
185382720 ps |
T126 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1198509896 |
|
|
Mar 03 02:10:15 PM PST 24 |
Mar 03 02:10:53 PM PST 24 |
560021658 ps |
T146 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3567810990 |
|
|
Mar 03 02:10:17 PM PST 24 |
Mar 03 02:10:19 PM PST 24 |
83698467 ps |
T990 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.622874826 |
|
|
Mar 03 02:10:30 PM PST 24 |
Mar 03 02:10:31 PM PST 24 |
17081389 ps |
T103 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3307939720 |
|
|
Mar 03 02:10:30 PM PST 24 |
Mar 03 02:10:45 PM PST 24 |
1133940719 ps |
T991 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2364673347 |
|
|
Mar 03 02:10:09 PM PST 24 |
Mar 03 02:10:34 PM PST 24 |
1464032008 ps |
T992 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1869445371 |
|
|
Mar 03 02:10:44 PM PST 24 |
Mar 03 02:10:44 PM PST 24 |
13387798 ps |
T993 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4129643971 |
|
|
Mar 03 02:10:08 PM PST 24 |
Mar 03 02:10:09 PM PST 24 |
54079050 ps |
T127 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.882618835 |
|
|
Mar 03 02:10:28 PM PST 24 |
Mar 03 02:10:30 PM PST 24 |
32065117 ps |
T104 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2716828163 |
|
|
Mar 03 02:10:26 PM PST 24 |
Mar 03 02:10:28 PM PST 24 |
213487208 ps |
T105 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3579820202 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:31 PM PST 24 |
143844022 ps |
T106 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3039775137 |
|
|
Mar 03 02:10:09 PM PST 24 |
Mar 03 02:10:29 PM PST 24 |
1133317515 ps |
T994 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2275598008 |
|
|
Mar 03 02:10:24 PM PST 24 |
Mar 03 02:10:26 PM PST 24 |
313187660 ps |
T995 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3601942298 |
|
|
Mar 03 02:10:24 PM PST 24 |
Mar 03 02:10:26 PM PST 24 |
118382131 ps |
T996 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.703857801 |
|
|
Mar 03 02:10:26 PM PST 24 |
Mar 03 02:10:28 PM PST 24 |
144232434 ps |
T107 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2186021659 |
|
|
Mar 03 02:10:10 PM PST 24 |
Mar 03 02:10:30 PM PST 24 |
5034587261 ps |
T108 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2404878826 |
|
|
Mar 03 02:10:28 PM PST 24 |
Mar 03 02:10:30 PM PST 24 |
45100215 ps |
T93 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3665229523 |
|
|
Mar 03 02:10:13 PM PST 24 |
Mar 03 02:10:15 PM PST 24 |
65739256 ps |
T997 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.2321470057 |
|
|
Mar 03 02:10:22 PM PST 24 |
Mar 03 02:10:23 PM PST 24 |
43670068 ps |
T998 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2486926675 |
|
|
Mar 03 02:10:14 PM PST 24 |
Mar 03 02:10:18 PM PST 24 |
111598435 ps |
T999 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.1057638022 |
|
|
Mar 03 02:10:26 PM PST 24 |
Mar 03 02:10:27 PM PST 24 |
47901325 ps |
T109 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1631444586 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:31 PM PST 24 |
534223043 ps |
T1000 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.1092327005 |
|
|
Mar 03 02:10:19 PM PST 24 |
Mar 03 02:10:19 PM PST 24 |
22740132 ps |
T128 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2384703478 |
|
|
Mar 03 02:10:07 PM PST 24 |
Mar 03 02:10:09 PM PST 24 |
93923174 ps |
T1001 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2679029126 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:30 PM PST 24 |
81732221 ps |
T121 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1329019961 |
|
|
Mar 03 02:10:19 PM PST 24 |
Mar 03 02:10:32 PM PST 24 |
764881662 ps |
T1002 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3917080469 |
|
|
Mar 03 02:10:08 PM PST 24 |
Mar 03 02:10:24 PM PST 24 |
884818340 ps |
T1003 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2500541983 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:31 PM PST 24 |
67472098 ps |
T129 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1526828882 |
|
|
Mar 03 02:10:06 PM PST 24 |
Mar 03 02:10:29 PM PST 24 |
1984031825 ps |
T130 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4080983945 |
|
|
Mar 03 02:10:12 PM PST 24 |
Mar 03 02:10:37 PM PST 24 |
3921502276 ps |
T1004 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3350675726 |
|
|
Mar 03 02:10:33 PM PST 24 |
Mar 03 02:10:34 PM PST 24 |
20933154 ps |
T115 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2063063947 |
|
|
Mar 03 02:10:24 PM PST 24 |
Mar 03 02:10:29 PM PST 24 |
277630266 ps |
T113 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2916820582 |
|
|
Mar 03 02:10:17 PM PST 24 |
Mar 03 02:10:22 PM PST 24 |
299339285 ps |
T116 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3589458847 |
|
|
Mar 03 02:10:17 PM PST 24 |
Mar 03 02:10:21 PM PST 24 |
50188209 ps |
T120 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2288870611 |
|
|
Mar 03 02:10:13 PM PST 24 |
Mar 03 02:10:16 PM PST 24 |
86233896 ps |
T1005 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3389718388 |
|
|
Mar 03 02:10:14 PM PST 24 |
Mar 03 02:10:18 PM PST 24 |
169851791 ps |
T1006 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3692632205 |
|
|
Mar 03 02:10:22 PM PST 24 |
Mar 03 02:10:23 PM PST 24 |
14565719 ps |
T94 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3676281500 |
|
|
Mar 03 02:10:07 PM PST 24 |
Mar 03 02:10:09 PM PST 24 |
37222698 ps |
T1007 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.690321630 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:31 PM PST 24 |
15416522 ps |
T131 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3567910725 |
|
|
Mar 03 02:10:22 PM PST 24 |
Mar 03 02:10:24 PM PST 24 |
260953894 ps |
T1008 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3539929617 |
|
|
Mar 03 02:10:20 PM PST 24 |
Mar 03 02:10:24 PM PST 24 |
60794905 ps |
T132 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3035633823 |
|
|
Mar 03 02:10:08 PM PST 24 |
Mar 03 02:10:43 PM PST 24 |
1065528206 ps |
T171 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1764213056 |
|
|
Mar 03 02:10:21 PM PST 24 |
Mar 03 02:10:43 PM PST 24 |
1644737780 ps |
T1009 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.860314237 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:30 PM PST 24 |
29386383 ps |
T1010 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1679497520 |
|
|
Mar 03 02:10:26 PM PST 24 |
Mar 03 02:10:27 PM PST 24 |
31055304 ps |
T173 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.192907293 |
|
|
Mar 03 02:10:21 PM PST 24 |
Mar 03 02:10:28 PM PST 24 |
112646925 ps |
T133 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.551407069 |
|
|
Mar 03 02:10:23 PM PST 24 |
Mar 03 02:10:25 PM PST 24 |
146668006 ps |
T1011 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.396363571 |
|
|
Mar 03 02:10:14 PM PST 24 |
Mar 03 02:10:28 PM PST 24 |
1272469930 ps |
T147 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2873618760 |
|
|
Mar 03 02:10:07 PM PST 24 |
Mar 03 02:10:25 PM PST 24 |
876066050 ps |
T148 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2244964505 |
|
|
Mar 03 02:10:32 PM PST 24 |
Mar 03 02:10:40 PM PST 24 |
299539211 ps |
T1012 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.2006781174 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:31 PM PST 24 |
14369459 ps |
T1013 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3907019025 |
|
|
Mar 03 02:10:22 PM PST 24 |
Mar 03 02:10:23 PM PST 24 |
17315479 ps |
T1014 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3314501444 |
|
|
Mar 03 02:10:22 PM PST 24 |
Mar 03 02:10:24 PM PST 24 |
31070644 ps |
T177 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.521885021 |
|
|
Mar 03 02:10:10 PM PST 24 |
Mar 03 02:10:34 PM PST 24 |
1404985116 ps |
T1015 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3135687346 |
|
|
Mar 03 02:10:24 PM PST 24 |
Mar 03 02:10:26 PM PST 24 |
82078708 ps |
T1016 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.566738395 |
|
|
Mar 03 02:10:22 PM PST 24 |
Mar 03 02:10:26 PM PST 24 |
53257546 ps |
T1017 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.1613202907 |
|
|
Mar 03 02:10:33 PM PST 24 |
Mar 03 02:10:34 PM PST 24 |
111329813 ps |
T149 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2880537225 |
|
|
Mar 03 02:10:10 PM PST 24 |
Mar 03 02:10:15 PM PST 24 |
205862293 ps |
T1018 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.389236221 |
|
|
Mar 03 02:10:13 PM PST 24 |
Mar 03 02:10:17 PM PST 24 |
38366256 ps |
T1019 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.909368891 |
|
|
Mar 03 02:10:29 PM PST 24 |
Mar 03 02:10:30 PM PST 24 |
13642775 ps |
T134 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4136789935 |
|
|
Mar 03 02:10:09 PM PST 24 |
Mar 03 02:10:11 PM PST 24 |
37004289 ps |
T1020 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1236003246 |
|
|
Mar 03 02:10:18 PM PST 24 |
Mar 03 02:10:20 PM PST 24 |
52083615 ps |