Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.38 94.45 98.61 89.36 97.08 95.82 98.22


Total test records in report: 1113
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T1021 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.11036725 Mar 03 02:10:22 PM PST 24 Mar 03 02:10:25 PM PST 24 152871426 ps
T1022 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2881456818 Mar 03 02:10:30 PM PST 24 Mar 03 02:10:31 PM PST 24 17500263 ps
T117 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.918294856 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:27 PM PST 24 209984477 ps
T1023 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1906464205 Mar 03 02:10:34 PM PST 24 Mar 03 02:10:35 PM PST 24 25445394 ps
T1024 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3440837152 Mar 03 02:10:24 PM PST 24 Mar 03 02:10:25 PM PST 24 40985335 ps
T118 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3428463551 Mar 03 02:10:12 PM PST 24 Mar 03 02:10:39 PM PST 24 4701540612 ps
T150 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.928019625 Mar 03 02:10:29 PM PST 24 Mar 03 02:10:32 PM PST 24 583812263 ps
T1025 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1425628868 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:24 PM PST 24 15459040 ps
T135 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3689563570 Mar 03 02:10:15 PM PST 24 Mar 03 02:10:18 PM PST 24 66777549 ps
T1026 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3917364477 Mar 03 02:10:26 PM PST 24 Mar 03 02:10:29 PM PST 24 40105163 ps
T1027 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4092174270 Mar 03 02:10:13 PM PST 24 Mar 03 02:10:22 PM PST 24 510447989 ps
T1028 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1064727428 Mar 03 02:10:16 PM PST 24 Mar 03 02:10:17 PM PST 24 12871010 ps
T136 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3307982214 Mar 03 02:10:08 PM PST 24 Mar 03 02:10:11 PM PST 24 208623467 ps
T1029 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.136271825 Mar 03 02:10:14 PM PST 24 Mar 03 02:10:22 PM PST 24 655679795 ps
T1030 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2616435111 Mar 03 02:10:12 PM PST 24 Mar 03 02:10:15 PM PST 24 178112173 ps
T1031 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1944569905 Mar 03 02:10:32 PM PST 24 Mar 03 02:10:33 PM PST 24 80150442 ps
T151 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3505966653 Mar 03 02:10:31 PM PST 24 Mar 03 02:10:34 PM PST 24 498359957 ps
T1032 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1808491956 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:24 PM PST 24 27220301 ps
T152 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.233519415 Mar 03 02:10:17 PM PST 24 Mar 03 02:10:19 PM PST 24 67924413 ps
T174 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1062789429 Mar 03 02:10:16 PM PST 24 Mar 03 02:10:24 PM PST 24 543945405 ps
T1033 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2581611374 Mar 03 02:10:10 PM PST 24 Mar 03 02:10:12 PM PST 24 11429232 ps
T1034 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3985769872 Mar 03 02:10:09 PM PST 24 Mar 03 02:10:10 PM PST 24 13684095 ps
T1035 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1871638413 Mar 03 02:10:22 PM PST 24 Mar 03 02:10:26 PM PST 24 469106025 ps
T1036 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.22413835 Mar 03 02:10:14 PM PST 24 Mar 03 02:10:17 PM PST 24 136036823 ps
T1037 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1934797817 Mar 03 02:10:30 PM PST 24 Mar 03 02:10:31 PM PST 24 42688721 ps
T1038 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.79447089 Mar 03 02:10:30 PM PST 24 Mar 03 02:10:31 PM PST 24 25227656 ps
T1039 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4253714728 Mar 03 02:10:26 PM PST 24 Mar 03 02:10:33 PM PST 24 427135028 ps
T137 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2554246521 Mar 03 02:10:13 PM PST 24 Mar 03 02:10:16 PM PST 24 27722248 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3748564797 Mar 03 02:10:11 PM PST 24 Mar 03 02:10:12 PM PST 24 174890315 ps
T1041 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1324325475 Mar 03 02:10:29 PM PST 24 Mar 03 02:10:31 PM PST 24 13800947 ps
T1042 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3312136933 Mar 03 02:10:34 PM PST 24 Mar 03 02:10:35 PM PST 24 26665711 ps
T1043 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1894086378 Mar 03 02:10:28 PM PST 24 Mar 03 02:10:29 PM PST 24 12161476 ps
T1044 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2822262149 Mar 03 02:10:33 PM PST 24 Mar 03 02:10:34 PM PST 24 20630998 ps
T1045 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.938278170 Mar 03 02:10:22 PM PST 24 Mar 03 02:10:24 PM PST 24 90111336 ps
T119 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2254211163 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:25 PM PST 24 62706332 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3817759120 Mar 03 02:10:07 PM PST 24 Mar 03 02:10:09 PM PST 24 606540558 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2173397703 Mar 03 02:10:14 PM PST 24 Mar 03 02:10:19 PM PST 24 197050339 ps
T1048 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.161711561 Mar 03 02:10:29 PM PST 24 Mar 03 02:10:30 PM PST 24 23323096 ps
T1049 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2427177068 Mar 03 02:10:14 PM PST 24 Mar 03 02:10:17 PM PST 24 45291204 ps
T1050 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2472213565 Mar 03 02:10:11 PM PST 24 Mar 03 02:10:14 PM PST 24 144300540 ps
T114 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2598957585 Mar 03 02:10:21 PM PST 24 Mar 03 02:10:25 PM PST 24 426268089 ps
T175 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1598319413 Mar 03 02:10:07 PM PST 24 Mar 03 02:10:14 PM PST 24 110392859 ps
T1051 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3023470851 Mar 03 02:10:14 PM PST 24 Mar 03 02:10:15 PM PST 24 14712285 ps
T1052 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1559582784 Mar 03 02:10:27 PM PST 24 Mar 03 02:10:33 PM PST 24 13210115 ps
T1053 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4049851805 Mar 03 02:10:22 PM PST 24 Mar 03 02:10:24 PM PST 24 46881182 ps
T1054 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.569442540 Mar 03 02:10:35 PM PST 24 Mar 03 02:10:36 PM PST 24 14083302 ps
T1055 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1928480781 Mar 03 02:10:27 PM PST 24 Mar 03 02:10:28 PM PST 24 36148522 ps
T1056 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1116366348 Mar 03 02:10:26 PM PST 24 Mar 03 02:10:27 PM PST 24 16404691 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1180046367 Mar 03 02:10:11 PM PST 24 Mar 03 02:10:15 PM PST 24 142386117 ps
T1058 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1681320896 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:24 PM PST 24 118841053 ps
T1059 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.288681140 Mar 03 02:10:35 PM PST 24 Mar 03 02:10:39 PM PST 24 340256923 ps
T1060 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1338146400 Mar 03 02:10:26 PM PST 24 Mar 03 02:10:31 PM PST 24 661570058 ps
T1061 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.237373028 Mar 03 02:10:32 PM PST 24 Mar 03 02:10:33 PM PST 24 18782956 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3244137118 Mar 03 02:10:09 PM PST 24 Mar 03 02:10:12 PM PST 24 198510836 ps
T1063 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1971750447 Mar 03 02:10:21 PM PST 24 Mar 03 02:10:25 PM PST 24 717461961 ps
T1064 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3627001123 Mar 03 02:10:28 PM PST 24 Mar 03 02:10:29 PM PST 24 18063942 ps
T1065 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1973167901 Mar 03 02:10:29 PM PST 24 Mar 03 02:10:52 PM PST 24 16087742977 ps
T1066 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1369035526 Mar 03 02:10:28 PM PST 24 Mar 03 02:10:30 PM PST 24 75254009 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1759999055 Mar 03 02:10:25 PM PST 24 Mar 03 02:10:28 PM PST 24 43092818 ps
T110 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3084983500 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:26 PM PST 24 108323359 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1784550031 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:27 PM PST 24 915052606 ps
T1069 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2395620004 Mar 03 02:10:29 PM PST 24 Mar 03 02:10:33 PM PST 24 118415609 ps
T1070 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3749130657 Mar 03 02:10:34 PM PST 24 Mar 03 02:10:35 PM PST 24 58847598 ps
T1071 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1098625175 Mar 03 02:10:16 PM PST 24 Mar 03 02:10:19 PM PST 24 143779144 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1194463568 Mar 03 02:10:25 PM PST 24 Mar 03 02:10:26 PM PST 24 183118370 ps
T1073 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1504998687 Mar 03 02:10:36 PM PST 24 Mar 03 02:10:37 PM PST 24 15978563 ps
T1074 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2707707172 Mar 03 02:10:44 PM PST 24 Mar 03 02:10:44 PM PST 24 24907148 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1757539633 Mar 03 02:10:08 PM PST 24 Mar 03 02:10:09 PM PST 24 15362259 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2120847330 Mar 03 02:10:24 PM PST 24 Mar 03 02:10:29 PM PST 24 155305854 ps
T1077 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2417783220 Mar 03 02:10:32 PM PST 24 Mar 03 02:10:32 PM PST 24 14989690 ps
T1078 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.803990770 Mar 03 02:10:11 PM PST 24 Mar 03 02:10:14 PM PST 24 65986683 ps
T1079 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4123235011 Mar 03 02:10:29 PM PST 24 Mar 03 02:10:31 PM PST 24 36985474 ps
T172 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.251391034 Mar 03 02:10:17 PM PST 24 Mar 03 02:10:39 PM PST 24 862449460 ps
T111 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.530903868 Mar 03 02:10:07 PM PST 24 Mar 03 02:10:10 PM PST 24 98856236 ps
T1080 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1739218868 Mar 03 02:10:10 PM PST 24 Mar 03 02:10:11 PM PST 24 14021539 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1059780262 Mar 03 02:10:11 PM PST 24 Mar 03 02:10:15 PM PST 24 53693469 ps
T1082 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3393638046 Mar 03 02:10:16 PM PST 24 Mar 03 02:10:18 PM PST 24 167080832 ps
T1083 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1352737258 Mar 03 02:10:24 PM PST 24 Mar 03 02:10:32 PM PST 24 366858085 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1716450542 Mar 03 02:10:09 PM PST 24 Mar 03 02:10:18 PM PST 24 351589921 ps
T176 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.41239670 Mar 03 02:10:25 PM PST 24 Mar 03 02:10:41 PM PST 24 2608740462 ps
T112 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4055929352 Mar 03 02:10:17 PM PST 24 Mar 03 02:10:22 PM PST 24 174018459 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3578836692 Mar 03 02:10:09 PM PST 24 Mar 03 02:10:13 PM PST 24 387503426 ps
T1086 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3785152124 Mar 03 02:10:26 PM PST 24 Mar 03 02:10:28 PM PST 24 64464929 ps
T1087 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3559435712 Mar 03 02:10:14 PM PST 24 Mar 03 02:10:16 PM PST 24 27835962 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1404746350 Mar 03 02:10:07 PM PST 24 Mar 03 02:10:11 PM PST 24 223379124 ps
T1089 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1877902500 Mar 03 02:10:30 PM PST 24 Mar 03 02:10:33 PM PST 24 508656723 ps
T95 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4283045894 Mar 03 02:10:18 PM PST 24 Mar 03 02:10:20 PM PST 24 130930087 ps
T1090 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.674948875 Mar 03 02:10:32 PM PST 24 Mar 03 02:10:34 PM PST 24 96336997 ps
T1091 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4195318191 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:26 PM PST 24 301960417 ps
T1092 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3740522974 Mar 03 02:10:44 PM PST 24 Mar 03 02:10:44 PM PST 24 23714712 ps
T1093 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3831112393 Mar 03 02:10:28 PM PST 24 Mar 03 02:10:30 PM PST 24 67344804 ps
T1094 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2867924191 Mar 03 02:10:24 PM PST 24 Mar 03 02:10:26 PM PST 24 255085882 ps
T96 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1175062343 Mar 03 02:10:06 PM PST 24 Mar 03 02:10:08 PM PST 24 206299197 ps
T1095 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4122228845 Mar 03 02:10:22 PM PST 24 Mar 03 02:10:25 PM PST 24 1143433971 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2418213377 Mar 03 02:10:09 PM PST 24 Mar 03 02:10:13 PM PST 24 60655509 ps
T1097 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1562950189 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:25 PM PST 24 45087550 ps
T1098 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.943635466 Mar 03 02:10:21 PM PST 24 Mar 03 02:10:22 PM PST 24 18960182 ps
T1099 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.967381482 Mar 03 02:10:22 PM PST 24 Mar 03 02:10:29 PM PST 24 377792154 ps
T1100 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2158116610 Mar 03 02:10:12 PM PST 24 Mar 03 02:10:14 PM PST 24 19405886 ps
T1101 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.696211975 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:26 PM PST 24 114037819 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3833474934 Mar 03 02:10:17 PM PST 24 Mar 03 02:10:30 PM PST 24 635180873 ps
T1103 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2954224213 Mar 03 02:10:33 PM PST 24 Mar 03 02:10:35 PM PST 24 42198261 ps
T1104 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.826426151 Mar 03 02:10:25 PM PST 24 Mar 03 02:10:29 PM PST 24 459127121 ps
T1105 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.732940936 Mar 03 02:10:12 PM PST 24 Mar 03 02:10:15 PM PST 24 21837476 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1231475251 Mar 03 02:10:31 PM PST 24 Mar 03 02:10:38 PM PST 24 195573961 ps
T1107 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1951748616 Mar 03 02:10:30 PM PST 24 Mar 03 02:10:31 PM PST 24 71266628 ps
T1108 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.535407154 Mar 03 02:10:23 PM PST 24 Mar 03 02:10:24 PM PST 24 41767904 ps
T1109 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.40118886 Mar 03 02:10:26 PM PST 24 Mar 03 02:10:29 PM PST 24 356637822 ps
T1110 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4038591734 Mar 03 02:10:07 PM PST 24 Mar 03 02:10:09 PM PST 24 42669661 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.267228161 Mar 03 02:10:14 PM PST 24 Mar 03 02:10:16 PM PST 24 12846938 ps
T1112 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3984439462 Mar 03 02:10:29 PM PST 24 Mar 03 02:10:31 PM PST 24 20069313 ps
T170 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4017697979 Mar 03 02:10:14 PM PST 24 Mar 03 02:10:20 PM PST 24 1314186689 ps
T1113 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.304080537 Mar 03 02:10:29 PM PST 24 Mar 03 02:10:30 PM PST 24 67937058 ps

Test location /workspace/coverage/default/46.spi_device_mailbox.2724703557
Short name T9
Test name
Test status
Simulation time 4631765954 ps
CPU time 10.22 seconds
Started Mar 03 02:08:38 PM PST 24
Finished Mar 03 02:08:48 PM PST 24
Peak memory 234220 kb
Host smart-de4e817a-ead3-49d3-b241-a2632060bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724703557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2724703557
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.690426813
Short name T32
Test name
Test status
Simulation time 105088429013 ps
CPU time 660.94 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:16:48 PM PST 24
Peak memory 281948 kb
Host smart-bf5b3a1a-ffd8-42d2-aa6a-0996e9efb5a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690426813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.690426813
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1680590263
Short name T42
Test name
Test status
Simulation time 36284900353 ps
CPU time 21.53 seconds
Started Mar 03 02:06:21 PM PST 24
Finished Mar 03 02:06:43 PM PST 24
Peak memory 240712 kb
Host smart-218fc630-c63e-4d01-8631-ddeafe750c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680590263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1680590263
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.345772867
Short name T75
Test name
Test status
Simulation time 121986997683 ps
CPU time 366.55 seconds
Started Mar 03 02:06:08 PM PST 24
Finished Mar 03 02:12:15 PM PST 24
Peak memory 298248 kb
Host smart-733a68ae-ae94-4f10-8962-46178d857415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345772867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.345772867
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2186021659
Short name T107
Test name
Test status
Simulation time 5034587261 ps
CPU time 18.4 seconds
Started Mar 03 02:10:10 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 214632 kb
Host smart-1962b27b-0f73-43b3-b13f-70802537c2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186021659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2186021659
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1158751006
Short name T142
Test name
Test status
Simulation time 30223129322 ps
CPU time 388.11 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:13:54 PM PST 24
Peak memory 316316 kb
Host smart-ebd83056-5760-4a87-b9ad-7c8439cbf000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158751006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1158751006
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3221296479
Short name T325
Test name
Test status
Simulation time 32382485 ps
CPU time 0.73 seconds
Started Mar 03 02:05:39 PM PST 24
Finished Mar 03 02:05:41 PM PST 24
Peak memory 216060 kb
Host smart-912491aa-7aeb-494c-9f0c-e423e52d0a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221296479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3221296479
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1667488710
Short name T21
Test name
Test status
Simulation time 47906642382 ps
CPU time 161.15 seconds
Started Mar 03 02:05:52 PM PST 24
Finished Mar 03 02:08:33 PM PST 24
Peak memory 261488 kb
Host smart-83a20441-64db-456c-bd77-3908cc1572dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667488710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1667488710
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2686476688
Short name T154
Test name
Test status
Simulation time 260800214628 ps
CPU time 1653.4 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:35:42 PM PST 24
Peak memory 312400 kb
Host smart-b400391e-e802-4617-b1c2-2d50ebdf6bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686476688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2686476688
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2063063947
Short name T115
Test name
Test status
Simulation time 277630266 ps
CPU time 4.43 seconds
Started Mar 03 02:10:24 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 214672 kb
Host smart-a117b645-ece1-40c3-a28b-e45b13542db5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063063947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2063063947
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1261022895
Short name T57
Test name
Test status
Simulation time 70096307866 ps
CPU time 242.56 seconds
Started Mar 03 02:08:30 PM PST 24
Finished Mar 03 02:12:32 PM PST 24
Peak memory 282084 kb
Host smart-00751665-396d-4015-9f4e-ac7b32fe75bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261022895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1261022895
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.426028062
Short name T78
Test name
Test status
Simulation time 234707661 ps
CPU time 1.06 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:05:50 PM PST 24
Peak memory 235108 kb
Host smart-491e17f8-cda0-4855-bac8-cf4c01eda20f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426028062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.426028062
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2613889048
Short name T87
Test name
Test status
Simulation time 131437447512 ps
CPU time 354.57 seconds
Started Mar 03 02:08:19 PM PST 24
Finished Mar 03 02:14:15 PM PST 24
Peak memory 267776 kb
Host smart-379b5828-6aa4-4140-b688-d4e405a0b46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613889048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2613889048
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3665229523
Short name T93
Test name
Test status
Simulation time 65739256 ps
CPU time 1.16 seconds
Started Mar 03 02:10:13 PM PST 24
Finished Mar 03 02:10:15 PM PST 24
Peak memory 206192 kb
Host smart-344864aa-eabf-49e6-ab6e-47a689c570af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665229523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3665229523
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.973103434
Short name T26
Test name
Test status
Simulation time 177940373800 ps
CPU time 655.56 seconds
Started Mar 03 02:07:14 PM PST 24
Finished Mar 03 02:18:12 PM PST 24
Peak memory 273688 kb
Host smart-30e512f7-9fca-4923-9343-213727964a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973103434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.973103434
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.697921692
Short name T6
Test name
Test status
Simulation time 49378520 ps
CPU time 1.09 seconds
Started Mar 03 02:06:09 PM PST 24
Finished Mar 03 02:06:10 PM PST 24
Peak memory 216528 kb
Host smart-3896c874-5301-4b20-a50b-a9881361219f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697921692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.697921692
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3895246245
Short name T258
Test name
Test status
Simulation time 35926516081 ps
CPU time 171.02 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:11:06 PM PST 24
Peak memory 265476 kb
Host smart-e9874825-38ae-414a-a708-0b13651fb5a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895246245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3895246245
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1099356901
Short name T41
Test name
Test status
Simulation time 313490762937 ps
CPU time 362.52 seconds
Started Mar 03 02:07:57 PM PST 24
Finished Mar 03 02:14:00 PM PST 24
Peak memory 259724 kb
Host smart-2aa3d07f-ae60-4565-9bec-0bc9c9e914f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099356901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1099356901
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3393005647
Short name T166
Test name
Test status
Simulation time 20498042790 ps
CPU time 98.27 seconds
Started Mar 03 02:06:36 PM PST 24
Finished Mar 03 02:08:15 PM PST 24
Peak memory 264184 kb
Host smart-9f690351-864f-421c-8f9e-62e8d8d60f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393005647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3393005647
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2367011259
Short name T71
Test name
Test status
Simulation time 97099176 ps
CPU time 0.75 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:06:13 PM PST 24
Peak memory 204236 kb
Host smart-ee4195ae-907a-42ac-a4ea-993bf017f8ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367011259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2367011259
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.253097753
Short name T53
Test name
Test status
Simulation time 28676847297 ps
CPU time 89.48 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:08:56 PM PST 24
Peak memory 250208 kb
Host smart-5901ab7f-4d7e-4362-bb3d-f9ddf290df2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253097753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.253097753
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4172531645
Short name T187
Test name
Test status
Simulation time 49018683217 ps
CPU time 234.51 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:09:53 PM PST 24
Peak memory 272504 kb
Host smart-d30031e9-2410-4e1a-9134-6ec257be95ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172531645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4172531645
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.302992807
Short name T11
Test name
Test status
Simulation time 12875215460 ps
CPU time 100.26 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:08:47 PM PST 24
Peak memory 244364 kb
Host smart-41d73794-5b0f-4710-80a3-c081da51c8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302992807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.302992807
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2151546886
Short name T319
Test name
Test status
Simulation time 19426548013 ps
CPU time 30.98 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:06:19 PM PST 24
Peak memory 233892 kb
Host smart-fb30ca5a-167b-4330-a389-b93c806672e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151546886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2151546886
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1413444310
Short name T196
Test name
Test status
Simulation time 275948277533 ps
CPU time 590.89 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:16:52 PM PST 24
Peak memory 253100 kb
Host smart-48209b52-974f-4984-b7f0-bc245b6b34a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413444310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1413444310
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4055929352
Short name T112
Test name
Test status
Simulation time 174018459 ps
CPU time 4.65 seconds
Started Mar 03 02:10:17 PM PST 24
Finished Mar 03 02:10:22 PM PST 24
Peak memory 214692 kb
Host smart-ef75c248-7a99-4045-8d28-eeb37aacef07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055929352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
055929352
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3039775137
Short name T106
Test name
Test status
Simulation time 1133317515 ps
CPU time 19.55 seconds
Started Mar 03 02:10:09 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 214664 kb
Host smart-8a39efaa-e465-4c12-b4ba-ecc8456adeb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039775137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3039775137
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.306188830
Short name T180
Test name
Test status
Simulation time 156336649656 ps
CPU time 290.64 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:10:39 PM PST 24
Peak memory 254920 kb
Host smart-2c408bd8-79e0-4eff-b25c-fa328cda4808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306188830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.306188830
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3309830557
Short name T233
Test name
Test status
Simulation time 378060611591 ps
CPU time 403.94 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:13:31 PM PST 24
Peak memory 264976 kb
Host smart-53c53f09-9f39-4fc4-ae7e-f9a1a822f6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309830557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3309830557
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1322000312
Short name T267
Test name
Test status
Simulation time 31639931488 ps
CPU time 98.57 seconds
Started Mar 03 02:07:20 PM PST 24
Finished Mar 03 02:08:59 PM PST 24
Peak memory 264228 kb
Host smart-f8897702-b52e-4285-ab50-622a8691a7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322000312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1322000312
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1640277476
Short name T254
Test name
Test status
Simulation time 47641766691 ps
CPU time 251.6 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:11:38 PM PST 24
Peak memory 250980 kb
Host smart-cc2552b2-6438-4f39-8b9b-aec2e8f031e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640277476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1640277476
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3852619674
Short name T51
Test name
Test status
Simulation time 32984392782 ps
CPU time 23.86 seconds
Started Mar 03 02:05:56 PM PST 24
Finished Mar 03 02:06:20 PM PST 24
Peak memory 216284 kb
Host smart-1e3f45fd-519c-4887-82ed-fb5d1f3a4588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852619674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3852619674
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1628074360
Short name T191
Test name
Test status
Simulation time 702598047 ps
CPU time 6.48 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:08:23 PM PST 24
Peak memory 238156 kb
Host smart-428c8f0b-9c99-43df-91b9-c729bd071215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628074360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1628074360
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.41239670
Short name T176
Test name
Test status
Simulation time 2608740462 ps
CPU time 15.82 seconds
Started Mar 03 02:10:25 PM PST 24
Finished Mar 03 02:10:41 PM PST 24
Peak memory 214720 kb
Host smart-9ea7e1b5-9ecc-4222-ba82-178f6b8c516f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41239670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_
tl_intg_err.41239670
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1764213056
Short name T171
Test name
Test status
Simulation time 1644737780 ps
CPU time 22.33 seconds
Started Mar 03 02:10:21 PM PST 24
Finished Mar 03 02:10:43 PM PST 24
Peak memory 214660 kb
Host smart-f64f4a90-d806-41ac-a534-8e4807dac893
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764213056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1764213056
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2467331287
Short name T99
Test name
Test status
Simulation time 114543501 ps
CPU time 1.07 seconds
Started Mar 03 02:05:40 PM PST 24
Finished Mar 03 02:05:42 PM PST 24
Peak memory 206300 kb
Host smart-0d95c4f3-3983-46fd-bdbb-0052e1b57a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467331287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2467331287
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1708670969
Short name T253
Test name
Test status
Simulation time 48475484655 ps
CPU time 193.13 seconds
Started Mar 03 02:06:20 PM PST 24
Finished Mar 03 02:09:33 PM PST 24
Peak memory 273696 kb
Host smart-32d60a87-5306-407c-8c70-a3d72fb8a571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708670969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1708670969
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.604431269
Short name T250
Test name
Test status
Simulation time 351903212142 ps
CPU time 469.6 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:14:17 PM PST 24
Peak memory 258708 kb
Host smart-4ed2b1b1-04eb-4d74-8c01-0f7952c3b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604431269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.604431269
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.507573451
Short name T269
Test name
Test status
Simulation time 41058938703 ps
CPU time 322.57 seconds
Started Mar 03 02:06:40 PM PST 24
Finished Mar 03 02:12:03 PM PST 24
Peak memory 249204 kb
Host smart-00ba75e6-63eb-49df-a87c-931a3e14e34f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507573451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.507573451
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3783251624
Short name T265
Test name
Test status
Simulation time 29083958871 ps
CPU time 225.58 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:12:01 PM PST 24
Peak memory 251064 kb
Host smart-70975bf2-4ee5-4084-984c-3a94092ddabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783251624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3783251624
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1185250375
Short name T262
Test name
Test status
Simulation time 67740725912 ps
CPU time 233.33 seconds
Started Mar 03 02:05:50 PM PST 24
Finished Mar 03 02:09:44 PM PST 24
Peak memory 262092 kb
Host smart-5ec0ac2f-ec13-477e-8873-4d825b640044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185250375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1185250375
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3084983500
Short name T110
Test name
Test status
Simulation time 108323359 ps
CPU time 3.72 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 215772 kb
Host smart-9946a3eb-72aa-4b2c-91e9-78a3c91caf45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084983500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3084983500
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3428463551
Short name T118
Test name
Test status
Simulation time 4701540612 ps
CPU time 25.57 seconds
Started Mar 03 02:10:12 PM PST 24
Finished Mar 03 02:10:39 PM PST 24
Peak memory 222904 kb
Host smart-d9dd0f84-3c8c-40f8-84ab-97d63ea8dddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428463551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3428463551
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3917080469
Short name T1002
Test name
Test status
Simulation time 884818340 ps
CPU time 15.66 seconds
Started Mar 03 02:10:08 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 206320 kb
Host smart-4fd76f1f-1723-4186-8ca6-5d5f2c604947
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917080469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3917080469
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2364673347
Short name T991
Test name
Test status
Simulation time 1464032008 ps
CPU time 25.01 seconds
Started Mar 03 02:10:09 PM PST 24
Finished Mar 03 02:10:34 PM PST 24
Peak memory 206376 kb
Host smart-7063adbf-1b2d-46f1-9087-9ebd40b93ac6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364673347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2364673347
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3676281500
Short name T94
Test name
Test status
Simulation time 37222698 ps
CPU time 1.2 seconds
Started Mar 03 02:10:07 PM PST 24
Finished Mar 03 02:10:09 PM PST 24
Peak memory 206412 kb
Host smart-193febfa-b771-48a4-827a-0093b6b8b86d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676281500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3676281500
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2427177068
Short name T1049
Test name
Test status
Simulation time 45291204 ps
CPU time 2.53 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:17 PM PST 24
Peak memory 214796 kb
Host smart-9bdb5b5d-06b1-4d7a-ad93-6ad1943b067c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427177068 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2427177068
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4136789935
Short name T134
Test name
Test status
Simulation time 37004289 ps
CPU time 1.31 seconds
Started Mar 03 02:10:09 PM PST 24
Finished Mar 03 02:10:11 PM PST 24
Peak memory 218144 kb
Host smart-37797690-15e6-4832-b0f0-01fdb8a608e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136789935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
136789935
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3748564797
Short name T1040
Test name
Test status
Simulation time 174890315 ps
CPU time 0.73 seconds
Started Mar 03 02:10:11 PM PST 24
Finished Mar 03 02:10:12 PM PST 24
Peak memory 202436 kb
Host smart-572fb648-8f1e-45d3-ac88-8b26666a6f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748564797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
748564797
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2384703478
Short name T128
Test name
Test status
Simulation time 93923174 ps
CPU time 1.8 seconds
Started Mar 03 02:10:07 PM PST 24
Finished Mar 03 02:10:09 PM PST 24
Peak memory 214548 kb
Host smart-db454e56-71b4-4c83-ba6b-6b6739158b97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384703478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2384703478
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4129643971
Short name T993
Test name
Test status
Simulation time 54079050 ps
CPU time 0.65 seconds
Started Mar 03 02:10:08 PM PST 24
Finished Mar 03 02:10:09 PM PST 24
Peak memory 202376 kb
Host smart-774a5048-ab77-4df9-9199-0924b1864282
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129643971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4129643971
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2880537225
Short name T149
Test name
Test status
Simulation time 205862293 ps
CPU time 4.84 seconds
Started Mar 03 02:10:10 PM PST 24
Finished Mar 03 02:10:15 PM PST 24
Peak memory 206464 kb
Host smart-0f928609-d319-4dd3-88cc-6d49c619216d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880537225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2880537225
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2173397703
Short name T1047
Test name
Test status
Simulation time 197050339 ps
CPU time 3.53 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:19 PM PST 24
Peak memory 214756 kb
Host smart-276aa310-1ed9-4deb-95a8-ef3d1491973c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173397703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
173397703
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.521885021
Short name T177
Test name
Test status
Simulation time 1404985116 ps
CPU time 23.39 seconds
Started Mar 03 02:10:10 PM PST 24
Finished Mar 03 02:10:34 PM PST 24
Peak memory 214624 kb
Host smart-db3519e2-181c-428a-936f-c7987c2297e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521885021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.521885021
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1526828882
Short name T129
Test name
Test status
Simulation time 1984031825 ps
CPU time 22.76 seconds
Started Mar 03 02:10:06 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 214692 kb
Host smart-6c613197-328a-4f98-98fb-d20dd247ce29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526828882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1526828882
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3035633823
Short name T132
Test name
Test status
Simulation time 1065528206 ps
CPU time 35.38 seconds
Started Mar 03 02:10:08 PM PST 24
Finished Mar 03 02:10:43 PM PST 24
Peak memory 206324 kb
Host smart-b0732d3e-7145-41e2-92ec-348837d7d2c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035633823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3035633823
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1175062343
Short name T96
Test name
Test status
Simulation time 206299197 ps
CPU time 1.47 seconds
Started Mar 03 02:10:06 PM PST 24
Finished Mar 03 02:10:08 PM PST 24
Peak memory 206176 kb
Host smart-dc3d1e06-59e5-46d5-ab09-2214f2c0215c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175062343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1175062343
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1180046367
Short name T1057
Test name
Test status
Simulation time 142386117 ps
CPU time 2.79 seconds
Started Mar 03 02:10:11 PM PST 24
Finished Mar 03 02:10:15 PM PST 24
Peak memory 215712 kb
Host smart-418ee25b-cba1-4ff0-b869-f7f3ecc64ea0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180046367 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1180046367
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4038591734
Short name T1110
Test name
Test status
Simulation time 42669661 ps
CPU time 1.4 seconds
Started Mar 03 02:10:07 PM PST 24
Finished Mar 03 02:10:09 PM PST 24
Peak memory 206432 kb
Host smart-436d763e-f6f5-474e-a22e-31627c59d53e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038591734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
038591734
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3985769872
Short name T1034
Test name
Test status
Simulation time 13684095 ps
CPU time 0.72 seconds
Started Mar 03 02:10:09 PM PST 24
Finished Mar 03 02:10:10 PM PST 24
Peak memory 202464 kb
Host smart-253dae07-de84-4a6d-87d6-c04404398564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985769872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
985769872
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.803990770
Short name T1078
Test name
Test status
Simulation time 65986683 ps
CPU time 2.35 seconds
Started Mar 03 02:10:11 PM PST 24
Finished Mar 03 02:10:14 PM PST 24
Peak memory 214536 kb
Host smart-1e45f3f3-0e0e-4c7f-bb3d-3cfe5b3b8b64
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803990770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.803990770
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2581611374
Short name T1033
Test name
Test status
Simulation time 11429232 ps
CPU time 0.73 seconds
Started Mar 03 02:10:10 PM PST 24
Finished Mar 03 02:10:12 PM PST 24
Peak memory 202376 kb
Host smart-0d9c5436-7df8-4480-98ed-93a336188689
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581611374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2581611374
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2418213377
Short name T1096
Test name
Test status
Simulation time 60655509 ps
CPU time 3.99 seconds
Started Mar 03 02:10:09 PM PST 24
Finished Mar 03 02:10:13 PM PST 24
Peak memory 214432 kb
Host smart-e235a064-abfb-4789-b6fa-fb25b8f31c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418213377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2418213377
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3578836692
Short name T1085
Test name
Test status
Simulation time 387503426 ps
CPU time 3.02 seconds
Started Mar 03 02:10:09 PM PST 24
Finished Mar 03 02:10:13 PM PST 24
Peak memory 214728 kb
Host smart-085a009c-3103-4859-adae-da87a90741cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578836692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
578836692
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1871638413
Short name T1035
Test name
Test status
Simulation time 469106025 ps
CPU time 3.94 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 216092 kb
Host smart-1b7e6314-7839-4881-a857-a702fb662c9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871638413 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1871638413
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3567910725
Short name T131
Test name
Test status
Simulation time 260953894 ps
CPU time 1.35 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 214608 kb
Host smart-9b5f868e-a356-4205-912a-8d2c38f0b482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567910725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3567910725
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1681320896
Short name T1058
Test name
Test status
Simulation time 118841053 ps
CPU time 0.73 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 202484 kb
Host smart-040a06c9-a531-41a2-be54-8044b14f875a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681320896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1681320896
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2867924191
Short name T1094
Test name
Test status
Simulation time 255085882 ps
CPU time 1.85 seconds
Started Mar 03 02:10:24 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 206288 kb
Host smart-85961c0d-28ca-45d7-a55e-81f0f709a160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867924191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2867924191
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2598957585
Short name T114
Test name
Test status
Simulation time 426268089 ps
CPU time 3.82 seconds
Started Mar 03 02:10:21 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 214708 kb
Host smart-baa4af3a-f390-49af-a4fc-177fe4de2ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598957585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2598957585
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.192907293
Short name T173
Test name
Test status
Simulation time 112646925 ps
CPU time 7.75 seconds
Started Mar 03 02:10:21 PM PST 24
Finished Mar 03 02:10:28 PM PST 24
Peak memory 214616 kb
Host smart-edeeed6e-a4f4-472d-b167-3cd8388c51a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192907293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.192907293
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.11036725
Short name T1021
Test name
Test status
Simulation time 152871426 ps
CPU time 2.85 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 215728 kb
Host smart-bb64e130-fb0a-47d4-b6b8-09b184123727
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11036725 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.11036725
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.943635466
Short name T1098
Test name
Test status
Simulation time 18960182 ps
CPU time 1.27 seconds
Started Mar 03 02:10:21 PM PST 24
Finished Mar 03 02:10:22 PM PST 24
Peak memory 214584 kb
Host smart-628e3ef5-d4de-44b0-9ef1-a8887b021572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943635466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.943635466
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1808491956
Short name T1032
Test name
Test status
Simulation time 27220301 ps
CPU time 0.76 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 202472 kb
Host smart-c201d53f-b59b-45cf-8022-9c282fb0530a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808491956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1808491956
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1759999055
Short name T1067
Test name
Test status
Simulation time 43092818 ps
CPU time 2.79 seconds
Started Mar 03 02:10:25 PM PST 24
Finished Mar 03 02:10:28 PM PST 24
Peak memory 206052 kb
Host smart-d9f4106c-4414-4f4f-a28f-e3599346c516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759999055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1759999055
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1352737258
Short name T1083
Test name
Test status
Simulation time 366858085 ps
CPU time 8.48 seconds
Started Mar 03 02:10:24 PM PST 24
Finished Mar 03 02:10:32 PM PST 24
Peak memory 214632 kb
Host smart-25d2f657-0143-4b39-a6fc-a40e2628ed28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352737258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1352737258
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1971750447
Short name T1063
Test name
Test status
Simulation time 717461961 ps
CPU time 3.75 seconds
Started Mar 03 02:10:21 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 216372 kb
Host smart-68b7f9c1-0bb3-47a6-998d-07407952ea60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971750447 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1971750447
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4195318191
Short name T1091
Test name
Test status
Simulation time 301960417 ps
CPU time 2.25 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 214648 kb
Host smart-215249f4-92e8-404c-bcaf-f40ca7c3df3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195318191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4195318191
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1425628868
Short name T1025
Test name
Test status
Simulation time 15459040 ps
CPU time 0.7 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 202472 kb
Host smart-b3c15452-eea0-458e-8682-2b7b090274c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425628868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1425628868
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2120847330
Short name T1076
Test name
Test status
Simulation time 155305854 ps
CPU time 4.51 seconds
Started Mar 03 02:10:24 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 214412 kb
Host smart-8e85223a-9385-49fb-8a42-f6f6f50fccc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120847330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2120847330
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.918294856
Short name T117
Test name
Test status
Simulation time 209984477 ps
CPU time 4.42 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:27 PM PST 24
Peak memory 214680 kb
Host smart-fe0fab5d-7bf5-4e25-9050-39366e5caf57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918294856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.918294856
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4253714728
Short name T1039
Test name
Test status
Simulation time 427135028 ps
CPU time 7.09 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:33 PM PST 24
Peak memory 214632 kb
Host smart-e5ee3193-8e48-4378-b9e1-f01ebd5b562e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253714728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4253714728
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1562950189
Short name T1097
Test name
Test status
Simulation time 45087550 ps
CPU time 1.71 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 214780 kb
Host smart-2d711191-5eed-49f5-888b-f68e79b03c52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562950189 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1562950189
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3917364477
Short name T1026
Test name
Test status
Simulation time 40105163 ps
CPU time 2.45 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 214632 kb
Host smart-13121251-5820-4413-9985-3fda1b121230
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917364477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3917364477
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3440837152
Short name T1024
Test name
Test status
Simulation time 40985335 ps
CPU time 0.78 seconds
Started Mar 03 02:10:24 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 202512 kb
Host smart-c04a4b1e-2586-4420-81e2-5f1927e04440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440837152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3440837152
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3539929617
Short name T1008
Test name
Test status
Simulation time 60794905 ps
CPU time 3.8 seconds
Started Mar 03 02:10:20 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 214476 kb
Host smart-293b74e1-47a5-42e6-b9d1-1434ad619c7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539929617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3539929617
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2254211163
Short name T119
Test name
Test status
Simulation time 62706332 ps
CPU time 1.58 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 214556 kb
Host smart-509c6068-ee6a-4d22-bc66-6dca4ee30ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254211163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2254211163
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.696211975
Short name T1101
Test name
Test status
Simulation time 114037819 ps
CPU time 2.96 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 214696 kb
Host smart-60df7aca-2bd0-46c2-9af9-5000adecea66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696211975 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.696211975
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.535407154
Short name T1108
Test name
Test status
Simulation time 41767904 ps
CPU time 1.35 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 214592 kb
Host smart-a822ef8a-4171-47e5-a4ce-648fead44b32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535407154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.535407154
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1194463568
Short name T1072
Test name
Test status
Simulation time 183118370 ps
CPU time 0.77 seconds
Started Mar 03 02:10:25 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 202448 kb
Host smart-d22350ec-40cb-418d-8b1a-d5a092f300d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194463568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1194463568
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3601942298
Short name T995
Test name
Test status
Simulation time 118382131 ps
CPU time 2.06 seconds
Started Mar 03 02:10:24 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 214496 kb
Host smart-13b0ea3a-b8d6-4ce4-9101-6ad3100cd6d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601942298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3601942298
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.967381482
Short name T1099
Test name
Test status
Simulation time 377792154 ps
CPU time 6.59 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 214644 kb
Host smart-bb2e88b2-5a18-4f19-be66-bcf572a30718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967381482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.967381482
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4122228845
Short name T1095
Test name
Test status
Simulation time 1143433971 ps
CPU time 2.78 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 215920 kb
Host smart-aee70cce-1aca-4a6f-81d3-904143a57b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122228845 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4122228845
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.551407069
Short name T133
Test name
Test status
Simulation time 146668006 ps
CPU time 2.1 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 206380 kb
Host smart-3a18be76-908d-4a4c-8be3-d87443713f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551407069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.551407069
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3692632205
Short name T1006
Test name
Test status
Simulation time 14565719 ps
CPU time 0.74 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:23 PM PST 24
Peak memory 202760 kb
Host smart-1a07c780-d752-4de1-bbf9-0e7d00d30099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692632205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3692632205
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3135687346
Short name T1015
Test name
Test status
Simulation time 82078708 ps
CPU time 1.89 seconds
Started Mar 03 02:10:24 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 214648 kb
Host smart-4e82ff7f-a701-483e-92c4-5b080f80c2c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135687346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3135687346
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4049851805
Short name T1053
Test name
Test status
Simulation time 46881182 ps
CPU time 1.59 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 214736 kb
Host smart-06d3f742-ec10-4208-8726-d819c17a5877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049851805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4049851805
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3123539228
Short name T102
Test name
Test status
Simulation time 185382720 ps
CPU time 3.14 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:32 PM PST 24
Peak memory 215688 kb
Host smart-935ae9b2-ad6c-4c5a-b0cb-43b57cbf0c02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123539228 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3123539228
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3831112393
Short name T1093
Test name
Test status
Simulation time 67344804 ps
CPU time 1.25 seconds
Started Mar 03 02:10:28 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 206396 kb
Host smart-2864f367-070d-4c3b-b24b-082e0d30efc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831112393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3831112393
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.161711561
Short name T1048
Test name
Test status
Simulation time 23323096 ps
CPU time 0.78 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 202676 kb
Host smart-2b018b5f-cd2e-4c93-9580-ce1197cd6cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161711561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.161711561
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.928019625
Short name T150
Test name
Test status
Simulation time 583812263 ps
CPU time 3.29 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:32 PM PST 24
Peak memory 214696 kb
Host smart-fd11ab00-1f30-4c9b-baa8-116d42042ba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928019625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.928019625
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.826426151
Short name T1104
Test name
Test status
Simulation time 459127121 ps
CPU time 3.6 seconds
Started Mar 03 02:10:25 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 214800 kb
Host smart-e264e9da-483a-44ba-bc47-b127f6253462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826426151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.826426151
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1973167901
Short name T1065
Test name
Test status
Simulation time 16087742977 ps
CPU time 22.75 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:52 PM PST 24
Peak memory 214900 kb
Host smart-ebaf3788-101d-4cc2-afa5-d3a02fe9fc94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973167901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1973167901
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.674948875
Short name T1090
Test name
Test status
Simulation time 96336997 ps
CPU time 1.75 seconds
Started Mar 03 02:10:32 PM PST 24
Finished Mar 03 02:10:34 PM PST 24
Peak memory 214712 kb
Host smart-f1d58695-5b52-4d82-8d44-2736da39f493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674948875 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.674948875
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.882618835
Short name T127
Test name
Test status
Simulation time 32065117 ps
CPU time 1.85 seconds
Started Mar 03 02:10:28 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 206376 kb
Host smart-7263320b-7e3a-44ba-8b48-30dc6e1e82e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882618835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.882618835
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2679029126
Short name T1001
Test name
Test status
Simulation time 81732221 ps
CPU time 0.75 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 202772 kb
Host smart-d468a9df-cc35-437b-9b30-9d01250afe57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679029126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2679029126
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3505966653
Short name T151
Test name
Test status
Simulation time 498359957 ps
CPU time 2.92 seconds
Started Mar 03 02:10:31 PM PST 24
Finished Mar 03 02:10:34 PM PST 24
Peak memory 206516 kb
Host smart-6a1a52d2-1762-4d49-a102-74fac6533b49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505966653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3505966653
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1631444586
Short name T109
Test name
Test status
Simulation time 534223043 ps
CPU time 1.94 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 214616 kb
Host smart-f2051aa8-bbda-473e-a771-f979e384bd9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631444586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1631444586
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3307939720
Short name T103
Test name
Test status
Simulation time 1133940719 ps
CPU time 15.18 seconds
Started Mar 03 02:10:30 PM PST 24
Finished Mar 03 02:10:45 PM PST 24
Peak memory 214648 kb
Host smart-9b9d7f8f-8065-4a7a-b624-edf4e691a9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307939720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3307939720
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3579820202
Short name T105
Test name
Test status
Simulation time 143844022 ps
CPU time 2.83 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 215756 kb
Host smart-f2d0b1e6-92ac-412f-9b00-4dd46abd1e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579820202 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3579820202
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1369035526
Short name T1066
Test name
Test status
Simulation time 75254009 ps
CPU time 2.17 seconds
Started Mar 03 02:10:28 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 214588 kb
Host smart-08ccfc7b-dd65-4331-b32c-941204e0e4b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369035526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1369035526
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.909368891
Short name T1019
Test name
Test status
Simulation time 13642775 ps
CPU time 0.8 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 202524 kb
Host smart-e1be25b6-d359-4332-a11f-fc62bd98e748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909368891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.909368891
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1877902500
Short name T1089
Test name
Test status
Simulation time 508656723 ps
CPU time 3.19 seconds
Started Mar 03 02:10:30 PM PST 24
Finished Mar 03 02:10:33 PM PST 24
Peak memory 214408 kb
Host smart-6d050032-6631-4365-9a98-fffd392d121b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877902500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1877902500
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2954224213
Short name T1103
Test name
Test status
Simulation time 42198261 ps
CPU time 2.83 seconds
Started Mar 03 02:10:33 PM PST 24
Finished Mar 03 02:10:35 PM PST 24
Peak memory 214660 kb
Host smart-7e7e034a-48ba-4607-af8c-75ee1972568c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954224213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2954224213
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2244964505
Short name T148
Test name
Test status
Simulation time 299539211 ps
CPU time 7.82 seconds
Started Mar 03 02:10:32 PM PST 24
Finished Mar 03 02:10:40 PM PST 24
Peak memory 214660 kb
Host smart-464f911d-3bbc-4f1f-a305-b0d5a09d252b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244964505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2244964505
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2395620004
Short name T1069
Test name
Test status
Simulation time 118415609 ps
CPU time 3.1 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:33 PM PST 24
Peak memory 215792 kb
Host smart-d56c8d2b-48ea-40b0-a39b-467f99379f63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395620004 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2395620004
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2500541983
Short name T1003
Test name
Test status
Simulation time 67472098 ps
CPU time 1.37 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 206448 kb
Host smart-3c34ed18-ecd8-48ea-9fe2-f9f01736fab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500541983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2500541983
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4123235011
Short name T1079
Test name
Test status
Simulation time 36985474 ps
CPU time 0.76 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202796 kb
Host smart-3d4e7837-a71c-4537-93d4-efec153fe983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123235011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4123235011
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.288681140
Short name T1059
Test name
Test status
Simulation time 340256923 ps
CPU time 3.86 seconds
Started Mar 03 02:10:35 PM PST 24
Finished Mar 03 02:10:39 PM PST 24
Peak memory 214576 kb
Host smart-4ac75b40-012f-430c-887b-ee819284b4e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288681140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.288681140
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2404878826
Short name T108
Test name
Test status
Simulation time 45100215 ps
CPU time 1.68 seconds
Started Mar 03 02:10:28 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 215744 kb
Host smart-7a5eed55-eed2-4104-a811-6f69e0ed0169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404878826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2404878826
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1231475251
Short name T1106
Test name
Test status
Simulation time 195573961 ps
CPU time 7.02 seconds
Started Mar 03 02:10:31 PM PST 24
Finished Mar 03 02:10:38 PM PST 24
Peak memory 214648 kb
Host smart-b923be56-528f-4ebd-98d3-f3dd26ede775
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231475251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1231475251
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2873618760
Short name T147
Test name
Test status
Simulation time 876066050 ps
CPU time 17.79 seconds
Started Mar 03 02:10:07 PM PST 24
Finished Mar 03 02:10:25 PM PST 24
Peak memory 214624 kb
Host smart-455cb9d0-e2bc-4d57-a65d-f24eedff512f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873618760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2873618760
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.396363571
Short name T1011
Test name
Test status
Simulation time 1272469930 ps
CPU time 13.7 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:28 PM PST 24
Peak memory 206436 kb
Host smart-d05ce7a4-5e59-41b0-8f80-d56796116d07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396363571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.396363571
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3244137118
Short name T1062
Test name
Test status
Simulation time 198510836 ps
CPU time 2.93 seconds
Started Mar 03 02:10:09 PM PST 24
Finished Mar 03 02:10:12 PM PST 24
Peak memory 215948 kb
Host smart-db03162f-5670-4aeb-ac28-589e97ddb2b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244137118 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3244137118
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3817759120
Short name T1046
Test name
Test status
Simulation time 606540558 ps
CPU time 1.83 seconds
Started Mar 03 02:10:07 PM PST 24
Finished Mar 03 02:10:09 PM PST 24
Peak memory 214600 kb
Host smart-9a1279f3-6922-4ec6-b2e6-dbf08dbf043c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817759120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
817759120
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1757539633
Short name T1075
Test name
Test status
Simulation time 15362259 ps
CPU time 0.71 seconds
Started Mar 03 02:10:08 PM PST 24
Finished Mar 03 02:10:09 PM PST 24
Peak memory 202460 kb
Host smart-b51011fd-b24a-4d8a-bd95-ae240d339169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757539633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
757539633
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3307982214
Short name T136
Test name
Test status
Simulation time 208623467 ps
CPU time 2.37 seconds
Started Mar 03 02:10:08 PM PST 24
Finished Mar 03 02:10:11 PM PST 24
Peak memory 214620 kb
Host smart-a135d39d-c211-4a64-9a53-103f49ca3b84
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307982214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3307982214
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1739218868
Short name T1080
Test name
Test status
Simulation time 14021539 ps
CPU time 0.7 seconds
Started Mar 03 02:10:10 PM PST 24
Finished Mar 03 02:10:11 PM PST 24
Peak memory 202700 kb
Host smart-12a98925-1f3a-42f3-84fd-4519a83f25eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739218868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1739218868
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1404746350
Short name T1088
Test name
Test status
Simulation time 223379124 ps
CPU time 4.05 seconds
Started Mar 03 02:10:07 PM PST 24
Finished Mar 03 02:10:11 PM PST 24
Peak memory 206420 kb
Host smart-e6324671-fdee-40bd-889e-11fe1764addf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404746350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1404746350
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1059780262
Short name T1081
Test name
Test status
Simulation time 53693469 ps
CPU time 3.58 seconds
Started Mar 03 02:10:11 PM PST 24
Finished Mar 03 02:10:15 PM PST 24
Peak memory 214608 kb
Host smart-bab949d2-768f-431f-a105-e93e48ae39f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059780262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
059780262
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1716450542
Short name T1084
Test name
Test status
Simulation time 351589921 ps
CPU time 8.83 seconds
Started Mar 03 02:10:09 PM PST 24
Finished Mar 03 02:10:18 PM PST 24
Peak memory 214940 kb
Host smart-3beee00d-5af9-48c0-a561-1a0bef47f9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716450542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1716450542
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.622874826
Short name T990
Test name
Test status
Simulation time 17081389 ps
CPU time 0.72 seconds
Started Mar 03 02:10:30 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202784 kb
Host smart-2c23de54-91a5-482a-9bb8-0546301edcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622874826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.622874826
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.304080537
Short name T1113
Test name
Test status
Simulation time 67937058 ps
CPU time 0.72 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 202748 kb
Host smart-c7ebcafb-47b4-4cb8-80c6-8c90fb1e5713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304080537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.304080537
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.860314237
Short name T1009
Test name
Test status
Simulation time 29386383 ps
CPU time 0.78 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 202444 kb
Host smart-956fe38b-df13-4bdc-92ea-d84f016afbab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860314237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.860314237
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.237373028
Short name T1061
Test name
Test status
Simulation time 18782956 ps
CPU time 0.81 seconds
Started Mar 03 02:10:32 PM PST 24
Finished Mar 03 02:10:33 PM PST 24
Peak memory 202476 kb
Host smart-be26d19b-0bb2-435a-bf0a-0a8b4e5ce2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237373028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.237373028
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3350675726
Short name T1004
Test name
Test status
Simulation time 20933154 ps
CPU time 0.73 seconds
Started Mar 03 02:10:33 PM PST 24
Finished Mar 03 02:10:34 PM PST 24
Peak memory 202796 kb
Host smart-75ae063a-640a-474e-a3bb-5777a01fa630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350675726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3350675726
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3984439462
Short name T1112
Test name
Test status
Simulation time 20069313 ps
CPU time 0.81 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202520 kb
Host smart-8f2c5d6f-c189-46c9-a44e-c21a592e72ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984439462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3984439462
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1559582784
Short name T1052
Test name
Test status
Simulation time 13210115 ps
CPU time 0.72 seconds
Started Mar 03 02:10:27 PM PST 24
Finished Mar 03 02:10:33 PM PST 24
Peak memory 202460 kb
Host smart-10ae5ec4-0a29-43e4-b93d-66d896502b82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559582784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1559582784
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1944569905
Short name T1031
Test name
Test status
Simulation time 80150442 ps
CPU time 0.72 seconds
Started Mar 03 02:10:32 PM PST 24
Finished Mar 03 02:10:33 PM PST 24
Peak memory 202512 kb
Host smart-29fcdc61-ae09-482d-857d-1aff95ace3a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944569905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1944569905
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1679497520
Short name T1010
Test name
Test status
Simulation time 31055304 ps
CPU time 0.77 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:27 PM PST 24
Peak memory 202460 kb
Host smart-ddaf9ef7-bd53-4483-b03f-8705f4e9e1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679497520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1679497520
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3312136933
Short name T1042
Test name
Test status
Simulation time 26665711 ps
CPU time 0.76 seconds
Started Mar 03 02:10:34 PM PST 24
Finished Mar 03 02:10:35 PM PST 24
Peak memory 202508 kb
Host smart-f625bc0b-dfd2-4ba6-b2d3-abee457f673d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312136933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3312136933
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4092174270
Short name T1027
Test name
Test status
Simulation time 510447989 ps
CPU time 8.45 seconds
Started Mar 03 02:10:13 PM PST 24
Finished Mar 03 02:10:22 PM PST 24
Peak memory 206308 kb
Host smart-89c5181c-4fa6-4e08-bb40-f47c93652c25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092174270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4092174270
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3833474934
Short name T1102
Test name
Test status
Simulation time 635180873 ps
CPU time 12.99 seconds
Started Mar 03 02:10:17 PM PST 24
Finished Mar 03 02:10:30 PM PST 24
Peak memory 205936 kb
Host smart-991fce3d-a64e-45cd-b5a3-19bd64eef092
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833474934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3833474934
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4283045894
Short name T95
Test name
Test status
Simulation time 130930087 ps
CPU time 1.15 seconds
Started Mar 03 02:10:18 PM PST 24
Finished Mar 03 02:10:20 PM PST 24
Peak memory 206400 kb
Host smart-669c780e-d918-432f-8171-d74a289fc4ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283045894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4283045894
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.566738395
Short name T1016
Test name
Test status
Simulation time 53257546 ps
CPU time 3.94 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 215864 kb
Host smart-46013f66-decf-4ec5-b28a-c4cc56edb457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566738395 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.566738395
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.22413835
Short name T1036
Test name
Test status
Simulation time 136036823 ps
CPU time 2.07 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:17 PM PST 24
Peak memory 206368 kb
Host smart-b0c822b6-b20b-4293-bf8a-6739be49d61d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22413835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.22413835
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.267228161
Short name T1111
Test name
Test status
Simulation time 12846938 ps
CPU time 0.72 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:16 PM PST 24
Peak memory 202740 kb
Host smart-b0b3a29b-d07c-42ff-9833-42781be7f978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267228161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.267228161
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.732940936
Short name T1105
Test name
Test status
Simulation time 21837476 ps
CPU time 1.66 seconds
Started Mar 03 02:10:12 PM PST 24
Finished Mar 03 02:10:15 PM PST 24
Peak memory 214472 kb
Host smart-e7abe330-4309-4974-af4a-1ca7da470503
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732940936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.732940936
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1064727428
Short name T1028
Test name
Test status
Simulation time 12871010 ps
CPU time 0.7 seconds
Started Mar 03 02:10:16 PM PST 24
Finished Mar 03 02:10:17 PM PST 24
Peak memory 202344 kb
Host smart-f82be6bb-f5c0-495b-ac64-95bf22c24fa3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064727428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1064727428
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1784550031
Short name T1068
Test name
Test status
Simulation time 915052606 ps
CPU time 4.83 seconds
Started Mar 03 02:10:23 PM PST 24
Finished Mar 03 02:10:27 PM PST 24
Peak memory 214620 kb
Host smart-cc8afc27-e421-4db9-bc8a-351f8928488a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784550031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1784550031
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.530903868
Short name T111
Test name
Test status
Simulation time 98856236 ps
CPU time 3.05 seconds
Started Mar 03 02:10:07 PM PST 24
Finished Mar 03 02:10:10 PM PST 24
Peak memory 214812 kb
Host smart-a5a2b813-830d-454f-ab67-482d46a53f88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530903868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.530903868
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1598319413
Short name T175
Test name
Test status
Simulation time 110392859 ps
CPU time 7.29 seconds
Started Mar 03 02:10:07 PM PST 24
Finished Mar 03 02:10:14 PM PST 24
Peak memory 220772 kb
Host smart-fcafd9a7-1789-4ecd-b12d-ded7b3813eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598319413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1598319413
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2881456818
Short name T1022
Test name
Test status
Simulation time 17500263 ps
CPU time 0.78 seconds
Started Mar 03 02:10:30 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202472 kb
Host smart-0584bb64-ebf5-47ee-9dac-e4252637c1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881456818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2881456818
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1894086378
Short name T1043
Test name
Test status
Simulation time 12161476 ps
CPU time 0.79 seconds
Started Mar 03 02:10:28 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 202760 kb
Host smart-a59bb9b9-a8fb-40e6-9782-57a8ecacb1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894086378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1894086378
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1928480781
Short name T1055
Test name
Test status
Simulation time 36148522 ps
CPU time 0.78 seconds
Started Mar 03 02:10:27 PM PST 24
Finished Mar 03 02:10:28 PM PST 24
Peak memory 202744 kb
Host smart-7be89543-bd9f-45bc-9918-1a398aa5f5cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928480781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1928480781
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3740522974
Short name T1092
Test name
Test status
Simulation time 23714712 ps
CPU time 0.77 seconds
Started Mar 03 02:10:44 PM PST 24
Finished Mar 03 02:10:44 PM PST 24
Peak memory 202348 kb
Host smart-8bdedec7-91e5-40af-8b82-f8e9f7ae09f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740522974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3740522974
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2417783220
Short name T1077
Test name
Test status
Simulation time 14989690 ps
CPU time 0.74 seconds
Started Mar 03 02:10:32 PM PST 24
Finished Mar 03 02:10:32 PM PST 24
Peak memory 202464 kb
Host smart-b7303705-926d-4f98-8499-1f2c8403ec90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417783220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2417783220
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3627001123
Short name T1064
Test name
Test status
Simulation time 18063942 ps
CPU time 0.76 seconds
Started Mar 03 02:10:28 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 202476 kb
Host smart-961dcbba-f9c9-48b0-9891-eb1cfc744bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627001123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3627001123
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2707707172
Short name T1074
Test name
Test status
Simulation time 24907148 ps
CPU time 0.76 seconds
Started Mar 03 02:10:44 PM PST 24
Finished Mar 03 02:10:44 PM PST 24
Peak memory 202348 kb
Host smart-0df5db6f-9f40-463a-8225-13b53f7197b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707707172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2707707172
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1934797817
Short name T1037
Test name
Test status
Simulation time 42688721 ps
CPU time 0.72 seconds
Started Mar 03 02:10:30 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202792 kb
Host smart-027541d3-3ad3-4b0c-ae0a-94897510a176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934797817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1934797817
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.690321630
Short name T1007
Test name
Test status
Simulation time 15416522 ps
CPU time 0.74 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202788 kb
Host smart-8e2e5a53-fce8-46ce-a797-ac91023ef149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690321630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.690321630
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1869445371
Short name T992
Test name
Test status
Simulation time 13387798 ps
CPU time 0.74 seconds
Started Mar 03 02:10:44 PM PST 24
Finished Mar 03 02:10:44 PM PST 24
Peak memory 202340 kb
Host smart-3556a055-05ec-4f01-b3c9-0b8b4457348b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869445371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1869445371
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4080983945
Short name T130
Test name
Test status
Simulation time 3921502276 ps
CPU time 23.61 seconds
Started Mar 03 02:10:12 PM PST 24
Finished Mar 03 02:10:37 PM PST 24
Peak memory 206428 kb
Host smart-b227eb88-bfd0-43e8-8f8e-2471cae802ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080983945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4080983945
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1198509896
Short name T126
Test name
Test status
Simulation time 560021658 ps
CPU time 37.24 seconds
Started Mar 03 02:10:15 PM PST 24
Finished Mar 03 02:10:53 PM PST 24
Peak memory 206436 kb
Host smart-ca60f978-fd9a-4486-bb34-72485f18bfe1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198509896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1198509896
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2158116610
Short name T1100
Test name
Test status
Simulation time 19405886 ps
CPU time 1.19 seconds
Started Mar 03 02:10:12 PM PST 24
Finished Mar 03 02:10:14 PM PST 24
Peak memory 206472 kb
Host smart-3b2ad530-7959-49ee-b53c-75c103d9a585
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158116610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2158116610
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.389236221
Short name T1018
Test name
Test status
Simulation time 38366256 ps
CPU time 2.75 seconds
Started Mar 03 02:10:13 PM PST 24
Finished Mar 03 02:10:17 PM PST 24
Peak memory 215676 kb
Host smart-4ec870ba-b47d-40cc-8cc8-bd5a8e232dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389236221 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.389236221
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.703857801
Short name T996
Test name
Test status
Simulation time 144232434 ps
CPU time 1.41 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:28 PM PST 24
Peak memory 206280 kb
Host smart-422d2618-1ae5-4951-8dc7-fd26854cb406
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703857801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.703857801
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3559435712
Short name T1087
Test name
Test status
Simulation time 27835962 ps
CPU time 0.74 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:16 PM PST 24
Peak memory 202460 kb
Host smart-2d342dbc-63ba-4be9-9349-570be44074aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559435712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
559435712
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2554246521
Short name T137
Test name
Test status
Simulation time 27722248 ps
CPU time 2.16 seconds
Started Mar 03 02:10:13 PM PST 24
Finished Mar 03 02:10:16 PM PST 24
Peak memory 214584 kb
Host smart-776f5d23-c410-45ef-9203-6bb29d855d7f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554246521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2554246521
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3907019025
Short name T1013
Test name
Test status
Simulation time 17315479 ps
CPU time 0.67 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:23 PM PST 24
Peak memory 202356 kb
Host smart-7f374d64-4540-425c-bc26-52995af9affe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907019025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3907019025
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3389718388
Short name T1005
Test name
Test status
Simulation time 169851791 ps
CPU time 3.06 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:18 PM PST 24
Peak memory 214696 kb
Host smart-8f413cda-7416-4f17-a016-2a10fa389828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389718388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3389718388
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4017697979
Short name T170
Test name
Test status
Simulation time 1314186689 ps
CPU time 4.43 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:20 PM PST 24
Peak memory 214640 kb
Host smart-78b40577-a9fc-4482-adc2-cfcc04faba2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017697979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
017697979
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.251391034
Short name T172
Test name
Test status
Simulation time 862449460 ps
CPU time 21.99 seconds
Started Mar 03 02:10:17 PM PST 24
Finished Mar 03 02:10:39 PM PST 24
Peak memory 214668 kb
Host smart-85b57698-2c3c-43c2-a74e-184fd483278b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251391034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.251391034
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1324325475
Short name T1041
Test name
Test status
Simulation time 13800947 ps
CPU time 0.73 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202456 kb
Host smart-2e7641dc-83cd-4cc5-aa04-16118a772dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324325475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1324325475
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2822262149
Short name T1044
Test name
Test status
Simulation time 20630998 ps
CPU time 0.8 seconds
Started Mar 03 02:10:33 PM PST 24
Finished Mar 03 02:10:34 PM PST 24
Peak memory 202508 kb
Host smart-c2265c85-30a6-432d-ba91-a735e73ee45f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822262149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2822262149
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.79447089
Short name T1038
Test name
Test status
Simulation time 25227656 ps
CPU time 0.77 seconds
Started Mar 03 02:10:30 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202508 kb
Host smart-176d10c7-1aea-4511-81b0-9048e6028da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79447089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.79447089
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1906464205
Short name T1023
Test name
Test status
Simulation time 25445394 ps
CPU time 0.77 seconds
Started Mar 03 02:10:34 PM PST 24
Finished Mar 03 02:10:35 PM PST 24
Peak memory 202476 kb
Host smart-da3f4111-30f2-40ce-9e80-9ebae4ce3f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906464205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1906464205
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2006781174
Short name T1012
Test name
Test status
Simulation time 14369459 ps
CPU time 0.7 seconds
Started Mar 03 02:10:29 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202792 kb
Host smart-fb862813-9423-45d6-a2df-03f09e24682f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006781174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2006781174
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1613202907
Short name T1017
Test name
Test status
Simulation time 111329813 ps
CPU time 0.74 seconds
Started Mar 03 02:10:33 PM PST 24
Finished Mar 03 02:10:34 PM PST 24
Peak memory 202812 kb
Host smart-5c2fcdd7-949a-4242-914f-3fe0a36e333b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613202907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1613202907
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1951748616
Short name T1107
Test name
Test status
Simulation time 71266628 ps
CPU time 0.7 seconds
Started Mar 03 02:10:30 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 202792 kb
Host smart-d2bfd0d3-4ac7-4ae7-8a5f-35fea2de9912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951748616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1951748616
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3749130657
Short name T1070
Test name
Test status
Simulation time 58847598 ps
CPU time 0.76 seconds
Started Mar 03 02:10:34 PM PST 24
Finished Mar 03 02:10:35 PM PST 24
Peak memory 202496 kb
Host smart-641ba6c8-d5be-4374-9983-36123f3d782b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749130657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3749130657
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1504998687
Short name T1073
Test name
Test status
Simulation time 15978563 ps
CPU time 0.73 seconds
Started Mar 03 02:10:36 PM PST 24
Finished Mar 03 02:10:37 PM PST 24
Peak memory 202392 kb
Host smart-8fb282d7-3c26-4294-8ef0-0c8b1b93b3dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504998687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1504998687
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.569442540
Short name T1054
Test name
Test status
Simulation time 14083302 ps
CPU time 0.73 seconds
Started Mar 03 02:10:35 PM PST 24
Finished Mar 03 02:10:36 PM PST 24
Peak memory 202452 kb
Host smart-c9405daf-e2e8-45e1-9964-08458708d569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569442540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.569442540
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1236003246
Short name T1020
Test name
Test status
Simulation time 52083615 ps
CPU time 1.87 seconds
Started Mar 03 02:10:18 PM PST 24
Finished Mar 03 02:10:20 PM PST 24
Peak memory 214660 kb
Host smart-8a294f85-5d97-4794-b90f-be077269f1d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236003246 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1236003246
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3689563570
Short name T135
Test name
Test status
Simulation time 66777549 ps
CPU time 2.45 seconds
Started Mar 03 02:10:15 PM PST 24
Finished Mar 03 02:10:18 PM PST 24
Peak memory 218864 kb
Host smart-bcd26008-d6b4-4da1-b86e-f497a34ad49e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689563570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
689563570
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3023470851
Short name T1051
Test name
Test status
Simulation time 14712285 ps
CPU time 0.75 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:15 PM PST 24
Peak memory 202720 kb
Host smart-7f19a2d3-665d-4fa4-9426-e15889bf0148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023470851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
023470851
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1098625175
Short name T1071
Test name
Test status
Simulation time 143779144 ps
CPU time 3.37 seconds
Started Mar 03 02:10:16 PM PST 24
Finished Mar 03 02:10:19 PM PST 24
Peak memory 206356 kb
Host smart-72173613-1cfb-4a11-af59-9ce90e0c1b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098625175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1098625175
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3589458847
Short name T116
Test name
Test status
Simulation time 50188209 ps
CPU time 3.8 seconds
Started Mar 03 02:10:17 PM PST 24
Finished Mar 03 02:10:21 PM PST 24
Peak memory 215640 kb
Host smart-f9b2edb7-a188-4b98-820e-24b90709f4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589458847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
589458847
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.136271825
Short name T1029
Test name
Test status
Simulation time 655679795 ps
CPU time 8.09 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:22 PM PST 24
Peak memory 214632 kb
Host smart-5fd80f00-8890-475a-b1d4-dddc2e0b57c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136271825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.136271825
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2288870611
Short name T120
Test name
Test status
Simulation time 86233896 ps
CPU time 3.13 seconds
Started Mar 03 02:10:13 PM PST 24
Finished Mar 03 02:10:16 PM PST 24
Peak memory 216848 kb
Host smart-9a757a22-3415-4cab-a268-a0bf2656e5b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288870611 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2288870611
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3314501444
Short name T1014
Test name
Test status
Simulation time 31070644 ps
CPU time 2.01 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 206460 kb
Host smart-7b896542-81b8-441e-9422-10fc3007314a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314501444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
314501444
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1116366348
Short name T1056
Test name
Test status
Simulation time 16404691 ps
CPU time 0.75 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:27 PM PST 24
Peak memory 202708 kb
Host smart-faac8944-35cb-4db5-8c63-82955fee693f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116366348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
116366348
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2486926675
Short name T998
Test name
Test status
Simulation time 111598435 ps
CPU time 3.32 seconds
Started Mar 03 02:10:14 PM PST 24
Finished Mar 03 02:10:18 PM PST 24
Peak memory 206464 kb
Host smart-d8706e23-22ef-406e-a6af-8296d46c5cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486926675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2486926675
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1062789429
Short name T174
Test name
Test status
Simulation time 543945405 ps
CPU time 8.46 seconds
Started Mar 03 02:10:16 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 214604 kb
Host smart-50960bb3-0f73-4f44-80e9-8cc215295dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062789429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1062789429
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.233519415
Short name T152
Test name
Test status
Simulation time 67924413 ps
CPU time 2.14 seconds
Started Mar 03 02:10:17 PM PST 24
Finished Mar 03 02:10:19 PM PST 24
Peak memory 214304 kb
Host smart-de7de560-81ba-4c97-bd7e-8243ed7eb5a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233519415 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.233519415
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2472213565
Short name T1050
Test name
Test status
Simulation time 144300540 ps
CPU time 2.64 seconds
Started Mar 03 02:10:11 PM PST 24
Finished Mar 03 02:10:14 PM PST 24
Peak memory 206468 kb
Host smart-54c27cff-e33f-4256-b5be-53921c12e3db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472213565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
472213565
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1092327005
Short name T1000
Test name
Test status
Simulation time 22740132 ps
CPU time 0.76 seconds
Started Mar 03 02:10:19 PM PST 24
Finished Mar 03 02:10:19 PM PST 24
Peak memory 202512 kb
Host smart-8d2481c1-4927-4fe7-9b98-5bf04a4ea6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092327005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
092327005
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3567810990
Short name T146
Test name
Test status
Simulation time 83698467 ps
CPU time 1.9 seconds
Started Mar 03 02:10:17 PM PST 24
Finished Mar 03 02:10:19 PM PST 24
Peak memory 206348 kb
Host smart-62eb3099-f1c2-4851-b2c1-490df917541b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567810990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3567810990
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2916820582
Short name T113
Test name
Test status
Simulation time 299339285 ps
CPU time 4.47 seconds
Started Mar 03 02:10:17 PM PST 24
Finished Mar 03 02:10:22 PM PST 24
Peak memory 215740 kb
Host smart-4aa9787b-ea07-48a2-8044-b5a9eb00bb23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916820582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
916820582
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2616435111
Short name T1030
Test name
Test status
Simulation time 178112173 ps
CPU time 1.79 seconds
Started Mar 03 02:10:12 PM PST 24
Finished Mar 03 02:10:15 PM PST 24
Peak memory 214600 kb
Host smart-146c7700-0568-4e24-892d-8087b275ab91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616435111 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2616435111
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3785152124
Short name T1086
Test name
Test status
Simulation time 64464929 ps
CPU time 1.32 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:28 PM PST 24
Peak memory 214544 kb
Host smart-d39d6c5d-1719-436b-8357-2f76592b289e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785152124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
785152124
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1057638022
Short name T999
Test name
Test status
Simulation time 47901325 ps
CPU time 0.73 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:27 PM PST 24
Peak memory 202376 kb
Host smart-939f71ba-c419-4bd9-85d5-9ebad5c42927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057638022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
057638022
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1338146400
Short name T1060
Test name
Test status
Simulation time 661570058 ps
CPU time 4.41 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:31 PM PST 24
Peak memory 214536 kb
Host smart-d69a1202-b6f9-463f-b611-25beefc5be18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338146400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1338146400
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3393638046
Short name T1082
Test name
Test status
Simulation time 167080832 ps
CPU time 2.49 seconds
Started Mar 03 02:10:16 PM PST 24
Finished Mar 03 02:10:18 PM PST 24
Peak memory 214796 kb
Host smart-b013dc9e-c90f-4317-85de-0726ede13222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393638046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
393638046
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1329019961
Short name T121
Test name
Test status
Simulation time 764881662 ps
CPU time 12.98 seconds
Started Mar 03 02:10:19 PM PST 24
Finished Mar 03 02:10:32 PM PST 24
Peak memory 214648 kb
Host smart-6c272560-60bc-4092-b89b-466ced417426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329019961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1329019961
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.938278170
Short name T1045
Test name
Test status
Simulation time 90111336 ps
CPU time 2.03 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:24 PM PST 24
Peak memory 214708 kb
Host smart-08105736-d95b-413f-ac11-08c5bebd6852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938278170 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.938278170
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.40118886
Short name T1109
Test name
Test status
Simulation time 356637822 ps
CPU time 2.94 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:29 PM PST 24
Peak memory 214564 kb
Host smart-9ce6cbaf-2c57-4b6b-bb79-6b24ed82e9f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.40118886
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2321470057
Short name T997
Test name
Test status
Simulation time 43670068 ps
CPU time 0.78 seconds
Started Mar 03 02:10:22 PM PST 24
Finished Mar 03 02:10:23 PM PST 24
Peak memory 202472 kb
Host smart-b55aca9e-ca29-4d04-8d0e-3cc6bf933031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321470057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
321470057
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2275598008
Short name T994
Test name
Test status
Simulation time 313187660 ps
CPU time 2.09 seconds
Started Mar 03 02:10:24 PM PST 24
Finished Mar 03 02:10:26 PM PST 24
Peak memory 214644 kb
Host smart-6cb1f230-6535-4533-8347-d330f249b544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275598008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2275598008
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2716828163
Short name T104
Test name
Test status
Simulation time 213487208 ps
CPU time 1.55 seconds
Started Mar 03 02:10:26 PM PST 24
Finished Mar 03 02:10:28 PM PST 24
Peak memory 214596 kb
Host smart-ae2a9d45-b364-46fb-981a-03043b1aaef4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716828163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
716828163
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3837914981
Short name T910
Test name
Test status
Simulation time 35665558 ps
CPU time 0.73 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:05:45 PM PST 24
Peak memory 204724 kb
Host smart-bd9e742c-cfc3-4330-9476-fdd01eccaea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837914981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
837914981
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3628890059
Short name T602
Test name
Test status
Simulation time 38394152 ps
CPU time 2.29 seconds
Started Mar 03 02:05:39 PM PST 24
Finished Mar 03 02:05:42 PM PST 24
Peak memory 218280 kb
Host smart-c8f08940-d50d-458f-a0c3-54a54d673b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628890059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3628890059
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1326235801
Short name T674
Test name
Test status
Simulation time 44349304 ps
CPU time 0.78 seconds
Started Mar 03 02:05:40 PM PST 24
Finished Mar 03 02:05:41 PM PST 24
Peak memory 204956 kb
Host smart-ac81cb72-3c38-41a6-9b39-f085e57e73af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326235801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1326235801
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3993110393
Short name T200
Test name
Test status
Simulation time 14584673039 ps
CPU time 80.72 seconds
Started Mar 03 02:05:40 PM PST 24
Finished Mar 03 02:07:01 PM PST 24
Peak memory 248860 kb
Host smart-a6cd933a-b508-419b-ab64-9c68edc377cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993110393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3993110393
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1690974494
Short name T195
Test name
Test status
Simulation time 310606496937 ps
CPU time 573.72 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:15:17 PM PST 24
Peak memory 262892 kb
Host smart-a766dd28-a835-4b34-b798-b7f4e9ae95da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690974494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1690974494
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3636756011
Short name T732
Test name
Test status
Simulation time 84395200032 ps
CPU time 180.98 seconds
Started Mar 03 02:05:50 PM PST 24
Finished Mar 03 02:08:51 PM PST 24
Peak memory 249160 kb
Host smart-c43f8ff1-e74a-4bc0-83ed-c6378fcaef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636756011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3636756011
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1668583030
Short name T409
Test name
Test status
Simulation time 8978834498 ps
CPU time 27.88 seconds
Started Mar 03 02:05:40 PM PST 24
Finished Mar 03 02:06:09 PM PST 24
Peak memory 224416 kb
Host smart-3709f00b-ec86-401a-9880-c5d983c48c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668583030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1668583030
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3567540208
Short name T678
Test name
Test status
Simulation time 1539567148 ps
CPU time 7.27 seconds
Started Mar 03 02:05:37 PM PST 24
Finished Mar 03 02:05:44 PM PST 24
Peak memory 216732 kb
Host smart-c084b9dd-f89e-4d7c-b3c4-3e598a10df31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567540208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3567540208
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3393743813
Short name T680
Test name
Test status
Simulation time 14839382488 ps
CPU time 16.1 seconds
Started Mar 03 02:05:39 PM PST 24
Finished Mar 03 02:05:56 PM PST 24
Peak memory 238088 kb
Host smart-3e9d9d8e-fb56-4c4d-8a47-a73d56e83313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393743813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3393743813
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.4123046790
Short name T24
Test name
Test status
Simulation time 23720096 ps
CPU time 1.09 seconds
Started Mar 03 02:05:36 PM PST 24
Finished Mar 03 02:05:37 PM PST 24
Peak memory 217784 kb
Host smart-417d961c-2c18-4ef8-a11b-c5b17741d95e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123046790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.4123046790
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3168677536
Short name T979
Test name
Test status
Simulation time 2979175883 ps
CPU time 17.32 seconds
Started Mar 03 02:05:39 PM PST 24
Finished Mar 03 02:05:57 PM PST 24
Peak memory 229084 kb
Host smart-479ece17-dd50-4d1f-8f9b-ee625e5b195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168677536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3168677536
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.49284802
Short name T380
Test name
Test status
Simulation time 138689742 ps
CPU time 3.47 seconds
Started Mar 03 02:05:39 PM PST 24
Finished Mar 03 02:05:43 PM PST 24
Peak memory 233292 kb
Host smart-271d78d9-420a-4c0d-aaa2-0c563f691866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49284802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.49284802
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3201589522
Short name T938
Test name
Test status
Simulation time 2214246816 ps
CPU time 4.42 seconds
Started Mar 03 02:05:39 PM PST 24
Finished Mar 03 02:05:44 PM PST 24
Peak memory 218548 kb
Host smart-cc3a7625-1b93-423d-98f4-6e568c961f50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3201589522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3201589522
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4082878425
Short name T81
Test name
Test status
Simulation time 168887112 ps
CPU time 1.18 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:05:49 PM PST 24
Peak memory 234904 kb
Host smart-7deac4f2-fe5f-4006-b941-7faee5bb6c22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082878425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4082878425
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4105960230
Short name T157
Test name
Test status
Simulation time 45027348962 ps
CPU time 145.23 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:08:11 PM PST 24
Peak memory 256888 kb
Host smart-2306671f-9891-419d-970d-3469b5fc8ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105960230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4105960230
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.418861827
Short name T651
Test name
Test status
Simulation time 7545419327 ps
CPU time 26.45 seconds
Started Mar 03 02:05:40 PM PST 24
Finished Mar 03 02:06:07 PM PST 24
Peak memory 216252 kb
Host smart-fae953ee-dda5-4309-9527-53f172dfd7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418861827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.418861827
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.378265764
Short name T516
Test name
Test status
Simulation time 47141697222 ps
CPU time 21.96 seconds
Started Mar 03 02:05:37 PM PST 24
Finished Mar 03 02:06:00 PM PST 24
Peak memory 216308 kb
Host smart-a5352860-e998-4a80-8307-98503e727d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378265764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.378265764
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2465805475
Short name T527
Test name
Test status
Simulation time 166789099 ps
CPU time 6.68 seconds
Started Mar 03 02:05:38 PM PST 24
Finished Mar 03 02:05:47 PM PST 24
Peak memory 216224 kb
Host smart-f52503d6-c394-4164-a2f9-63d7285004f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465805475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2465805475
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_upload.1751200870
Short name T557
Test name
Test status
Simulation time 10284011885 ps
CPU time 37.44 seconds
Started Mar 03 02:05:39 PM PST 24
Finished Mar 03 02:06:17 PM PST 24
Peak memory 240500 kb
Host smart-7e6093f0-dd7a-4d7a-856a-b713acddc7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751200870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1751200870
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2447234753
Short name T898
Test name
Test status
Simulation time 18080177 ps
CPU time 0.72 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:05:48 PM PST 24
Peak memory 204824 kb
Host smart-8f32d9d5-d910-48ca-9f6f-440b61ef61fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447234753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
447234753
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3833404133
Short name T243
Test name
Test status
Simulation time 924028928 ps
CPU time 3.85 seconds
Started Mar 03 02:05:45 PM PST 24
Finished Mar 03 02:05:49 PM PST 24
Peak memory 217676 kb
Host smart-97a000c8-cb32-46ac-988b-c66782cdee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833404133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3833404133
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1274209776
Short name T464
Test name
Test status
Simulation time 93423899 ps
CPU time 0.82 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:05:48 PM PST 24
Peak memory 205992 kb
Host smart-8e5a523e-ea15-46a5-99fd-bba1a574881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274209776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1274209776
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.774462313
Short name T917
Test name
Test status
Simulation time 1102657155 ps
CPU time 6.3 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:05:53 PM PST 24
Peak memory 236000 kb
Host smart-ae3d03a5-6b6f-472c-ba15-f21302a90492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774462313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.774462313
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2992667836
Short name T907
Test name
Test status
Simulation time 75460441288 ps
CPU time 516.39 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:14:25 PM PST 24
Peak memory 266556 kb
Host smart-1bda8a84-746f-4cc9-b3dd-e9b93e03455e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992667836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2992667836
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1034266974
Short name T223
Test name
Test status
Simulation time 13035859087 ps
CPU time 91.33 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:07:18 PM PST 24
Peak memory 223496 kb
Host smart-64e0c0a7-7505-4d00-b132-d594eb2c259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034266974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1034266974
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.870844054
Short name T138
Test name
Test status
Simulation time 315405041 ps
CPU time 4.29 seconds
Started Mar 03 02:05:49 PM PST 24
Finished Mar 03 02:05:53 PM PST 24
Peak memory 232916 kb
Host smart-3f62d447-b9cf-4a9f-b5f5-0cb892f6b6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870844054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.870844054
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.106974417
Short name T823
Test name
Test status
Simulation time 3607013933 ps
CPU time 9.96 seconds
Started Mar 03 02:05:45 PM PST 24
Finished Mar 03 02:05:56 PM PST 24
Peak memory 230352 kb
Host smart-d18431d5-76e4-4b00-8c46-12a2b1da4950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106974417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.106974417
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1098977271
Short name T604
Test name
Test status
Simulation time 106515102 ps
CPU time 1.14 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:05:48 PM PST 24
Peak memory 217764 kb
Host smart-50a5a9f3-de9f-41f6-aa05-2991960f3119
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098977271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1098977271
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3582370422
Short name T190
Test name
Test status
Simulation time 10172747485 ps
CPU time 10.86 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:05:57 PM PST 24
Peak memory 224368 kb
Host smart-79599bf2-8b03-4ffd-83dd-799bff43c1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582370422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3582370422
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4023915149
Short name T962
Test name
Test status
Simulation time 762854728 ps
CPU time 3.58 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:05:51 PM PST 24
Peak memory 218168 kb
Host smart-1372d858-2608-44ee-8720-20c966c050cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023915149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4023915149
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3475564650
Short name T574
Test name
Test status
Simulation time 76968426 ps
CPU time 0.76 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:05:48 PM PST 24
Peak memory 216084 kb
Host smart-4d3ce23c-fead-43c5-be7c-51644da84de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475564650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3475564650
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1234895269
Short name T293
Test name
Test status
Simulation time 814232852 ps
CPU time 3.89 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:05:48 PM PST 24
Peak memory 220044 kb
Host smart-bc091cc9-2e6c-4652-aaa4-fc47fe42daaf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1234895269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1234895269
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3017202966
Short name T82
Test name
Test status
Simulation time 124118543 ps
CPU time 1.12 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:05:50 PM PST 24
Peak memory 235100 kb
Host smart-7306132b-fbe9-4bc8-addd-69b8753a44e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017202966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3017202966
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2599494076
Short name T156
Test name
Test status
Simulation time 18315349566 ps
CPU time 202.86 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:09:07 PM PST 24
Peak memory 269904 kb
Host smart-89158272-e934-4363-8d1b-635564b12791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599494076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2599494076
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3020776236
Short name T469
Test name
Test status
Simulation time 177239705414 ps
CPU time 51.5 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:06:40 PM PST 24
Peak memory 216256 kb
Host smart-8aaac7b0-37c4-4c7d-9b1b-fa0ddbbd2dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020776236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3020776236
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.658811417
Short name T358
Test name
Test status
Simulation time 224306052 ps
CPU time 2.25 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:05:49 PM PST 24
Peak memory 207700 kb
Host smart-3cf8f9f0-ec9d-4a11-a902-d980359d5996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658811417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.658811417
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.651386041
Short name T377
Test name
Test status
Simulation time 48474199 ps
CPU time 1.05 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:05:47 PM PST 24
Peak memory 206308 kb
Host smart-9cf89753-333a-47ff-91ab-4c9453543e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651386041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.651386041
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.128705100
Short name T584
Test name
Test status
Simulation time 22747927 ps
CPU time 0.75 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:05:45 PM PST 24
Peak memory 205344 kb
Host smart-ea085662-bba2-4667-912a-bf2bd1d1a258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128705100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.128705100
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3176562318
Short name T340
Test name
Test status
Simulation time 5401838932 ps
CPU time 16.35 seconds
Started Mar 03 02:05:45 PM PST 24
Finished Mar 03 02:06:02 PM PST 24
Peak memory 233804 kb
Host smart-20a177d3-1d22-4e86-976d-d4d4ead0ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176562318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3176562318
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2798870160
Short name T354
Test name
Test status
Simulation time 456402394 ps
CPU time 2.49 seconds
Started Mar 03 02:06:19 PM PST 24
Finished Mar 03 02:06:22 PM PST 24
Peak memory 218628 kb
Host smart-9572ca19-643c-46b3-af87-5cc14ac38c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798870160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2798870160
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1736041610
Short name T619
Test name
Test status
Simulation time 16665757 ps
CPU time 0.83 seconds
Started Mar 03 02:06:18 PM PST 24
Finished Mar 03 02:06:19 PM PST 24
Peak memory 206244 kb
Host smart-4c3bc7f8-bea7-46ac-b08c-1980bdd4a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736041610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1736041610
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2282273229
Short name T909
Test name
Test status
Simulation time 74362333039 ps
CPU time 86.56 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:07:40 PM PST 24
Peak memory 235844 kb
Host smart-4f469c10-2b22-4ffa-b440-edd5132c0554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282273229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2282273229
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2151602785
Short name T38
Test name
Test status
Simulation time 5016051648 ps
CPU time 107.22 seconds
Started Mar 03 02:06:19 PM PST 24
Finished Mar 03 02:08:06 PM PST 24
Peak memory 269928 kb
Host smart-73e29879-eded-4870-9f82-a59a62409b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151602785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2151602785
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.703871139
Short name T185
Test name
Test status
Simulation time 91176200145 ps
CPU time 559.7 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:15:33 PM PST 24
Peak memory 271008 kb
Host smart-39b14fd7-498d-4ac7-921a-60d2735ea36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703871139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.703871139
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3905727656
Short name T793
Test name
Test status
Simulation time 36819924131 ps
CPU time 39.52 seconds
Started Mar 03 02:06:16 PM PST 24
Finished Mar 03 02:06:55 PM PST 24
Peak memory 240648 kb
Host smart-0eba2579-1d73-494e-a0f4-f941ea6fcd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905727656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3905727656
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1654114535
Short name T675
Test name
Test status
Simulation time 7629946633 ps
CPU time 7.89 seconds
Started Mar 03 02:06:14 PM PST 24
Finished Mar 03 02:06:22 PM PST 24
Peak memory 224428 kb
Host smart-98fba984-22c5-459b-b67c-b0bc23f2e86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654114535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1654114535
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3358815336
Short name T482
Test name
Test status
Simulation time 247313173 ps
CPU time 3.82 seconds
Started Mar 03 02:06:18 PM PST 24
Finished Mar 03 02:06:22 PM PST 24
Peak memory 235248 kb
Host smart-c7bf8c6c-da66-4bef-9cbd-bceedca5fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358815336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3358815336
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2701763657
Short name T465
Test name
Test status
Simulation time 104005322 ps
CPU time 1.04 seconds
Started Mar 03 02:06:11 PM PST 24
Finished Mar 03 02:06:12 PM PST 24
Peak memory 216552 kb
Host smart-1ee0e5e4-ee27-4dff-95c2-e7f22c060888
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701763657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2701763657
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2036235529
Short name T402
Test name
Test status
Simulation time 15126596281 ps
CPU time 14.91 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:29 PM PST 24
Peak memory 232632 kb
Host smart-32be4e00-524b-4e50-a034-f5dcfdb4265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036235529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2036235529
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3360952721
Short name T819
Test name
Test status
Simulation time 1438738648 ps
CPU time 9.36 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:06:22 PM PST 24
Peak memory 233476 kb
Host smart-a7fd39d9-3f86-4704-a857-2907b5e34e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360952721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3360952721
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.614195937
Short name T953
Test name
Test status
Simulation time 66107921 ps
CPU time 0.79 seconds
Started Mar 03 02:06:18 PM PST 24
Finished Mar 03 02:06:19 PM PST 24
Peak memory 216084 kb
Host smart-644adf29-923b-4d70-a762-57488660364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614195937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.614195937
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1474404509
Short name T410
Test name
Test status
Simulation time 2356532742 ps
CPU time 4.86 seconds
Started Mar 03 02:06:15 PM PST 24
Finished Mar 03 02:06:20 PM PST 24
Peak memory 222048 kb
Host smart-fb823d2d-7ea3-4d1d-aff1-99f064a22c7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1474404509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1474404509
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.125037258
Short name T821
Test name
Test status
Simulation time 45584605472 ps
CPU time 206.5 seconds
Started Mar 03 02:06:14 PM PST 24
Finished Mar 03 02:09:41 PM PST 24
Peak memory 264160 kb
Host smart-f7080a29-b9cd-4764-a861-2ee6fa10a666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125037258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.125037258
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2299882687
Short name T852
Test name
Test status
Simulation time 4188479256 ps
CPU time 11.43 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:25 PM PST 24
Peak memory 216324 kb
Host smart-45b258dc-0f17-4fa0-a21b-3a647b738354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299882687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2299882687
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3817993630
Short name T805
Test name
Test status
Simulation time 9588638216 ps
CPU time 7.39 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:06:21 PM PST 24
Peak memory 216240 kb
Host smart-21c75879-8f58-4319-97b2-458f100fac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817993630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3817993630
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.385390262
Short name T872
Test name
Test status
Simulation time 48216868 ps
CPU time 1.74 seconds
Started Mar 03 02:06:11 PM PST 24
Finished Mar 03 02:06:13 PM PST 24
Peak memory 216184 kb
Host smart-398b055f-a6b5-4de6-a366-98388afab543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385390262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.385390262
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4102774636
Short name T848
Test name
Test status
Simulation time 167157570 ps
CPU time 0.85 seconds
Started Mar 03 02:06:14 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 205368 kb
Host smart-a619ebc9-5748-4194-ba07-0cb4e0beacbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102774636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4102774636
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1086991251
Short name T521
Test name
Test status
Simulation time 73250774499 ps
CPU time 23.96 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:38 PM PST 24
Peak memory 231812 kb
Host smart-a1bae225-160d-4375-9e17-0dd06de374e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086991251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1086991251
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1076089582
Short name T981
Test name
Test status
Simulation time 13729403 ps
CPU time 0.7 seconds
Started Mar 03 02:06:18 PM PST 24
Finished Mar 03 02:06:19 PM PST 24
Peak memory 204220 kb
Host smart-edb29bff-1ac4-4634-873a-faeae10d43a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076089582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1076089582
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.884881690
Short name T533
Test name
Test status
Simulation time 482035040 ps
CPU time 2.42 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:16 PM PST 24
Peak memory 224348 kb
Host smart-745e3c99-4ffb-42d2-b7ea-fea750efe097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884881690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.884881690
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1279903806
Short name T781
Test name
Test status
Simulation time 64315817 ps
CPU time 0.8 seconds
Started Mar 03 02:06:14 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 206336 kb
Host smart-a2981e1e-dbf7-42ed-b86a-a333e28ee07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279903806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1279903806
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3032008002
Short name T231
Test name
Test status
Simulation time 64460832910 ps
CPU time 130.4 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:08:24 PM PST 24
Peak memory 250932 kb
Host smart-1681c9cf-7a99-4517-9d32-7a9bf0f37fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032008002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3032008002
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2699795602
Short name T279
Test name
Test status
Simulation time 28862027337 ps
CPU time 95.39 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:07:48 PM PST 24
Peak memory 255964 kb
Host smart-ec14bd44-8341-4840-ad35-7c237cfd42f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699795602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2699795602
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2848341794
Short name T880
Test name
Test status
Simulation time 5825662161 ps
CPU time 45.72 seconds
Started Mar 03 02:06:19 PM PST 24
Finished Mar 03 02:07:05 PM PST 24
Peak memory 249172 kb
Host smart-f227640e-798c-4cbb-9bb4-86b934084b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848341794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2848341794
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2126805161
Short name T520
Test name
Test status
Simulation time 1295808019 ps
CPU time 10.19 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:06:22 PM PST 24
Peak memory 240764 kb
Host smart-05e8e714-5cc3-49b5-b49f-4fa38cca133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126805161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2126805161
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4065502511
Short name T673
Test name
Test status
Simulation time 56097067 ps
CPU time 2.6 seconds
Started Mar 03 02:06:14 PM PST 24
Finished Mar 03 02:06:17 PM PST 24
Peak memory 224368 kb
Host smart-0c651605-4499-4fd2-8e06-4caece2c44fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065502511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4065502511
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3007481527
Short name T915
Test name
Test status
Simulation time 13451267492 ps
CPU time 27.36 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:41 PM PST 24
Peak memory 248488 kb
Host smart-a5ef43c2-37cd-4fcc-898d-b3263778f790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007481527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3007481527
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.565957685
Short name T707
Test name
Test status
Simulation time 45489720 ps
CPU time 1.06 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 216524 kb
Host smart-857e4cf4-6103-4798-a2eb-af82887599e9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565957685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.565957685
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2404440652
Short name T37
Test name
Test status
Simulation time 51115793534 ps
CPU time 12.21 seconds
Started Mar 03 02:06:18 PM PST 24
Finished Mar 03 02:06:30 PM PST 24
Peak memory 233544 kb
Host smart-2862a33d-75d6-4c66-b04c-2021560989ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404440652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2404440652
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1690294824
Short name T865
Test name
Test status
Simulation time 38677201915 ps
CPU time 17.79 seconds
Started Mar 03 02:06:18 PM PST 24
Finished Mar 03 02:06:36 PM PST 24
Peak memory 232472 kb
Host smart-bdebb99f-e914-4b82-b9a9-aee4145366fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690294824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1690294824
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.2355683087
Short name T563
Test name
Test status
Simulation time 39095729 ps
CPU time 0.74 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:06:13 PM PST 24
Peak memory 215948 kb
Host smart-3506086a-6459-413e-9135-f11089fb5618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355683087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.2355683087
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.241202143
Short name T143
Test name
Test status
Simulation time 874363731 ps
CPU time 5.84 seconds
Started Mar 03 02:06:15 PM PST 24
Finished Mar 03 02:06:21 PM PST 24
Peak memory 222392 kb
Host smart-964e3626-2696-413e-9f2f-2d595e7db961
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=241202143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.241202143
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1627272299
Short name T153
Test name
Test status
Simulation time 14098821211 ps
CPU time 122.75 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:08:17 PM PST 24
Peak memory 249172 kb
Host smart-7fae111e-840b-43e7-a95f-382516dd9077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627272299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1627272299
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1042208229
Short name T827
Test name
Test status
Simulation time 16404373277 ps
CPU time 6.64 seconds
Started Mar 03 02:06:14 PM PST 24
Finished Mar 03 02:06:21 PM PST 24
Peak memory 216320 kb
Host smart-4a054bf7-42c1-4a7d-b316-8dcd471377e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042208229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1042208229
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1090080869
Short name T62
Test name
Test status
Simulation time 59547904707 ps
CPU time 35.55 seconds
Started Mar 03 02:06:19 PM PST 24
Finished Mar 03 02:06:54 PM PST 24
Peak memory 216332 kb
Host smart-c584fb5b-1c05-4ee9-a5dc-301fb225b8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090080869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1090080869
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3543096653
Short name T587
Test name
Test status
Simulation time 33444161 ps
CPU time 0.93 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 206040 kb
Host smart-44862109-9be6-4948-b98e-377013e4b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543096653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3543096653
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.287334273
Short name T937
Test name
Test status
Simulation time 521997515 ps
CPU time 0.95 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 206400 kb
Host smart-33329520-5ef4-4093-a8d5-238d5fe3523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287334273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.287334273
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2511776685
Short name T519
Test name
Test status
Simulation time 7812012422 ps
CPU time 16.26 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:06:29 PM PST 24
Peak memory 234956 kb
Host smart-cc84cea3-1374-42d4-ae0a-ed63cd16ebc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511776685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2511776685
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.144010530
Short name T417
Test name
Test status
Simulation time 31720124 ps
CPU time 0.71 seconds
Started Mar 03 02:06:20 PM PST 24
Finished Mar 03 02:06:21 PM PST 24
Peak memory 205236 kb
Host smart-08ebc886-bd21-4cf8-974d-1916a803c67d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144010530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.144010530
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2686161781
Short name T546
Test name
Test status
Simulation time 250557977 ps
CPU time 2.51 seconds
Started Mar 03 02:06:25 PM PST 24
Finished Mar 03 02:06:28 PM PST 24
Peak memory 233216 kb
Host smart-d63c8bf0-8769-4faa-bf56-e74d388bc5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686161781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2686161781
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2387969003
Short name T161
Test name
Test status
Simulation time 33428989 ps
CPU time 0.77 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:06:13 PM PST 24
Peak memory 206340 kb
Host smart-1110e553-f505-4691-b04f-c463a38c6ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387969003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2387969003
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.229174807
Short name T650
Test name
Test status
Simulation time 17693376801 ps
CPU time 111.75 seconds
Started Mar 03 02:06:20 PM PST 24
Finished Mar 03 02:08:12 PM PST 24
Peak memory 256412 kb
Host smart-bd07a8ca-9c53-4f6f-ac24-ac531a481c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229174807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.229174807
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2398592126
Short name T92
Test name
Test status
Simulation time 63428579355 ps
CPU time 177.75 seconds
Started Mar 03 02:06:24 PM PST 24
Finished Mar 03 02:09:22 PM PST 24
Peak memory 264688 kb
Host smart-0cd82dc2-0c64-42b5-9b94-2c3ea455e1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398592126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2398592126
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.681173279
Short name T268
Test name
Test status
Simulation time 503364817449 ps
CPU time 283.42 seconds
Started Mar 03 02:06:22 PM PST 24
Finished Mar 03 02:11:06 PM PST 24
Peak memory 252944 kb
Host smart-4befbc14-be91-4e69-b0e3-dab658b1648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681173279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.681173279
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1512996722
Short name T444
Test name
Test status
Simulation time 556772235 ps
CPU time 2.86 seconds
Started Mar 03 02:06:26 PM PST 24
Finished Mar 03 02:06:29 PM PST 24
Peak memory 224308 kb
Host smart-79caa31f-592e-446e-851c-995c4b30268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512996722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1512996722
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4256713502
Short name T984
Test name
Test status
Simulation time 4631981899 ps
CPU time 22.7 seconds
Started Mar 03 02:06:27 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 235904 kb
Host smart-52efbeb1-e4a0-4aa8-8538-a052d1f472c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256713502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4256713502
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3451334885
Short name T28
Test name
Test status
Simulation time 49278641 ps
CPU time 1.04 seconds
Started Mar 03 02:06:18 PM PST 24
Finished Mar 03 02:06:19 PM PST 24
Peak memory 216540 kb
Host smart-315d2b7e-3a9f-4ee8-b24e-f3182cc67021
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451334885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3451334885
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3898710136
Short name T552
Test name
Test status
Simulation time 23389938824 ps
CPU time 17.45 seconds
Started Mar 03 02:06:18 PM PST 24
Finished Mar 03 02:06:36 PM PST 24
Peak memory 233408 kb
Host smart-e28623c9-0fcb-419a-95d1-4350f48da5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898710136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3898710136
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.389880952
Short name T13
Test name
Test status
Simulation time 20525551945 ps
CPU time 16.33 seconds
Started Mar 03 02:06:22 PM PST 24
Finished Mar 03 02:06:39 PM PST 24
Peak memory 245632 kb
Host smart-4073801d-3b67-47f3-b3db-c3aa7d829b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389880952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.389880952
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3147137686
Short name T334
Test name
Test status
Simulation time 39322967 ps
CPU time 0.79 seconds
Started Mar 03 02:06:15 PM PST 24
Finished Mar 03 02:06:16 PM PST 24
Peak memory 216076 kb
Host smart-0a8c5bcf-71b6-4515-9d2e-68fab3213ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147137686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3147137686
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3279697664
Short name T414
Test name
Test status
Simulation time 151154722 ps
CPU time 3.77 seconds
Started Mar 03 02:06:21 PM PST 24
Finished Mar 03 02:06:25 PM PST 24
Peak memory 222548 kb
Host smart-632ccae0-4349-4f48-b474-f6447cba315b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3279697664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3279697664
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1722878440
Short name T959
Test name
Test status
Simulation time 11872336533 ps
CPU time 18.83 seconds
Started Mar 03 02:06:19 PM PST 24
Finished Mar 03 02:06:38 PM PST 24
Peak memory 216200 kb
Host smart-9fd165ee-6785-49e8-b592-186424d98b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722878440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1722878440
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.824950284
Short name T684
Test name
Test status
Simulation time 7412718238 ps
CPU time 11.64 seconds
Started Mar 03 02:06:21 PM PST 24
Finished Mar 03 02:06:33 PM PST 24
Peak memory 216156 kb
Host smart-2f4e426a-b489-405e-ad36-cc51b8d8fd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824950284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.824950284
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2777074476
Short name T290
Test name
Test status
Simulation time 22242370 ps
CPU time 0.83 seconds
Started Mar 03 02:06:22 PM PST 24
Finished Mar 03 02:06:23 PM PST 24
Peak memory 205344 kb
Host smart-8a39b134-a663-4a43-870e-10d045fc21a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777074476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2777074476
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1083582678
Short name T579
Test name
Test status
Simulation time 23750216 ps
CPU time 0.78 seconds
Started Mar 03 02:06:21 PM PST 24
Finished Mar 03 02:06:22 PM PST 24
Peak memory 205372 kb
Host smart-94856e64-2b78-48a3-8dfd-114c7f390f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083582678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1083582678
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3835178807
Short name T43
Test name
Test status
Simulation time 1273744071 ps
CPU time 4.01 seconds
Started Mar 03 02:06:20 PM PST 24
Finished Mar 03 02:06:25 PM PST 24
Peak memory 218780 kb
Host smart-17ca513c-8391-4ee3-b316-384ddaeb7c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835178807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3835178807
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1080451240
Short name T435
Test name
Test status
Simulation time 67340499 ps
CPU time 0.78 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:06:30 PM PST 24
Peak memory 204292 kb
Host smart-6dd24248-b84e-44e4-8c68-c9874b820d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080451240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1080451240
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1500308396
Short name T967
Test name
Test status
Simulation time 98601933 ps
CPU time 3.06 seconds
Started Mar 03 02:06:25 PM PST 24
Finished Mar 03 02:06:28 PM PST 24
Peak memory 233948 kb
Host smart-283972ff-b698-420e-a4e8-9387f5717a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500308396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1500308396
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2029927541
Short name T918
Test name
Test status
Simulation time 20959204 ps
CPU time 0.8 seconds
Started Mar 03 02:06:19 PM PST 24
Finished Mar 03 02:06:20 PM PST 24
Peak memory 206288 kb
Host smart-8c5a1f5e-5160-49ab-9828-c21a83d792b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029927541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2029927541
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2286105744
Short name T948
Test name
Test status
Simulation time 56570333167 ps
CPU time 161.37 seconds
Started Mar 03 02:06:19 PM PST 24
Finished Mar 03 02:09:00 PM PST 24
Peak memory 248864 kb
Host smart-17a38b71-6a97-4ab8-a2b2-aecc3124e54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286105744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2286105744
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3939330286
Short name T741
Test name
Test status
Simulation time 76857920408 ps
CPU time 286.95 seconds
Started Mar 03 02:06:24 PM PST 24
Finished Mar 03 02:11:12 PM PST 24
Peak memory 249720 kb
Host smart-55c65801-3cda-45bb-9bd0-987792e67109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939330286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3939330286
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2111290315
Short name T806
Test name
Test status
Simulation time 20944480800 ps
CPU time 45.64 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:07:16 PM PST 24
Peak memory 232784 kb
Host smart-d2dc72bd-fa01-4d66-b26c-06920f0a2cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111290315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2111290315
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2074565090
Short name T359
Test name
Test status
Simulation time 6006573072 ps
CPU time 30.01 seconds
Started Mar 03 02:06:24 PM PST 24
Finished Mar 03 02:06:55 PM PST 24
Peak memory 237028 kb
Host smart-e44e7695-fe42-4b06-bb8a-057f98876638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074565090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2074565090
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3590787122
Short name T755
Test name
Test status
Simulation time 229161606 ps
CPU time 4.41 seconds
Started Mar 03 02:06:21 PM PST 24
Finished Mar 03 02:06:25 PM PST 24
Peak memory 233432 kb
Host smart-f5e09067-c452-4266-8259-f6566fe56c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590787122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3590787122
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.405677161
Short name T615
Test name
Test status
Simulation time 9330398615 ps
CPU time 11.26 seconds
Started Mar 03 02:06:25 PM PST 24
Finished Mar 03 02:06:36 PM PST 24
Peak memory 231872 kb
Host smart-713e320c-70a0-420f-ac39-c0efb727ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405677161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.405677161
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1715671518
Short name T345
Test name
Test status
Simulation time 16593567 ps
CPU time 1.09 seconds
Started Mar 03 02:06:24 PM PST 24
Finished Mar 03 02:06:26 PM PST 24
Peak memory 217772 kb
Host smart-efb971e1-7aa3-4701-bd04-e579af3d041c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715671518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1715671518
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2539046025
Short name T399
Test name
Test status
Simulation time 857991451 ps
CPU time 7.13 seconds
Started Mar 03 02:06:20 PM PST 24
Finished Mar 03 02:06:27 PM PST 24
Peak memory 227820 kb
Host smart-64e1f8f7-b484-405d-bbee-fa37447a250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539046025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2539046025
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4191269930
Short name T735
Test name
Test status
Simulation time 2918718596 ps
CPU time 17.21 seconds
Started Mar 03 02:06:21 PM PST 24
Finished Mar 03 02:06:39 PM PST 24
Peak memory 227032 kb
Host smart-86b05223-71ca-43f1-b3f4-19c9d502eba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191269930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4191269930
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1687665337
Short name T538
Test name
Test status
Simulation time 97731832 ps
CPU time 0.74 seconds
Started Mar 03 02:06:20 PM PST 24
Finished Mar 03 02:06:21 PM PST 24
Peak memory 216068 kb
Host smart-4c65a707-74b0-41f3-911f-0088d183b54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687665337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1687665337
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4167347614
Short name T763
Test name
Test status
Simulation time 798496495 ps
CPU time 4.71 seconds
Started Mar 03 02:06:24 PM PST 24
Finished Mar 03 02:06:29 PM PST 24
Peak memory 219940 kb
Host smart-e98387fa-720b-48ab-a177-8a3b442fb4a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4167347614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4167347614
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1189159972
Short name T159
Test name
Test status
Simulation time 52619581418 ps
CPU time 137.32 seconds
Started Mar 03 02:06:31 PM PST 24
Finished Mar 03 02:08:49 PM PST 24
Peak memory 255916 kb
Host smart-ae167fce-5840-446c-831e-bd5e22809b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189159972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1189159972
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.413804479
Short name T906
Test name
Test status
Simulation time 9407614362 ps
CPU time 38.18 seconds
Started Mar 03 02:06:21 PM PST 24
Finished Mar 03 02:06:59 PM PST 24
Peak memory 216296 kb
Host smart-19183473-ad46-4f31-a2a9-691f4827ae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413804479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.413804479
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.754427437
Short name T896
Test name
Test status
Simulation time 1086076549 ps
CPU time 7.08 seconds
Started Mar 03 02:06:20 PM PST 24
Finished Mar 03 02:06:27 PM PST 24
Peak memory 216256 kb
Host smart-c0b70d84-e5de-4127-b71a-906a245ba4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754427437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.754427437
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2619886821
Short name T683
Test name
Test status
Simulation time 105173694 ps
CPU time 0.86 seconds
Started Mar 03 02:06:21 PM PST 24
Finished Mar 03 02:06:22 PM PST 24
Peak memory 206044 kb
Host smart-0138f4c8-ea2f-448c-ac1c-d684f536d94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619886821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2619886821
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1889643564
Short name T531
Test name
Test status
Simulation time 120087448 ps
CPU time 0.93 seconds
Started Mar 03 02:06:23 PM PST 24
Finished Mar 03 02:06:24 PM PST 24
Peak memory 206372 kb
Host smart-ec22b3fc-fa2c-4f99-9c5d-32714be134e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889643564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1889643564
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3142081809
Short name T585
Test name
Test status
Simulation time 7388702653 ps
CPU time 8.53 seconds
Started Mar 03 02:06:24 PM PST 24
Finished Mar 03 02:06:33 PM PST 24
Peak memory 233472 kb
Host smart-7b619a19-c9f2-4020-bd92-11e4116864cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142081809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3142081809
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3407931902
Short name T571
Test name
Test status
Simulation time 26026171 ps
CPU time 0.71 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:06:31 PM PST 24
Peak memory 204856 kb
Host smart-90677304-b3c1-4a4b-acaf-c6815560d9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407931902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3407931902
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1200206602
Short name T217
Test name
Test status
Simulation time 1187333736 ps
CPU time 3.97 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:33 PM PST 24
Peak memory 233496 kb
Host smart-9fdf9110-1ff4-48d8-be27-a3a338162bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200206602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1200206602
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1626176402
Short name T64
Test name
Test status
Simulation time 16931396 ps
CPU time 0.88 seconds
Started Mar 03 02:06:30 PM PST 24
Finished Mar 03 02:06:32 PM PST 24
Peak memory 206000 kb
Host smart-7ec8cff5-6f88-4937-ae62-c0593e009321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626176402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1626176402
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2136812508
Short name T620
Test name
Test status
Simulation time 5239053800 ps
CPU time 49.41 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:07:19 PM PST 24
Peak memory 250620 kb
Host smart-e3dc7c55-a18a-46ea-b047-64ca28e6875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136812508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2136812508
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1845031112
Short name T198
Test name
Test status
Simulation time 4419914007 ps
CPU time 89.42 seconds
Started Mar 03 02:06:27 PM PST 24
Finished Mar 03 02:07:58 PM PST 24
Peak memory 255228 kb
Host smart-cf1d6745-8bb8-4743-8d9d-40b51f942eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845031112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1845031112
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3545488919
Short name T432
Test name
Test status
Simulation time 6649371209 ps
CPU time 41.25 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:07:10 PM PST 24
Peak memory 246148 kb
Host smart-0b5af7d2-368f-452c-8b38-853c3a8cebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545488919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3545488919
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1357506975
Short name T222
Test name
Test status
Simulation time 655364353 ps
CPU time 6.49 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:06:36 PM PST 24
Peak memory 224364 kb
Host smart-d4a24d0e-e8c0-437d-b2b6-3ee18cc91b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357506975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1357506975
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1237670295
Short name T342
Test name
Test status
Simulation time 1603467387 ps
CPU time 3.67 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:33 PM PST 24
Peak memory 224320 kb
Host smart-fbd87fe4-67da-403e-9790-acc33f97e877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237670295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1237670295
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3521817060
Short name T929
Test name
Test status
Simulation time 35534999 ps
CPU time 1.13 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:06:32 PM PST 24
Peak memory 216524 kb
Host smart-b26bf92c-ffd5-48cb-be64-ad55425d083c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521817060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3521817060
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2271335872
Short name T236
Test name
Test status
Simulation time 4025303381 ps
CPU time 13.22 seconds
Started Mar 03 02:06:27 PM PST 24
Finished Mar 03 02:06:40 PM PST 24
Peak memory 224360 kb
Host smart-8fd333cf-bf56-4a01-bef5-b418e492bde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271335872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2271335872
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1429714868
Short name T488
Test name
Test status
Simulation time 4587224685 ps
CPU time 5.23 seconds
Started Mar 03 02:06:30 PM PST 24
Finished Mar 03 02:06:36 PM PST 24
Peak memory 224320 kb
Host smart-19065e0c-98ec-44b4-ab11-c31e8c19679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429714868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1429714868
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1498864712
Short name T77
Test name
Test status
Simulation time 85518193 ps
CPU time 0.7 seconds
Started Mar 03 02:06:30 PM PST 24
Finished Mar 03 02:06:31 PM PST 24
Peak memory 215992 kb
Host smart-0682899d-2fe9-4d2e-8fc0-55d62bb01011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498864712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1498864712
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3360805976
Short name T891
Test name
Test status
Simulation time 954201047 ps
CPU time 3.89 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:33 PM PST 24
Peak memory 222080 kb
Host smart-1a0d9b1e-0d03-401e-bf5d-8298f183053d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3360805976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3360805976
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1701238618
Short name T913
Test name
Test status
Simulation time 69268304856 ps
CPU time 323.05 seconds
Started Mar 03 02:06:27 PM PST 24
Finished Mar 03 02:11:51 PM PST 24
Peak memory 270296 kb
Host smart-e93e2059-430e-4d9a-9cee-3d887a770d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701238618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1701238618
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2555708767
Short name T648
Test name
Test status
Simulation time 10896326644 ps
CPU time 62.04 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:07:32 PM PST 24
Peak memory 216308 kb
Host smart-11b9bf68-62b0-4583-948f-0b7bf3f316fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555708767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2555708767
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3848197563
Short name T18
Test name
Test status
Simulation time 1879373188 ps
CPU time 10.29 seconds
Started Mar 03 02:06:30 PM PST 24
Finished Mar 03 02:06:41 PM PST 24
Peak memory 216280 kb
Host smart-eeabb990-05e7-4fe6-881d-a01a1a64822a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848197563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3848197563
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.960569871
Short name T31
Test name
Test status
Simulation time 70167837 ps
CPU time 1.42 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:30 PM PST 24
Peak memory 216228 kb
Host smart-ddde149b-f19a-4417-b700-20cb322cbce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960569871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.960569871
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4044241492
Short name T712
Test name
Test status
Simulation time 31070567 ps
CPU time 0.76 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:06:31 PM PST 24
Peak memory 205332 kb
Host smart-bc7991a8-d91e-40e5-a710-eeec3be2e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044241492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4044241492
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3655188104
Short name T626
Test name
Test status
Simulation time 60747764569 ps
CPU time 31.36 seconds
Started Mar 03 02:06:27 PM PST 24
Finished Mar 03 02:06:59 PM PST 24
Peak memory 230068 kb
Host smart-7fcbd3f2-1cb1-4b42-82c2-b0e088fb90e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655188104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3655188104
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.235260476
Short name T952
Test name
Test status
Simulation time 11309255 ps
CPU time 0.74 seconds
Started Mar 03 02:06:40 PM PST 24
Finished Mar 03 02:06:42 PM PST 24
Peak memory 204860 kb
Host smart-75019937-23e4-45aa-a823-9796c3d0de92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235260476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.235260476
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3083420804
Short name T220
Test name
Test status
Simulation time 765429646 ps
CPU time 4.52 seconds
Started Mar 03 02:06:36 PM PST 24
Finished Mar 03 02:06:40 PM PST 24
Peak memory 233616 kb
Host smart-09ae568a-875f-4c56-98b0-d34e53cc40e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083420804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3083420804
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.24258379
Short name T808
Test name
Test status
Simulation time 16543577 ps
CPU time 0.79 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:30 PM PST 24
Peak memory 204980 kb
Host smart-7e2aa6c7-2b1f-4291-ae23-07bd0b5a00a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24258379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.24258379
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.26846588
Short name T669
Test name
Test status
Simulation time 13088274522 ps
CPU time 109.83 seconds
Started Mar 03 02:06:33 PM PST 24
Finished Mar 03 02:08:23 PM PST 24
Peak memory 248940 kb
Host smart-e458e769-1d51-474d-83c2-f6ff27ec6964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26846588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.26846588
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2761730865
Short name T272
Test name
Test status
Simulation time 38503852696 ps
CPU time 96.94 seconds
Started Mar 03 02:06:34 PM PST 24
Finished Mar 03 02:08:11 PM PST 24
Peak memory 240960 kb
Host smart-87dd2ec2-2509-410a-84ac-a3b050ffbb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761730865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2761730865
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2843436878
Short name T983
Test name
Test status
Simulation time 1396378813 ps
CPU time 6.99 seconds
Started Mar 03 02:06:35 PM PST 24
Finished Mar 03 02:06:42 PM PST 24
Peak memory 223952 kb
Host smart-c8f7eddd-0dd2-4712-95cd-24dbde1a7ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843436878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2843436878
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1539053031
Short name T930
Test name
Test status
Simulation time 1668222660 ps
CPU time 7.35 seconds
Started Mar 03 02:06:37 PM PST 24
Finished Mar 03 02:06:44 PM PST 24
Peak memory 224280 kb
Host smart-a8c25785-75a7-42e3-b2df-efccc4ad29a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539053031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1539053031
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4051965651
Short name T730
Test name
Test status
Simulation time 86466638563 ps
CPU time 17.48 seconds
Started Mar 03 02:06:35 PM PST 24
Finished Mar 03 02:06:52 PM PST 24
Peak memory 238752 kb
Host smart-5dd3516e-b7e3-44b0-90aa-0044a1906f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051965651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4051965651
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1915495232
Short name T440
Test name
Test status
Simulation time 62085039 ps
CPU time 1.07 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:29 PM PST 24
Peak memory 216512 kb
Host smart-a1ce74eb-752f-4070-96ca-8aa612fdc065
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915495232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1915495232
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.904506128
Short name T717
Test name
Test status
Simulation time 2634553281 ps
CPU time 13.54 seconds
Started Mar 03 02:06:30 PM PST 24
Finished Mar 03 02:06:44 PM PST 24
Peak memory 229592 kb
Host smart-2d968bea-dee4-411d-970c-1cb6f06e2604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904506128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.904506128
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1549567873
Short name T182
Test name
Test status
Simulation time 727942810 ps
CPU time 10.11 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:06:39 PM PST 24
Peak memory 238860 kb
Host smart-203b144f-99aa-41bb-a56e-2e36009c1eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549567873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1549567873
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2044480325
Short name T350
Test name
Test status
Simulation time 27380909 ps
CPU time 0.75 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:30 PM PST 24
Peak memory 215960 kb
Host smart-5941b4b9-e542-4a22-ae59-db83925f91b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044480325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2044480325
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4062803075
Short name T702
Test name
Test status
Simulation time 433404319 ps
CPU time 3.36 seconds
Started Mar 03 02:06:33 PM PST 24
Finished Mar 03 02:06:37 PM PST 24
Peak memory 222520 kb
Host smart-05f9b492-7f3c-451d-a352-c1d600d08b86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4062803075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4062803075
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4205303805
Short name T278
Test name
Test status
Simulation time 34832293495 ps
CPU time 16.37 seconds
Started Mar 03 02:06:29 PM PST 24
Finished Mar 03 02:06:46 PM PST 24
Peak memory 216276 kb
Host smart-ab5d52f7-a48d-4a73-9444-9373e114f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205303805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4205303805
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3632505055
Short name T609
Test name
Test status
Simulation time 2785277737 ps
CPU time 7.53 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:37 PM PST 24
Peak memory 216276 kb
Host smart-e5336860-4be2-4f8c-9e11-88c75ebfd7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632505055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3632505055
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1653048609
Short name T461
Test name
Test status
Simulation time 205397387 ps
CPU time 3.25 seconds
Started Mar 03 02:06:30 PM PST 24
Finished Mar 03 02:06:34 PM PST 24
Peak memory 216148 kb
Host smart-95bab659-234b-4339-b8a0-10f46615763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653048609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1653048609
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.634662881
Short name T453
Test name
Test status
Simulation time 176604785 ps
CPU time 1.09 seconds
Started Mar 03 02:06:28 PM PST 24
Finished Mar 03 02:06:30 PM PST 24
Peak memory 206400 kb
Host smart-62ea3248-30e3-4a68-97ef-40c7ca95a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634662881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.634662881
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3567332083
Short name T809
Test name
Test status
Simulation time 9522133377 ps
CPU time 32.93 seconds
Started Mar 03 02:06:35 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 244044 kb
Host smart-1e649a95-1eac-408d-96de-cac792afdd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567332083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3567332083
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2235218625
Short name T921
Test name
Test status
Simulation time 92698998 ps
CPU time 0.81 seconds
Started Mar 03 02:06:41 PM PST 24
Finished Mar 03 02:06:42 PM PST 24
Peak memory 204876 kb
Host smart-5e4c8242-a82e-4552-a1ab-b914dbff1ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235218625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2235218625
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1962652939
Short name T1
Test name
Test status
Simulation time 558215277 ps
CPU time 2.48 seconds
Started Mar 03 02:06:37 PM PST 24
Finished Mar 03 02:06:40 PM PST 24
Peak memory 224200 kb
Host smart-710c4d51-0e7d-4de4-95d2-b9259d354f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962652939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1962652939
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2780751226
Short name T7
Test name
Test status
Simulation time 82598075 ps
CPU time 0.82 seconds
Started Mar 03 02:06:34 PM PST 24
Finished Mar 03 02:06:35 PM PST 24
Peak memory 206000 kb
Host smart-23cf05f3-d875-4715-a0e9-6d2b4928c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780751226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2780751226
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4216165624
Short name T168
Test name
Test status
Simulation time 15626780402 ps
CPU time 117.51 seconds
Started Mar 03 02:06:44 PM PST 24
Finished Mar 03 02:08:41 PM PST 24
Peak memory 265056 kb
Host smart-4b119656-a5ec-42cc-be36-4dacff8bf8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216165624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4216165624
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.529372135
Short name T205
Test name
Test status
Simulation time 556556156330 ps
CPU time 244.59 seconds
Started Mar 03 02:06:45 PM PST 24
Finished Mar 03 02:10:51 PM PST 24
Peak memory 260964 kb
Host smart-01fe5f05-62aa-42f7-8f61-f59bb42af65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529372135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.529372135
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2476676987
Short name T897
Test name
Test status
Simulation time 8972504503 ps
CPU time 111.11 seconds
Started Mar 03 02:06:44 PM PST 24
Finished Mar 03 02:08:37 PM PST 24
Peak memory 261196 kb
Host smart-131bf806-31f5-414c-b42a-4122629368a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476676987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2476676987
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2310332009
Short name T633
Test name
Test status
Simulation time 684216093 ps
CPU time 10.92 seconds
Started Mar 03 02:06:37 PM PST 24
Finished Mar 03 02:06:48 PM PST 24
Peak memory 236796 kb
Host smart-02bea802-da8c-4253-b220-5f5ac4c0e19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310332009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2310332009
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3727629020
Short name T610
Test name
Test status
Simulation time 2466299016 ps
CPU time 5.11 seconds
Started Mar 03 02:06:36 PM PST 24
Finished Mar 03 02:06:41 PM PST 24
Peak memory 224440 kb
Host smart-d6d95ea8-979a-4e06-89cf-8afe0fc04ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727629020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3727629020
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1818204054
Short name T616
Test name
Test status
Simulation time 34536654780 ps
CPU time 13.93 seconds
Started Mar 03 02:06:33 PM PST 24
Finished Mar 03 02:06:47 PM PST 24
Peak memory 231276 kb
Host smart-2c44f877-29a9-4a84-917e-a3a80d81429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818204054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1818204054
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.774202910
Short name T553
Test name
Test status
Simulation time 110624881 ps
CPU time 1.07 seconds
Started Mar 03 02:06:37 PM PST 24
Finished Mar 03 02:06:39 PM PST 24
Peak memory 217768 kb
Host smart-e9961222-cdc2-4300-b602-15a2c564d434
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774202910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.774202910
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1731993663
Short name T824
Test name
Test status
Simulation time 19322083514 ps
CPU time 16.7 seconds
Started Mar 03 02:06:37 PM PST 24
Finished Mar 03 02:06:55 PM PST 24
Peak memory 236852 kb
Host smart-f8c5ef72-b103-43ef-88ff-44df9d25e2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731993663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1731993663
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.246225127
Short name T908
Test name
Test status
Simulation time 3944659622 ps
CPU time 12.92 seconds
Started Mar 03 02:06:35 PM PST 24
Finished Mar 03 02:06:48 PM PST 24
Peak memory 232680 kb
Host smart-dee7b602-0e26-45cd-88b3-c69bcd29599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246225127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.246225127
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.172247953
Short name T655
Test name
Test status
Simulation time 18115742 ps
CPU time 0.78 seconds
Started Mar 03 02:06:34 PM PST 24
Finished Mar 03 02:06:35 PM PST 24
Peak memory 215944 kb
Host smart-c680ceac-7c76-4ef4-a0d7-f90d7372eda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172247953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.172247953
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.407420604
Short name T12
Test name
Test status
Simulation time 181331090 ps
CPU time 3.36 seconds
Started Mar 03 02:06:41 PM PST 24
Finished Mar 03 02:06:45 PM PST 24
Peak memory 216364 kb
Host smart-56f5fafa-4062-4b41-88f5-763c61738a7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=407420604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.407420604
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.150690718
Short name T165
Test name
Test status
Simulation time 12366295389 ps
CPU time 81.52 seconds
Started Mar 03 02:06:42 PM PST 24
Finished Mar 03 02:08:05 PM PST 24
Peak memory 256296 kb
Host smart-6bd990df-a3fb-4305-a378-eead8237e619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150690718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.150690718
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3304365063
Short name T791
Test name
Test status
Simulation time 8735885225 ps
CPU time 36.75 seconds
Started Mar 03 02:06:35 PM PST 24
Finished Mar 03 02:07:12 PM PST 24
Peak memory 216260 kb
Host smart-4522c320-29de-431f-82a2-74dffa31d3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304365063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3304365063
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.801549626
Short name T285
Test name
Test status
Simulation time 634499862 ps
CPU time 4.12 seconds
Started Mar 03 02:06:40 PM PST 24
Finished Mar 03 02:06:45 PM PST 24
Peak memory 208224 kb
Host smart-dace5e68-2062-4283-8a1f-b2c59c89c7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801549626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.801549626
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1549923343
Short name T928
Test name
Test status
Simulation time 32204631 ps
CPU time 0.8 seconds
Started Mar 03 02:06:35 PM PST 24
Finished Mar 03 02:06:36 PM PST 24
Peak memory 205368 kb
Host smart-a8dc761c-bd18-4e2f-974f-14a2112d4452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549923343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1549923343
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2430658162
Short name T890
Test name
Test status
Simulation time 60040135 ps
CPU time 0.73 seconds
Started Mar 03 02:06:35 PM PST 24
Finished Mar 03 02:06:35 PM PST 24
Peak memory 205372 kb
Host smart-8caaa641-daa4-4edd-b622-e76b041b2a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430658162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2430658162
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3417689442
Short name T370
Test name
Test status
Simulation time 15343348849 ps
CPU time 11.55 seconds
Started Mar 03 02:06:35 PM PST 24
Finished Mar 03 02:06:47 PM PST 24
Peak memory 217848 kb
Host smart-671dd24d-d5ae-4241-bd32-a11be3655670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417689442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3417689442
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3927736819
Short name T425
Test name
Test status
Simulation time 44895154 ps
CPU time 0.73 seconds
Started Mar 03 02:06:41 PM PST 24
Finished Mar 03 02:06:42 PM PST 24
Peak memory 204860 kb
Host smart-6865e7f3-feea-41f7-b414-840a158db01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927736819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3927736819
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4293580918
Short name T485
Test name
Test status
Simulation time 16788634773 ps
CPU time 8.22 seconds
Started Mar 03 02:06:41 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 233824 kb
Host smart-b471111e-126c-4f69-a8ef-87aa21639c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293580918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4293580918
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2581686649
Short name T815
Test name
Test status
Simulation time 15740195 ps
CPU time 0.77 seconds
Started Mar 03 02:06:46 PM PST 24
Finished Mar 03 02:06:47 PM PST 24
Peak memory 206008 kb
Host smart-a9c68385-faec-470e-a9b0-50f030304cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581686649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2581686649
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.109158595
Short name T883
Test name
Test status
Simulation time 9915559297 ps
CPU time 24.66 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 240856 kb
Host smart-5dcdaf66-bbeb-45c2-91ef-41000db9e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109158595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.109158595
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.352766619
Short name T400
Test name
Test status
Simulation time 14932712866 ps
CPU time 145.55 seconds
Started Mar 03 02:06:42 PM PST 24
Finished Mar 03 02:09:09 PM PST 24
Peak memory 260396 kb
Host smart-89b54447-d566-40ce-8cbb-961b0bb4591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352766619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.352766619
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1305965829
Short name T759
Test name
Test status
Simulation time 63045194525 ps
CPU time 82.72 seconds
Started Mar 03 02:06:45 PM PST 24
Finished Mar 03 02:08:09 PM PST 24
Peak memory 223364 kb
Host smart-24a05b04-f324-4d1b-a2e1-c74b34d525c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305965829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1305965829
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2850572011
Short name T697
Test name
Test status
Simulation time 105308822201 ps
CPU time 36.87 seconds
Started Mar 03 02:06:42 PM PST 24
Finished Mar 03 02:07:21 PM PST 24
Peak memory 232580 kb
Host smart-40ed1c25-d6f3-4686-9d5f-311885392675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850572011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2850572011
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3486183121
Short name T951
Test name
Test status
Simulation time 6864739815 ps
CPU time 12.38 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:06:56 PM PST 24
Peak memory 224368 kb
Host smart-060e24a6-b4cc-4840-b006-872a933a3c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486183121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3486183121
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4189718263
Short name T946
Test name
Test status
Simulation time 18829942842 ps
CPU time 18.46 seconds
Started Mar 03 02:06:41 PM PST 24
Finished Mar 03 02:07:00 PM PST 24
Peak memory 233636 kb
Host smart-3c21899d-934e-4124-90ad-27874ad3c13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189718263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4189718263
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1838450183
Short name T595
Test name
Test status
Simulation time 26500834 ps
CPU time 1.08 seconds
Started Mar 03 02:06:42 PM PST 24
Finished Mar 03 02:06:45 PM PST 24
Peak memory 217760 kb
Host smart-f11ddb3f-0e3c-4127-bec5-7cf1429de335
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838450183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1838450183
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2056323104
Short name T623
Test name
Test status
Simulation time 1994072585 ps
CPU time 7.03 seconds
Started Mar 03 02:06:44 PM PST 24
Finished Mar 03 02:06:51 PM PST 24
Peak memory 226524 kb
Host smart-fdd880de-73bf-4ef0-bf0c-32f14a50d262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056323104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2056323104
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.558219634
Short name T879
Test name
Test status
Simulation time 9422870404 ps
CPU time 26.89 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 232928 kb
Host smart-16e6e055-24be-446f-9d68-4da57dd15748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558219634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.558219634
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2251944674
Short name T288
Test name
Test status
Simulation time 33582497 ps
CPU time 0.73 seconds
Started Mar 03 02:06:44 PM PST 24
Finished Mar 03 02:06:45 PM PST 24
Peak memory 216040 kb
Host smart-9b54bb00-e3df-49d4-ba24-85b79ee20b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251944674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2251944674
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1347935583
Short name T481
Test name
Test status
Simulation time 200694081 ps
CPU time 3.51 seconds
Started Mar 03 02:06:42 PM PST 24
Finished Mar 03 02:06:46 PM PST 24
Peak memory 218488 kb
Host smart-8bbc3c51-231e-4c94-b050-af894be8f987
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1347935583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1347935583
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2976695766
Short name T72
Test name
Test status
Simulation time 214977186049 ps
CPU time 368.26 seconds
Started Mar 03 02:06:42 PM PST 24
Finished Mar 03 02:12:52 PM PST 24
Peak memory 254572 kb
Host smart-ea1728f6-9e77-423c-a166-bd2d3730e1b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976695766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2976695766
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4257008583
Short name T935
Test name
Test status
Simulation time 8016271376 ps
CPU time 46.01 seconds
Started Mar 03 02:06:40 PM PST 24
Finished Mar 03 02:07:27 PM PST 24
Peak memory 216308 kb
Host smart-e521616a-0980-4b04-a0e9-30ab7ad5e405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257008583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4257008583
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.337412128
Short name T286
Test name
Test status
Simulation time 3661176858 ps
CPU time 6.67 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 216240 kb
Host smart-f0c8c1ce-cff0-482c-9d81-24b763498378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337412128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.337412128
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3034746053
Short name T528
Test name
Test status
Simulation time 430250333 ps
CPU time 6 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 216220 kb
Host smart-88a45963-e6af-4d9d-b19c-17ee3a665ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034746053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3034746053
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2754432948
Short name T294
Test name
Test status
Simulation time 296118420 ps
CPU time 0.93 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:06:45 PM PST 24
Peak memory 205368 kb
Host smart-2802b469-09d5-4d24-9c33-7863ac72be94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754432948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2754432948
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3204297651
Short name T653
Test name
Test status
Simulation time 963060944 ps
CPU time 6.73 seconds
Started Mar 03 02:06:42 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 219340 kb
Host smart-50b80119-2fbd-4ecd-90ea-2ff5a8b4ab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204297651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3204297651
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3876951433
Short name T384
Test name
Test status
Simulation time 112182651 ps
CPU time 0.75 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:06:48 PM PST 24
Peak memory 205160 kb
Host smart-6e3aa9e2-5fe1-41f2-8b48-251784107ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876951433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3876951433
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1671480010
Short name T502
Test name
Test status
Simulation time 12234775752 ps
CPU time 7.2 seconds
Started Mar 03 02:06:46 PM PST 24
Finished Mar 03 02:06:54 PM PST 24
Peak memory 219736 kb
Host smart-571b0504-2953-4a21-b78f-73e65bf93e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671480010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1671480010
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4164293035
Short name T543
Test name
Test status
Simulation time 14183056 ps
CPU time 0.74 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:06:45 PM PST 24
Peak memory 205300 kb
Host smart-77c06808-3cfb-4b3c-8241-ac87786a2360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164293035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4164293035
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2176771195
Short name T758
Test name
Test status
Simulation time 5135587816 ps
CPU time 38.18 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:07:26 PM PST 24
Peak memory 237540 kb
Host smart-566702dc-317a-44ee-978d-05d20ee8fcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176771195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2176771195
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2281876405
Short name T430
Test name
Test status
Simulation time 2900057372 ps
CPU time 31.44 seconds
Started Mar 03 02:06:48 PM PST 24
Finished Mar 03 02:07:20 PM PST 24
Peak memory 232784 kb
Host smart-9d92cb97-c969-45c8-987b-5510c523c316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281876405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2281876405
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2963830417
Short name T27
Test name
Test status
Simulation time 21583220217 ps
CPU time 93.07 seconds
Started Mar 03 02:06:49 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 250772 kb
Host smart-51e342c1-8492-4bc3-9af8-e8b2292119d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963830417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2963830417
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3721659064
Short name T49
Test name
Test status
Simulation time 2442153461 ps
CPU time 13.74 seconds
Started Mar 03 02:06:45 PM PST 24
Finished Mar 03 02:07:00 PM PST 24
Peak memory 237324 kb
Host smart-5b7b9fd5-9144-447a-9b8a-a946691f3a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721659064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3721659064
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.841571438
Short name T868
Test name
Test status
Simulation time 5296782295 ps
CPU time 9.37 seconds
Started Mar 03 02:06:46 PM PST 24
Finished Mar 03 02:06:56 PM PST 24
Peak memory 219960 kb
Host smart-774e1b64-bb44-4ace-a357-212f70e64fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841571438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.841571438
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2997702855
Short name T548
Test name
Test status
Simulation time 15475814892 ps
CPU time 42.82 seconds
Started Mar 03 02:06:46 PM PST 24
Finished Mar 03 02:07:29 PM PST 24
Peak memory 233528 kb
Host smart-43181602-aff3-4215-a4b5-b444b3d4f47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997702855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2997702855
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2370932150
Short name T987
Test name
Test status
Simulation time 48055832 ps
CPU time 1.07 seconds
Started Mar 03 02:06:42 PM PST 24
Finished Mar 03 02:06:44 PM PST 24
Peak memory 216512 kb
Host smart-76bab2d0-9a77-4ffa-a786-d7f389c869b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370932150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2370932150
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1235112400
Short name T760
Test name
Test status
Simulation time 10033118655 ps
CPU time 33.67 seconds
Started Mar 03 02:06:45 PM PST 24
Finished Mar 03 02:07:20 PM PST 24
Peak memory 232648 kb
Host smart-fc4a1d61-c370-4937-b4b2-9a072241d92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235112400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1235112400
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1563815839
Short name T529
Test name
Test status
Simulation time 5500160901 ps
CPU time 10.88 seconds
Started Mar 03 02:06:46 PM PST 24
Finished Mar 03 02:06:58 PM PST 24
Peak memory 224364 kb
Host smart-72033bad-2acd-4ceb-90b6-7c3bde8f23bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563815839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1563815839
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3924543921
Short name T446
Test name
Test status
Simulation time 26457580 ps
CPU time 0.73 seconds
Started Mar 03 02:06:44 PM PST 24
Finished Mar 03 02:06:47 PM PST 24
Peak memory 216060 kb
Host smart-10c90f60-37b9-4f53-9a10-8aeb9b39b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924543921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3924543921
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.341797954
Short name T885
Test name
Test status
Simulation time 1076688216 ps
CPU time 6.16 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:06:53 PM PST 24
Peak memory 222120 kb
Host smart-81e5a622-4a9a-4b32-8067-077b29999e31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=341797954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.341797954
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1535322349
Short name T266
Test name
Test status
Simulation time 77879564214 ps
CPU time 519.46 seconds
Started Mar 03 02:06:48 PM PST 24
Finished Mar 03 02:15:27 PM PST 24
Peak memory 288528 kb
Host smart-3e82863f-a93c-4795-96a0-bc59f7376c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535322349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1535322349
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1207843399
Short name T394
Test name
Test status
Simulation time 1029205315 ps
CPU time 11.44 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:06:58 PM PST 24
Peak memory 216256 kb
Host smart-fc1a41d7-095b-4b66-8385-5a441d09a387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207843399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1207843399
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3746240975
Short name T804
Test name
Test status
Simulation time 6286358670 ps
CPU time 7.89 seconds
Started Mar 03 02:06:45 PM PST 24
Finished Mar 03 02:06:54 PM PST 24
Peak memory 216308 kb
Host smart-414929d5-ca13-4e13-9f81-719bcd8c616a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746240975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3746240975
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1696072156
Short name T404
Test name
Test status
Simulation time 103803777 ps
CPU time 3.01 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:06:47 PM PST 24
Peak memory 216352 kb
Host smart-5f13cf9a-ce7d-4c2c-aaa8-32f8e377db5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696072156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1696072156
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1892026279
Short name T407
Test name
Test status
Simulation time 173916217 ps
CPU time 0.76 seconds
Started Mar 03 02:06:43 PM PST 24
Finished Mar 03 02:06:44 PM PST 24
Peak memory 205292 kb
Host smart-3ee587e8-cb99-4ef9-9b6e-85791917ca5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892026279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1892026279
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1851206618
Short name T34
Test name
Test status
Simulation time 1478745013 ps
CPU time 11.56 seconds
Started Mar 03 02:06:44 PM PST 24
Finished Mar 03 02:06:57 PM PST 24
Peak memory 233324 kb
Host smart-5dc256e0-62ed-4ace-861b-a59f9ce39203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851206618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1851206618
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3654086053
Short name T347
Test name
Test status
Simulation time 19681343 ps
CPU time 0.75 seconds
Started Mar 03 02:06:52 PM PST 24
Finished Mar 03 02:06:53 PM PST 24
Peak memory 204864 kb
Host smart-748b5140-d9f3-4c01-b87f-3a6f2a2ff2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654086053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3654086053
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.896852513
Short name T479
Test name
Test status
Simulation time 2595358319 ps
CPU time 3.68 seconds
Started Mar 03 02:06:45 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 224416 kb
Host smart-defe4d92-82c7-445f-8a31-7dd8ce0e271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896852513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.896852513
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.318820455
Short name T283
Test name
Test status
Simulation time 65680927 ps
CPU time 0.78 seconds
Started Mar 03 02:06:51 PM PST 24
Finished Mar 03 02:06:52 PM PST 24
Peak memory 206012 kb
Host smart-bd6a879d-00a0-4658-96be-72214a1432a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318820455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.318820455
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2731139904
Short name T308
Test name
Test status
Simulation time 685165660 ps
CPU time 6.59 seconds
Started Mar 03 02:06:49 PM PST 24
Finished Mar 03 02:06:56 PM PST 24
Peak memory 238224 kb
Host smart-4399abeb-d5e6-4c81-bbac-7c2a032a1b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731139904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2731139904
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.82273457
Short name T549
Test name
Test status
Simulation time 99566520650 ps
CPU time 332.05 seconds
Started Mar 03 02:06:50 PM PST 24
Finished Mar 03 02:12:23 PM PST 24
Peak memory 257356 kb
Host smart-23f8c97b-337d-47e1-bed2-91a3fe8b48cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82273457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.82273457
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2633650764
Short name T589
Test name
Test status
Simulation time 32361502885 ps
CPU time 130.66 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:08:58 PM PST 24
Peak memory 253908 kb
Host smart-eaf0e28a-297a-4798-8704-d0a1c7d5bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633650764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2633650764
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3947979010
Short name T501
Test name
Test status
Simulation time 31237774061 ps
CPU time 31.16 seconds
Started Mar 03 02:06:55 PM PST 24
Finished Mar 03 02:07:26 PM PST 24
Peak memory 240472 kb
Host smart-4936f7ba-0df9-4486-848f-5ad6cf2c1d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947979010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3947979010
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1542990110
Short name T757
Test name
Test status
Simulation time 207966586 ps
CPU time 3.77 seconds
Started Mar 03 02:06:48 PM PST 24
Finished Mar 03 02:06:52 PM PST 24
Peak memory 233552 kb
Host smart-1984d6c9-cbd5-4903-8db6-43ecd565fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542990110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1542990110
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3450307220
Short name T692
Test name
Test status
Simulation time 30992748600 ps
CPU time 26.65 seconds
Started Mar 03 02:06:48 PM PST 24
Finished Mar 03 02:07:15 PM PST 24
Peak memory 227868 kb
Host smart-31b39a6f-f72f-4649-b5f8-7f47f4fa6d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450307220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3450307220
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2190834110
Short name T468
Test name
Test status
Simulation time 118198481 ps
CPU time 1.11 seconds
Started Mar 03 02:06:46 PM PST 24
Finished Mar 03 02:06:48 PM PST 24
Peak memory 216540 kb
Host smart-6b10c5be-7d31-4402-9453-ac715443a686
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190834110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2190834110
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4271373047
Short name T490
Test name
Test status
Simulation time 10201479618 ps
CPU time 8.89 seconds
Started Mar 03 02:06:46 PM PST 24
Finished Mar 03 02:06:56 PM PST 24
Peak memory 224376 kb
Host smart-d7451783-08bf-4d6d-b940-0f7232fc1fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271373047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4271373047
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2705064729
Short name T612
Test name
Test status
Simulation time 1820755067 ps
CPU time 3.32 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 232900 kb
Host smart-6590fcec-23ca-44f5-997e-6ce842c34723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705064729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2705064729
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2353454730
Short name T76
Test name
Test status
Simulation time 16719215 ps
CPU time 0.77 seconds
Started Mar 03 02:06:48 PM PST 24
Finished Mar 03 02:06:49 PM PST 24
Peak memory 216076 kb
Host smart-b1afd86b-b195-456f-bba5-a9e8090f018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353454730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2353454730
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2279337862
Short name T545
Test name
Test status
Simulation time 1059400465 ps
CPU time 3.83 seconds
Started Mar 03 02:06:55 PM PST 24
Finished Mar 03 02:06:59 PM PST 24
Peak memory 216372 kb
Host smart-1d2a38c7-b8cf-4e1a-b28f-03b60ff1284d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2279337862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2279337862
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2095750949
Short name T714
Test name
Test status
Simulation time 55661413516 ps
CPU time 301.73 seconds
Started Mar 03 02:06:48 PM PST 24
Finished Mar 03 02:11:50 PM PST 24
Peak memory 257328 kb
Host smart-d9e8e7e4-3a76-4d87-ba6e-2e28a546f4d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095750949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2095750949
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.594884059
Short name T870
Test name
Test status
Simulation time 7390918550 ps
CPU time 15.16 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:07:02 PM PST 24
Peak memory 216252 kb
Host smart-2797976a-515d-4ba3-806f-9b1010c1e5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594884059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.594884059
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4260323344
Short name T437
Test name
Test status
Simulation time 7978581248 ps
CPU time 6.69 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:06:54 PM PST 24
Peak memory 216276 kb
Host smart-78e88b25-d4e2-4c41-a9ae-e05a922f0235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260323344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4260323344
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2406085852
Short name T522
Test name
Test status
Simulation time 65232427 ps
CPU time 0.85 seconds
Started Mar 03 02:06:46 PM PST 24
Finished Mar 03 02:06:47 PM PST 24
Peak memory 206080 kb
Host smart-f4f62229-5fc9-415a-aeff-109d26ff8b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406085852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2406085852
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3252731619
Short name T408
Test name
Test status
Simulation time 122309103 ps
CPU time 0.98 seconds
Started Mar 03 02:06:45 PM PST 24
Finished Mar 03 02:06:47 PM PST 24
Peak memory 205920 kb
Host smart-06f19a04-0ef0-419e-8803-28a9ce29abfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252731619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3252731619
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1918320474
Short name T944
Test name
Test status
Simulation time 14932597743 ps
CPU time 9.87 seconds
Started Mar 03 02:06:49 PM PST 24
Finished Mar 03 02:06:59 PM PST 24
Peak memory 234344 kb
Host smart-206584a7-44fe-445d-af69-821241731b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918320474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1918320474
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.823820814
Short name T696
Test name
Test status
Simulation time 14106302 ps
CPU time 0.76 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:05:48 PM PST 24
Peak memory 204892 kb
Host smart-86eec2d1-b2c0-420d-842c-ca7e5e94fb40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823820814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.823820814
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1137877851
Short name T509
Test name
Test status
Simulation time 124914537 ps
CPU time 2.57 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:05:49 PM PST 24
Peak memory 224364 kb
Host smart-4e8b559e-f22c-441b-ae60-dcab309d2992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137877851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1137877851
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2461160208
Short name T317
Test name
Test status
Simulation time 21040878 ps
CPU time 0.79 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:05:49 PM PST 24
Peak memory 205984 kb
Host smart-02503d17-73bc-4c00-95ca-4a40cb254b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461160208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2461160208
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1102762630
Short name T141
Test name
Test status
Simulation time 7308574866 ps
CPU time 79.34 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:07:07 PM PST 24
Peak memory 257340 kb
Host smart-96403a65-3e9c-4e6c-a4c6-4fc1cffc5ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102762630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1102762630
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.213439356
Short name T328
Test name
Test status
Simulation time 73254497715 ps
CPU time 89.45 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:07:17 PM PST 24
Peak memory 263968 kb
Host smart-4d243c0a-3394-40c0-a6f7-aa5135027c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213439356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
213439356
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_intercept.881755782
Short name T800
Test name
Test status
Simulation time 58116233 ps
CPU time 2.46 seconds
Started Mar 03 02:05:45 PM PST 24
Finished Mar 03 02:05:47 PM PST 24
Peak memory 216236 kb
Host smart-45993861-bb92-4efd-92c2-56cd2735c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881755782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.881755782
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1042495259
Short name T779
Test name
Test status
Simulation time 30540305025 ps
CPU time 23.78 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:06:08 PM PST 24
Peak memory 232624 kb
Host smart-f4fbf5f5-e292-4cbf-af6b-00d63ccf49d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042495259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1042495259
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3831682608
Short name T945
Test name
Test status
Simulation time 42289943 ps
CPU time 1.07 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:05:45 PM PST 24
Peak memory 216528 kb
Host smart-48fd61a7-1e46-428a-90e3-f9e97f85440c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831682608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3831682608
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3039623848
Short name T785
Test name
Test status
Simulation time 189435876593 ps
CPU time 34 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:06:18 PM PST 24
Peak memory 227012 kb
Host smart-14e93c9d-659f-465f-abd5-3038c543c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039623848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3039623848
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1299465671
Short name T583
Test name
Test status
Simulation time 1881097273 ps
CPU time 15.51 seconds
Started Mar 03 02:05:45 PM PST 24
Finished Mar 03 02:06:00 PM PST 24
Peak memory 232408 kb
Host smart-ce3f6d1d-a9c0-4e1d-a938-c5c9db17d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299465671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1299465671
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.3686225277
Short name T832
Test name
Test status
Simulation time 52689957 ps
CPU time 0.74 seconds
Started Mar 03 02:05:45 PM PST 24
Finished Mar 03 02:05:46 PM PST 24
Peak memory 216028 kb
Host smart-2664f200-952b-404d-8643-7f9022372e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686225277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.3686225277
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3473600677
Short name T518
Test name
Test status
Simulation time 1750853891 ps
CPU time 6.62 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:05:55 PM PST 24
Peak memory 218760 kb
Host smart-bfa1b5d3-b512-4467-ac2b-26fa534b3a61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3473600677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3473600677
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1873659034
Short name T912
Test name
Test status
Simulation time 12727781786 ps
CPU time 67.9 seconds
Started Mar 03 02:05:46 PM PST 24
Finished Mar 03 02:06:54 PM PST 24
Peak memory 216216 kb
Host smart-9b48c37a-e885-4257-8047-77a595b8725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873659034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1873659034
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.931482622
Short name T796
Test name
Test status
Simulation time 51242060663 ps
CPU time 13.54 seconds
Started Mar 03 02:05:44 PM PST 24
Finished Mar 03 02:05:58 PM PST 24
Peak memory 216244 kb
Host smart-896109bf-166b-4711-9dc3-94a9f7c3ee8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931482622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.931482622
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3702531175
Short name T878
Test name
Test status
Simulation time 277749736 ps
CPU time 2.88 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:05:50 PM PST 24
Peak memory 217316 kb
Host smart-b007784a-1800-46fa-a964-f0f93124d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702531175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3702531175
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.751835590
Short name T337
Test name
Test status
Simulation time 558090817 ps
CPU time 0.96 seconds
Started Mar 03 02:05:45 PM PST 24
Finished Mar 03 02:05:47 PM PST 24
Peak memory 206376 kb
Host smart-6a005478-a6b3-486a-a09f-c0457b5e94eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751835590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.751835590
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2191222787
Short name T227
Test name
Test status
Simulation time 4021437627 ps
CPU time 11.56 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:05:59 PM PST 24
Peak memory 240812 kb
Host smart-c416e715-a809-4a63-8d67-cd94a2126e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191222787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2191222787
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2886795874
Short name T540
Test name
Test status
Simulation time 11518658 ps
CPU time 0.74 seconds
Started Mar 03 02:06:53 PM PST 24
Finished Mar 03 02:06:54 PM PST 24
Peak memory 205224 kb
Host smart-5c765411-a778-454c-99ac-0f003e062a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886795874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2886795874
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.587482805
Short name T989
Test name
Test status
Simulation time 869171646 ps
CPU time 2.59 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 224264 kb
Host smart-9d953ac6-0193-4455-a38c-c8ba824ba2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587482805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.587482805
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.796885225
Short name T484
Test name
Test status
Simulation time 29112871 ps
CPU time 0.74 seconds
Started Mar 03 02:06:50 PM PST 24
Finished Mar 03 02:06:51 PM PST 24
Peak memory 204972 kb
Host smart-646dba20-52c6-4b13-8878-ce66c2a02cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796885225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.796885225
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2578365881
Short name T903
Test name
Test status
Simulation time 57863026477 ps
CPU time 377.72 seconds
Started Mar 03 02:06:55 PM PST 24
Finished Mar 03 02:13:13 PM PST 24
Peak memory 270112 kb
Host smart-b0ef814a-98d3-48dc-b255-18fc1535c2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578365881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2578365881
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4164351223
Short name T356
Test name
Test status
Simulation time 2193746652 ps
CPU time 11.53 seconds
Started Mar 03 02:06:48 PM PST 24
Finished Mar 03 02:07:00 PM PST 24
Peak memory 232660 kb
Host smart-a64892f8-07eb-4df4-ae3a-94312cb93b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164351223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4164351223
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2371466963
Short name T282
Test name
Test status
Simulation time 12888167020 ps
CPU time 16.67 seconds
Started Mar 03 02:06:55 PM PST 24
Finished Mar 03 02:07:12 PM PST 24
Peak memory 224352 kb
Host smart-804f36f1-8f66-4840-aa8d-c41f1decf487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371466963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2371466963
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4148754272
Short name T713
Test name
Test status
Simulation time 154082916 ps
CPU time 2.08 seconds
Started Mar 03 02:06:48 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 216384 kb
Host smart-6f41769d-d69a-4aa0-921b-89534a9b3bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148754272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4148754272
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3266945747
Short name T968
Test name
Test status
Simulation time 1014829136 ps
CPU time 9.45 seconds
Started Mar 03 02:06:55 PM PST 24
Finished Mar 03 02:07:04 PM PST 24
Peak memory 251172 kb
Host smart-85989be4-1a04-4274-b322-9692c2df0aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266945747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3266945747
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2341021585
Short name T451
Test name
Test status
Simulation time 2026325744 ps
CPU time 9.77 seconds
Started Mar 03 02:06:49 PM PST 24
Finished Mar 03 02:06:59 PM PST 24
Peak memory 245980 kb
Host smart-878a834a-2dc4-41e8-8580-66e98bca3bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341021585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2341021585
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3080455921
Short name T788
Test name
Test status
Simulation time 2506543107 ps
CPU time 7.04 seconds
Started Mar 03 02:06:49 PM PST 24
Finished Mar 03 02:06:56 PM PST 24
Peak memory 233428 kb
Host smart-9b34709c-435f-4711-95a3-35ce2f047681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080455921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3080455921
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2805357742
Short name T462
Test name
Test status
Simulation time 934265837 ps
CPU time 5.74 seconds
Started Mar 03 02:06:53 PM PST 24
Finished Mar 03 02:06:59 PM PST 24
Peak memory 221956 kb
Host smart-577afca4-1f23-4860-8557-1ac8e8bc608b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2805357742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2805357742
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2006833920
Short name T264
Test name
Test status
Simulation time 199542850914 ps
CPU time 1337.44 seconds
Started Mar 03 02:06:53 PM PST 24
Finished Mar 03 02:29:11 PM PST 24
Peak memory 305544 kb
Host smart-1c4fd8d7-0445-434f-90c1-8de093a70371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006833920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2006833920
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.998345850
Short name T744
Test name
Test status
Simulation time 2482183388 ps
CPU time 13.73 seconds
Started Mar 03 02:06:49 PM PST 24
Finished Mar 03 02:07:04 PM PST 24
Peak memory 216340 kb
Host smart-073ec152-981e-4395-ad02-65f1d84a7d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998345850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.998345850
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1459962438
Short name T50
Test name
Test status
Simulation time 2536491847 ps
CPU time 14.87 seconds
Started Mar 03 02:06:47 PM PST 24
Finished Mar 03 02:07:02 PM PST 24
Peak memory 216288 kb
Host smart-515dda6e-d9e7-446f-a70a-6c6fbb965860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459962438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1459962438
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2409833729
Short name T367
Test name
Test status
Simulation time 144759245 ps
CPU time 1.24 seconds
Started Mar 03 02:06:52 PM PST 24
Finished Mar 03 02:06:53 PM PST 24
Peak memory 207816 kb
Host smart-ef911d47-a942-45f5-b87e-7da6c382ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409833729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2409833729
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3330873653
Short name T22
Test name
Test status
Simulation time 241814564 ps
CPU time 0.94 seconds
Started Mar 03 02:06:51 PM PST 24
Finished Mar 03 02:06:52 PM PST 24
Peak memory 205356 kb
Host smart-dbfff3e0-1f5a-4ca2-a254-8351ac94d3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330873653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3330873653
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2454771558
Short name T570
Test name
Test status
Simulation time 9823506654 ps
CPU time 24.31 seconds
Started Mar 03 02:06:50 PM PST 24
Finished Mar 03 02:07:14 PM PST 24
Peak memory 219644 kb
Host smart-df087307-7bb3-4576-a33e-3229f1403df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454771558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2454771558
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1262796073
Short name T70
Test name
Test status
Simulation time 32783077 ps
CPU time 0.73 seconds
Started Mar 03 02:06:54 PM PST 24
Finished Mar 03 02:06:54 PM PST 24
Peak memory 205208 kb
Host smart-47f6b8d6-c8b6-40c2-b430-c9e080318ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262796073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1262796073
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2346779007
Short name T660
Test name
Test status
Simulation time 847796577 ps
CPU time 4.73 seconds
Started Mar 03 02:06:53 PM PST 24
Finished Mar 03 02:06:58 PM PST 24
Peak memory 224380 kb
Host smart-79a1727c-24a5-4f46-ba94-b5d56c1bd24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346779007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2346779007
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.960500633
Short name T780
Test name
Test status
Simulation time 34649417 ps
CPU time 0.81 seconds
Started Mar 03 02:06:56 PM PST 24
Finished Mar 03 02:06:57 PM PST 24
Peak memory 206000 kb
Host smart-3b7d4617-8e07-442e-978b-12e3c3dbd627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960500633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.960500633
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3797484412
Short name T244
Test name
Test status
Simulation time 3953373416 ps
CPU time 6.28 seconds
Started Mar 03 02:06:59 PM PST 24
Finished Mar 03 02:07:06 PM PST 24
Peak memory 220216 kb
Host smart-3d620eb7-36e3-4962-81ab-cbbce85e9dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797484412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3797484412
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.236073014
Short name T926
Test name
Test status
Simulation time 60320516859 ps
CPU time 431.39 seconds
Started Mar 03 02:06:56 PM PST 24
Finished Mar 03 02:14:08 PM PST 24
Peak memory 255468 kb
Host smart-1b6ce6e7-3d97-4fd0-9a4c-6015c6fb31e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236073014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.236073014
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.378338190
Short name T249
Test name
Test status
Simulation time 97187408661 ps
CPU time 534.79 seconds
Started Mar 03 02:06:54 PM PST 24
Finished Mar 03 02:15:49 PM PST 24
Peak memory 288188 kb
Host smart-6513d006-7057-445e-b963-c6fdc21b06ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378338190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.378338190
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1316888687
Short name T45
Test name
Test status
Simulation time 9987782335 ps
CPU time 16.61 seconds
Started Mar 03 02:06:54 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 239632 kb
Host smart-42753ec4-6bab-4a4b-a1e3-c42d11070715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316888687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1316888687
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1674176076
Short name T15
Test name
Test status
Simulation time 3992238318 ps
CPU time 3.9 seconds
Started Mar 03 02:06:51 PM PST 24
Finished Mar 03 02:06:55 PM PST 24
Peak memory 217816 kb
Host smart-1bd1c4ca-8bd2-4cf1-b645-03e785af0179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674176076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1674176076
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2165506387
Short name T515
Test name
Test status
Simulation time 2716845600 ps
CPU time 10.8 seconds
Started Mar 03 02:06:54 PM PST 24
Finished Mar 03 02:07:05 PM PST 24
Peak memory 217740 kb
Host smart-e593e538-8427-4730-add9-dc11827caf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165506387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2165506387
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2378838066
Short name T719
Test name
Test status
Simulation time 7890703135 ps
CPU time 7.54 seconds
Started Mar 03 02:06:55 PM PST 24
Finished Mar 03 02:07:02 PM PST 24
Peak memory 216288 kb
Host smart-432b89e7-1914-4e00-997f-a488fae33137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378838066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2378838066
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3506506708
Short name T357
Test name
Test status
Simulation time 77746385561 ps
CPU time 47.79 seconds
Started Mar 03 02:06:52 PM PST 24
Finished Mar 03 02:07:40 PM PST 24
Peak memory 228752 kb
Host smart-8917a13c-7046-4eb9-b633-e7c84ff98eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506506708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3506506708
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2547833929
Short name T123
Test name
Test status
Simulation time 384073247 ps
CPU time 4.3 seconds
Started Mar 03 02:07:01 PM PST 24
Finished Mar 03 02:07:07 PM PST 24
Peak memory 222512 kb
Host smart-9eacbb6d-ccfb-4043-9710-dcd1b75e6c59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2547833929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2547833929
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3264546010
Short name T668
Test name
Test status
Simulation time 70242033136 ps
CPU time 128.59 seconds
Started Mar 03 02:06:56 PM PST 24
Finished Mar 03 02:09:05 PM PST 24
Peak memory 248988 kb
Host smart-3cd35c8a-df17-4456-a9a5-d0ab4aa4eedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264546010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3264546010
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3233789580
Short name T277
Test name
Test status
Simulation time 27803783760 ps
CPU time 73.83 seconds
Started Mar 03 02:06:57 PM PST 24
Finished Mar 03 02:08:12 PM PST 24
Peak memory 216268 kb
Host smart-fea8f6d6-9a3b-44ed-b8d6-d12ba7331c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233789580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3233789580
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3247564171
Short name T434
Test name
Test status
Simulation time 6260283143 ps
CPU time 20.38 seconds
Started Mar 03 02:06:55 PM PST 24
Finished Mar 03 02:07:16 PM PST 24
Peak memory 217332 kb
Host smart-f3315169-4851-4ccb-9a02-4e3d6c76a295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247564171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3247564171
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.57094097
Short name T382
Test name
Test status
Simulation time 688392723 ps
CPU time 2.46 seconds
Started Mar 03 02:06:58 PM PST 24
Finished Mar 03 02:07:01 PM PST 24
Peak memory 216276 kb
Host smart-996a1378-c060-4b4c-a8df-0d4b9e9fa10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57094097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.57094097
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1405506095
Short name T530
Test name
Test status
Simulation time 26841048 ps
CPU time 0.76 seconds
Started Mar 03 02:06:56 PM PST 24
Finished Mar 03 02:06:58 PM PST 24
Peak memory 205244 kb
Host smart-2c168c12-3f83-4e8d-a6cf-df69656e3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405506095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1405506095
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.401271085
Short name T960
Test name
Test status
Simulation time 14069800948 ps
CPU time 15.54 seconds
Started Mar 03 02:06:56 PM PST 24
Finished Mar 03 02:07:12 PM PST 24
Peak memory 239552 kb
Host smart-41d47d67-ad4d-4d22-87f1-7b4b3feee4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401271085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.401271085
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2863171807
Short name T704
Test name
Test status
Simulation time 16948615 ps
CPU time 0.77 seconds
Started Mar 03 02:07:01 PM PST 24
Finished Mar 03 02:07:02 PM PST 24
Peak memory 204288 kb
Host smart-31061ce4-519e-4c9e-b2ff-1f6d2885a140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863171807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2863171807
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2614242944
Short name T458
Test name
Test status
Simulation time 251390149 ps
CPU time 2.79 seconds
Started Mar 03 02:06:58 PM PST 24
Finished Mar 03 02:07:01 PM PST 24
Peak memory 234480 kb
Host smart-350613a1-2398-4167-bf9d-b97705bf2899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614242944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2614242944
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.322389320
Short name T624
Test name
Test status
Simulation time 17527366 ps
CPU time 0.8 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:01 PM PST 24
Peak memory 204968 kb
Host smart-0a41a961-a7b9-4f34-8cc2-10485ef2a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322389320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.322389320
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3381827197
Short name T526
Test name
Test status
Simulation time 263048258087 ps
CPU time 224.21 seconds
Started Mar 03 02:07:01 PM PST 24
Finished Mar 03 02:10:46 PM PST 24
Peak memory 253500 kb
Host smart-a5cdcdb0-995f-4e18-9f21-1bbaf7e207ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381827197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3381827197
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.252694617
Short name T344
Test name
Test status
Simulation time 10012621753 ps
CPU time 53.92 seconds
Started Mar 03 02:07:03 PM PST 24
Finished Mar 03 02:07:59 PM PST 24
Peak memory 249108 kb
Host smart-7d77f04e-9383-45a3-91ab-fcbf5005a797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252694617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.252694617
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.314322664
Short name T876
Test name
Test status
Simulation time 29126085146 ps
CPU time 83.94 seconds
Started Mar 03 02:07:02 PM PST 24
Finished Mar 03 02:08:27 PM PST 24
Peak memory 240956 kb
Host smart-d67cde2c-6a8c-41a5-b6e0-323065ecad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314322664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.314322664
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.160401835
Short name T523
Test name
Test status
Simulation time 990325244 ps
CPU time 10.45 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 230088 kb
Host smart-8a172366-a471-4f8f-9a11-6022d505e5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160401835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.160401835
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1842738826
Short name T679
Test name
Test status
Simulation time 2565812154 ps
CPU time 9 seconds
Started Mar 03 02:06:56 PM PST 24
Finished Mar 03 02:07:06 PM PST 24
Peak memory 224424 kb
Host smart-376c8ba1-8df3-4c85-ba43-2aed32a47b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842738826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1842738826
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1280337067
Short name T556
Test name
Test status
Simulation time 2471061169 ps
CPU time 13.83 seconds
Started Mar 03 02:06:54 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 232552 kb
Host smart-30a5185f-64ae-4d3d-b26f-6cec596f9790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280337067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1280337067
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1649061948
Short name T664
Test name
Test status
Simulation time 2009445678 ps
CPU time 2.51 seconds
Started Mar 03 02:06:55 PM PST 24
Finished Mar 03 02:06:58 PM PST 24
Peak memory 224244 kb
Host smart-41575c32-13eb-4710-87fe-65cf39f3aea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649061948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1649061948
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.251731787
Short name T184
Test name
Test status
Simulation time 976329856 ps
CPU time 9.4 seconds
Started Mar 03 02:06:53 PM PST 24
Finished Mar 03 02:07:03 PM PST 24
Peak memory 232892 kb
Host smart-d9274de1-8237-4d3a-a8db-1ec232313991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251731787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.251731787
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.588033299
Short name T969
Test name
Test status
Simulation time 4505975084 ps
CPU time 5.55 seconds
Started Mar 03 02:07:05 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 222512 kb
Host smart-1599c236-6e71-40b0-b43e-b17dcb54e135
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=588033299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.588033299
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2172622433
Short name T450
Test name
Test status
Simulation time 4353727603 ps
CPU time 12.97 seconds
Started Mar 03 02:06:57 PM PST 24
Finished Mar 03 02:07:10 PM PST 24
Peak memory 216304 kb
Host smart-eaeb0a2c-2e2d-4567-859a-cf93b093dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172622433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2172622433
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.309463680
Short name T860
Test name
Test status
Simulation time 6076384316 ps
CPU time 17.89 seconds
Started Mar 03 02:06:53 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 216728 kb
Host smart-96100847-1afb-425b-afaf-a242465b8725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309463680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.309463680
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.234784187
Short name T412
Test name
Test status
Simulation time 352409121 ps
CPU time 3.95 seconds
Started Mar 03 02:06:57 PM PST 24
Finished Mar 03 02:07:01 PM PST 24
Peak memory 216448 kb
Host smart-bc4e2d6d-c0cb-4321-ac52-f6a6c8a1c591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234784187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.234784187
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.509675335
Short name T532
Test name
Test status
Simulation time 364373894 ps
CPU time 0.91 seconds
Started Mar 03 02:06:54 PM PST 24
Finished Mar 03 02:06:55 PM PST 24
Peak memory 205820 kb
Host smart-59561d8a-7d33-4cbb-8a95-77aeffadc483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509675335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.509675335
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3171944359
Short name T988
Test name
Test status
Simulation time 990257887 ps
CPU time 5.97 seconds
Started Mar 03 02:06:59 PM PST 24
Finished Mar 03 02:07:06 PM PST 24
Peak memory 217256 kb
Host smart-ddce3981-b2af-4ffe-9f18-ded9c921a909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171944359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3171944359
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3658745939
Short name T922
Test name
Test status
Simulation time 41367949 ps
CPU time 0.73 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:01 PM PST 24
Peak memory 204880 kb
Host smart-a1703b68-b6cd-40bd-9ec2-6b1fc98efcce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658745939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3658745939
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.456169559
Short name T974
Test name
Test status
Simulation time 1517068487 ps
CPU time 6.56 seconds
Started Mar 03 02:06:59 PM PST 24
Finished Mar 03 02:07:06 PM PST 24
Peak memory 233488 kb
Host smart-215b0eca-eebe-4c7f-be6b-7243b7bb4b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456169559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.456169559
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4241929778
Short name T567
Test name
Test status
Simulation time 67325367 ps
CPU time 0.81 seconds
Started Mar 03 02:07:01 PM PST 24
Finished Mar 03 02:07:03 PM PST 24
Peak memory 205980 kb
Host smart-de5a2c9b-a890-4c79-99e8-a3eb527ed304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241929778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4241929778
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.645153943
Short name T355
Test name
Test status
Simulation time 2313245658 ps
CPU time 10.11 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 232636 kb
Host smart-f58de406-73a0-4ca6-a8b0-da9050cb1ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645153943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.645153943
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1471022707
Short name T255
Test name
Test status
Simulation time 17392577236 ps
CPU time 133.19 seconds
Started Mar 03 02:06:58 PM PST 24
Finished Mar 03 02:09:12 PM PST 24
Peak memory 255944 kb
Host smart-58760dee-d994-4f13-995e-f1e7ba59b5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471022707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1471022707
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3771266387
Short name T30
Test name
Test status
Simulation time 37044810567 ps
CPU time 73.43 seconds
Started Mar 03 02:06:59 PM PST 24
Finished Mar 03 02:08:13 PM PST 24
Peak memory 239516 kb
Host smart-fd305c4f-3f8e-4dc2-b564-bd007e71f75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771266387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3771266387
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1711550453
Short name T598
Test name
Test status
Simulation time 6336501081 ps
CPU time 11.52 seconds
Started Mar 03 02:06:58 PM PST 24
Finished Mar 03 02:07:10 PM PST 24
Peak memory 232600 kb
Host smart-2654100f-7bb1-47c9-a5c3-6ca30ece29f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711550453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1711550453
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.7336596
Short name T124
Test name
Test status
Simulation time 3527217946 ps
CPU time 13.66 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:14 PM PST 24
Peak memory 233588 kb
Host smart-fa2e9713-abda-494b-aa0d-30efe724a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7336596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.7336596
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1084480580
Short name T874
Test name
Test status
Simulation time 15427310992 ps
CPU time 48.61 seconds
Started Mar 03 02:07:02 PM PST 24
Finished Mar 03 02:07:52 PM PST 24
Peak memory 233208 kb
Host smart-1acd5792-9f2c-4a50-b24f-14a3a79bd645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084480580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1084480580
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.538317625
Short name T17
Test name
Test status
Simulation time 16878059189 ps
CPU time 9.53 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 224384 kb
Host smart-aed4d013-928c-4102-899c-122d1fe1185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538317625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.538317625
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1474280002
Short name T706
Test name
Test status
Simulation time 9602920912 ps
CPU time 26.28 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:27 PM PST 24
Peak memory 230712 kb
Host smart-ac7a7b67-24be-4478-a895-36dbceeb25d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474280002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1474280002
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1395489103
Short name T661
Test name
Test status
Simulation time 2415018201 ps
CPU time 4.42 seconds
Started Mar 03 02:07:01 PM PST 24
Finished Mar 03 02:07:07 PM PST 24
Peak memory 221976 kb
Host smart-df22ca2c-21aa-4ec5-94e3-c5469a0731ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1395489103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1395489103
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3180573241
Short name T924
Test name
Test status
Simulation time 49976796 ps
CPU time 1.04 seconds
Started Mar 03 02:06:59 PM PST 24
Finished Mar 03 02:07:01 PM PST 24
Peak memory 206196 kb
Host smart-697766dd-a2a6-4c99-8aa2-2281f43f525a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180573241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3180573241
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1708563686
Short name T426
Test name
Test status
Simulation time 2943908887 ps
CPU time 27.51 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:28 PM PST 24
Peak memory 216252 kb
Host smart-874690d9-b910-4ec7-8453-b8ca02f69072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708563686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1708563686
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3057072790
Short name T630
Test name
Test status
Simulation time 290185308 ps
CPU time 1.08 seconds
Started Mar 03 02:07:05 PM PST 24
Finished Mar 03 02:07:06 PM PST 24
Peak memory 206680 kb
Host smart-5808603e-1fad-4a0b-8035-3050c66405de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057072790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3057072790
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4017816681
Short name T341
Test name
Test status
Simulation time 66600868 ps
CPU time 2.7 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:04 PM PST 24
Peak memory 216380 kb
Host smart-36eae4e8-c2b7-46de-9708-02a8b1971b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017816681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4017816681
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1980598146
Short name T632
Test name
Test status
Simulation time 130973461 ps
CPU time 0.79 seconds
Started Mar 03 02:07:02 PM PST 24
Finished Mar 03 02:07:03 PM PST 24
Peak memory 205360 kb
Host smart-53a701ce-0a0c-4b4c-a72c-b59ff1b76d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980598146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1980598146
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.648199187
Short name T786
Test name
Test status
Simulation time 1485367812 ps
CPU time 8.69 seconds
Started Mar 03 02:06:59 PM PST 24
Finished Mar 03 02:07:09 PM PST 24
Peak memory 236028 kb
Host smart-2d128b24-fa88-4e80-94c4-f115acfd3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648199187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.648199187
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.806858379
Short name T474
Test name
Test status
Simulation time 25778175 ps
CPU time 0.74 seconds
Started Mar 03 02:07:05 PM PST 24
Finished Mar 03 02:07:06 PM PST 24
Peak memory 204896 kb
Host smart-42fac026-7979-4353-9386-c50c315853b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806858379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.806858379
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.364865990
Short name T933
Test name
Test status
Simulation time 304002753 ps
CPU time 4.5 seconds
Started Mar 03 02:07:01 PM PST 24
Finished Mar 03 02:07:06 PM PST 24
Peak memory 219768 kb
Host smart-c91446db-c8b6-426f-af88-8e2dcd87fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364865990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.364865990
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.111454027
Short name T542
Test name
Test status
Simulation time 36868788 ps
CPU time 0.98 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:02 PM PST 24
Peak memory 206016 kb
Host smart-de873406-12be-4b35-aa8e-e6ad13140a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111454027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.111454027
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3653957204
Short name T385
Test name
Test status
Simulation time 82165530333 ps
CPU time 111.78 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:08:58 PM PST 24
Peak memory 250164 kb
Host smart-5c6bfc83-397c-40ed-9d24-31d7c59ddc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653957204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3653957204
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3082867940
Short name T746
Test name
Test status
Simulation time 239569271918 ps
CPU time 447.79 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:14:35 PM PST 24
Peak memory 255676 kb
Host smart-5ffe5b07-77d4-472c-a42e-a08fec197aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082867940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3082867940
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3906649723
Short name T950
Test name
Test status
Simulation time 7896885794 ps
CPU time 38.83 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:07:46 PM PST 24
Peak memory 246844 kb
Host smart-5f9d8e90-b067-441e-85ae-31f758f74ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906649723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3906649723
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.467319905
Short name T586
Test name
Test status
Simulation time 2869192265 ps
CPU time 9.1 seconds
Started Mar 03 02:07:01 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 218324 kb
Host smart-b360d46e-2282-4d6d-8e68-62eea0a10668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467319905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.467319905
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2988237704
Short name T905
Test name
Test status
Simulation time 1262695194 ps
CPU time 15.79 seconds
Started Mar 03 02:06:59 PM PST 24
Finished Mar 03 02:07:16 PM PST 24
Peak memory 235768 kb
Host smart-e88ee41b-a4aa-476f-926e-9d0730078834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988237704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2988237704
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1975363459
Short name T980
Test name
Test status
Simulation time 936459193 ps
CPU time 5.98 seconds
Started Mar 03 02:07:02 PM PST 24
Finished Mar 03 02:07:09 PM PST 24
Peak memory 238800 kb
Host smart-5286a3f3-bdbe-4c20-a20c-edbe756e176f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975363459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1975363459
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3011728735
Short name T753
Test name
Test status
Simulation time 680633782 ps
CPU time 6.24 seconds
Started Mar 03 02:07:04 PM PST 24
Finished Mar 03 02:07:12 PM PST 24
Peak memory 233532 kb
Host smart-b8d46368-08bf-467c-868a-d8d641e838e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011728735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3011728735
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.997258277
Short name T480
Test name
Test status
Simulation time 174815144 ps
CPU time 3.78 seconds
Started Mar 03 02:07:08 PM PST 24
Finished Mar 03 02:07:12 PM PST 24
Peak memory 222460 kb
Host smart-c781ea9e-3be2-4a99-920a-a204e93e384b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=997258277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.997258277
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.569839498
Short name T73
Test name
Test status
Simulation time 215407556315 ps
CPU time 339.79 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:12:47 PM PST 24
Peak memory 270492 kb
Host smart-f1c1ebed-f96b-4428-91b6-dc9c890549c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569839498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.569839498
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.917480960
Short name T492
Test name
Test status
Simulation time 6131272868 ps
CPU time 31.62 seconds
Started Mar 03 02:07:01 PM PST 24
Finished Mar 03 02:07:34 PM PST 24
Peak memory 216308 kb
Host smart-63d2cbb8-dabf-4d1a-b297-a90456da13ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917480960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.917480960
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.246041880
Short name T813
Test name
Test status
Simulation time 1219652987 ps
CPU time 1.91 seconds
Started Mar 03 02:07:02 PM PST 24
Finished Mar 03 02:07:05 PM PST 24
Peak memory 206696 kb
Host smart-db61cd85-8273-49d3-a049-12e2d6464d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246041880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.246041880
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.597604893
Short name T431
Test name
Test status
Simulation time 102798911 ps
CPU time 3.07 seconds
Started Mar 03 02:07:03 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 207900 kb
Host smart-1d62f350-5da4-4019-9d6a-73c4f38ed9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597604893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.597604893
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3306622570
Short name T376
Test name
Test status
Simulation time 60032716 ps
CPU time 0.73 seconds
Started Mar 03 02:07:00 PM PST 24
Finished Mar 03 02:07:01 PM PST 24
Peak memory 205228 kb
Host smart-6f722dfe-e75c-4cab-80a0-e606f2738b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306622570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3306622570
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4124659830
Short name T700
Test name
Test status
Simulation time 148017707414 ps
CPU time 42.54 seconds
Started Mar 03 02:07:04 PM PST 24
Finished Mar 03 02:07:48 PM PST 24
Peak memory 247404 kb
Host smart-4db0093f-34de-4ddf-b484-14864a1a45e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124659830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4124659830
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1373787362
Short name T65
Test name
Test status
Simulation time 14569833 ps
CPU time 0.73 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 204224 kb
Host smart-a37c4749-9128-4824-b9a3-16b68527bcda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373787362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1373787362
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3221748788
Short name T627
Test name
Test status
Simulation time 214743145 ps
CPU time 3.43 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 218676 kb
Host smart-09b2a1db-4e85-4796-9d38-e9fe1750f6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221748788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3221748788
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3991712020
Short name T422
Test name
Test status
Simulation time 46378071 ps
CPU time 0.76 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 205936 kb
Host smart-ec1271da-05be-4cb0-b1bc-b7e289d7bb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991712020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3991712020
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4023700504
Short name T657
Test name
Test status
Simulation time 1265355766 ps
CPU time 24.26 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:30 PM PST 24
Peak memory 248940 kb
Host smart-bf2da4a0-4fbe-4c33-be84-b5dd216b2291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023700504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4023700504
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2306667390
Short name T958
Test name
Test status
Simulation time 12197484186 ps
CPU time 46.44 seconds
Started Mar 03 02:07:05 PM PST 24
Finished Mar 03 02:07:52 PM PST 24
Peak memory 236408 kb
Host smart-ed914f99-8ce3-4654-9a18-1dc675570a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306667390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2306667390
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.168904546
Short name T916
Test name
Test status
Simulation time 9016337790 ps
CPU time 101.71 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:08:49 PM PST 24
Peak memory 255216 kb
Host smart-1053f7c2-cf0b-4000-ba79-f70642b1d959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168904546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.168904546
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1507736363
Short name T433
Test name
Test status
Simulation time 5244247715 ps
CPU time 34.35 seconds
Started Mar 03 02:07:08 PM PST 24
Finished Mar 03 02:07:42 PM PST 24
Peak memory 236396 kb
Host smart-553c122c-674c-46b6-a6fd-b1dd081f5c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507736363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1507736363
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.882149788
Short name T36
Test name
Test status
Simulation time 1175973531 ps
CPU time 4.62 seconds
Started Mar 03 02:07:05 PM PST 24
Finished Mar 03 02:07:10 PM PST 24
Peak memory 233076 kb
Host smart-ee7c15ea-174d-46be-b4ea-cb496bf498f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882149788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.882149788
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1203598824
Short name T665
Test name
Test status
Simulation time 9940967109 ps
CPU time 8.58 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:15 PM PST 24
Peak memory 224376 kb
Host smart-b03d19c6-bc92-46eb-890d-fa0a4ba22bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203598824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1203598824
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.361001995
Short name T539
Test name
Test status
Simulation time 22719683137 ps
CPU time 12.46 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:07:20 PM PST 24
Peak memory 217180 kb
Host smart-59089f60-ed64-4045-a8d4-f585e5a841e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361001995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.361001995
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2965054659
Short name T167
Test name
Test status
Simulation time 38958504067 ps
CPU time 15.11 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:07:23 PM PST 24
Peak memory 236312 kb
Host smart-aa8faa30-abda-4e5c-9c0e-8ed78d83cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965054659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2965054659
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2924637505
Short name T871
Test name
Test status
Simulation time 3159046321 ps
CPU time 5.48 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:11 PM PST 24
Peak memory 217180 kb
Host smart-6a09b0f7-841e-4831-8fcd-3aadde622992
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2924637505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2924637505
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1068146422
Short name T74
Test name
Test status
Simulation time 37924017662 ps
CPU time 200.85 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:10:28 PM PST 24
Peak memory 257344 kb
Host smart-194d8d34-475f-4116-beeb-d5102427f978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068146422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1068146422
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1658689891
Short name T352
Test name
Test status
Simulation time 4405984783 ps
CPU time 22.6 seconds
Started Mar 03 02:07:05 PM PST 24
Finished Mar 03 02:07:28 PM PST 24
Peak memory 216268 kb
Host smart-2098292a-ec7f-4825-a8fe-5536c7a18131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658689891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1658689891
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2080516401
Short name T299
Test name
Test status
Simulation time 348735090 ps
CPU time 2.01 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 206824 kb
Host smart-a8c4b922-2b0b-42d4-a448-be333088c793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080516401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2080516401
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.323182325
Short name T887
Test name
Test status
Simulation time 585908995 ps
CPU time 2.58 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 216220 kb
Host smart-1c612391-12cd-481b-9bf1-55c8199fae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323182325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.323182325
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.343497229
Short name T300
Test name
Test status
Simulation time 113185353 ps
CPU time 1.05 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:07 PM PST 24
Peak memory 205360 kb
Host smart-18bedb85-ba10-40f8-a6dc-9c316364d39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343497229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.343497229
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1425074539
Short name T214
Test name
Test status
Simulation time 1492051609 ps
CPU time 11.96 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:18 PM PST 24
Peak memory 219536 kb
Host smart-665eeedd-441a-49dc-ab83-fe75d90f07b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425074539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1425074539
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2738121018
Short name T649
Test name
Test status
Simulation time 47066024 ps
CPU time 0.76 seconds
Started Mar 03 02:07:12 PM PST 24
Finished Mar 03 02:07:13 PM PST 24
Peak memory 205200 kb
Host smart-bf918b8a-7e8b-4f68-9ec4-947c00ca5153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738121018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2738121018
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.367519570
Short name T771
Test name
Test status
Simulation time 1117981168 ps
CPU time 5.22 seconds
Started Mar 03 02:07:14 PM PST 24
Finished Mar 03 02:07:22 PM PST 24
Peak memory 224388 kb
Host smart-454d3abe-b6f0-485e-b7f6-ed86134efeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367519570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.367519570
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.943399089
Short name T318
Test name
Test status
Simulation time 16874839 ps
CPU time 0.75 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:07 PM PST 24
Peak memory 204964 kb
Host smart-6c49ae94-12cd-4a6a-b031-ee422af6b592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943399089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.943399089
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2971387461
Short name T597
Test name
Test status
Simulation time 234160830358 ps
CPU time 212.8 seconds
Started Mar 03 02:07:13 PM PST 24
Finished Mar 03 02:10:46 PM PST 24
Peak memory 256300 kb
Host smart-f24e3b27-f2cb-49b9-9d91-a74b688b89ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971387461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2971387461
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3448610607
Short name T85
Test name
Test status
Simulation time 65325063696 ps
CPU time 251.17 seconds
Started Mar 03 02:07:14 PM PST 24
Finished Mar 03 02:11:28 PM PST 24
Peak memory 250048 kb
Host smart-dee377f4-e2be-43e5-b57e-fd1088581401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448610607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3448610607
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3274380119
Short name T942
Test name
Test status
Simulation time 2577038723 ps
CPU time 19.19 seconds
Started Mar 03 02:07:11 PM PST 24
Finished Mar 03 02:07:30 PM PST 24
Peak memory 233512 kb
Host smart-1964a919-28c9-4744-841e-1e9849023874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274380119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3274380119
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3088929558
Short name T617
Test name
Test status
Simulation time 620405561 ps
CPU time 3.61 seconds
Started Mar 03 02:07:14 PM PST 24
Finished Mar 03 02:07:20 PM PST 24
Peak memory 233056 kb
Host smart-5f411374-e01f-4cbf-8805-72054de92659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088929558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3088929558
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1353823949
Short name T83
Test name
Test status
Simulation time 3999743287 ps
CPU time 9.93 seconds
Started Mar 03 02:07:13 PM PST 24
Finished Mar 03 02:07:23 PM PST 24
Peak memory 217044 kb
Host smart-b59a7b79-5f9d-499d-8c08-81f7daa71962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353823949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1353823949
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1393515263
Short name T829
Test name
Test status
Simulation time 13845060125 ps
CPU time 20.76 seconds
Started Mar 03 02:07:11 PM PST 24
Finished Mar 03 02:07:32 PM PST 24
Peak memory 224472 kb
Host smart-65f7fd4e-1cab-49e0-ada0-b20a9ae63f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393515263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1393515263
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1415980826
Short name T738
Test name
Test status
Simulation time 1995284939 ps
CPU time 5.07 seconds
Started Mar 03 02:07:13 PM PST 24
Finished Mar 03 02:07:19 PM PST 24
Peak memory 216580 kb
Host smart-03923fbf-9eb9-4dbd-b9d2-16723ec5c56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415980826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1415980826
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1740456111
Short name T534
Test name
Test status
Simulation time 212960429 ps
CPU time 4.18 seconds
Started Mar 03 02:07:12 PM PST 24
Finished Mar 03 02:07:16 PM PST 24
Peak memory 222424 kb
Host smart-4ea047f9-006e-4a7f-a877-b17644a50e04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1740456111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1740456111
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2953338044
Short name T729
Test name
Test status
Simulation time 1899858079 ps
CPU time 30.94 seconds
Started Mar 03 02:07:06 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 216204 kb
Host smart-d80530d7-61c9-4796-813d-c209041380ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953338044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2953338044
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1747426102
Short name T517
Test name
Test status
Simulation time 37910329954 ps
CPU time 24.99 seconds
Started Mar 03 02:07:07 PM PST 24
Finished Mar 03 02:07:32 PM PST 24
Peak memory 216340 kb
Host smart-b76f5853-5e3a-45e4-ab2f-9d624cb7a5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747426102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1747426102
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.205831186
Short name T320
Test name
Test status
Simulation time 62748916 ps
CPU time 1.39 seconds
Started Mar 03 02:07:12 PM PST 24
Finished Mar 03 02:07:14 PM PST 24
Peak memory 216156 kb
Host smart-17f78740-e3af-4b65-81f3-f369831f96b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205831186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.205831186
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2369268225
Short name T736
Test name
Test status
Simulation time 56450389 ps
CPU time 0.87 seconds
Started Mar 03 02:07:08 PM PST 24
Finished Mar 03 02:07:09 PM PST 24
Peak memory 205252 kb
Host smart-3fa869cd-3fcb-4ae1-aa5d-139ebdf346c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369268225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2369268225
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2999435427
Short name T932
Test name
Test status
Simulation time 859326231 ps
CPU time 10.21 seconds
Started Mar 03 02:07:13 PM PST 24
Finished Mar 03 02:07:23 PM PST 24
Peak memory 244228 kb
Host smart-80a7c3ce-d0bf-40b1-a626-9f3b84685be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999435427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2999435427
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2221909793
Short name T512
Test name
Test status
Simulation time 14220608 ps
CPU time 0.75 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:21 PM PST 24
Peak memory 204232 kb
Host smart-3fc9291f-9e36-4dee-8963-b16f8b3a3196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221909793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2221909793
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1502288708
Short name T803
Test name
Test status
Simulation time 756149674 ps
CPU time 6.53 seconds
Started Mar 03 02:07:17 PM PST 24
Finished Mar 03 02:07:25 PM PST 24
Peak memory 220848 kb
Host smart-3ad96f3e-51a7-44fc-b5da-a0e2edd6b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502288708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1502288708
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3264625793
Short name T986
Test name
Test status
Simulation time 16815570 ps
CPU time 0.77 seconds
Started Mar 03 02:07:14 PM PST 24
Finished Mar 03 02:07:17 PM PST 24
Peak memory 204980 kb
Host smart-48520557-31c2-47dc-ab06-5f96e0840986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264625793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3264625793
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2730839536
Short name T188
Test name
Test status
Simulation time 34475497580 ps
CPU time 143.34 seconds
Started Mar 03 02:07:20 PM PST 24
Finished Mar 03 02:09:44 PM PST 24
Peak memory 249036 kb
Host smart-265cd719-c0a2-43f6-910c-b8df1ee22514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730839536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2730839536
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1965325389
Short name T55
Test name
Test status
Simulation time 178541336496 ps
CPU time 348 seconds
Started Mar 03 02:07:20 PM PST 24
Finished Mar 03 02:13:08 PM PST 24
Peak memory 252280 kb
Host smart-bb074cbd-cac1-4270-b337-1c3b2a62082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965325389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1965325389
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2114394689
Short name T374
Test name
Test status
Simulation time 433543735 ps
CPU time 8.07 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:28 PM PST 24
Peak memory 224340 kb
Host smart-18b84cd6-0db4-4913-b8b0-0e09b19b6d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114394689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2114394689
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.276685961
Short name T499
Test name
Test status
Simulation time 305315921 ps
CPU time 4.31 seconds
Started Mar 03 02:07:13 PM PST 24
Finished Mar 03 02:07:17 PM PST 24
Peak memory 233360 kb
Host smart-6fabd8c0-17c6-4a06-9ace-db5b76874a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276685961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.276685961
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.345716446
Short name T44
Test name
Test status
Simulation time 9529828085 ps
CPU time 17.77 seconds
Started Mar 03 02:07:18 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 240076 kb
Host smart-c7808289-e6af-483c-8890-a98f8c17c894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345716446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.345716446
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2640456506
Short name T877
Test name
Test status
Simulation time 23437709636 ps
CPU time 23.44 seconds
Started Mar 03 02:07:13 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 227608 kb
Host smart-edcd0fd0-1b95-4fa8-b3fc-197f88787866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640456506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2640456506
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3146860575
Short name T820
Test name
Test status
Simulation time 63633107521 ps
CPU time 17.75 seconds
Started Mar 03 02:07:11 PM PST 24
Finished Mar 03 02:07:29 PM PST 24
Peak memory 249568 kb
Host smart-37ada5e3-37c2-4432-a990-6734ed746e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146860575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3146860575
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4120656486
Short name T596
Test name
Test status
Simulation time 197229658 ps
CPU time 3.22 seconds
Started Mar 03 02:07:20 PM PST 24
Finished Mar 03 02:07:24 PM PST 24
Peak memory 216340 kb
Host smart-e31007f2-11ba-4878-901c-6fa9f88fcc5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4120656486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4120656486
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2242222094
Short name T164
Test name
Test status
Simulation time 60493819 ps
CPU time 1.09 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:21 PM PST 24
Peak memory 206388 kb
Host smart-126938f9-85ce-4947-98fb-804e308b6da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242222094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2242222094
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1247019593
Short name T646
Test name
Test status
Simulation time 41058903215 ps
CPU time 45.48 seconds
Started Mar 03 02:07:14 PM PST 24
Finished Mar 03 02:08:02 PM PST 24
Peak memory 216332 kb
Host smart-63acdec3-b766-45f2-ab22-8ace326fe841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247019593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1247019593
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1238024851
Short name T982
Test name
Test status
Simulation time 12101350755 ps
CPU time 24.61 seconds
Started Mar 03 02:07:12 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 216240 kb
Host smart-d92ffa30-c8f9-46b9-a0df-54029a2d7d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238024851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1238024851
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3774195810
Short name T752
Test name
Test status
Simulation time 96383836 ps
CPU time 2.76 seconds
Started Mar 03 02:07:12 PM PST 24
Finished Mar 03 02:07:16 PM PST 24
Peak memory 216208 kb
Host smart-0fbce9e7-a18b-423d-9237-2d87e87e7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774195810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3774195810
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2678386786
Short name T603
Test name
Test status
Simulation time 228232974 ps
CPU time 1.08 seconds
Started Mar 03 02:07:15 PM PST 24
Finished Mar 03 02:07:18 PM PST 24
Peak memory 206392 kb
Host smart-5d80a465-0287-42e8-b515-1c1977ed9187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678386786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2678386786
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2376743206
Short name T654
Test name
Test status
Simulation time 792387806 ps
CPU time 8.6 seconds
Started Mar 03 02:07:21 PM PST 24
Finished Mar 03 02:07:29 PM PST 24
Peak memory 218552 kb
Host smart-28b8dfcd-ed33-440e-ab21-4e84e0333fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376743206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2376743206
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.94467819
Short name T892
Test name
Test status
Simulation time 44967472 ps
CPU time 0.74 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:07:28 PM PST 24
Peak memory 204840 kb
Host smart-00774601-798b-4b60-8b09-67f363fcbe13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94467819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.94467819
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3175452644
Short name T731
Test name
Test status
Simulation time 424195593 ps
CPU time 2.69 seconds
Started Mar 03 02:07:24 PM PST 24
Finished Mar 03 02:07:27 PM PST 24
Peak memory 224396 kb
Host smart-ab771f02-eb65-4450-a816-9a7eb75ed422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175452644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3175452644
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2292512247
Short name T582
Test name
Test status
Simulation time 16687066 ps
CPU time 0.8 seconds
Started Mar 03 02:07:21 PM PST 24
Finished Mar 03 02:07:22 PM PST 24
Peak memory 205984 kb
Host smart-bf07426d-108a-497f-b4e1-652e7f6b953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292512247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2292512247
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1914454426
Short name T708
Test name
Test status
Simulation time 99205684275 ps
CPU time 170.61 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:10:16 PM PST 24
Peak memory 257292 kb
Host smart-5f654dc7-def4-40fe-9d25-277f98bb7d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914454426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1914454426
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.718655652
Short name T60
Test name
Test status
Simulation time 14475126165 ps
CPU time 139.66 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:09:47 PM PST 24
Peak memory 253476 kb
Host smart-cbed29de-3a1d-44ec-829d-e7b3a136a0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718655652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.718655652
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1910167689
Short name T782
Test name
Test status
Simulation time 716532208 ps
CPU time 14.73 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:07:39 PM PST 24
Peak memory 249076 kb
Host smart-c5f6b8d7-3fb3-467c-9d0a-91c44e428c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910167689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1910167689
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1143594712
Short name T405
Test name
Test status
Simulation time 895489642 ps
CPU time 3.79 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:23 PM PST 24
Peak memory 233492 kb
Host smart-af28da95-3eaf-4693-a2d4-b3c94b743360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143594712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1143594712
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3498920960
Short name T594
Test name
Test status
Simulation time 25425284583 ps
CPU time 7.29 seconds
Started Mar 03 02:07:30 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 222036 kb
Host smart-f971d572-14c1-4727-9f80-6f53c29b6ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498920960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3498920960
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2127796614
Short name T826
Test name
Test status
Simulation time 3825428277 ps
CPU time 13.78 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:34 PM PST 24
Peak memory 233416 kb
Host smart-2a599ed7-7ade-431e-9427-6534447cb087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127796614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2127796614
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.390255667
Short name T778
Test name
Test status
Simulation time 1286878275 ps
CPU time 4.14 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:24 PM PST 24
Peak memory 233136 kb
Host smart-cc03d480-fde0-41c2-b583-7fd2dc343dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390255667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.390255667
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2469846991
Short name T688
Test name
Test status
Simulation time 10584783903 ps
CPU time 6.26 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:07:32 PM PST 24
Peak memory 222460 kb
Host smart-ef0bc31b-64fe-4504-9caf-dd7dc78a30ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2469846991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2469846991
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3626150308
Short name T313
Test name
Test status
Simulation time 2218279697 ps
CPU time 4.31 seconds
Started Mar 03 02:07:18 PM PST 24
Finished Mar 03 02:07:23 PM PST 24
Peak memory 216324 kb
Host smart-8d4d5eea-7e42-4f42-8888-2ffa7564cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626150308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3626150308
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.179380805
Short name T323
Test name
Test status
Simulation time 3535730052 ps
CPU time 5.05 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:25 PM PST 24
Peak memory 216276 kb
Host smart-34bbca2e-b40f-40fc-9325-389e4764dddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179380805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.179380805
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2976375013
Short name T635
Test name
Test status
Simulation time 229506058 ps
CPU time 7.22 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:27 PM PST 24
Peak memory 216288 kb
Host smart-55f3cbf8-a3bf-45aa-ba4a-babae2ef6aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976375013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2976375013
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.782694638
Short name T312
Test name
Test status
Simulation time 97379681 ps
CPU time 0.96 seconds
Started Mar 03 02:07:19 PM PST 24
Finished Mar 03 02:07:21 PM PST 24
Peak memory 205344 kb
Host smart-1eda17f9-490d-47a9-8bfe-daad1efb8c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782694638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.782694638
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2114220978
Short name T966
Test name
Test status
Simulation time 47433926496 ps
CPU time 34.54 seconds
Started Mar 03 02:07:23 PM PST 24
Finished Mar 03 02:07:57 PM PST 24
Peak memory 234732 kb
Host smart-a4cd57ab-e2b0-4c5d-be54-feaaf8da092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114220978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2114220978
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2215156277
Short name T365
Test name
Test status
Simulation time 50738996 ps
CPU time 0.67 seconds
Started Mar 03 02:07:23 PM PST 24
Finished Mar 03 02:07:23 PM PST 24
Peak memory 204888 kb
Host smart-2aff2b3d-9cf1-4afa-8ced-eb9646546583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215156277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2215156277
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3102931806
Short name T213
Test name
Test status
Simulation time 502643456 ps
CPU time 5.16 seconds
Started Mar 03 02:07:27 PM PST 24
Finished Mar 03 02:07:32 PM PST 24
Peak memory 232972 kb
Host smart-1b761408-ad23-4a5b-93a4-608bc9992f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102931806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3102931806
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.783981467
Short name T315
Test name
Test status
Simulation time 18735601 ps
CPU time 0.81 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:07:26 PM PST 24
Peak memory 204996 kb
Host smart-4a5d7283-c8f2-447c-8c51-e14494a84936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783981467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.783981467
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2123222419
Short name T23
Test name
Test status
Simulation time 32473697798 ps
CPU time 81.41 seconds
Started Mar 03 02:07:24 PM PST 24
Finished Mar 03 02:08:46 PM PST 24
Peak memory 256148 kb
Host smart-ae96695e-c28d-46c7-ae2b-420c3101fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123222419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2123222419
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3812220077
Short name T169
Test name
Test status
Simulation time 176776941715 ps
CPU time 239.23 seconds
Started Mar 03 02:07:27 PM PST 24
Finished Mar 03 02:11:26 PM PST 24
Peak memory 260212 kb
Host smart-b93794d5-977f-43e5-940d-430f7ae1aea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812220077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3812220077
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4073783285
Short name T238
Test name
Test status
Simulation time 34180803545 ps
CPU time 67.69 seconds
Started Mar 03 02:07:24 PM PST 24
Finished Mar 03 02:08:32 PM PST 24
Peak memory 249112 kb
Host smart-3739d85d-e699-4afb-a4b4-000c68d99353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073783285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4073783285
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1842851344
Short name T818
Test name
Test status
Simulation time 170876357 ps
CPU time 2.96 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:07:28 PM PST 24
Peak memory 224380 kb
Host smart-d1334bbd-95fb-45aa-9391-0e7fdb8bbe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842851344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1842851344
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1650827160
Short name T843
Test name
Test status
Simulation time 10171211844 ps
CPU time 33.96 seconds
Started Mar 03 02:07:27 PM PST 24
Finished Mar 03 02:08:02 PM PST 24
Peak memory 240000 kb
Host smart-0cef6b95-bea7-4ca0-83f0-cf78dc6bc65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650827160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1650827160
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1031562855
Short name T493
Test name
Test status
Simulation time 2327406971 ps
CPU time 12.43 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:07:38 PM PST 24
Peak memory 224440 kb
Host smart-5f1c8cc3-e52c-4774-905a-66165cd4fe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031562855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1031562855
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4162672755
Short name T221
Test name
Test status
Simulation time 11328248782 ps
CPU time 20.45 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:07:47 PM PST 24
Peak memory 217768 kb
Host smart-bcf8f5c8-2c9b-4515-9233-f792a75de125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162672755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4162672755
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2972459780
Short name T500
Test name
Test status
Simulation time 1009644917 ps
CPU time 4.1 seconds
Started Mar 03 02:07:24 PM PST 24
Finished Mar 03 02:07:28 PM PST 24
Peak memory 221976 kb
Host smart-0dc8ee30-dc77-42be-beec-44092997cba0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2972459780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2972459780
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1799644567
Short name T301
Test name
Test status
Simulation time 2243116902 ps
CPU time 10.18 seconds
Started Mar 03 02:07:27 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 216312 kb
Host smart-30c62539-4b27-485d-b5e7-603ddd5c70c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799644567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1799644567
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1005719700
Short name T747
Test name
Test status
Simulation time 3007936218 ps
CPU time 9.76 seconds
Started Mar 03 02:07:24 PM PST 24
Finished Mar 03 02:07:34 PM PST 24
Peak memory 216300 kb
Host smart-42253029-df54-4f6b-a30f-a3870ccc8474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005719700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1005719700
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2947186759
Short name T302
Test name
Test status
Simulation time 21047434 ps
CPU time 1.01 seconds
Started Mar 03 02:07:28 PM PST 24
Finished Mar 03 02:07:29 PM PST 24
Peak memory 206368 kb
Host smart-81aaf239-9879-43a7-b82c-397f512fca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947186759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2947186759
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.194295581
Short name T326
Test name
Test status
Simulation time 56952852 ps
CPU time 0.88 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:07:27 PM PST 24
Peak memory 205376 kb
Host smart-2ea55350-f5c8-4838-919f-c49e809f0a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194295581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.194295581
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.197307289
Short name T241
Test name
Test status
Simulation time 9742256582 ps
CPU time 27.66 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:07:54 PM PST 24
Peak memory 233932 kb
Host smart-8af6632c-54ea-4aab-9719-1322903c6a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197307289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.197307289
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3448744219
Short name T810
Test name
Test status
Simulation time 28049403 ps
CPU time 0.72 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:06 PM PST 24
Peak memory 204172 kb
Host smart-bfa23001-2e5a-4ae7-81a8-833afec4b429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448744219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
448744219
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3702694569
Short name T772
Test name
Test status
Simulation time 517385779 ps
CPU time 3.52 seconds
Started Mar 03 02:05:52 PM PST 24
Finished Mar 03 02:05:56 PM PST 24
Peak memory 233464 kb
Host smart-b94fc8d2-ad2e-4085-903b-34f3f2a7ff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702694569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3702694569
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3649125886
Short name T833
Test name
Test status
Simulation time 33597553 ps
CPU time 0.84 seconds
Started Mar 03 02:05:49 PM PST 24
Finished Mar 03 02:05:50 PM PST 24
Peak memory 205996 kb
Host smart-a955970e-7fdd-4392-a2f2-4a6746b2d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649125886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3649125886
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1980368583
Short name T847
Test name
Test status
Simulation time 14323450313 ps
CPU time 32.23 seconds
Started Mar 03 02:05:51 PM PST 24
Finished Mar 03 02:06:24 PM PST 24
Peak memory 237648 kb
Host smart-b55884e5-ed8b-472f-a7e6-103ed75adc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980368583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1980368583
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.807921459
Short name T257
Test name
Test status
Simulation time 28988600294 ps
CPU time 96.2 seconds
Started Mar 03 02:05:53 PM PST 24
Finished Mar 03 02:07:31 PM PST 24
Peak memory 253888 kb
Host smart-848a24d5-e182-47b6-a319-f31e0235048f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807921459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
807921459
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3341402447
Short name T638
Test name
Test status
Simulation time 2629827197 ps
CPU time 7.37 seconds
Started Mar 03 02:05:52 PM PST 24
Finished Mar 03 02:06:00 PM PST 24
Peak memory 224440 kb
Host smart-27e14dd3-576c-4a5a-895b-0281399574cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341402447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3341402447
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2959494610
Short name T67
Test name
Test status
Simulation time 370337386 ps
CPU time 5.34 seconds
Started Mar 03 02:05:56 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 237176 kb
Host smart-fe834cba-cef6-47ad-be3e-a30c08cbdc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959494610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2959494610
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1811757125
Short name T284
Test name
Test status
Simulation time 69437108 ps
CPU time 1.05 seconds
Started Mar 03 02:05:47 PM PST 24
Finished Mar 03 02:05:49 PM PST 24
Peak memory 216556 kb
Host smart-3d4609c1-a140-4bb9-a27d-6b72c9ed466d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811757125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1811757125
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1394649163
Short name T792
Test name
Test status
Simulation time 16039228441 ps
CPU time 22.46 seconds
Started Mar 03 02:05:53 PM PST 24
Finished Mar 03 02:06:17 PM PST 24
Peak memory 233448 kb
Host smart-8d68ad30-5b7b-4278-a314-6b0acd9a0bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394649163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1394649163
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3877040045
Short name T940
Test name
Test status
Simulation time 5340822016 ps
CPU time 13.34 seconds
Started Mar 03 02:05:52 PM PST 24
Finished Mar 03 02:06:05 PM PST 24
Peak memory 236328 kb
Host smart-9ea290ae-e48b-4485-b953-00880d488eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877040045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3877040045
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.2824702177
Short name T977
Test name
Test status
Simulation time 33095666 ps
CPU time 0.73 seconds
Started Mar 03 02:05:48 PM PST 24
Finished Mar 03 02:05:49 PM PST 24
Peak memory 216044 kb
Host smart-70b46772-3f8e-4687-9dce-b026b8af47bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824702177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.2824702177
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4185756548
Short name T144
Test name
Test status
Simulation time 586612093 ps
CPU time 4.19 seconds
Started Mar 03 02:05:52 PM PST 24
Finished Mar 03 02:05:56 PM PST 24
Peak memory 219884 kb
Host smart-aff39fc4-10f5-48d9-abae-f7ac98ce37a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4185756548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4185756548
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2376267475
Short name T80
Test name
Test status
Simulation time 32538057 ps
CPU time 0.98 seconds
Started Mar 03 02:05:51 PM PST 24
Finished Mar 03 02:05:52 PM PST 24
Peak memory 233680 kb
Host smart-b3501578-d25d-410c-9ab1-7fb127e5d531
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376267475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2376267475
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.372761929
Short name T163
Test name
Test status
Simulation time 3568013970 ps
CPU time 9.57 seconds
Started Mar 03 02:05:53 PM PST 24
Finished Mar 03 02:06:04 PM PST 24
Peak memory 220492 kb
Host smart-d2d665fb-e85b-4954-ba61-e69f63967ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372761929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.372761929
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3781881818
Short name T830
Test name
Test status
Simulation time 30958711777 ps
CPU time 14.92 seconds
Started Mar 03 02:05:50 PM PST 24
Finished Mar 03 02:06:06 PM PST 24
Peak memory 216320 kb
Host smart-1c7062fb-8a30-4a65-9105-c57c9bfda8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781881818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3781881818
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2627289727
Short name T658
Test name
Test status
Simulation time 538060492 ps
CPU time 3.24 seconds
Started Mar 03 02:05:55 PM PST 24
Finished Mar 03 02:05:58 PM PST 24
Peak memory 216252 kb
Host smart-d9505d3c-2093-4d10-b822-0a1d928b1c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627289727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2627289727
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3687738095
Short name T561
Test name
Test status
Simulation time 120702519 ps
CPU time 0.95 seconds
Started Mar 03 02:05:53 PM PST 24
Finished Mar 03 02:05:55 PM PST 24
Peak memory 205360 kb
Host smart-8df995af-6c6c-4ea1-b207-5df0ef9dc566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687738095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3687738095
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1598207347
Short name T841
Test name
Test status
Simulation time 6216269590 ps
CPU time 19.63 seconds
Started Mar 03 02:05:50 PM PST 24
Finished Mar 03 02:06:09 PM PST 24
Peak memory 240144 kb
Host smart-8dfed58d-a7fb-468c-b728-269e726a35ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598207347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1598207347
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3716686761
Short name T419
Test name
Test status
Simulation time 40747674 ps
CPU time 0.72 seconds
Started Mar 03 02:07:33 PM PST 24
Finished Mar 03 02:07:35 PM PST 24
Peak memory 205112 kb
Host smart-9b7d9e55-4d31-4942-9cae-81556e28f724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716686761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3716686761
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2272711042
Short name T754
Test name
Test status
Simulation time 8073461221 ps
CPU time 4.76 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:39 PM PST 24
Peak memory 224416 kb
Host smart-c2e85150-937e-4cce-8528-0e6b92bce843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272711042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2272711042
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4005514731
Short name T835
Test name
Test status
Simulation time 16179755 ps
CPU time 0.85 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:07:27 PM PST 24
Peak memory 206328 kb
Host smart-8503f208-e54f-40e5-b5ea-fb7e708ca274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005514731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4005514731
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1113543939
Short name T52
Test name
Test status
Simulation time 78989168439 ps
CPU time 105.69 seconds
Started Mar 03 02:07:32 PM PST 24
Finished Mar 03 02:09:18 PM PST 24
Peak memory 240852 kb
Host smart-4f07402f-48e2-4dd5-9469-1af19dec6eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113543939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1113543939
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2745288459
Short name T863
Test name
Test status
Simulation time 72917442069 ps
CPU time 35.19 seconds
Started Mar 03 02:07:33 PM PST 24
Finished Mar 03 02:08:09 PM PST 24
Peak memory 232792 kb
Host smart-f1543d71-45d5-43dd-8d61-9d6db0846781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745288459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2745288459
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.486262322
Short name T335
Test name
Test status
Simulation time 13029747076 ps
CPU time 86.06 seconds
Started Mar 03 02:07:32 PM PST 24
Finished Mar 03 02:08:58 PM PST 24
Peak memory 232732 kb
Host smart-7e6aea78-a532-4e59-b988-c27cb4e8e3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486262322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.486262322
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3174713744
Short name T954
Test name
Test status
Simulation time 295769667 ps
CPU time 7.6 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:42 PM PST 24
Peak memory 242280 kb
Host smart-b87bff35-5a3e-4009-8631-51bd0b026b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174713744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3174713744
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4079906028
Short name T202
Test name
Test status
Simulation time 1470079165 ps
CPU time 7.67 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:07:33 PM PST 24
Peak memory 219528 kb
Host smart-8d2e47df-4269-4927-bb0b-cc746369ed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079906028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4079906028
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1908567560
Short name T687
Test name
Test status
Simulation time 23147075440 ps
CPU time 16.44 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:07:43 PM PST 24
Peak memory 216880 kb
Host smart-25cb02bb-4479-45ca-a3d1-7c7dbcc9f60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908567560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1908567560
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1563521093
Short name T544
Test name
Test status
Simulation time 20648169314 ps
CPU time 16.16 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:07:41 PM PST 24
Peak memory 240176 kb
Host smart-ecd1c77c-e2f4-45a8-8ea0-ec02fa929cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563521093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1563521093
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.268657596
Short name T722
Test name
Test status
Simulation time 5421214956 ps
CPU time 9.95 seconds
Started Mar 03 02:07:26 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 224348 kb
Host smart-e1d7aeb5-7c39-4e46-8dd3-64f91e379ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268657596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.268657596
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3553563927
Short name T622
Test name
Test status
Simulation time 9590561386 ps
CPU time 6.8 seconds
Started Mar 03 02:07:32 PM PST 24
Finished Mar 03 02:07:39 PM PST 24
Peak memory 222860 kb
Host smart-7a64cfbd-a691-4e70-a661-8eb69cb56659
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3553563927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3553563927
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1977637105
Short name T857
Test name
Test status
Simulation time 58367958476 ps
CPU time 175.06 seconds
Started Mar 03 02:07:31 PM PST 24
Finished Mar 03 02:10:27 PM PST 24
Peak memory 273748 kb
Host smart-84a040b1-3890-4b7d-9677-8f899db3e927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977637105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1977637105
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3840127924
Short name T368
Test name
Test status
Simulation time 52643247539 ps
CPU time 69.34 seconds
Started Mar 03 02:07:28 PM PST 24
Finished Mar 03 02:08:37 PM PST 24
Peak memory 216264 kb
Host smart-bb393453-bc64-4e10-9ef9-4549bd92eaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840127924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3840127924
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3373585951
Short name T524
Test name
Test status
Simulation time 1668919044 ps
CPU time 2.09 seconds
Started Mar 03 02:07:27 PM PST 24
Finished Mar 03 02:07:30 PM PST 24
Peak memory 206528 kb
Host smart-c704c7a1-91f9-41f5-9412-5e83231284d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373585951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3373585951
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1432654297
Short name T296
Test name
Test status
Simulation time 93602080 ps
CPU time 5.61 seconds
Started Mar 03 02:07:23 PM PST 24
Finished Mar 03 02:07:29 PM PST 24
Peak memory 216372 kb
Host smart-df39c46f-294f-4640-81f9-599d29ac09a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432654297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1432654297
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3623457683
Short name T311
Test name
Test status
Simulation time 74629035 ps
CPU time 0.99 seconds
Started Mar 03 02:07:25 PM PST 24
Finished Mar 03 02:07:26 PM PST 24
Peak memory 205244 kb
Host smart-d78b3351-aedc-4815-b4b2-bc614cb3d8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623457683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3623457683
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2319031139
Short name T189
Test name
Test status
Simulation time 8036934313 ps
CPU time 24.59 seconds
Started Mar 03 02:07:27 PM PST 24
Finished Mar 03 02:07:52 PM PST 24
Peak memory 218200 kb
Host smart-c582af48-1aaf-46c0-8b7b-9ee65636cb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319031139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2319031139
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4013157183
Short name T884
Test name
Test status
Simulation time 12073802 ps
CPU time 0.73 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:35 PM PST 24
Peak memory 204304 kb
Host smart-e9cb8f8a-7167-4258-b6ac-6b093715fc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013157183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4013157183
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.503226657
Short name T329
Test name
Test status
Simulation time 788849159 ps
CPU time 2.93 seconds
Started Mar 03 02:07:32 PM PST 24
Finished Mar 03 02:07:35 PM PST 24
Peak memory 216528 kb
Host smart-e9921e85-15e3-4760-9812-26dbb75db5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503226657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.503226657
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3079159976
Short name T298
Test name
Test status
Simulation time 18720673 ps
CPU time 0.85 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:35 PM PST 24
Peak memory 206340 kb
Host smart-e62dfa27-cb32-4b4f-858a-cca45a3e4be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079159976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3079159976
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.295181259
Short name T629
Test name
Test status
Simulation time 29852789970 ps
CPU time 36.12 seconds
Started Mar 03 02:07:35 PM PST 24
Finished Mar 03 02:08:11 PM PST 24
Peak memory 250620 kb
Host smart-50077738-48a0-4bd0-94db-9b9442eaae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295181259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.295181259
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1862054741
Short name T720
Test name
Test status
Simulation time 216703051314 ps
CPU time 407.32 seconds
Started Mar 03 02:07:32 PM PST 24
Finished Mar 03 02:14:20 PM PST 24
Peak memory 249784 kb
Host smart-ab15d49c-9032-4222-a160-5b270ca5178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862054741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1862054741
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4194349406
Short name T193
Test name
Test status
Simulation time 23273646875 ps
CPU time 92.86 seconds
Started Mar 03 02:07:33 PM PST 24
Finished Mar 03 02:09:07 PM PST 24
Peak memory 257156 kb
Host smart-1842b472-b46b-4680-a3db-e52750e9bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194349406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4194349406
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3582416226
Short name T666
Test name
Test status
Simulation time 6670768820 ps
CPU time 17.53 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:52 PM PST 24
Peak memory 254996 kb
Host smart-0ece8c01-035d-43eb-9c89-8fb1091feba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582416226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3582416226
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3680965509
Short name T888
Test name
Test status
Simulation time 381243729 ps
CPU time 2.56 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 216324 kb
Host smart-b7715b12-c6eb-4578-add2-98d59e153f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680965509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3680965509
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1177047774
Short name T470
Test name
Test status
Simulation time 2095137833 ps
CPU time 9.61 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:44 PM PST 24
Peak memory 233872 kb
Host smart-1fb9c0bf-5b03-4fb2-8da4-8708e4e5976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177047774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1177047774
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3154707056
Short name T849
Test name
Test status
Simulation time 172317444 ps
CPU time 2.91 seconds
Started Mar 03 02:07:31 PM PST 24
Finished Mar 03 02:07:34 PM PST 24
Peak memory 234400 kb
Host smart-7af7f6ca-aa8f-4219-843c-f651dc6dd215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154707056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3154707056
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.799997186
Short name T899
Test name
Test status
Simulation time 1742087320 ps
CPU time 4.12 seconds
Started Mar 03 02:07:31 PM PST 24
Finished Mar 03 02:07:36 PM PST 24
Peak memory 232516 kb
Host smart-fd6e182a-0020-4987-96a8-be88a3a0117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799997186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.799997186
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1558789013
Short name T799
Test name
Test status
Simulation time 1114895036 ps
CPU time 4.06 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:38 PM PST 24
Peak memory 218984 kb
Host smart-db5dcec5-6cb8-4084-82f5-8f1bd3b2c336
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1558789013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1558789013
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2533513690
Short name T155
Test name
Test status
Simulation time 5757303044 ps
CPU time 94.02 seconds
Started Mar 03 02:07:31 PM PST 24
Finished Mar 03 02:09:06 PM PST 24
Peak memory 265464 kb
Host smart-219116b0-d0be-4866-880d-53437df3979b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533513690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2533513690
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.10170717
Short name T275
Test name
Test status
Simulation time 27181136849 ps
CPU time 43.82 seconds
Started Mar 03 02:07:32 PM PST 24
Finished Mar 03 02:08:16 PM PST 24
Peak memory 216324 kb
Host smart-82c245f0-14c1-40ab-bdae-b6b1465fd376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10170717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.10170717
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3373475202
Short name T305
Test name
Test status
Simulation time 863889412 ps
CPU time 1.87 seconds
Started Mar 03 02:07:35 PM PST 24
Finished Mar 03 02:07:37 PM PST 24
Peak memory 206736 kb
Host smart-84843d45-c6e8-4a96-8620-f27538583700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373475202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3373475202
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.524493468
Short name T33
Test name
Test status
Simulation time 247764925 ps
CPU time 2.36 seconds
Started Mar 03 02:07:32 PM PST 24
Finished Mar 03 02:07:35 PM PST 24
Peak memory 208344 kb
Host smart-6b3a9c49-548e-499a-86e8-fec55ed9e0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524493468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.524493468
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1614695507
Short name T762
Test name
Test status
Simulation time 69478454 ps
CPU time 0.96 seconds
Started Mar 03 02:07:31 PM PST 24
Finished Mar 03 02:07:33 PM PST 24
Peak memory 206384 kb
Host smart-fc2443ff-7e34-43f5-9d8f-c2fa449e951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614695507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1614695507
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3074218474
Short name T229
Test name
Test status
Simulation time 2301205534 ps
CPU time 6.01 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:40 PM PST 24
Peak memory 217232 kb
Host smart-e8c5312e-b48f-4eef-b3fd-bd3b6949ac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074218474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3074218474
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1083334433
Short name T686
Test name
Test status
Simulation time 35745680 ps
CPU time 0.74 seconds
Started Mar 03 02:07:39 PM PST 24
Finished Mar 03 02:07:40 PM PST 24
Peak memory 204292 kb
Host smart-c6d05731-9c2b-4209-84a8-19d7a87efa57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083334433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1083334433
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2862955665
Short name T971
Test name
Test status
Simulation time 360458507 ps
CPU time 3.31 seconds
Started Mar 03 02:07:44 PM PST 24
Finished Mar 03 02:07:47 PM PST 24
Peak memory 223964 kb
Host smart-7ee43cc8-c421-490e-b727-e5a4aef0f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862955665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2862955665
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3685721314
Short name T976
Test name
Test status
Simulation time 41109126 ps
CPU time 0.75 seconds
Started Mar 03 02:07:31 PM PST 24
Finished Mar 03 02:07:33 PM PST 24
Peak memory 205272 kb
Host smart-af191c83-8a6f-4085-a0fb-9a5b4b0658ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685721314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3685721314
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3713465962
Short name T372
Test name
Test status
Simulation time 112709859265 ps
CPU time 141.23 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:10:01 PM PST 24
Peak memory 252996 kb
Host smart-c6cfe84e-24e5-4589-ae4c-985303188262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713465962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3713465962
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4048336046
Short name T689
Test name
Test status
Simulation time 27101467933 ps
CPU time 183.14 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:10:45 PM PST 24
Peak memory 249620 kb
Host smart-97fb38b6-2eed-402c-9f4b-c488703b7004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048336046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4048336046
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2066147830
Short name T789
Test name
Test status
Simulation time 3833543352 ps
CPU time 57.81 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:08:40 PM PST 24
Peak memory 249184 kb
Host smart-3a5893f1-32ac-495d-9631-8fd7560daf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066147830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2066147830
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3392265342
Short name T506
Test name
Test status
Simulation time 9350983644 ps
CPU time 38.86 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:08:21 PM PST 24
Peak memory 251712 kb
Host smart-2a43419a-e89f-4de1-8ef8-2209c6b890a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392265342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3392265342
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1544081839
Short name T387
Test name
Test status
Simulation time 166068622 ps
CPU time 3.34 seconds
Started Mar 03 02:07:42 PM PST 24
Finished Mar 03 02:07:45 PM PST 24
Peak memory 233520 kb
Host smart-3db6d75c-548c-458e-a9c6-30670e45c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544081839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1544081839
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2678765116
Short name T209
Test name
Test status
Simulation time 84839231082 ps
CPU time 23.52 seconds
Started Mar 03 02:07:39 PM PST 24
Finished Mar 03 02:08:02 PM PST 24
Peak memory 233208 kb
Host smart-6a5c7d59-5dd2-490f-9f44-b4a595e8a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678765116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2678765116
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2556661407
Short name T210
Test name
Test status
Simulation time 1491357996 ps
CPU time 8.51 seconds
Started Mar 03 02:07:42 PM PST 24
Finished Mar 03 02:07:51 PM PST 24
Peak memory 232580 kb
Host smart-fae2c73d-44f7-4a66-82cd-afe745cfe0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556661407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2556661407
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1025227008
Short name T690
Test name
Test status
Simulation time 24658293774 ps
CPU time 15.49 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:07:55 PM PST 24
Peak memory 233272 kb
Host smart-a774a04b-1555-4468-a612-6e2abe5ff570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025227008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1025227008
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2738395458
Short name T578
Test name
Test status
Simulation time 308732464 ps
CPU time 2.96 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:07:43 PM PST 24
Peak memory 218356 kb
Host smart-2b30596a-e645-4dd3-8354-cc5603e7441b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2738395458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2738395458
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1302812148
Short name T475
Test name
Test status
Simulation time 129977688368 ps
CPU time 334.06 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:13:14 PM PST 24
Peak memory 261208 kb
Host smart-4847d6a3-0b36-4215-89c6-e5b241288bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302812148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1302812148
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3938999284
Short name T336
Test name
Test status
Simulation time 1858398978 ps
CPU time 2.55 seconds
Started Mar 03 02:07:42 PM PST 24
Finished Mar 03 02:07:45 PM PST 24
Peak memory 216260 kb
Host smart-3c911276-a43a-4d61-a5ed-6fed4509658f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938999284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3938999284
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1729589776
Short name T621
Test name
Test status
Simulation time 2781701836 ps
CPU time 4.77 seconds
Started Mar 03 02:07:34 PM PST 24
Finished Mar 03 02:07:39 PM PST 24
Peak memory 216256 kb
Host smart-a2b3eabd-65d7-4d87-8677-d39186186239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729589776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1729589776
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1606902984
Short name T965
Test name
Test status
Simulation time 294326478 ps
CPU time 1.76 seconds
Started Mar 03 02:07:39 PM PST 24
Finished Mar 03 02:07:41 PM PST 24
Peak memory 216280 kb
Host smart-2d3fbed4-16ee-4229-87f7-7cc6fb254f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606902984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1606902984
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1966926241
Short name T716
Test name
Test status
Simulation time 20130771 ps
CPU time 0.8 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:07:43 PM PST 24
Peak memory 205348 kb
Host smart-e0560d54-533c-4a17-b87c-23f1070762a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966926241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1966926241
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1286501887
Short name T66
Test name
Test status
Simulation time 39206853638 ps
CPU time 29.42 seconds
Started Mar 03 02:07:42 PM PST 24
Finished Mar 03 02:08:12 PM PST 24
Peak memory 240656 kb
Host smart-f616e55a-5926-42ed-af1b-a14d7e24d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286501887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1286501887
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3953147653
Short name T875
Test name
Test status
Simulation time 11794151 ps
CPU time 0.71 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:07:42 PM PST 24
Peak memory 204296 kb
Host smart-db9f629e-58c4-4fff-ab50-61bf01e74d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953147653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3953147653
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2882528995
Short name T247
Test name
Test status
Simulation time 5130826809 ps
CPU time 5.51 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:07:46 PM PST 24
Peak memory 233464 kb
Host smart-cf5ab5bb-fc3b-4e56-83b1-cb382b2cbfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882528995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2882528995
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2715613490
Short name T625
Test name
Test status
Simulation time 52889213 ps
CPU time 0.8 seconds
Started Mar 03 02:07:42 PM PST 24
Finished Mar 03 02:07:43 PM PST 24
Peak memory 205960 kb
Host smart-3a9f5544-ec99-4b2d-8642-ec699ae9f97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715613490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2715613490
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.774831366
Short name T212
Test name
Test status
Simulation time 10329337926 ps
CPU time 91.07 seconds
Started Mar 03 02:07:38 PM PST 24
Finished Mar 03 02:09:09 PM PST 24
Peak memory 255708 kb
Host smart-00641770-ce09-4edd-9a2c-ec4a64f09af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774831366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.774831366
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.725326877
Short name T194
Test name
Test status
Simulation time 28041953678 ps
CPU time 143.57 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:10:05 PM PST 24
Peak memory 249128 kb
Host smart-c98d21ee-ffc1-4466-9159-4b7e5d5a86fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725326877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.725326877
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2471946444
Short name T178
Test name
Test status
Simulation time 14936394145 ps
CPU time 134.06 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:09:55 PM PST 24
Peak memory 251988 kb
Host smart-aa59914b-0d51-4755-aba6-71c769b89c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471946444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2471946444
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2250419937
Short name T978
Test name
Test status
Simulation time 1968448033 ps
CPU time 4.41 seconds
Started Mar 03 02:07:38 PM PST 24
Finished Mar 03 02:07:42 PM PST 24
Peak memory 224308 kb
Host smart-251de84f-e686-402e-9c92-816ebd866cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250419937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2250419937
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.380962205
Short name T162
Test name
Test status
Simulation time 4490249712 ps
CPU time 13.83 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:07:56 PM PST 24
Peak memory 232652 kb
Host smart-7774a285-8f97-42fd-8ba0-d76406b5c507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380962205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.380962205
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3573486849
Short name T5
Test name
Test status
Simulation time 1314883985 ps
CPU time 4.83 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:07:47 PM PST 24
Peak memory 216176 kb
Host smart-d78f56ec-43eb-439b-8ea9-88b0b89c6458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573486849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3573486849
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4076796847
Short name T324
Test name
Test status
Simulation time 294256942 ps
CPU time 2.59 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:07:44 PM PST 24
Peak memory 232880 kb
Host smart-cadc3584-6ae7-4070-a0cb-7aadb3838644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076796847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4076796847
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4012748305
Short name T443
Test name
Test status
Simulation time 1201877688 ps
CPU time 3.88 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:07:46 PM PST 24
Peak memory 219632 kb
Host smart-1cf36d45-336e-4221-8514-0a9eae39d9c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4012748305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4012748305
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.567349610
Short name T581
Test name
Test status
Simulation time 2448564265 ps
CPU time 24.77 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:08:05 PM PST 24
Peak memory 240940 kb
Host smart-fddabfb6-7876-4244-ac19-4e8110453b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567349610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.567349610
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.763885079
Short name T862
Test name
Test status
Simulation time 15936084982 ps
CPU time 36.51 seconds
Started Mar 03 02:07:42 PM PST 24
Finished Mar 03 02:08:19 PM PST 24
Peak memory 216316 kb
Host smart-57cfcea5-44b6-436a-804c-874307076045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763885079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.763885079
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.986115593
Short name T477
Test name
Test status
Simulation time 450504481 ps
CPU time 1.07 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:07:41 PM PST 24
Peak memory 205480 kb
Host smart-1769681f-b7e7-4730-a0c1-d9dd3ab6b242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986115593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.986115593
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.190613926
Short name T322
Test name
Test status
Simulation time 213388788 ps
CPU time 3.82 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:07:44 PM PST 24
Peak memory 216256 kb
Host smart-2f6d0197-21a1-49c6-97b7-babf4238f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190613926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.190613926
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2334893503
Short name T740
Test name
Test status
Simulation time 28071588 ps
CPU time 0.77 seconds
Started Mar 03 02:07:38 PM PST 24
Finished Mar 03 02:07:39 PM PST 24
Peak memory 205376 kb
Host smart-3354b9b9-028f-48d3-a0ef-907e5d1e470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334893503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2334893503
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1075241739
Short name T230
Test name
Test status
Simulation time 933423361 ps
CPU time 3.21 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:07:45 PM PST 24
Peak memory 234068 kb
Host smart-6bf53da5-ee3c-4bdd-90a9-1477d7147bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075241739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1075241739
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1933905039
Short name T577
Test name
Test status
Simulation time 11896611 ps
CPU time 0.72 seconds
Started Mar 03 02:07:50 PM PST 24
Finished Mar 03 02:07:51 PM PST 24
Peak memory 204860 kb
Host smart-92dbadcd-03ef-4ca9-b353-e6a68a884168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933905039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1933905039
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2949737588
Short name T10
Test name
Test status
Simulation time 55286175 ps
CPU time 2.35 seconds
Started Mar 03 02:07:47 PM PST 24
Finished Mar 03 02:07:49 PM PST 24
Peak memory 216536 kb
Host smart-f3651ca4-fd0b-4fcc-9a98-7f6eacad7d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949737588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2949737588
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.288276004
Short name T715
Test name
Test status
Simulation time 40152082 ps
CPU time 0.81 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:07:42 PM PST 24
Peak memory 206000 kb
Host smart-03e62d68-4c78-4648-993f-9b1f63a7cb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288276004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.288276004
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2267423935
Short name T251
Test name
Test status
Simulation time 34082788763 ps
CPU time 80.86 seconds
Started Mar 03 02:07:52 PM PST 24
Finished Mar 03 02:09:13 PM PST 24
Peak memory 249052 kb
Host smart-1282136c-114c-4750-8550-62ccd9cce1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267423935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2267423935
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3301284522
Short name T427
Test name
Test status
Simulation time 10328644841 ps
CPU time 112.53 seconds
Started Mar 03 02:07:51 PM PST 24
Finished Mar 03 02:09:44 PM PST 24
Peak memory 267900 kb
Host smart-ff737414-bdfc-4b2b-9d36-206a2375db16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301284522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3301284522
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3961609365
Short name T551
Test name
Test status
Simulation time 18562685203 ps
CPU time 121 seconds
Started Mar 03 02:07:51 PM PST 24
Finished Mar 03 02:09:53 PM PST 24
Peak memory 233824 kb
Host smart-1722a7f0-63a1-460f-a27d-8890ba80cad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961609365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3961609365
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.878218110
Short name T392
Test name
Test status
Simulation time 8418562019 ps
CPU time 53.14 seconds
Started Mar 03 02:07:49 PM PST 24
Finished Mar 03 02:08:42 PM PST 24
Peak memory 238244 kb
Host smart-e7eea4ec-5ea9-46f6-b91a-20766e82ef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878218110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.878218110
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4200803770
Short name T225
Test name
Test status
Simulation time 11901712725 ps
CPU time 11.05 seconds
Started Mar 03 02:07:54 PM PST 24
Finished Mar 03 02:08:07 PM PST 24
Peak memory 233428 kb
Host smart-95c188e8-de40-44e4-b3af-4ca28b977471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200803770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4200803770
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3050507909
Short name T100
Test name
Test status
Simulation time 25414371070 ps
CPU time 19.77 seconds
Started Mar 03 02:07:55 PM PST 24
Finished Mar 03 02:08:17 PM PST 24
Peak memory 232180 kb
Host smart-e2c63d8f-ed55-4ec8-bed0-4d1e6a7fee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050507909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3050507909
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1735169921
Short name T416
Test name
Test status
Simulation time 9898714756 ps
CPU time 7.37 seconds
Started Mar 03 02:07:54 PM PST 24
Finished Mar 03 02:08:03 PM PST 24
Peak memory 235792 kb
Host smart-cc3b43de-5e11-4f82-9754-252391dda5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735169921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1735169921
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2157311271
Short name T711
Test name
Test status
Simulation time 186793103 ps
CPU time 3.08 seconds
Started Mar 03 02:07:48 PM PST 24
Finished Mar 03 02:07:51 PM PST 24
Peak memory 233124 kb
Host smart-104cc6ab-684b-4834-b0ce-8ea65091f309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157311271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2157311271
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2107819093
Short name T701
Test name
Test status
Simulation time 1285185963 ps
CPU time 4.03 seconds
Started Mar 03 02:07:48 PM PST 24
Finished Mar 03 02:07:52 PM PST 24
Peak memory 220172 kb
Host smart-0262e84f-12f5-49b5-90f2-8167d911e267
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2107819093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2107819093
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1799922652
Short name T644
Test name
Test status
Simulation time 29908666526 ps
CPU time 116.47 seconds
Started Mar 03 02:07:51 PM PST 24
Finished Mar 03 02:09:48 PM PST 24
Peak memory 257372 kb
Host smart-4a24d61b-8f7b-4e5d-bcdb-89f1d0470d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799922652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1799922652
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3358673857
Short name T29
Test name
Test status
Simulation time 39323705261 ps
CPU time 44.88 seconds
Started Mar 03 02:07:41 PM PST 24
Finished Mar 03 02:08:27 PM PST 24
Peak memory 216272 kb
Host smart-72becb06-43c4-45d9-a833-fb84e4c45536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358673857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3358673857
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2344066617
Short name T316
Test name
Test status
Simulation time 11686532584 ps
CPU time 16.7 seconds
Started Mar 03 02:07:40 PM PST 24
Finished Mar 03 02:07:57 PM PST 24
Peak memory 216308 kb
Host smart-4433adca-d199-4858-a01c-94ba0f000ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344066617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2344066617
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2929657145
Short name T439
Test name
Test status
Simulation time 92241051 ps
CPU time 2.77 seconds
Started Mar 03 02:07:44 PM PST 24
Finished Mar 03 02:07:47 PM PST 24
Peak memory 215756 kb
Host smart-e3ab1f06-4736-4bdb-86a0-33e2c6829a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929657145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2929657145
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.784555320
Short name T861
Test name
Test status
Simulation time 190059531 ps
CPU time 0.98 seconds
Started Mar 03 02:07:38 PM PST 24
Finished Mar 03 02:07:39 PM PST 24
Peak memory 206396 kb
Host smart-b2cee5e3-27ac-450a-a24f-4aa7c95b1ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784555320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.784555320
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1545319427
Short name T613
Test name
Test status
Simulation time 3018617498 ps
CPU time 8.26 seconds
Started Mar 03 02:07:47 PM PST 24
Finished Mar 03 02:07:55 PM PST 24
Peak memory 239644 kb
Host smart-381f9c4a-af5d-4d66-8691-7b0fa102ba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545319427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1545319427
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2958211646
Short name T498
Test name
Test status
Simulation time 155554029 ps
CPU time 0.72 seconds
Started Mar 03 02:07:47 PM PST 24
Finished Mar 03 02:07:48 PM PST 24
Peak memory 204280 kb
Host smart-b0caaab1-529a-43ff-96af-ec5e4bb14e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958211646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2958211646
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2312463287
Short name T637
Test name
Test status
Simulation time 6262901259 ps
CPU time 6.46 seconds
Started Mar 03 02:07:47 PM PST 24
Finished Mar 03 02:07:54 PM PST 24
Peak memory 224284 kb
Host smart-65aa1306-cd68-4ce8-b04b-bd7d00e4f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312463287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2312463287
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2892517327
Short name T2
Test name
Test status
Simulation time 45688473 ps
CPU time 0.8 seconds
Started Mar 03 02:07:49 PM PST 24
Finished Mar 03 02:07:50 PM PST 24
Peak memory 205976 kb
Host smart-1109c858-cdfc-4dad-bae5-9e2b9db11ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892517327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2892517327
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.802332660
Short name T599
Test name
Test status
Simulation time 12323265481 ps
CPU time 48.82 seconds
Started Mar 03 02:07:46 PM PST 24
Finished Mar 03 02:08:35 PM PST 24
Peak memory 240820 kb
Host smart-b2d8d596-8c67-4511-8cd1-068d01e2bb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802332660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.802332660
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3778881392
Short name T739
Test name
Test status
Simulation time 30903924104 ps
CPU time 104.32 seconds
Started Mar 03 02:07:54 PM PST 24
Finished Mar 03 02:09:39 PM PST 24
Peak memory 257368 kb
Host smart-ce3ae1e4-ec7a-40e2-a6ef-41219887e440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778881392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3778881392
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4089997295
Short name T927
Test name
Test status
Simulation time 53853009576 ps
CPU time 150.24 seconds
Started Mar 03 02:07:46 PM PST 24
Finished Mar 03 02:10:16 PM PST 24
Peak memory 249340 kb
Host smart-ea5fe406-8805-4950-bc78-c803f312d388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089997295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4089997295
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.174317908
Short name T503
Test name
Test status
Simulation time 30813915430 ps
CPU time 41.27 seconds
Started Mar 03 02:07:47 PM PST 24
Finished Mar 03 02:08:28 PM PST 24
Peak memory 240804 kb
Host smart-ac4a81b6-f280-47a2-ac64-38b6b05cac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174317908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.174317908
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4209440438
Short name T459
Test name
Test status
Simulation time 18628541431 ps
CPU time 13.2 seconds
Started Mar 03 02:07:50 PM PST 24
Finished Mar 03 02:08:04 PM PST 24
Peak memory 233120 kb
Host smart-75789037-bd03-4db2-970c-b8dfae2af3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209440438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4209440438
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3064861062
Short name T139
Test name
Test status
Simulation time 1331020634 ps
CPU time 5.06 seconds
Started Mar 03 02:07:51 PM PST 24
Finished Mar 03 02:07:56 PM PST 24
Peak memory 222624 kb
Host smart-02b7d403-2369-4832-862b-3cc2db275756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064861062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3064861062
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3137661058
Short name T413
Test name
Test status
Simulation time 1729366353 ps
CPU time 3.55 seconds
Started Mar 03 02:07:47 PM PST 24
Finished Mar 03 02:07:51 PM PST 24
Peak memory 233476 kb
Host smart-9087b908-695f-4a70-a491-4478054b6587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137661058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3137661058
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2934463192
Short name T101
Test name
Test status
Simulation time 3165964768 ps
CPU time 7.01 seconds
Started Mar 03 02:07:55 PM PST 24
Finished Mar 03 02:08:04 PM PST 24
Peak memory 217784 kb
Host smart-dbb481b0-300a-42d0-80d7-9632dca182f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934463192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2934463192
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3952169585
Short name T919
Test name
Test status
Simulation time 158517541 ps
CPU time 4.02 seconds
Started Mar 03 02:07:54 PM PST 24
Finished Mar 03 02:07:59 PM PST 24
Peak memory 222664 kb
Host smart-22ed1879-ad49-4e46-83b3-c9afdad1b852
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3952169585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3952169585
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.763738246
Short name T748
Test name
Test status
Simulation time 344758927 ps
CPU time 0.92 seconds
Started Mar 03 02:07:49 PM PST 24
Finished Mar 03 02:07:50 PM PST 24
Peak memory 205312 kb
Host smart-673d767e-ebc1-44d0-a2e6-d97eaa074537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763738246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.763738246
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1910650452
Short name T537
Test name
Test status
Simulation time 8397449037 ps
CPU time 14.73 seconds
Started Mar 03 02:07:53 PM PST 24
Finished Mar 03 02:08:09 PM PST 24
Peak memory 216308 kb
Host smart-e13e1e47-4211-4f5d-82fc-c85a9e139ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910650452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1910650452
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.827701206
Short name T851
Test name
Test status
Simulation time 31291686261 ps
CPU time 22.54 seconds
Started Mar 03 02:07:53 PM PST 24
Finished Mar 03 02:08:16 PM PST 24
Peak memory 216300 kb
Host smart-adb37f11-0bdb-4103-a39c-2ba8599a2dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827701206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.827701206
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2481088092
Short name T331
Test name
Test status
Simulation time 500866834 ps
CPU time 8.14 seconds
Started Mar 03 02:07:49 PM PST 24
Finished Mar 03 02:07:58 PM PST 24
Peak memory 216584 kb
Host smart-1db88168-6ca9-4658-a015-40a87b0ff991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481088092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2481088092
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2341709091
Short name T4
Test name
Test status
Simulation time 80831075 ps
CPU time 0.93 seconds
Started Mar 03 02:07:45 PM PST 24
Finished Mar 03 02:07:46 PM PST 24
Peak memory 205248 kb
Host smart-7d0f49cf-64d4-45b4-b93e-019b8366b32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341709091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2341709091
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1192948198
Short name T86
Test name
Test status
Simulation time 4616376854 ps
CPU time 22.78 seconds
Started Mar 03 02:07:49 PM PST 24
Finished Mar 03 02:08:12 PM PST 24
Peak memory 230520 kb
Host smart-70524786-172c-42f9-9ca5-eb98a374bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192948198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1192948198
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.114931206
Short name T441
Test name
Test status
Simulation time 13053670 ps
CPU time 0.79 seconds
Started Mar 03 02:07:58 PM PST 24
Finished Mar 03 02:07:59 PM PST 24
Peak memory 204860 kb
Host smart-b4b54477-b691-434e-b77a-2baaf421f5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114931206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.114931206
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1201602146
Short name T773
Test name
Test status
Simulation time 8600972538 ps
CPU time 3.78 seconds
Started Mar 03 02:07:49 PM PST 24
Finished Mar 03 02:07:53 PM PST 24
Peak memory 224432 kb
Host smart-2350f270-3e0c-4e59-9a45-c2c49a5f0893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201602146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1201602146
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3249931775
Short name T839
Test name
Test status
Simulation time 47471360 ps
CPU time 0.8 seconds
Started Mar 03 02:07:48 PM PST 24
Finished Mar 03 02:07:49 PM PST 24
Peak memory 206016 kb
Host smart-9c2f370e-c9cd-4187-9a26-fd182e2e9a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249931775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3249931775
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2962237000
Short name T652
Test name
Test status
Simulation time 93081409376 ps
CPU time 308.52 seconds
Started Mar 03 02:07:56 PM PST 24
Finished Mar 03 02:13:06 PM PST 24
Peak memory 261480 kb
Host smart-0a9f3360-49ee-4fe4-ba02-a57b5c85da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962237000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2962237000
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3929759173
Short name T39
Test name
Test status
Simulation time 77874100039 ps
CPU time 203.33 seconds
Started Mar 03 02:07:56 PM PST 24
Finished Mar 03 02:11:21 PM PST 24
Peak memory 257308 kb
Host smart-44b7dc71-44a2-4e8f-b574-e526dbf79a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929759173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3929759173
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2580656116
Short name T363
Test name
Test status
Simulation time 2018104442 ps
CPU time 12.28 seconds
Started Mar 03 02:07:57 PM PST 24
Finished Mar 03 02:08:10 PM PST 24
Peak memory 238804 kb
Host smart-887158ea-ef5d-497a-8005-60422479a804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580656116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2580656116
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2861529672
Short name T787
Test name
Test status
Simulation time 15047410021 ps
CPU time 8.65 seconds
Started Mar 03 02:07:54 PM PST 24
Finished Mar 03 02:08:04 PM PST 24
Peak memory 221344 kb
Host smart-2275ad44-6a93-4e3a-a1c8-b6f7a2000bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861529672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2861529672
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3814878415
Short name T765
Test name
Test status
Simulation time 745289474 ps
CPU time 3.05 seconds
Started Mar 03 02:07:54 PM PST 24
Finished Mar 03 02:07:59 PM PST 24
Peak memory 224308 kb
Host smart-73f2658e-6e85-49db-bc55-b493833c0f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814878415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3814878415
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1726011670
Short name T199
Test name
Test status
Simulation time 6453409251 ps
CPU time 17.64 seconds
Started Mar 03 02:07:49 PM PST 24
Finished Mar 03 02:08:07 PM PST 24
Peak memory 233044 kb
Host smart-805fab59-af92-4762-a175-431b9119b19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726011670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1726011670
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3104858364
Short name T858
Test name
Test status
Simulation time 736616185 ps
CPU time 3.55 seconds
Started Mar 03 02:07:46 PM PST 24
Finished Mar 03 02:07:50 PM PST 24
Peak memory 218608 kb
Host smart-3f110947-6cdb-4fb1-a41d-93d1285710ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104858364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3104858364
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3362722149
Short name T737
Test name
Test status
Simulation time 1169550402 ps
CPU time 5.35 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:04 PM PST 24
Peak memory 222452 kb
Host smart-ba8fb0bd-264c-4281-8330-053944c45548
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3362722149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3362722149
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2871501982
Short name T562
Test name
Test status
Simulation time 2303105091 ps
CPU time 53.94 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:53 PM PST 24
Peak memory 237628 kb
Host smart-9b00075b-e263-4f32-a934-e4b86b64d46e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871501982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2871501982
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2692797501
Short name T749
Test name
Test status
Simulation time 9498480039 ps
CPU time 39.66 seconds
Started Mar 03 02:07:48 PM PST 24
Finished Mar 03 02:08:28 PM PST 24
Peak memory 216244 kb
Host smart-c49d3a52-5a81-4457-a5bc-56a1720e1487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692797501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2692797501
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3416374164
Short name T764
Test name
Test status
Simulation time 398823656 ps
CPU time 2.48 seconds
Started Mar 03 02:07:49 PM PST 24
Finished Mar 03 02:07:52 PM PST 24
Peak memory 208048 kb
Host smart-0ad10f52-98df-4655-b36e-3670d7ac4bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416374164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3416374164
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3553307552
Short name T963
Test name
Test status
Simulation time 94248108 ps
CPU time 1.5 seconds
Started Mar 03 02:07:54 PM PST 24
Finished Mar 03 02:07:57 PM PST 24
Peak memory 207900 kb
Host smart-34c4bd83-d344-4488-a1b8-77714608b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553307552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3553307552
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1033146714
Short name T8
Test name
Test status
Simulation time 51356647 ps
CPU time 0.98 seconds
Started Mar 03 02:07:48 PM PST 24
Finished Mar 03 02:07:50 PM PST 24
Peak memory 206384 kb
Host smart-bc97a661-6bde-4c39-abc6-a8dd6550796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033146714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1033146714
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3503870404
Short name T726
Test name
Test status
Simulation time 589258732 ps
CPU time 4.61 seconds
Started Mar 03 02:07:53 PM PST 24
Finished Mar 03 02:07:58 PM PST 24
Peak memory 217180 kb
Host smart-a14cee19-cbfc-4e0f-9584-6016ab8c719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503870404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3503870404
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.254308487
Short name T816
Test name
Test status
Simulation time 16320718 ps
CPU time 0.73 seconds
Started Mar 03 02:07:53 PM PST 24
Finished Mar 03 02:07:54 PM PST 24
Peak memory 204868 kb
Host smart-6c6b28cc-d160-4107-8ff8-8dbca07555f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254308487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.254308487
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2772518187
Short name T349
Test name
Test status
Simulation time 627369387 ps
CPU time 3.52 seconds
Started Mar 03 02:07:56 PM PST 24
Finished Mar 03 02:08:01 PM PST 24
Peak memory 236636 kb
Host smart-86094ee4-5c0e-49be-b394-ac8871f7c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772518187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2772518187
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2413092377
Short name T636
Test name
Test status
Simulation time 67685026 ps
CPU time 0.76 seconds
Started Mar 03 02:07:56 PM PST 24
Finished Mar 03 02:07:58 PM PST 24
Peak memory 204976 kb
Host smart-cd948f53-4f43-4154-8f4a-dac31b90200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413092377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2413092377
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2992938486
Short name T728
Test name
Test status
Simulation time 39744319455 ps
CPU time 204.28 seconds
Started Mar 03 02:07:56 PM PST 24
Finished Mar 03 02:11:22 PM PST 24
Peak memory 272192 kb
Host smart-d3283dba-3a1d-4aee-9019-ba61a5db75a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992938486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2992938486
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1749256224
Short name T398
Test name
Test status
Simulation time 14349102029 ps
CPU time 29.98 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:29 PM PST 24
Peak memory 232784 kb
Host smart-851d1cfd-aed9-48e7-84b3-3ed7cef8a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749256224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1749256224
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2083001266
Short name T206
Test name
Test status
Simulation time 623838803 ps
CPU time 6.59 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:06 PM PST 24
Peak memory 233116 kb
Host smart-89d27844-4645-4259-bfc3-5463a20f61c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083001266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2083001266
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3007330707
Short name T842
Test name
Test status
Simulation time 4086210655 ps
CPU time 13.16 seconds
Started Mar 03 02:07:57 PM PST 24
Finished Mar 03 02:08:11 PM PST 24
Peak memory 224444 kb
Host smart-b610bc53-46b8-4c22-8307-7087b3b5b805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007330707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3007330707
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3737552469
Short name T216
Test name
Test status
Simulation time 22993117308 ps
CPU time 32.98 seconds
Started Mar 03 02:07:57 PM PST 24
Finished Mar 03 02:08:30 PM PST 24
Peak memory 236032 kb
Host smart-56d7674b-5fc2-4593-9114-95c4366fba31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737552469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3737552469
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3337959684
Short name T46
Test name
Test status
Simulation time 336488127 ps
CPU time 2.27 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:01 PM PST 24
Peak memory 216812 kb
Host smart-369a55e9-bbd7-45dc-b2da-4c1b24a256b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337959684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3337959684
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2661694355
Short name T611
Test name
Test status
Simulation time 36002755756 ps
CPU time 45.64 seconds
Started Mar 03 02:07:58 PM PST 24
Finished Mar 03 02:08:44 PM PST 24
Peak memory 233544 kb
Host smart-8e99db63-2044-43ce-8326-e9fcfb0555d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661694355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2661694355
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4104807443
Short name T663
Test name
Test status
Simulation time 79725385 ps
CPU time 3.8 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:03 PM PST 24
Peak memory 222476 kb
Host smart-62afc1c6-51b4-4550-bf9d-dea263b514c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4104807443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4104807443
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4153963724
Short name T797
Test name
Test status
Simulation time 36580392 ps
CPU time 0.98 seconds
Started Mar 03 02:07:58 PM PST 24
Finished Mar 03 02:07:59 PM PST 24
Peak memory 206420 kb
Host smart-742d0697-c7a9-44b6-9698-9e99c0fdee3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153963724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4153963724
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1976304320
Short name T812
Test name
Test status
Simulation time 6669648136 ps
CPU time 21.78 seconds
Started Mar 03 02:07:57 PM PST 24
Finished Mar 03 02:08:19 PM PST 24
Peak memory 216336 kb
Host smart-0d891ca6-1973-44a0-b180-1b10436f9252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976304320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1976304320
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.612631713
Short name T456
Test name
Test status
Simulation time 17980172542 ps
CPU time 12.08 seconds
Started Mar 03 02:08:01 PM PST 24
Finished Mar 03 02:08:13 PM PST 24
Peak memory 216232 kb
Host smart-7b27b3f1-f506-442a-b00f-6bfce91d3a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612631713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.612631713
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1190943991
Short name T750
Test name
Test status
Simulation time 82819606 ps
CPU time 0.82 seconds
Started Mar 03 02:07:56 PM PST 24
Finished Mar 03 02:07:58 PM PST 24
Peak memory 205980 kb
Host smart-a875fbda-1fdc-4df8-a214-03bc480759e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190943991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1190943991
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.612382292
Short name T292
Test name
Test status
Simulation time 169718111 ps
CPU time 1.01 seconds
Started Mar 03 02:07:56 PM PST 24
Finished Mar 03 02:07:58 PM PST 24
Peak memory 206392 kb
Host smart-194fa99c-7610-445d-8fa8-9ad5fd3d533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612382292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.612382292
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3572420282
Short name T242
Test name
Test status
Simulation time 5136746000 ps
CPU time 16.78 seconds
Started Mar 03 02:07:58 PM PST 24
Finished Mar 03 02:08:15 PM PST 24
Peak memory 217756 kb
Host smart-a7fac70a-d9ea-46cc-a247-4ea1a10f9bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572420282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3572420282
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.981849742
Short name T783
Test name
Test status
Simulation time 18192233 ps
CPU time 0.68 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:00 PM PST 24
Peak memory 204252 kb
Host smart-8bbb8ecf-1cc3-40fc-949b-e0666f419b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981849742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.981849742
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1410197388
Short name T245
Test name
Test status
Simulation time 1632162331 ps
CPU time 5.85 seconds
Started Mar 03 02:08:00 PM PST 24
Finished Mar 03 02:08:06 PM PST 24
Peak memory 224360 kb
Host smart-136f35d3-f8be-44dd-a2c1-90815e577c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410197388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1410197388
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3227656533
Short name T291
Test name
Test status
Simulation time 15963252 ps
CPU time 0.79 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:00 PM PST 24
Peak memory 204960 kb
Host smart-45cb0464-081f-4870-b508-cc3f4250ddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227656533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3227656533
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2103034207
Short name T270
Test name
Test status
Simulation time 52420377614 ps
CPU time 250.36 seconds
Started Mar 03 02:08:01 PM PST 24
Finished Mar 03 02:12:12 PM PST 24
Peak memory 257136 kb
Host smart-e904f34a-1d6c-43e6-8519-f0dc80506325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103034207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2103034207
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.965917809
Short name T555
Test name
Test status
Simulation time 129653785644 ps
CPU time 265.71 seconds
Started Mar 03 02:08:00 PM PST 24
Finished Mar 03 02:12:26 PM PST 24
Peak memory 256376 kb
Host smart-e545ee83-1f95-4f16-b800-adaa5e7d40a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965917809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.965917809
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1877624267
Short name T423
Test name
Test status
Simulation time 15603680376 ps
CPU time 60.01 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:59 PM PST 24
Peak memory 236144 kb
Host smart-437905d6-bf77-4a9d-920b-a7ad39d1f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877624267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1877624267
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1400882015
Short name T869
Test name
Test status
Simulation time 25491039168 ps
CPU time 29.67 seconds
Started Mar 03 02:08:01 PM PST 24
Finished Mar 03 02:08:31 PM PST 24
Peak memory 240600 kb
Host smart-522d5d8e-543a-441c-a869-16c1cb71263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400882015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1400882015
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1225903928
Short name T955
Test name
Test status
Simulation time 4176384596 ps
CPU time 4.02 seconds
Started Mar 03 02:08:02 PM PST 24
Finished Mar 03 02:08:06 PM PST 24
Peak memory 224440 kb
Host smart-46315e89-8b2d-47dd-8ed9-6505485c8806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225903928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1225903928
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2636851070
Short name T84
Test name
Test status
Simulation time 2103204010 ps
CPU time 10.14 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:10 PM PST 24
Peak memory 232468 kb
Host smart-beb55585-7d4b-4505-953a-e242441ddae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636851070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2636851070
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1628770395
Short name T601
Test name
Test status
Simulation time 5313222983 ps
CPU time 14.12 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 233412 kb
Host smart-13d07373-1fbc-4971-89f0-d2204a92a3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628770395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1628770395
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2238705105
Short name T483
Test name
Test status
Simulation time 5942904896 ps
CPU time 13.21 seconds
Started Mar 03 02:08:00 PM PST 24
Finished Mar 03 02:08:14 PM PST 24
Peak memory 237436 kb
Host smart-c1d0cf6c-160f-49fe-8bbf-288b2057835b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238705105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2238705105
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2878864861
Short name T573
Test name
Test status
Simulation time 777113502 ps
CPU time 4.38 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:04 PM PST 24
Peak memory 221916 kb
Host smart-eeb02c72-07ba-40bb-b1b8-5a48c2fdb615
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2878864861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2878864861
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.973454951
Short name T97
Test name
Test status
Simulation time 24780194807 ps
CPU time 269.21 seconds
Started Mar 03 02:08:04 PM PST 24
Finished Mar 03 02:12:34 PM PST 24
Peak memory 273732 kb
Host smart-bb0cc29d-8ed9-4589-87ab-dc69c0f5fc26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973454951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.973454951
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1077668388
Short name T332
Test name
Test status
Simulation time 1529602977 ps
CPU time 5.52 seconds
Started Mar 03 02:07:59 PM PST 24
Finished Mar 03 02:08:05 PM PST 24
Peak memory 216236 kb
Host smart-647c410b-fbd4-46ca-9e64-6b0f719352df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077668388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1077668388
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3928921213
Short name T463
Test name
Test status
Simulation time 6849787423 ps
CPU time 23.31 seconds
Started Mar 03 02:07:58 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 216324 kb
Host smart-e2c244b4-147e-4ad9-ab43-2378e0f017ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928921213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3928921213
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.792045040
Short name T310
Test name
Test status
Simulation time 175314225 ps
CPU time 6.41 seconds
Started Mar 03 02:08:00 PM PST 24
Finished Mar 03 02:08:07 PM PST 24
Peak memory 216476 kb
Host smart-c3cb854b-b42d-40e1-b1bd-adb67d3be71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792045040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.792045040
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.847344166
Short name T814
Test name
Test status
Simulation time 247007163 ps
CPU time 0.96 seconds
Started Mar 03 02:08:01 PM PST 24
Finished Mar 03 02:08:02 PM PST 24
Peak memory 205372 kb
Host smart-a3375c04-3f0f-4927-9c27-451f92b8f1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847344166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.847344166
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3963894455
Short name T844
Test name
Test status
Simulation time 28574892681 ps
CPU time 20.32 seconds
Started Mar 03 02:08:06 PM PST 24
Finished Mar 03 02:08:26 PM PST 24
Peak memory 234844 kb
Host smart-ceca08bc-ca2b-4b1d-9575-ef893a391dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963894455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3963894455
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4284001190
Short name T466
Test name
Test status
Simulation time 22742959 ps
CPU time 0.74 seconds
Started Mar 03 02:08:09 PM PST 24
Finished Mar 03 02:08:09 PM PST 24
Peak memory 204228 kb
Host smart-93923f1b-f0b2-4a49-9997-8561cb24f285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284001190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4284001190
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1998278394
Short name T859
Test name
Test status
Simulation time 1504751667 ps
CPU time 2.97 seconds
Started Mar 03 02:08:03 PM PST 24
Finished Mar 03 02:08:06 PM PST 24
Peak memory 233996 kb
Host smart-606a7724-b4d3-4fa7-b9fa-740da4aa3d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998278394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1998278394
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4104819717
Short name T825
Test name
Test status
Simulation time 16032211 ps
CPU time 0.81 seconds
Started Mar 03 02:08:04 PM PST 24
Finished Mar 03 02:08:06 PM PST 24
Peak memory 204968 kb
Host smart-38b1d35a-d2aa-4156-a7c8-b6934c1207af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104819717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4104819717
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1382532048
Short name T442
Test name
Test status
Simulation time 10622324080 ps
CPU time 59.74 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:09:07 PM PST 24
Peak memory 248864 kb
Host smart-99a15b6e-fcef-4958-9acf-43c18b566122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382532048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1382532048
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1612567717
Short name T607
Test name
Test status
Simulation time 3825633883 ps
CPU time 23.65 seconds
Started Mar 03 02:08:05 PM PST 24
Finished Mar 03 02:08:29 PM PST 24
Peak memory 233832 kb
Host smart-8ded7667-13fb-46fa-96f4-ceefc5302c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612567717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1612567717
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4201510823
Short name T572
Test name
Test status
Simulation time 1471731682 ps
CPU time 14.86 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:08:23 PM PST 24
Peak memory 241968 kb
Host smart-11eb660e-b567-4d4b-9b42-a2c65276441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201510823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4201510823
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.221075887
Short name T639
Test name
Test status
Simulation time 687435555 ps
CPU time 4.53 seconds
Started Mar 03 02:08:01 PM PST 24
Finished Mar 03 02:08:05 PM PST 24
Peak memory 224316 kb
Host smart-5968c7b9-6b9e-4359-9500-b78d88b79602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221075887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.221075887
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2794420633
Short name T204
Test name
Test status
Simulation time 20711113861 ps
CPU time 20.22 seconds
Started Mar 03 02:08:01 PM PST 24
Finished Mar 03 02:08:21 PM PST 24
Peak memory 240572 kb
Host smart-06093998-2b0c-45f2-9907-e7e80faceaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794420633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2794420633
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1955635674
Short name T794
Test name
Test status
Simulation time 1182541198 ps
CPU time 7.78 seconds
Started Mar 03 02:08:01 PM PST 24
Finished Mar 03 02:08:09 PM PST 24
Peak memory 234080 kb
Host smart-20fbe9d5-83d7-49b0-975f-ebbf1d157bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955635674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1955635674
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2231546334
Short name T845
Test name
Test status
Simulation time 2721910925 ps
CPU time 4.8 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:08:12 PM PST 24
Peak memory 224420 kb
Host smart-8025ce27-dc48-40e1-b6b1-cefa67ed740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231546334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2231546334
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1185662927
Short name T575
Test name
Test status
Simulation time 522656613 ps
CPU time 3.95 seconds
Started Mar 03 02:08:09 PM PST 24
Finished Mar 03 02:08:13 PM PST 24
Peak memory 218192 kb
Host smart-b3db7cbf-0cff-479d-b31b-f0ce971aee6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1185662927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1185662927
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3249501581
Short name T445
Test name
Test status
Simulation time 4188157912 ps
CPU time 19.46 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:08:26 PM PST 24
Peak memory 216280 kb
Host smart-4bb21a16-eb28-488f-91f3-15e431b34bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249501581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3249501581
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3239160763
Short name T281
Test name
Test status
Simulation time 721015632 ps
CPU time 4.72 seconds
Started Mar 03 02:08:00 PM PST 24
Finished Mar 03 02:08:05 PM PST 24
Peak memory 208008 kb
Host smart-66ffba5f-8ed1-4aaf-860c-ca2cf8a2bdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239160763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3239160763
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1763104273
Short name T525
Test name
Test status
Simulation time 370596751 ps
CPU time 4.44 seconds
Started Mar 03 02:08:01 PM PST 24
Finished Mar 03 02:08:05 PM PST 24
Peak memory 216364 kb
Host smart-74f878a1-162d-4f23-b670-2b50b7969fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763104273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1763104273
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1602649007
Short name T670
Test name
Test status
Simulation time 96700273 ps
CPU time 1.06 seconds
Started Mar 03 02:08:03 PM PST 24
Finished Mar 03 02:08:04 PM PST 24
Peak memory 205356 kb
Host smart-ccce8271-2d1e-4e82-8ab6-f6766b6a7cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602649007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1602649007
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.366516050
Short name T900
Test name
Test status
Simulation time 1433093802 ps
CPU time 10.42 seconds
Started Mar 03 02:08:03 PM PST 24
Finished Mar 03 02:08:13 PM PST 24
Peak memory 246748 kb
Host smart-99605642-a390-4baf-9d8e-609bbe469c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366516050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.366516050
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2708585868
Short name T734
Test name
Test status
Simulation time 10843812 ps
CPU time 0.7 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:00 PM PST 24
Peak memory 205132 kb
Host smart-eed5548a-ea7d-4c93-a26a-182e8656901e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708585868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
708585868
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4053366442
Short name T504
Test name
Test status
Simulation time 597398845 ps
CPU time 2.58 seconds
Started Mar 03 02:06:03 PM PST 24
Finished Mar 03 02:06:05 PM PST 24
Peak memory 223972 kb
Host smart-bfca5235-4099-4238-bb7c-7f27253760b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053366442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4053366442
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3193562731
Short name T494
Test name
Test status
Simulation time 40550670 ps
CPU time 0.81 seconds
Started Mar 03 02:05:51 PM PST 24
Finished Mar 03 02:05:52 PM PST 24
Peak memory 206308 kb
Host smart-10077fd3-7c0a-449a-8da0-cb64671f0929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193562731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3193562731
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2442043719
Short name T391
Test name
Test status
Simulation time 820140696 ps
CPU time 14.86 seconds
Started Mar 03 02:05:56 PM PST 24
Finished Mar 03 02:06:11 PM PST 24
Peak memory 248416 kb
Host smart-5ca03068-7290-45d0-9ff9-6adcb2936cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442043719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2442043719
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.489715269
Short name T40
Test name
Test status
Simulation time 1235725636827 ps
CPU time 410.26 seconds
Started Mar 03 02:05:53 PM PST 24
Finished Mar 03 02:12:43 PM PST 24
Peak memory 256944 kb
Host smart-03fa3f44-253d-4154-81e9-8781e59b2204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489715269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.489715269
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2040151716
Short name T436
Test name
Test status
Simulation time 1234696417 ps
CPU time 9.37 seconds
Started Mar 03 02:06:05 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 254628 kb
Host smart-da28de9e-a8ae-4a21-872d-6eec614ebaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040151716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2040151716
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.177489245
Short name T218
Test name
Test status
Simulation time 1802780912 ps
CPU time 3.77 seconds
Started Mar 03 02:06:05 PM PST 24
Finished Mar 03 02:06:09 PM PST 24
Peak memory 218452 kb
Host smart-b0e8f7fd-8ca8-4a70-a11f-64b5f5ab17c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177489245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.177489245
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2223273574
Short name T125
Test name
Test status
Simulation time 116852642884 ps
CPU time 20.93 seconds
Started Mar 03 02:05:51 PM PST 24
Finished Mar 03 02:06:12 PM PST 24
Peak memory 236332 kb
Host smart-5da2743d-1bd6-4c63-8cfa-d81f28bd3c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223273574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2223273574
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2795424845
Short name T353
Test name
Test status
Simulation time 44891944 ps
CPU time 1.05 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 216516 kb
Host smart-10ca0d5a-02e6-40c5-806a-f36dd77b0c98
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795424845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2795424845
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2210219999
Short name T366
Test name
Test status
Simulation time 1226164404 ps
CPU time 6.33 seconds
Started Mar 03 02:05:56 PM PST 24
Finished Mar 03 02:06:02 PM PST 24
Peak memory 233040 kb
Host smart-54fda2d7-0940-4da9-bc4b-2cbb768960eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210219999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2210219999
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.394607365
Short name T240
Test name
Test status
Simulation time 10758921757 ps
CPU time 8.73 seconds
Started Mar 03 02:06:03 PM PST 24
Finished Mar 03 02:06:12 PM PST 24
Peak memory 227820 kb
Host smart-119d6123-9f5e-4727-a41d-37dfb627c078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394607365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.394607365
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3340018525
Short name T975
Test name
Test status
Simulation time 19099658 ps
CPU time 0.76 seconds
Started Mar 03 02:05:53 PM PST 24
Finished Mar 03 02:05:54 PM PST 24
Peak memory 215948 kb
Host smart-0a02c903-568a-402a-89e5-a820208e6a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340018525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3340018525
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3104621207
Short name T695
Test name
Test status
Simulation time 1431536630 ps
CPU time 5.06 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:11 PM PST 24
Peak memory 222000 kb
Host smart-f30f524e-2053-4de7-90e3-775d3433e02a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3104621207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3104621207
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.641094170
Short name T79
Test name
Test status
Simulation time 42027461 ps
CPU time 1.06 seconds
Started Mar 03 02:06:01 PM PST 24
Finished Mar 03 02:06:02 PM PST 24
Peak memory 234672 kb
Host smart-ccd9a5f5-6243-42b9-9536-e7f1365ab38e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641094170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.641094170
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2000960018
Short name T273
Test name
Test status
Simulation time 82439146309 ps
CPU time 233.43 seconds
Started Mar 03 02:06:04 PM PST 24
Finished Mar 03 02:09:59 PM PST 24
Peak memory 264968 kb
Host smart-bf9dd52d-ae86-4a4c-831b-f0f0dd287fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000960018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2000960018
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.78798691
Short name T766
Test name
Test status
Simulation time 13612203745 ps
CPU time 35.95 seconds
Started Mar 03 02:05:52 PM PST 24
Finished Mar 03 02:06:29 PM PST 24
Peak memory 216328 kb
Host smart-e5da1c36-42d8-49a0-8da6-45ab1edd8e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78798691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.78798691
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.534082511
Short name T438
Test name
Test status
Simulation time 1197216459 ps
CPU time 7.72 seconds
Started Mar 03 02:05:56 PM PST 24
Finished Mar 03 02:06:04 PM PST 24
Peak memory 216268 kb
Host smart-14b9bf51-4d0f-4a97-9618-a6ffc71e51fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534082511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.534082511
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3741036419
Short name T371
Test name
Test status
Simulation time 307054984 ps
CPU time 4.7 seconds
Started Mar 03 02:06:03 PM PST 24
Finished Mar 03 02:06:07 PM PST 24
Peak memory 216328 kb
Host smart-0bd72e12-d0cf-4586-bc4e-70565c2cb3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741036419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3741036419
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.287147539
Short name T381
Test name
Test status
Simulation time 29982561 ps
CPU time 0.85 seconds
Started Mar 03 02:06:03 PM PST 24
Finished Mar 03 02:06:04 PM PST 24
Peak memory 205332 kb
Host smart-0e802cc0-bcd5-4b46-802f-2f6fbbe8d66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287147539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.287147539
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.648070219
Short name T89
Test name
Test status
Simulation time 13440391283 ps
CPU time 13.86 seconds
Started Mar 03 02:05:52 PM PST 24
Finished Mar 03 02:06:06 PM PST 24
Peak memory 228896 kb
Host smart-ad273715-4e54-44e6-a1ec-9ba5c44cc993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648070219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.648070219
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.108711155
Short name T795
Test name
Test status
Simulation time 50703128 ps
CPU time 0.75 seconds
Started Mar 03 02:08:17 PM PST 24
Finished Mar 03 02:08:18 PM PST 24
Peak memory 204864 kb
Host smart-aea8ff70-c91b-4198-80ad-b471ca4ae543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108711155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.108711155
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3828322900
Short name T846
Test name
Test status
Simulation time 53245973 ps
CPU time 2.65 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:08:11 PM PST 24
Peak memory 233700 kb
Host smart-bfb32309-0c38-4247-8ab4-2fbc5ec6ec20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828322900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3828322900
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.625422566
Short name T389
Test name
Test status
Simulation time 29180036 ps
CPU time 0.77 seconds
Started Mar 03 02:08:05 PM PST 24
Finished Mar 03 02:08:06 PM PST 24
Peak memory 204968 kb
Host smart-cda6e082-63a0-4551-ad3f-74b36d47067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625422566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.625422566
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1322559756
Short name T756
Test name
Test status
Simulation time 5764503720 ps
CPU time 95.43 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:09:44 PM PST 24
Peak memory 263600 kb
Host smart-8531aa72-c397-4c4d-b281-4e4763e146b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322559756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1322559756
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.798024625
Short name T330
Test name
Test status
Simulation time 4951122138 ps
CPU time 72.87 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:09:21 PM PST 24
Peak memory 253932 kb
Host smart-37c6de68-ff03-4010-86df-6893365e4592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798024625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.798024625
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2299289648
Short name T183
Test name
Test status
Simulation time 149711394018 ps
CPU time 453.55 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:15:42 PM PST 24
Peak memory 281532 kb
Host smart-e25cb61f-545e-491e-bcbd-30485fbe05b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299289648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2299289648
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2934650786
Short name T295
Test name
Test status
Simulation time 14171393024 ps
CPU time 24.87 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:08:32 PM PST 24
Peak memory 239004 kb
Host smart-d423f508-591c-4c13-b18f-b072b9c9bb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934650786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2934650786
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1473447833
Short name T608
Test name
Test status
Simulation time 700776350 ps
CPU time 5.15 seconds
Started Mar 03 02:08:18 PM PST 24
Finished Mar 03 02:08:24 PM PST 24
Peak memory 232324 kb
Host smart-ab651ccf-2eb5-4f67-8d28-40aeb40cf0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473447833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1473447833
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3745960358
Short name T710
Test name
Test status
Simulation time 67263512099 ps
CPU time 13.95 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:08:30 PM PST 24
Peak memory 224416 kb
Host smart-d48c7176-1198-48ed-bd6a-25f3103becdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745960358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3745960358
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.103123703
Short name T672
Test name
Test status
Simulation time 46182570232 ps
CPU time 32.4 seconds
Started Mar 03 02:08:17 PM PST 24
Finished Mar 03 02:08:50 PM PST 24
Peak memory 239440 kb
Host smart-69cf9209-a01f-4b6f-8ae7-1ba07deccc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103123703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.103123703
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2490816931
Short name T333
Test name
Test status
Simulation time 13505568714 ps
CPU time 8.72 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:08:17 PM PST 24
Peak memory 232624 kb
Host smart-d470394c-6d53-4f77-a3f4-e34716ea8431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490816931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2490816931
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.386406317
Short name T505
Test name
Test status
Simulation time 1278536234 ps
CPU time 4.34 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:08:13 PM PST 24
Peak memory 222476 kb
Host smart-9592dfb9-95e1-4f93-9449-6bba67c17dfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=386406317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.386406317
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2822154920
Short name T373
Test name
Test status
Simulation time 4209604323 ps
CPU time 11.03 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:08:19 PM PST 24
Peak memory 216312 kb
Host smart-b47123d7-80d3-407b-93a1-eed4953e22e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822154920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2822154920
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.494258824
Short name T775
Test name
Test status
Simulation time 6403447970 ps
CPU time 3.94 seconds
Started Mar 03 02:08:17 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 216320 kb
Host smart-83935ec6-015d-42e9-a54e-c8c216ce00e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494258824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.494258824
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1836399106
Short name T454
Test name
Test status
Simulation time 568239065 ps
CPU time 7.25 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:08:15 PM PST 24
Peak memory 216456 kb
Host smart-39bf7db9-7b75-484f-a3e5-cc651bdee706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836399106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1836399106
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.494342921
Short name T834
Test name
Test status
Simulation time 139996234 ps
CPU time 0.93 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:08:17 PM PST 24
Peak memory 205348 kb
Host smart-b60b3a7a-8c62-45dc-b6ef-b1f89a302864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494342921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.494342921
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.615782422
Short name T569
Test name
Test status
Simulation time 297137149 ps
CPU time 2.71 seconds
Started Mar 03 02:08:06 PM PST 24
Finished Mar 03 02:08:09 PM PST 24
Peak memory 218596 kb
Host smart-4b220e6b-ab78-4cd6-a708-20e158da352d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615782422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.615782422
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3578463495
Short name T761
Test name
Test status
Simulation time 14742494 ps
CPU time 0.75 seconds
Started Mar 03 02:08:18 PM PST 24
Finished Mar 03 02:08:18 PM PST 24
Peak memory 204272 kb
Host smart-c9191c36-28e7-4645-b176-7a05e162a2f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578463495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3578463495
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1415185205
Short name T3
Test name
Test status
Simulation time 198862335 ps
CPU time 3.49 seconds
Started Mar 03 02:08:07 PM PST 24
Finished Mar 03 02:08:11 PM PST 24
Peak memory 217588 kb
Host smart-8ee87d9b-151c-4091-86f7-c072f388909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415185205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1415185205
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.554758937
Short name T559
Test name
Test status
Simulation time 39005408 ps
CPU time 0.83 seconds
Started Mar 03 02:08:06 PM PST 24
Finished Mar 03 02:08:07 PM PST 24
Peak memory 205996 kb
Host smart-1d07d7f2-29d7-4b09-a31f-b272e376224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554758937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.554758937
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1253065714
Short name T541
Test name
Test status
Simulation time 36560447391 ps
CPU time 93.21 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:09:49 PM PST 24
Peak memory 257168 kb
Host smart-6bb08978-51ca-4134-a471-d260cb39b812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253065714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1253065714
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.253949852
Short name T234
Test name
Test status
Simulation time 55955105270 ps
CPU time 352.99 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:14:09 PM PST 24
Peak memory 256224 kb
Host smart-d9406999-f94e-4fc0-8769-eb04b041a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253949852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.253949852
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.330458766
Short name T59
Test name
Test status
Simulation time 57223805107 ps
CPU time 413.13 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:15:09 PM PST 24
Peak memory 273348 kb
Host smart-6189c814-5b34-41e4-a36e-6641f0b6c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330458766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.330458766
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2430243224
Short name T338
Test name
Test status
Simulation time 13549726951 ps
CPU time 26.91 seconds
Started Mar 03 02:08:13 PM PST 24
Finished Mar 03 02:08:40 PM PST 24
Peak memory 238576 kb
Host smart-19688b73-2356-4c03-9953-f78040290919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430243224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2430243224
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.200420224
Short name T207
Test name
Test status
Simulation time 1614195001 ps
CPU time 3.53 seconds
Started Mar 03 02:08:18 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 216484 kb
Host smart-1da94637-a180-4619-9086-5ae4a3008a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200420224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.200420224
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2033804996
Short name T784
Test name
Test status
Simulation time 11590136468 ps
CPU time 17.92 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:08:40 PM PST 24
Peak memory 247408 kb
Host smart-1943c954-5e57-40bc-9136-8cf4cce49f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033804996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2033804996
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3516691524
Short name T232
Test name
Test status
Simulation time 727152398 ps
CPU time 4.29 seconds
Started Mar 03 02:08:18 PM PST 24
Finished Mar 03 02:08:24 PM PST 24
Peak memory 216236 kb
Host smart-16f8f20b-c3a8-4249-88f5-ad917572677c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516691524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3516691524
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2015928326
Short name T831
Test name
Test status
Simulation time 547789541 ps
CPU time 8.89 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:08:17 PM PST 24
Peak memory 228528 kb
Host smart-fbc280ff-eade-4c82-ad23-51f4a8a47cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015928326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2015928326
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1914827497
Short name T894
Test name
Test status
Simulation time 1873804282 ps
CPU time 5.23 seconds
Started Mar 03 02:08:13 PM PST 24
Finished Mar 03 02:08:19 PM PST 24
Peak memory 220000 kb
Host smart-b3405158-2fe3-44f7-841c-bc20302aade2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1914827497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1914827497
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.30062742
Short name T642
Test name
Test status
Simulation time 140465926568 ps
CPU time 543.83 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:17:19 PM PST 24
Peak memory 268036 kb
Host smart-f3b9a056-f419-474c-816b-8bc3e80bc71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30062742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress
_all.30062742
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1606559713
Short name T837
Test name
Test status
Simulation time 1066181882 ps
CPU time 14.7 seconds
Started Mar 03 02:08:18 PM PST 24
Finished Mar 03 02:08:35 PM PST 24
Peak memory 215860 kb
Host smart-34fbba8f-07fa-4471-8c78-2bedef213e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606559713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1606559713
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3028058235
Short name T428
Test name
Test status
Simulation time 326755004 ps
CPU time 1.69 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:08:10 PM PST 24
Peak memory 207832 kb
Host smart-1e04f87a-ebd9-47f2-84b7-1c91e195d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028058235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3028058235
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4088395299
Short name T390
Test name
Test status
Simulation time 57258195 ps
CPU time 0.87 seconds
Started Mar 03 02:08:08 PM PST 24
Finished Mar 03 02:08:09 PM PST 24
Peak memory 206220 kb
Host smart-c3bf3754-6cf7-4fdb-a06d-12bedfc1287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088395299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4088395299
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3948248356
Short name T88
Test name
Test status
Simulation time 121831182 ps
CPU time 1.12 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:08:16 PM PST 24
Peak memory 206320 kb
Host smart-3f7a48cd-4792-42db-a162-aa79fff3cd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948248356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3948248356
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3583015908
Short name T790
Test name
Test status
Simulation time 29857081652 ps
CPU time 29.63 seconds
Started Mar 03 02:08:06 PM PST 24
Finished Mar 03 02:08:36 PM PST 24
Peak memory 237380 kb
Host smart-132dd859-7e3f-438e-8fda-e5e9a1c9874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583015908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3583015908
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.266305929
Short name T798
Test name
Test status
Simulation time 18465241 ps
CPU time 0.72 seconds
Started Mar 03 02:08:17 PM PST 24
Finished Mar 03 02:08:18 PM PST 24
Peak memory 204848 kb
Host smart-963c3ead-5fc2-408b-b300-3d4bf6a2097c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266305929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.266305929
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.866322357
Short name T822
Test name
Test status
Simulation time 9007160988 ps
CPU time 8.4 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:23 PM PST 24
Peak memory 220220 kb
Host smart-faf7d801-9096-40ab-b0dd-4699c0eb6e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866322357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.866322357
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2796909658
Short name T421
Test name
Test status
Simulation time 22338225 ps
CPU time 0.81 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:08:17 PM PST 24
Peak memory 204956 kb
Host smart-6aab899c-f00d-4739-8d61-bcfca218a20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796909658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2796909658
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3960859276
Short name T271
Test name
Test status
Simulation time 290784832329 ps
CPU time 208.37 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:11:44 PM PST 24
Peak memory 273224 kb
Host smart-f87c560d-2a47-45e0-8c85-d836ea6ff268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960859276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3960859276
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1882591259
Short name T925
Test name
Test status
Simulation time 35238823537 ps
CPU time 80.97 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:09:37 PM PST 24
Peak memory 251388 kb
Host smart-afec8fcc-a84c-43d2-9fd1-025d112d4eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882591259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1882591259
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.436073091
Short name T208
Test name
Test status
Simulation time 211311822379 ps
CPU time 387.55 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:14:44 PM PST 24
Peak memory 271872 kb
Host smart-acf00640-d29b-4436-8d0e-625f83e5b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436073091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.436073091
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1287033736
Short name T941
Test name
Test status
Simulation time 743649521 ps
CPU time 11.16 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:26 PM PST 24
Peak memory 238540 kb
Host smart-39e11e79-24ce-4758-a2ab-fd03195968a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287033736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1287033736
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2263665465
Short name T943
Test name
Test status
Simulation time 9466793906 ps
CPU time 13.37 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:08:30 PM PST 24
Peak memory 224448 kb
Host smart-75b7e5a5-c32f-4423-b5e8-98bbc9c641d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263665465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2263665465
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2032932007
Short name T351
Test name
Test status
Simulation time 1629290398 ps
CPU time 2.37 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:08:18 PM PST 24
Peak memory 224204 kb
Host smart-bdd991cf-d25d-4392-b81d-7ab5df4b9223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032932007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2032932007
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1491307660
Short name T742
Test name
Test status
Simulation time 779480688 ps
CPU time 2.86 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:18 PM PST 24
Peak memory 216680 kb
Host smart-07aa132f-1eb7-42f7-a21a-ec784e88e867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491307660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1491307660
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2704226137
Short name T807
Test name
Test status
Simulation time 295407871 ps
CPU time 3.17 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:18 PM PST 24
Peak memory 219936 kb
Host smart-feb012f3-fd9b-4a23-91ac-dd27e6c9a899
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2704226137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2704226137
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4051405397
Short name T256
Test name
Test status
Simulation time 30068348027 ps
CPU time 243.81 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:12:20 PM PST 24
Peak memory 253108 kb
Host smart-a21eff62-f7eb-4c91-a949-3d89d46e4e26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051405397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4051405397
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.302115786
Short name T947
Test name
Test status
Simulation time 11543292458 ps
CPU time 41.44 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:08:58 PM PST 24
Peak memory 217564 kb
Host smart-78a0327d-3094-44b5-978e-90415a2e72f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302115786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.302115786
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3256209586
Short name T297
Test name
Test status
Simulation time 9564875931 ps
CPU time 8.25 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:23 PM PST 24
Peak memory 216316 kb
Host smart-07434344-a94c-45c0-9f23-ce6955ce704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256209586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3256209586
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3140790106
Short name T280
Test name
Test status
Simulation time 65750744 ps
CPU time 1.64 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:16 PM PST 24
Peak memory 216228 kb
Host smart-92fabe4e-eaed-435c-968e-1ca26fb77d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140790106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3140790106
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2676782490
Short name T558
Test name
Test status
Simulation time 28072436 ps
CPU time 0.74 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:16 PM PST 24
Peak memory 205356 kb
Host smart-4044a533-2745-4c89-b03a-d2ffb63f46f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676782490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2676782490
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3299838130
Short name T856
Test name
Test status
Simulation time 4231236377 ps
CPU time 18.11 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:08:33 PM PST 24
Peak memory 233548 kb
Host smart-3b51e8f2-3f35-4ae2-9219-fa7a9f6dfc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299838130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3299838130
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.784815790
Short name T487
Test name
Test status
Simulation time 38789317 ps
CPU time 0.76 seconds
Started Mar 03 02:08:23 PM PST 24
Finished Mar 03 02:08:24 PM PST 24
Peak memory 205192 kb
Host smart-f625f0ec-2a64-4ca1-b73e-7417d847afa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784815790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.784815790
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3880877548
Short name T685
Test name
Test status
Simulation time 436442353 ps
CPU time 2.54 seconds
Started Mar 03 02:08:23 PM PST 24
Finished Mar 03 02:08:25 PM PST 24
Peak memory 233332 kb
Host smart-c791d8e4-4f27-4289-b90d-34dec11fce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880877548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3880877548
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4160459392
Short name T904
Test name
Test status
Simulation time 64312777 ps
CPU time 0.77 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:08:16 PM PST 24
Peak memory 206320 kb
Host smart-2f3e3b28-16fb-4fbc-9b8d-e670b9c0931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160459392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4160459392
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.598581177
Short name T307
Test name
Test status
Simulation time 7637008269 ps
CPU time 22.94 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:08:45 PM PST 24
Peak memory 240840 kb
Host smart-2ea42e13-8794-4d6d-ae17-8e93409bf102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598581177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.598581177
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.942144662
Short name T361
Test name
Test status
Simulation time 64201866461 ps
CPU time 107.56 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:10:10 PM PST 24
Peak memory 236968 kb
Host smart-0fcd5e92-5eb6-4262-8a27-7df150d02e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942144662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.942144662
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.323349123
Short name T321
Test name
Test status
Simulation time 5991917799 ps
CPU time 24.29 seconds
Started Mar 03 02:08:21 PM PST 24
Finished Mar 03 02:08:46 PM PST 24
Peak memory 224440 kb
Host smart-4757fdaf-14f9-483d-8f02-92e289634630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323349123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.323349123
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1192175916
Short name T745
Test name
Test status
Simulation time 767179825 ps
CPU time 4.36 seconds
Started Mar 03 02:08:18 PM PST 24
Finished Mar 03 02:08:25 PM PST 24
Peak memory 233188 kb
Host smart-660c9036-c5af-4c25-bfe6-e919856937bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192175916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1192175916
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3824773256
Short name T802
Test name
Test status
Simulation time 858547097 ps
CPU time 8.4 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 224388 kb
Host smart-7591bf3c-6251-4af7-9985-a002a9df9b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824773256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3824773256
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.89750657
Short name T448
Test name
Test status
Simulation time 3612330264 ps
CPU time 5.85 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 233560 kb
Host smart-2951dd6e-87f7-4cad-96d1-e557f43fa225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89750657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.89750657
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.225594547
Short name T682
Test name
Test status
Simulation time 15154976169 ps
CPU time 7.72 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:08:24 PM PST 24
Peak memory 219960 kb
Host smart-d1bcb1de-290f-4402-b797-c83e4816be24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225594547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.225594547
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2445629951
Short name T314
Test name
Test status
Simulation time 2832502055 ps
CPU time 5.07 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:08:28 PM PST 24
Peak memory 222048 kb
Host smart-ab6244a5-74b5-4e65-bdab-4dc64401f147
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2445629951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2445629951
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1123348292
Short name T743
Test name
Test status
Simulation time 51744908167 ps
CPU time 294.89 seconds
Started Mar 03 02:08:20 PM PST 24
Finished Mar 03 02:13:16 PM PST 24
Peak memory 282132 kb
Host smart-6102c4b6-aeac-40f5-b931-d2682ee344d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123348292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1123348292
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.108489053
Short name T449
Test name
Test status
Simulation time 5229791112 ps
CPU time 23.71 seconds
Started Mar 03 02:08:15 PM PST 24
Finished Mar 03 02:08:39 PM PST 24
Peak memory 216340 kb
Host smart-b2936251-7079-49f8-a1fd-ea27f53ed519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108489053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.108489053
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3793045178
Short name T568
Test name
Test status
Simulation time 16488451768 ps
CPU time 15.33 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:30 PM PST 24
Peak memory 216288 kb
Host smart-76dad6c0-b8e1-4caf-9ba6-3ddabfc0058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793045178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3793045178
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2047111566
Short name T914
Test name
Test status
Simulation time 215723996 ps
CPU time 1.48 seconds
Started Mar 03 02:08:16 PM PST 24
Finished Mar 03 02:08:18 PM PST 24
Peak memory 216288 kb
Host smart-e204f992-4f87-4e53-bba2-a9fb996d733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047111566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2047111566
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3025148633
Short name T486
Test name
Test status
Simulation time 290664994 ps
CPU time 0.97 seconds
Started Mar 03 02:08:14 PM PST 24
Finished Mar 03 02:08:16 PM PST 24
Peak memory 205780 kb
Host smart-4211aa2e-18ab-46c2-9ea9-acb8922d0f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025148633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3025148633
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3749596992
Short name T828
Test name
Test status
Simulation time 1605992430 ps
CPU time 13.61 seconds
Started Mar 03 02:08:24 PM PST 24
Finished Mar 03 02:08:38 PM PST 24
Peak memory 223148 kb
Host smart-1c3ed880-508e-40cc-836a-5f653e79b0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749596992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3749596992
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3236374531
Short name T776
Test name
Test status
Simulation time 14125221 ps
CPU time 0.73 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:08:23 PM PST 24
Peak memory 204872 kb
Host smart-794c3e0e-9627-437c-9784-beb625fdf82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236374531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3236374531
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3333209474
Short name T140
Test name
Test status
Simulation time 2811565405 ps
CPU time 4.53 seconds
Started Mar 03 02:08:23 PM PST 24
Finished Mar 03 02:08:27 PM PST 24
Peak memory 233464 kb
Host smart-449d2d7f-1f9f-4adb-aba5-a04d4ee249d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333209474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3333209474
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3095572941
Short name T721
Test name
Test status
Simulation time 17960648 ps
CPU time 0.81 seconds
Started Mar 03 02:08:21 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 204960 kb
Host smart-8b751397-743b-4090-8f5f-4b32df5246a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095572941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3095572941
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1799545806
Short name T35
Test name
Test status
Simulation time 11745475121 ps
CPU time 75.25 seconds
Started Mar 03 02:08:21 PM PST 24
Finished Mar 03 02:09:37 PM PST 24
Peak memory 257180 kb
Host smart-ea960f7d-bd46-47a7-b8c9-d19909802652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799545806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1799545806
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2842348529
Short name T424
Test name
Test status
Simulation time 10212873959 ps
CPU time 23.08 seconds
Started Mar 03 02:08:23 PM PST 24
Finished Mar 03 02:08:46 PM PST 24
Peak memory 250144 kb
Host smart-a3eac5bd-628c-42cf-8b08-71c7708dd1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842348529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2842348529
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3184803096
Short name T252
Test name
Test status
Simulation time 68574520181 ps
CPU time 486.54 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:16:29 PM PST 24
Peak memory 273732 kb
Host smart-b5803961-5aac-4df2-b2af-02582b941c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184803096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3184803096
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.130032197
Short name T122
Test name
Test status
Simulation time 8242197377 ps
CPU time 14.74 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:08:37 PM PST 24
Peak memory 222076 kb
Host smart-f7e9ce33-2474-4415-b611-e4f22358aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130032197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.130032197
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2551293711
Short name T186
Test name
Test status
Simulation time 1902694586 ps
CPU time 9.26 seconds
Started Mar 03 02:08:23 PM PST 24
Finished Mar 03 02:08:32 PM PST 24
Peak memory 217260 kb
Host smart-48f758da-3907-483b-8988-a46a02a9b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551293711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2551293711
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.947001365
Short name T867
Test name
Test status
Simulation time 33972659144 ps
CPU time 26.41 seconds
Started Mar 03 02:08:24 PM PST 24
Finished Mar 03 02:08:51 PM PST 24
Peak memory 232636 kb
Host smart-451fc2a4-6c06-4239-913f-9aa4e2e5eb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947001365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.947001365
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3369235633
Short name T768
Test name
Test status
Simulation time 9247062787 ps
CPU time 7.41 seconds
Started Mar 03 02:08:20 PM PST 24
Finished Mar 03 02:08:28 PM PST 24
Peak memory 216428 kb
Host smart-eedc47d6-c548-48ae-bc5c-78c2856414d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369235633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3369235633
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3170258116
Short name T667
Test name
Test status
Simulation time 630965680 ps
CPU time 4.77 seconds
Started Mar 03 02:08:20 PM PST 24
Finished Mar 03 02:08:25 PM PST 24
Peak memory 233552 kb
Host smart-94e65718-28e3-4b32-82df-472c549496d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170258116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3170258116
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3270769156
Short name T91
Test name
Test status
Simulation time 4486754419 ps
CPU time 6.55 seconds
Started Mar 03 02:08:24 PM PST 24
Finished Mar 03 02:08:31 PM PST 24
Peak memory 220240 kb
Host smart-7f5dcfda-4c0f-4ffc-b636-6e5e4048876a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3270769156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3270769156
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1718862028
Short name T197
Test name
Test status
Simulation time 236213363130 ps
CPU time 461.99 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:16:04 PM PST 24
Peak memory 289804 kb
Host smart-a5a3aec4-4a35-499f-9939-3182a06001e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718862028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1718862028
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.229582076
Short name T348
Test name
Test status
Simulation time 17654709660 ps
CPU time 33.84 seconds
Started Mar 03 02:08:24 PM PST 24
Finished Mar 03 02:08:58 PM PST 24
Peak memory 216244 kb
Host smart-e682acbb-e513-4e6c-9d04-450dbbd16c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229582076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.229582076
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3026441170
Short name T304
Test name
Test status
Simulation time 19579903833 ps
CPU time 29.44 seconds
Started Mar 03 02:08:20 PM PST 24
Finished Mar 03 02:08:50 PM PST 24
Peak memory 216316 kb
Host smart-28380e92-3909-4deb-ac11-ebdf233ca4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026441170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3026441170
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1027190878
Short name T276
Test name
Test status
Simulation time 12518439 ps
CPU time 0.76 seconds
Started Mar 03 02:08:21 PM PST 24
Finished Mar 03 02:08:22 PM PST 24
Peak memory 205356 kb
Host smart-5d363354-ba21-4a46-9c6a-ace079172f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027190878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1027190878
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.448557906
Short name T645
Test name
Test status
Simulation time 22713400 ps
CPU time 0.75 seconds
Started Mar 03 02:08:24 PM PST 24
Finished Mar 03 02:08:25 PM PST 24
Peak memory 205348 kb
Host smart-374ba7c7-b529-4055-8ee9-c06a29a5c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448557906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.448557906
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2331557622
Short name T920
Test name
Test status
Simulation time 67524654383 ps
CPU time 33.45 seconds
Started Mar 03 02:08:20 PM PST 24
Finished Mar 03 02:08:55 PM PST 24
Peak memory 237244 kb
Host smart-f07049a8-b562-4b69-a834-35115fb3d9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331557622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2331557622
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2576923687
Short name T511
Test name
Test status
Simulation time 44264714 ps
CPU time 0.69 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:08:29 PM PST 24
Peak memory 204748 kb
Host smart-359827ec-3741-4087-a8b1-b35998a37d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576923687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2576923687
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3954115346
Short name T383
Test name
Test status
Simulation time 290345725 ps
CPU time 4.19 seconds
Started Mar 03 02:08:31 PM PST 24
Finished Mar 03 02:08:35 PM PST 24
Peak memory 224340 kb
Host smart-fc83de32-796d-495a-a803-6c32d2c03130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954115346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3954115346
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.245878947
Short name T19
Test name
Test status
Simulation time 64481086 ps
CPU time 0.76 seconds
Started Mar 03 02:08:22 PM PST 24
Finished Mar 03 02:08:23 PM PST 24
Peak memory 205300 kb
Host smart-eff76ece-7f8a-498a-bcaa-f3bb57ec4abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245878947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.245878947
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1470650014
Short name T535
Test name
Test status
Simulation time 3870438084 ps
CPU time 35.82 seconds
Started Mar 03 02:08:31 PM PST 24
Finished Mar 03 02:09:08 PM PST 24
Peak memory 232616 kb
Host smart-369b906c-6cc7-4661-a5d5-ea5dba0fb84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470650014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1470650014
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.434334236
Short name T605
Test name
Test status
Simulation time 5525640342 ps
CPU time 70.25 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:09:39 PM PST 24
Peak memory 238708 kb
Host smart-59401abb-5201-42fb-aba5-aa8976d32fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434334236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.434334236
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3437929528
Short name T677
Test name
Test status
Simulation time 20959778578 ps
CPU time 62.26 seconds
Started Mar 03 02:08:29 PM PST 24
Finished Mar 03 02:09:31 PM PST 24
Peak memory 241948 kb
Host smart-5d0a0ada-8593-4bd3-bc9b-65b129180fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437929528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3437929528
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1512516553
Short name T881
Test name
Test status
Simulation time 21163766831 ps
CPU time 54.12 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:09:22 PM PST 24
Peak memory 250184 kb
Host smart-76f5390f-93c8-4a5f-ae96-859503a66f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512516553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1512516553
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.459335303
Short name T415
Test name
Test status
Simulation time 1708272110 ps
CPU time 4.37 seconds
Started Mar 03 02:08:29 PM PST 24
Finished Mar 03 02:08:34 PM PST 24
Peak memory 233220 kb
Host smart-c285aa04-7d6d-406d-87d8-8e66b6433114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459335303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.459335303
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2717994638
Short name T643
Test name
Test status
Simulation time 190745384 ps
CPU time 2.99 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:08:32 PM PST 24
Peak memory 233472 kb
Host smart-9fbaae78-a01a-4b6e-9cb1-815165b80d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717994638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2717994638
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1925817454
Short name T246
Test name
Test status
Simulation time 1270648334 ps
CPU time 9.59 seconds
Started Mar 03 02:08:30 PM PST 24
Finished Mar 03 02:08:39 PM PST 24
Peak memory 235812 kb
Host smart-f8425763-3332-450a-ac21-8846f944c89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925817454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1925817454
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3836783980
Short name T447
Test name
Test status
Simulation time 10054031826 ps
CPU time 8.32 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:08:36 PM PST 24
Peak memory 224368 kb
Host smart-b6184cc2-7553-45f9-b643-9427abab73d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836783980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3836783980
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2213318651
Short name T510
Test name
Test status
Simulation time 21933209766 ps
CPU time 6.15 seconds
Started Mar 03 02:08:33 PM PST 24
Finished Mar 03 02:08:40 PM PST 24
Peak memory 222224 kb
Host smart-3928dd5b-5016-4a17-9429-f7988c32914a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2213318651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2213318651
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3645900163
Short name T949
Test name
Test status
Simulation time 353409843 ps
CPU time 4.38 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:08:33 PM PST 24
Peak memory 216180 kb
Host smart-b1106208-3cae-45b5-89b3-b47fff378b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645900163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3645900163
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.452689421
Short name T634
Test name
Test status
Simulation time 2077618913 ps
CPU time 5.41 seconds
Started Mar 03 02:08:33 PM PST 24
Finished Mar 03 02:08:39 PM PST 24
Peak memory 216120 kb
Host smart-0d1d484c-20ee-4a27-b16b-5e5755213956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452689421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.452689421
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1444054074
Short name T855
Test name
Test status
Simulation time 51733834 ps
CPU time 1.47 seconds
Started Mar 03 02:08:27 PM PST 24
Finished Mar 03 02:08:28 PM PST 24
Peak memory 216240 kb
Host smart-54f39231-808b-41e3-9831-d243e8abefc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444054074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1444054074
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2951302879
Short name T698
Test name
Test status
Simulation time 225368265 ps
CPU time 0.99 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:08:30 PM PST 24
Peak memory 205656 kb
Host smart-580c574d-2bb5-4948-80a6-91d1ca2c3bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951302879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2951302879
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1821497453
Short name T160
Test name
Test status
Simulation time 47386332857 ps
CPU time 15.14 seconds
Started Mar 03 02:08:29 PM PST 24
Finished Mar 03 02:08:44 PM PST 24
Peak memory 233180 kb
Host smart-01347858-62cf-4b0d-90b7-7e484cf728a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821497453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1821497453
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1671997807
Short name T972
Test name
Test status
Simulation time 49818267 ps
CPU time 0.74 seconds
Started Mar 03 02:08:36 PM PST 24
Finished Mar 03 02:08:37 PM PST 24
Peak memory 204848 kb
Host smart-c1702faa-5924-467f-8aaf-9eb59a483654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671997807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1671997807
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2757212276
Short name T836
Test name
Test status
Simulation time 196532763 ps
CPU time 2.63 seconds
Started Mar 03 02:08:36 PM PST 24
Finished Mar 03 02:08:39 PM PST 24
Peak memory 233604 kb
Host smart-e607d31b-8dea-46b8-a075-18227ee2b65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757212276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2757212276
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.595584447
Short name T751
Test name
Test status
Simulation time 18281726 ps
CPU time 0.78 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:08:29 PM PST 24
Peak memory 204980 kb
Host smart-fd1f85f6-0123-49e4-be11-e64deaeea264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595584447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.595584447
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4071209579
Short name T393
Test name
Test status
Simulation time 7021598817 ps
CPU time 16.45 seconds
Started Mar 03 02:08:35 PM PST 24
Finished Mar 03 02:08:52 PM PST 24
Peak memory 224396 kb
Host smart-fa4cedff-b700-4d5d-9c65-32275c2ccb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071209579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4071209579
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3252614107
Short name T495
Test name
Test status
Simulation time 34263479466 ps
CPU time 250.16 seconds
Started Mar 03 02:08:36 PM PST 24
Finished Mar 03 02:12:47 PM PST 24
Peak memory 249116 kb
Host smart-7a909709-9098-4afe-9bfc-8e953315693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252614107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3252614107
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3357423698
Short name T901
Test name
Test status
Simulation time 3209859639 ps
CPU time 51.6 seconds
Started Mar 03 02:08:36 PM PST 24
Finished Mar 03 02:09:28 PM PST 24
Peak memory 237932 kb
Host smart-6c808217-ecaa-40e2-b2df-cd6f4d6651f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357423698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3357423698
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.653898829
Short name T274
Test name
Test status
Simulation time 21775009581 ps
CPU time 40.73 seconds
Started Mar 03 02:08:34 PM PST 24
Finished Mar 03 02:09:15 PM PST 24
Peak memory 232668 kb
Host smart-0f2900bf-7811-4b77-ad35-5317f500a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653898829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.653898829
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3108993786
Short name T691
Test name
Test status
Simulation time 146685592 ps
CPU time 3.08 seconds
Started Mar 03 02:08:29 PM PST 24
Finished Mar 03 02:08:32 PM PST 24
Peak memory 232588 kb
Host smart-9e65be96-36ea-4432-8c92-49b9a306cefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108993786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3108993786
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1605359837
Short name T261
Test name
Test status
Simulation time 58702264221 ps
CPU time 42.25 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:09:10 PM PST 24
Peak memory 250504 kb
Host smart-9353829b-06e7-4b8a-b75e-79de8836d0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605359837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1605359837
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2360846958
Short name T593
Test name
Test status
Simulation time 129044216 ps
CPU time 2.37 seconds
Started Mar 03 02:08:31 PM PST 24
Finished Mar 03 02:08:33 PM PST 24
Peak memory 216164 kb
Host smart-2abf21f0-7de3-46f2-8261-c602a0f09fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360846958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2360846958
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3934850737
Short name T508
Test name
Test status
Simulation time 256131401 ps
CPU time 3.86 seconds
Started Mar 03 02:08:36 PM PST 24
Finished Mar 03 02:08:41 PM PST 24
Peak memory 219708 kb
Host smart-b6765d58-c1f2-4243-ae83-83a6c775b78a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3934850737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3934850737
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4012977962
Short name T923
Test name
Test status
Simulation time 134848414989 ps
CPU time 188.15 seconds
Started Mar 03 02:08:35 PM PST 24
Finished Mar 03 02:11:43 PM PST 24
Peak memory 257364 kb
Host smart-2f0b57dc-9902-4d82-b939-2a18a2874fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012977962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4012977962
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2168576807
Short name T939
Test name
Test status
Simulation time 11953195604 ps
CPU time 18.54 seconds
Started Mar 03 02:08:33 PM PST 24
Finished Mar 03 02:08:52 PM PST 24
Peak memory 216336 kb
Host smart-e5cce0d0-abcc-44eb-a956-8bc7ef6e6737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168576807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2168576807
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3025777347
Short name T961
Test name
Test status
Simulation time 1946481312 ps
CPU time 9.28 seconds
Started Mar 03 02:08:29 PM PST 24
Finished Mar 03 02:08:39 PM PST 24
Peak memory 208168 kb
Host smart-c8c62a93-8b11-42ac-9b38-94049bdac866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025777347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3025777347
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3631853912
Short name T592
Test name
Test status
Simulation time 956022760 ps
CPU time 2.63 seconds
Started Mar 03 02:08:28 PM PST 24
Finished Mar 03 02:08:31 PM PST 24
Peak memory 217452 kb
Host smart-208332db-ec35-4558-819d-8a8cfbdccba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631853912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3631853912
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1874379384
Short name T379
Test name
Test status
Simulation time 40563238 ps
CPU time 0.78 seconds
Started Mar 03 02:08:33 PM PST 24
Finished Mar 03 02:08:34 PM PST 24
Peak memory 205376 kb
Host smart-5cff1a2e-ab4e-4092-a976-0cdf50c18d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874379384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1874379384
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3892257706
Short name T224
Test name
Test status
Simulation time 457447643 ps
CPU time 7.92 seconds
Started Mar 03 02:08:39 PM PST 24
Finished Mar 03 02:08:47 PM PST 24
Peak memory 230488 kb
Host smart-6f418316-75da-4602-bf7c-5090e41dbc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892257706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3892257706
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.878143579
Short name T536
Test name
Test status
Simulation time 21049564 ps
CPU time 0.72 seconds
Started Mar 03 02:08:38 PM PST 24
Finished Mar 03 02:08:39 PM PST 24
Peak memory 205200 kb
Host smart-06bb3062-1263-4a58-a7ae-adeb4648100f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878143579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.878143579
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.904045285
Short name T429
Test name
Test status
Simulation time 110294193 ps
CPU time 2.22 seconds
Started Mar 03 02:08:35 PM PST 24
Finished Mar 03 02:08:38 PM PST 24
Peak memory 224280 kb
Host smart-7e984fdc-4bf7-4086-9771-9a896fa25229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904045285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.904045285
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1892278746
Short name T893
Test name
Test status
Simulation time 20857223 ps
CPU time 0.8 seconds
Started Mar 03 02:08:38 PM PST 24
Finished Mar 03 02:08:40 PM PST 24
Peak memory 206264 kb
Host smart-a5db7828-0656-459b-841c-f0db92e79c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892278746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1892278746
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3907620180
Short name T727
Test name
Test status
Simulation time 6259949438 ps
CPU time 42.65 seconds
Started Mar 03 02:08:39 PM PST 24
Finished Mar 03 02:09:23 PM PST 24
Peak memory 255596 kb
Host smart-cd479dbf-1cf3-4957-8da8-bf8df316e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907620180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3907620180
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1662926584
Short name T181
Test name
Test status
Simulation time 21256426279 ps
CPU time 87.24 seconds
Started Mar 03 02:08:37 PM PST 24
Finished Mar 03 02:10:05 PM PST 24
Peak memory 258208 kb
Host smart-0336cde6-2ad4-4fee-8f69-441a4005cc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662926584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1662926584
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1097605695
Short name T98
Test name
Test status
Simulation time 30590675417 ps
CPU time 80.38 seconds
Started Mar 03 02:08:36 PM PST 24
Finished Mar 03 02:09:57 PM PST 24
Peak memory 266128 kb
Host smart-34aa8e3e-f1a5-413f-b3fa-740b4dbb1860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097605695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1097605695
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1264912668
Short name T343
Test name
Test status
Simulation time 2026166576 ps
CPU time 11.38 seconds
Started Mar 03 02:08:37 PM PST 24
Finished Mar 03 02:08:48 PM PST 24
Peak memory 249980 kb
Host smart-f5e7b328-61ef-4b92-bdaf-3bb39062e478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264912668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1264912668
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1978327744
Short name T588
Test name
Test status
Simulation time 3491958999 ps
CPU time 12.22 seconds
Started Mar 03 02:08:35 PM PST 24
Finished Mar 03 02:08:47 PM PST 24
Peak memory 235244 kb
Host smart-8144cce1-a7ac-43fc-b0a1-78bee3ffaba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978327744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1978327744
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3681016751
Short name T718
Test name
Test status
Simulation time 13591429233 ps
CPU time 10.53 seconds
Started Mar 03 02:08:34 PM PST 24
Finished Mar 03 02:08:45 PM PST 24
Peak memory 224372 kb
Host smart-5af60876-0f6e-47dd-8140-1f71abaad492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681016751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3681016751
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1691178886
Short name T614
Test name
Test status
Simulation time 209027744 ps
CPU time 3 seconds
Started Mar 03 02:08:39 PM PST 24
Finished Mar 03 02:08:42 PM PST 24
Peak memory 216336 kb
Host smart-6f24cf1e-baaa-4e78-afb2-bb26f14f58dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691178886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1691178886
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2495561600
Short name T838
Test name
Test status
Simulation time 956203741 ps
CPU time 8.82 seconds
Started Mar 03 02:08:35 PM PST 24
Finished Mar 03 02:08:44 PM PST 24
Peak memory 224316 kb
Host smart-1258fb29-b9a8-417e-b9d1-d8842aeb041f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495561600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2495561600
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1974273489
Short name T889
Test name
Test status
Simulation time 917142324 ps
CPU time 4.66 seconds
Started Mar 03 02:08:35 PM PST 24
Finished Mar 03 02:08:40 PM PST 24
Peak memory 220008 kb
Host smart-35bf7da6-b3bd-4e5b-bb87-472029441479
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1974273489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1974273489
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4149780205
Short name T514
Test name
Test status
Simulation time 2375221576 ps
CPU time 25.31 seconds
Started Mar 03 02:08:37 PM PST 24
Finished Mar 03 02:09:03 PM PST 24
Peak memory 216276 kb
Host smart-44c8301b-8110-46e8-86f5-9b19d856aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149780205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4149780205
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1992518254
Short name T676
Test name
Test status
Simulation time 25147830919 ps
CPU time 24.8 seconds
Started Mar 03 02:08:38 PM PST 24
Finished Mar 03 02:09:04 PM PST 24
Peak memory 216328 kb
Host smart-2f145054-bc1f-4787-a7f0-04d7bc74dc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992518254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1992518254
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2041281638
Short name T54
Test name
Test status
Simulation time 191859943 ps
CPU time 5.24 seconds
Started Mar 03 02:08:34 PM PST 24
Finished Mar 03 02:08:39 PM PST 24
Peak memory 216308 kb
Host smart-5b11b07c-e40d-430e-98ca-45df46bc2611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041281638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2041281638
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.720130772
Short name T287
Test name
Test status
Simulation time 77507668 ps
CPU time 0.76 seconds
Started Mar 03 02:08:34 PM PST 24
Finished Mar 03 02:08:35 PM PST 24
Peak memory 205256 kb
Host smart-f5185326-dfa4-4506-9903-f1ec3db87b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720130772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.720130772
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3930625292
Short name T69
Test name
Test status
Simulation time 6798958783 ps
CPU time 11.71 seconds
Started Mar 03 02:08:35 PM PST 24
Finished Mar 03 02:08:47 PM PST 24
Peak memory 235116 kb
Host smart-f9199dea-b3d5-4f97-b443-c169fdb5c3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930625292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3930625292
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.544457220
Short name T956
Test name
Test status
Simulation time 34818319 ps
CPU time 0.69 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:08:44 PM PST 24
Peak memory 204300 kb
Host smart-2af06dbf-34ff-401f-a6b1-d9721848f465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544457220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.544457220
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.686814120
Short name T215
Test name
Test status
Simulation time 5920785063 ps
CPU time 5.85 seconds
Started Mar 03 02:08:45 PM PST 24
Finished Mar 03 02:08:51 PM PST 24
Peak memory 234752 kb
Host smart-2d89ff27-71ca-4b09-be4a-5d50569b3543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686814120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.686814120
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2558504539
Short name T395
Test name
Test status
Simulation time 13992112 ps
CPU time 0.78 seconds
Started Mar 03 02:08:42 PM PST 24
Finished Mar 03 02:08:43 PM PST 24
Peak memory 206000 kb
Host smart-241ec22c-0b50-410e-938e-4853fc7d7da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558504539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2558504539
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3413338948
Short name T631
Test name
Test status
Simulation time 1011816263 ps
CPU time 17.47 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:09:02 PM PST 24
Peak memory 224320 kb
Host smart-18256f4a-85b4-47c3-b274-a1fcae9e523b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413338948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3413338948
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2644071309
Short name T47
Test name
Test status
Simulation time 60723048636 ps
CPU time 429.02 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:15:54 PM PST 24
Peak memory 262676 kb
Host smart-87999177-22ac-45c6-b62f-2352ba08b3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644071309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2644071309
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3243005855
Short name T699
Test name
Test status
Simulation time 20204653332 ps
CPU time 175.1 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:11:40 PM PST 24
Peak memory 254032 kb
Host smart-510b37a4-faba-4182-b2c9-ce04d4b28fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243005855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3243005855
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4131051713
Short name T14
Test name
Test status
Simulation time 34419744161 ps
CPU time 49.19 seconds
Started Mar 03 02:08:45 PM PST 24
Finished Mar 03 02:09:35 PM PST 24
Peak memory 233656 kb
Host smart-6c9da993-9c40-448c-bad4-fd91441c8bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131051713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4131051713
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3336604492
Short name T201
Test name
Test status
Simulation time 623117926 ps
CPU time 5.28 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:08:49 PM PST 24
Peak memory 219428 kb
Host smart-a47fa91d-a228-48f5-a9fb-4b5483f25093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336604492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3336604492
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3986312305
Short name T550
Test name
Test status
Simulation time 14002769966 ps
CPU time 31.63 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:09:15 PM PST 24
Peak memory 227380 kb
Host smart-b30fd12b-7824-446f-b0d0-951708635e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986312305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3986312305
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1361048875
Short name T235
Test name
Test status
Simulation time 13595440707 ps
CPU time 37.7 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:09:22 PM PST 24
Peak memory 233588 kb
Host smart-4372d7a8-fe1a-48aa-9d28-325082ce0af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361048875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1361048875
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3400491143
Short name T226
Test name
Test status
Simulation time 4201764195 ps
CPU time 12.21 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:08:55 PM PST 24
Peak memory 243464 kb
Host smart-66eee787-5430-4cd7-97de-0be3d6d31d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400491143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3400491143
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2073823134
Short name T306
Test name
Test status
Simulation time 166183349 ps
CPU time 3.8 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:08:48 PM PST 24
Peak memory 222548 kb
Host smart-06cbf24a-f2b8-4021-b3c4-b8f1ade2e764
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2073823134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2073823134
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2463205132
Short name T61
Test name
Test status
Simulation time 1319519281848 ps
CPU time 1006.39 seconds
Started Mar 03 02:08:42 PM PST 24
Finished Mar 03 02:25:29 PM PST 24
Peak memory 299276 kb
Host smart-323e8b26-cb06-44fd-a075-25255800be0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463205132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2463205132
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.92428619
Short name T406
Test name
Test status
Simulation time 2734132309 ps
CPU time 36.57 seconds
Started Mar 03 02:08:45 PM PST 24
Finished Mar 03 02:09:22 PM PST 24
Peak memory 220172 kb
Host smart-b09b5d28-0285-4f0c-8ed6-01ba3d8c3eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92428619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.92428619
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1541465794
Short name T289
Test name
Test status
Simulation time 34198419099 ps
CPU time 25.25 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:09:08 PM PST 24
Peak memory 216328 kb
Host smart-9b2a1ad7-74d1-41c6-96a2-6d05ee1b3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541465794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1541465794
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3344428253
Short name T606
Test name
Test status
Simulation time 132445580 ps
CPU time 1.44 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:08:46 PM PST 24
Peak memory 207736 kb
Host smart-297a1501-598f-47a0-aefd-962da1032996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344428253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3344428253
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2875323762
Short name T681
Test name
Test status
Simulation time 343824063 ps
CPU time 1.02 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:08:45 PM PST 24
Peak memory 206364 kb
Host smart-164a6249-5cfa-49a1-a834-8c666b14b04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875323762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2875323762
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1507446746
Short name T580
Test name
Test status
Simulation time 1995336408 ps
CPU time 6.18 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:08:50 PM PST 24
Peak memory 218836 kb
Host smart-7bd9d9c6-5544-426e-a507-134c060d5ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507446746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1507446746
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.881159484
Short name T640
Test name
Test status
Simulation time 11078647 ps
CPU time 0.74 seconds
Started Mar 03 02:08:51 PM PST 24
Finished Mar 03 02:08:52 PM PST 24
Peak memory 204844 kb
Host smart-0ddfbe64-07a3-4dd8-830c-612f174d5742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881159484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.881159484
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3579670658
Short name T723
Test name
Test status
Simulation time 213974378 ps
CPU time 2.88 seconds
Started Mar 03 02:08:46 PM PST 24
Finished Mar 03 02:08:49 PM PST 24
Peak memory 233532 kb
Host smart-62f69339-1a84-4d72-9ef9-c799ced9590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579670658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3579670658
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3810120988
Short name T411
Test name
Test status
Simulation time 41397183 ps
CPU time 0.78 seconds
Started Mar 03 02:08:45 PM PST 24
Finished Mar 03 02:08:46 PM PST 24
Peak memory 205988 kb
Host smart-0a69576d-6a0c-4aef-bab9-0e6ce565efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810120988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3810120988
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3859771768
Short name T401
Test name
Test status
Simulation time 2843264988 ps
CPU time 14.4 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:08:58 PM PST 24
Peak memory 232656 kb
Host smart-787cf3fe-7998-4a1f-bc6d-aefb8b27b300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859771768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3859771768
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2399811879
Short name T228
Test name
Test status
Simulation time 12459394801 ps
CPU time 89.16 seconds
Started Mar 03 02:08:41 PM PST 24
Finished Mar 03 02:10:10 PM PST 24
Peak memory 249172 kb
Host smart-15c15738-8509-4948-9efa-fcfeec4b1186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399811879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2399811879
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1322014372
Short name T25
Test name
Test status
Simulation time 12044213869 ps
CPU time 50.24 seconds
Started Mar 03 02:08:50 PM PST 24
Finished Mar 03 02:09:40 PM PST 24
Peak memory 249092 kb
Host smart-9db92708-8fbb-4f55-ba1a-607cda77c891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322014372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1322014372
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2303253823
Short name T211
Test name
Test status
Simulation time 457406010 ps
CPU time 10.87 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:08:55 PM PST 24
Peak memory 237224 kb
Host smart-4fde49a4-b402-49f1-a62c-c05743d66316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303253823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2303253823
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1535891276
Short name T467
Test name
Test status
Simulation time 3029416467 ps
CPU time 10.81 seconds
Started Mar 03 02:08:40 PM PST 24
Finished Mar 03 02:08:51 PM PST 24
Peak memory 238164 kb
Host smart-67878210-8e57-4c0d-bef1-8bb28933098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535891276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1535891276
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.896664171
Short name T16
Test name
Test status
Simulation time 25688387293 ps
CPU time 21.34 seconds
Started Mar 03 02:08:42 PM PST 24
Finished Mar 03 02:09:04 PM PST 24
Peak memory 237452 kb
Host smart-13ff41a8-c455-4258-9ed4-7d9814fc8f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896664171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.896664171
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2192112298
Short name T489
Test name
Test status
Simulation time 275728953 ps
CPU time 3.6 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:08:47 PM PST 24
Peak memory 218296 kb
Host smart-146d052b-8f14-4798-ad4d-776020b25d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192112298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2192112298
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.220539133
Short name T360
Test name
Test status
Simulation time 1103959430 ps
CPU time 2.69 seconds
Started Mar 03 02:08:42 PM PST 24
Finished Mar 03 02:08:45 PM PST 24
Peak memory 216752 kb
Host smart-fb8eecc3-11aa-448b-891b-5dff9aeea227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220539133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.220539133
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2243363820
Short name T866
Test name
Test status
Simulation time 7378845339 ps
CPU time 7.99 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:08:53 PM PST 24
Peak memory 222028 kb
Host smart-0c5f3013-9185-420a-86a4-a295858547fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2243363820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2243363820
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2688252869
Short name T158
Test name
Test status
Simulation time 426407172 ps
CPU time 0.93 seconds
Started Mar 03 02:08:48 PM PST 24
Finished Mar 03 02:08:49 PM PST 24
Peak memory 206304 kb
Host smart-a4039b25-e048-4bca-af8b-febf3e9e9220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688252869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2688252869
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1756427163
Short name T600
Test name
Test status
Simulation time 12056726972 ps
CPU time 36.64 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:09:19 PM PST 24
Peak memory 216272 kb
Host smart-52bcf629-91b2-46d3-8c03-dbefced74e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756427163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1756427163
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1263312209
Short name T68
Test name
Test status
Simulation time 6055586644 ps
CPU time 5.36 seconds
Started Mar 03 02:08:42 PM PST 24
Finished Mar 03 02:08:48 PM PST 24
Peak memory 216340 kb
Host smart-c8934279-11f8-49b6-b665-10a96af0f1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263312209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1263312209
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4270471774
Short name T303
Test name
Test status
Simulation time 138968727 ps
CPU time 1.06 seconds
Started Mar 03 02:08:46 PM PST 24
Finished Mar 03 02:08:48 PM PST 24
Peak memory 207624 kb
Host smart-a7327f4b-8f06-4c5f-8553-6df74df03337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270471774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4270471774
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.120306365
Short name T725
Test name
Test status
Simulation time 129507596 ps
CPU time 0.71 seconds
Started Mar 03 02:08:43 PM PST 24
Finished Mar 03 02:08:44 PM PST 24
Peak memory 205344 kb
Host smart-f328914a-3bc7-4ca4-bb3d-f7cdf4e20d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120306365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.120306365
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1794212887
Short name T985
Test name
Test status
Simulation time 2204255100 ps
CPU time 8.71 seconds
Started Mar 03 02:08:44 PM PST 24
Finished Mar 03 02:08:53 PM PST 24
Peak memory 221276 kb
Host smart-fa798e2e-0491-43f4-95da-fd6425e805ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794212887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1794212887
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3561914544
Short name T460
Test name
Test status
Simulation time 37739272 ps
CPU time 0.72 seconds
Started Mar 03 02:05:56 PM PST 24
Finished Mar 03 02:05:57 PM PST 24
Peak memory 204300 kb
Host smart-b65debc8-4bba-496b-b721-328988b4fe74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561914544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
561914544
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1989500037
Short name T769
Test name
Test status
Simulation time 1221817435 ps
CPU time 5.47 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:06:04 PM PST 24
Peak memory 219172 kb
Host smart-f087ff6a-4146-425d-914a-3169d0b9a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989500037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1989500037
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.409838200
Short name T397
Test name
Test status
Simulation time 17944565 ps
CPU time 0.78 seconds
Started Mar 03 02:06:04 PM PST 24
Finished Mar 03 02:06:04 PM PST 24
Peak memory 204952 kb
Host smart-79348c14-7389-485d-806d-4d523af23273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409838200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.409838200
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2368381526
Short name T767
Test name
Test status
Simulation time 13543485133 ps
CPU time 70.07 seconds
Started Mar 03 02:06:03 PM PST 24
Finished Mar 03 02:07:13 PM PST 24
Peak memory 251616 kb
Host smart-53ad6c0f-796b-4d54-b0de-4458d5b95e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368381526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2368381526
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4002862353
Short name T452
Test name
Test status
Simulation time 7881771003 ps
CPU time 85.89 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:07:26 PM PST 24
Peak memory 256008 kb
Host smart-dfa37931-9d9c-41ef-baf1-545ea830c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002862353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4002862353
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2419544918
Short name T554
Test name
Test status
Simulation time 1547443357 ps
CPU time 15.54 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:16 PM PST 24
Peak memory 225560 kb
Host smart-05857880-a7a2-4033-8b5d-9dd6df083ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419544918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2419544918
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4010623402
Short name T219
Test name
Test status
Simulation time 101471178 ps
CPU time 2.63 seconds
Started Mar 03 02:05:57 PM PST 24
Finished Mar 03 02:05:59 PM PST 24
Peak memory 216700 kb
Host smart-36943dc2-2eeb-42df-9af6-c96daca47b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010623402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4010623402
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2451884909
Short name T237
Test name
Test status
Simulation time 24196565421 ps
CPU time 16.25 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:06:14 PM PST 24
Peak memory 235156 kb
Host smart-509b5291-766d-4650-a39f-ed8eccffc541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451884909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2451884909
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.566993413
Short name T455
Test name
Test status
Simulation time 32510420 ps
CPU time 1.1 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 216552 kb
Host smart-e909b074-8fad-4029-b485-3319ccaf6f0f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566993413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.566993413
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4128290474
Short name T662
Test name
Test status
Simulation time 241759817 ps
CPU time 3.56 seconds
Started Mar 03 02:05:57 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 233544 kb
Host smart-737c462c-bdec-4dcd-92e4-c1342488f56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128290474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4128290474
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2392235812
Short name T693
Test name
Test status
Simulation time 251326096 ps
CPU time 4.32 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:06:02 PM PST 24
Peak memory 218256 kb
Host smart-03f2b897-beb2-4185-a137-799297bebe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392235812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2392235812
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1004372648
Short name T403
Test name
Test status
Simulation time 17793520 ps
CPU time 0.76 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 216036 kb
Host smart-ae59374c-2f42-420c-bd4c-6e922b3f2089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004372648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1004372648
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.806562488
Short name T369
Test name
Test status
Simulation time 159427995 ps
CPU time 3.5 seconds
Started Mar 03 02:06:01 PM PST 24
Finished Mar 03 02:06:04 PM PST 24
Peak memory 218832 kb
Host smart-f5e626f0-b74c-4b73-99fd-877d53839739
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=806562488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.806562488
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.562814379
Short name T564
Test name
Test status
Simulation time 342632925 ps
CPU time 7.63 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:08 PM PST 24
Peak memory 220584 kb
Host smart-5670dcd7-eb24-4b86-8132-a35a0e09daf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562814379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.562814379
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.870220367
Short name T902
Test name
Test status
Simulation time 28820594476 ps
CPU time 32.64 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:06:31 PM PST 24
Peak memory 216344 kb
Host smart-137c556d-4bd6-44df-b46d-46141671c754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870220367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.870220367
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2642892024
Short name T694
Test name
Test status
Simulation time 6845940405 ps
CPU time 19.41 seconds
Started Mar 03 02:05:57 PM PST 24
Finished Mar 03 02:06:17 PM PST 24
Peak memory 216288 kb
Host smart-869f85ee-95fb-4175-a797-2cb155c5ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642892024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2642892024
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3889911243
Short name T457
Test name
Test status
Simulation time 68074596 ps
CPU time 0.73 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:00 PM PST 24
Peak memory 205364 kb
Host smart-69cb09cb-d3d8-445a-89f3-ae36762f3c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889911243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3889911243
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1266943294
Short name T590
Test name
Test status
Simulation time 111932775 ps
CPU time 0.85 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:00 PM PST 24
Peak memory 205348 kb
Host smart-b6254c38-24f4-4efc-bf45-d5ff316d8c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266943294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1266943294
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1464999081
Short name T618
Test name
Test status
Simulation time 3711098923 ps
CPU time 11.75 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:12 PM PST 24
Peak memory 237360 kb
Host smart-3cf71e6f-4244-4030-81d9-4685306c8871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464999081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1464999081
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2114492617
Short name T811
Test name
Test status
Simulation time 11778713 ps
CPU time 0.73 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 205216 kb
Host smart-4e931349-c8c6-4fa3-bae3-99275b2e4523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114492617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
114492617
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1182062203
Short name T931
Test name
Test status
Simulation time 316414993 ps
CPU time 3.92 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:06:03 PM PST 24
Peak memory 219892 kb
Host smart-14b16c98-4b2d-4503-92ad-d58e6212f566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182062203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1182062203
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3251769813
Short name T709
Test name
Test status
Simulation time 19474884 ps
CPU time 0.78 seconds
Started Mar 03 02:06:01 PM PST 24
Finished Mar 03 02:06:02 PM PST 24
Peak memory 205312 kb
Host smart-687570c2-311f-48eb-98ac-5873df4e51a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251769813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3251769813
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1315811371
Short name T90
Test name
Test status
Simulation time 59162410649 ps
CPU time 156.63 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:08:37 PM PST 24
Peak memory 240712 kb
Host smart-d8f3879b-eb48-47aa-a0b9-66e250d09be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315811371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1315811371
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3661942990
Short name T724
Test name
Test status
Simulation time 123928981557 ps
CPU time 100.4 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:07:39 PM PST 24
Peak memory 260048 kb
Host smart-1bc55d30-85d4-407a-a019-8a6d2da5fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661942990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3661942990
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3541283291
Short name T873
Test name
Test status
Simulation time 34106488583 ps
CPU time 92.86 seconds
Started Mar 03 02:05:56 PM PST 24
Finished Mar 03 02:07:29 PM PST 24
Peak memory 253132 kb
Host smart-2c445f8d-0216-432d-827a-4d050ab82f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541283291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3541283291
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.157839559
Short name T327
Test name
Test status
Simulation time 13486206830 ps
CPU time 23.84 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:24 PM PST 24
Peak memory 234156 kb
Host smart-7f9290ee-c1b3-454a-8f78-12336a9ae24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157839559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.157839559
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.546485761
Short name T705
Test name
Test status
Simulation time 608429085 ps
CPU time 5.45 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:12 PM PST 24
Peak memory 218536 kb
Host smart-5227c22b-8663-478b-9b1a-d9abadeb718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546485761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.546485761
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.416297126
Short name T496
Test name
Test status
Simulation time 54322575572 ps
CPU time 33.71 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:33 PM PST 24
Peak memory 232524 kb
Host smart-2f01c79b-96c6-49a8-b5c8-bc717907707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416297126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.416297126
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1555250071
Short name T886
Test name
Test status
Simulation time 81814098 ps
CPU time 1.11 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:05:59 PM PST 24
Peak memory 216532 kb
Host smart-9b3d59f1-3004-4b28-94f0-c16b3dab17cd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555250071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1555250071
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1741334900
Short name T817
Test name
Test status
Simulation time 8557737381 ps
CPU time 8.18 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:06:07 PM PST 24
Peak memory 232840 kb
Host smart-53401f52-4eb9-42a4-8cf5-72d1e9d59488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741334900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1741334900
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2680282724
Short name T472
Test name
Test status
Simulation time 2368509748 ps
CPU time 15.89 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:16 PM PST 24
Peak memory 250120 kb
Host smart-6e11a8d6-4635-433e-86ce-f743b6f10f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680282724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2680282724
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.563971876
Short name T641
Test name
Test status
Simulation time 15680365 ps
CPU time 0.78 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 216064 kb
Host smart-3ac7ca39-091c-400d-9ef1-8a2d941d5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563971876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.563971876
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1111080412
Short name T770
Test name
Test status
Simulation time 956850765 ps
CPU time 5.43 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:05 PM PST 24
Peak memory 218556 kb
Host smart-88a7f1f9-7b41-4e47-8b45-479158e8f909
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1111080412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1111080412
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1676426985
Short name T263
Test name
Test status
Simulation time 75678076726 ps
CPU time 411.34 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:12:52 PM PST 24
Peak memory 300656 kb
Host smart-29f7dfe4-d2e1-4647-a24a-19e492bce594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676426985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1676426985
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2617380337
Short name T853
Test name
Test status
Simulation time 4429457674 ps
CPU time 23.46 seconds
Started Mar 03 02:06:03 PM PST 24
Finished Mar 03 02:06:26 PM PST 24
Peak memory 216272 kb
Host smart-c0181e6d-4bdb-4243-bb11-12fc22eb6078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617380337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2617380337
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.576815327
Short name T339
Test name
Test status
Simulation time 7727127185 ps
CPU time 27.45 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:28 PM PST 24
Peak memory 216280 kb
Host smart-f9b26a3b-f8cf-41b5-a04f-c8ef71eae83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576815327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.576815327
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3751998367
Short name T911
Test name
Test status
Simulation time 21810479 ps
CPU time 1.2 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:00 PM PST 24
Peak memory 207624 kb
Host smart-61574add-b8af-4cd5-bd4d-19698eaecca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751998367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3751998367
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2361782802
Short name T703
Test name
Test status
Simulation time 124743507 ps
CPU time 0.97 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:00 PM PST 24
Peak memory 206368 kb
Host smart-d80a6bc7-0565-4d6c-97c5-ee4ce4d3259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361782802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2361782802
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3104972564
Short name T513
Test name
Test status
Simulation time 14632862050 ps
CPU time 19.39 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:20 PM PST 24
Peak memory 227540 kb
Host smart-d74d23f7-dab6-488f-98d6-bc58a39821f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104972564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3104972564
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1516385277
Short name T497
Test name
Test status
Simulation time 13927824 ps
CPU time 0.71 seconds
Started Mar 03 02:06:03 PM PST 24
Finished Mar 03 02:06:03 PM PST 24
Peak memory 204752 kb
Host smart-6f45fc5b-6851-498f-8331-c22992e21040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516385277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
516385277
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.760216706
Short name T970
Test name
Test status
Simulation time 4895292437 ps
CPU time 8.9 seconds
Started Mar 03 02:06:11 PM PST 24
Finished Mar 03 02:06:20 PM PST 24
Peak memory 235252 kb
Host smart-f4a9bee7-a41f-4212-a591-9ca80e0120be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760216706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.760216706
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2897503010
Short name T895
Test name
Test status
Simulation time 57489069 ps
CPU time 0.83 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 205988 kb
Host smart-dab779ee-3398-461e-a472-f1e4b119f35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897503010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2897503010
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2567253806
Short name T179
Test name
Test status
Simulation time 36896570373 ps
CPU time 81.14 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:07:27 PM PST 24
Peak memory 250104 kb
Host smart-f433daf1-3a4c-4211-8a6f-76d84562aa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567253806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2567253806
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3575309702
Short name T259
Test name
Test status
Simulation time 82236453449 ps
CPU time 567.88 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:15:35 PM PST 24
Peak memory 250208 kb
Host smart-52e55644-054f-4354-ad4a-98b291ace1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575309702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3575309702
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.955179712
Short name T192
Test name
Test status
Simulation time 36489256534 ps
CPU time 233.19 seconds
Started Mar 03 02:06:04 PM PST 24
Finished Mar 03 02:09:58 PM PST 24
Peak memory 237396 kb
Host smart-2cbf0493-671f-4f8f-b2eb-c48c33f986a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955179712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
955179712
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2714909545
Short name T48
Test name
Test status
Simulation time 20982565952 ps
CPU time 29.08 seconds
Started Mar 03 02:06:10 PM PST 24
Finished Mar 03 02:06:40 PM PST 24
Peak memory 231092 kb
Host smart-437cdeff-8f91-4fda-8b04-ad9e06c1ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714909545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2714909545
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2675671505
Short name T964
Test name
Test status
Simulation time 4196356300 ps
CPU time 7.86 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:06:07 PM PST 24
Peak memory 234340 kb
Host smart-74af704d-defe-4ad8-a81d-3c628a0c40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675671505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2675671505
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.506381601
Short name T801
Test name
Test status
Simulation time 2913278505 ps
CPU time 12.3 seconds
Started Mar 03 02:05:59 PM PST 24
Finished Mar 03 02:06:12 PM PST 24
Peak memory 239928 kb
Host smart-767f322a-2b1a-4d13-bb76-30e8e89adf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506381601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.506381601
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3137609208
Short name T547
Test name
Test status
Simulation time 34441294 ps
CPU time 1.16 seconds
Started Mar 03 02:05:58 PM PST 24
Finished Mar 03 02:05:59 PM PST 24
Peak memory 216464 kb
Host smart-69e5357b-3045-4c99-8d71-f1be8f0a90ad
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137609208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3137609208
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2511971671
Short name T854
Test name
Test status
Simulation time 1807973872 ps
CPU time 5.66 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:06 PM PST 24
Peak memory 224344 kb
Host smart-301b77cf-3ada-4685-9a4f-09579d582b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511971671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2511971671
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2114478338
Short name T565
Test name
Test status
Simulation time 1731924035 ps
CPU time 3.13 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:10 PM PST 24
Peak memory 233376 kb
Host smart-c550b09b-bb8e-4243-af48-f534e057cbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114478338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2114478338
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.1376810879
Short name T576
Test name
Test status
Simulation time 49607775 ps
CPU time 0.75 seconds
Started Mar 03 02:06:02 PM PST 24
Finished Mar 03 02:06:03 PM PST 24
Peak memory 216072 kb
Host smart-5d3c336a-8205-4962-bec1-aa97fbd59839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376810879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.1376810879
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3433944367
Short name T309
Test name
Test status
Simulation time 991993998 ps
CPU time 6.33 seconds
Started Mar 03 02:06:03 PM PST 24
Finished Mar 03 02:06:10 PM PST 24
Peak memory 222460 kb
Host smart-944e9644-6fb1-4f2c-80e3-943909d727b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3433944367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3433944367
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1623181693
Short name T733
Test name
Test status
Simulation time 48429743 ps
CPU time 1.02 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:06:08 PM PST 24
Peak memory 205948 kb
Host smart-d1493960-0ef2-4f70-ba55-82d5e52a63c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623181693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1623181693
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3097806447
Short name T418
Test name
Test status
Simulation time 15433068145 ps
CPU time 10.61 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:11 PM PST 24
Peak memory 216300 kb
Host smart-37fa5150-4392-4a85-9c45-b7a64f5dd788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097806447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3097806447
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2953603939
Short name T386
Test name
Test status
Simulation time 560217469 ps
CPU time 2.51 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:03 PM PST 24
Peak memory 207828 kb
Host smart-eae7305a-2220-4c7c-bab8-b5145c0a6b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953603939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2953603939
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1271595472
Short name T936
Test name
Test status
Simulation time 47826250 ps
CPU time 1.24 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:02 PM PST 24
Peak memory 207812 kb
Host smart-879e000f-e896-4c59-9cb9-c3cb0464f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271595472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1271595472
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2806732120
Short name T850
Test name
Test status
Simulation time 91367637 ps
CPU time 0.81 seconds
Started Mar 03 02:06:00 PM PST 24
Finished Mar 03 02:06:01 PM PST 24
Peak memory 205348 kb
Host smart-ac359201-6bb6-4bf8-b603-1788ec49359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806732120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2806732120
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1429230546
Short name T396
Test name
Test status
Simulation time 5231986634 ps
CPU time 21.03 seconds
Started Mar 03 02:05:57 PM PST 24
Finished Mar 03 02:06:18 PM PST 24
Peak memory 232564 kb
Host smart-aac64ccb-2a75-44fb-a7d5-8e780dbdea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429230546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1429230546
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3943558442
Short name T507
Test name
Test status
Simulation time 14793048 ps
CPU time 0.75 seconds
Started Mar 03 02:06:08 PM PST 24
Finished Mar 03 02:06:09 PM PST 24
Peak memory 204864 kb
Host smart-132bc237-a1ec-4e15-ac8c-cecf11596e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943558442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
943558442
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.743592686
Short name T364
Test name
Test status
Simulation time 215594653 ps
CPU time 2.89 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:06:10 PM PST 24
Peak memory 233560 kb
Host smart-f94c0a44-a726-43ff-a236-3a3753e29bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743592686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.743592686
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1081346970
Short name T560
Test name
Test status
Simulation time 19382308 ps
CPU time 0.78 seconds
Started Mar 03 02:06:11 PM PST 24
Finished Mar 03 02:06:12 PM PST 24
Peak memory 206336 kb
Host smart-9fe0d3e8-eaad-48c5-96bf-9cd0c2a0cad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081346970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1081346970
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1521959422
Short name T260
Test name
Test status
Simulation time 173448781739 ps
CPU time 217.32 seconds
Started Mar 03 02:06:08 PM PST 24
Finished Mar 03 02:09:45 PM PST 24
Peak memory 271684 kb
Host smart-6b53f8dd-b4eb-438d-83d8-109a7a475f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521959422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1521959422
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.151579511
Short name T934
Test name
Test status
Simulation time 4739519121 ps
CPU time 33.97 seconds
Started Mar 03 02:06:04 PM PST 24
Finished Mar 03 02:06:39 PM PST 24
Peak memory 236192 kb
Host smart-706efc08-87d1-4ee3-be02-13ae36780b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151579511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.151579511
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1333074373
Short name T58
Test name
Test status
Simulation time 53643438441 ps
CPU time 384.78 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:12:32 PM PST 24
Peak memory 257360 kb
Host smart-1d734a24-3516-4893-8429-79c6307cc836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333074373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1333074373
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2031307879
Short name T388
Test name
Test status
Simulation time 40070848257 ps
CPU time 52.04 seconds
Started Mar 03 02:06:10 PM PST 24
Finished Mar 03 02:07:03 PM PST 24
Peak memory 240832 kb
Host smart-9ad295be-c77e-4533-ae1e-b63ed54e2656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031307879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2031307879
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4176256501
Short name T362
Test name
Test status
Simulation time 505671527 ps
CPU time 4.72 seconds
Started Mar 03 02:06:05 PM PST 24
Finished Mar 03 02:06:10 PM PST 24
Peak memory 224324 kb
Host smart-566c3f1e-a1f1-4a89-8556-628feb078b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176256501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4176256501
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1067619338
Short name T239
Test name
Test status
Simulation time 93047354650 ps
CPU time 46.47 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:53 PM PST 24
Peak memory 232640 kb
Host smart-9ceb0330-3461-44eb-8b74-e38a5a0b3e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067619338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1067619338
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.4124640384
Short name T840
Test name
Test status
Simulation time 60844679 ps
CPU time 1.18 seconds
Started Mar 03 02:06:08 PM PST 24
Finished Mar 03 02:06:10 PM PST 24
Peak memory 216552 kb
Host smart-b66b8d0c-081b-4b32-8ee9-21e2af5f3c7f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124640384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.4124640384
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3909920114
Short name T346
Test name
Test status
Simulation time 4737915326 ps
CPU time 8.04 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 233508 kb
Host smart-ec6a3dab-6b0d-404c-9fe7-38162d3bec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909920114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3909920114
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2263638024
Short name T478
Test name
Test status
Simulation time 16741090320 ps
CPU time 15.83 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:22 PM PST 24
Peak memory 240656 kb
Host smart-cb5d03e5-e988-442f-82cb-ad9ce8db927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263638024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2263638024
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.4044461042
Short name T63
Test name
Test status
Simulation time 37893203 ps
CPU time 0.75 seconds
Started Mar 03 02:06:08 PM PST 24
Finished Mar 03 02:06:10 PM PST 24
Peak memory 216068 kb
Host smart-9fbd9656-b436-4e9b-ab72-f23c192c2068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044461042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.4044461042
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2084216716
Short name T864
Test name
Test status
Simulation time 415081806 ps
CPU time 4.69 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:06:13 PM PST 24
Peak memory 222440 kb
Host smart-4200b70a-268f-4a37-a746-18a97ff8d8d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2084216716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2084216716
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1878731748
Short name T566
Test name
Test status
Simulation time 189952070 ps
CPU time 2.68 seconds
Started Mar 03 02:06:10 PM PST 24
Finished Mar 03 02:06:13 PM PST 24
Peak memory 216224 kb
Host smart-6ff6eea9-1b87-4ee9-820b-b76d520bbc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878731748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1878731748
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3501934740
Short name T491
Test name
Test status
Simulation time 17954961726 ps
CPU time 19.24 seconds
Started Mar 03 02:06:08 PM PST 24
Finished Mar 03 02:06:27 PM PST 24
Peak memory 216324 kb
Host smart-1b06a240-f044-41f5-b836-93fe77c1f223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501934740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3501934740
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2682000014
Short name T659
Test name
Test status
Simulation time 1117771157 ps
CPU time 5.94 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:13 PM PST 24
Peak memory 216092 kb
Host smart-be829859-b2e5-4c7b-86ee-2376a6a8e0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682000014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2682000014
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3384454435
Short name T774
Test name
Test status
Simulation time 119365654 ps
CPU time 0.98 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:08 PM PST 24
Peak memory 206388 kb
Host smart-2a22e31a-0512-4f78-ada5-86f34aea683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384454435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3384454435
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4222739315
Short name T647
Test name
Test status
Simulation time 12394879546 ps
CPU time 14.42 seconds
Started Mar 03 02:06:08 PM PST 24
Finished Mar 03 02:06:23 PM PST 24
Peak memory 218780 kb
Host smart-baac9692-d897-4ff0-b567-fb352bcd829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222739315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4222739315
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2096104032
Short name T628
Test name
Test status
Simulation time 46755849 ps
CPU time 0.75 seconds
Started Mar 03 02:06:15 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 205184 kb
Host smart-0a8c2760-7e44-444a-bfb3-e731ac87dd90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096104032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
096104032
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4225585838
Short name T476
Test name
Test status
Simulation time 49562655 ps
CPU time 2.88 seconds
Started Mar 03 02:06:14 PM PST 24
Finished Mar 03 02:06:17 PM PST 24
Peak memory 233416 kb
Host smart-b838433e-24c2-4902-ac85-fd122ae0b0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225585838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4225585838
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3202883469
Short name T591
Test name
Test status
Simulation time 50616035 ps
CPU time 0.81 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:06:08 PM PST 24
Peak memory 206336 kb
Host smart-eaabf55e-808c-4b10-9ad4-d3919a02edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202883469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3202883469
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1724434144
Short name T656
Test name
Test status
Simulation time 20029317292 ps
CPU time 54.56 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:07:08 PM PST 24
Peak memory 269088 kb
Host smart-4b8a659a-5430-41b4-a411-d02f9f2e9502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724434144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1724434144
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2230889692
Short name T248
Test name
Test status
Simulation time 149462861909 ps
CPU time 630.23 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:16:43 PM PST 24
Peak memory 265448 kb
Host smart-2594d542-899f-44dd-8e23-ee53da503f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230889692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2230889692
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1499418421
Short name T56
Test name
Test status
Simulation time 104028135836 ps
CPU time 223.9 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:09:58 PM PST 24
Peak memory 256032 kb
Host smart-1ed3f8f2-404a-415f-8b53-221c54c9151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499418421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1499418421
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2039299564
Short name T145
Test name
Test status
Simulation time 2172793884 ps
CPU time 11.93 seconds
Started Mar 03 02:06:13 PM PST 24
Finished Mar 03 02:06:26 PM PST 24
Peak memory 248160 kb
Host smart-10b9a0e1-0375-46bf-9fda-0c4cce15436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039299564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2039299564
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2534387818
Short name T671
Test name
Test status
Simulation time 656729291 ps
CPU time 4.43 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:06:11 PM PST 24
Peak memory 217428 kb
Host smart-f6e63c0b-d864-4bdb-ab78-2460def384c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534387818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2534387818
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1482230754
Short name T203
Test name
Test status
Simulation time 2828723724 ps
CPU time 13.71 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:06:21 PM PST 24
Peak memory 232200 kb
Host smart-929efc7a-41d4-47b3-9e9f-66e81069f51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482230754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1482230754
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2711424822
Short name T471
Test name
Test status
Simulation time 442274009 ps
CPU time 3.78 seconds
Started Mar 03 02:06:05 PM PST 24
Finished Mar 03 02:06:09 PM PST 24
Peak memory 233236 kb
Host smart-a1c2b234-a754-4c49-84b6-6feb6340229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711424822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2711424822
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.225811783
Short name T957
Test name
Test status
Simulation time 5656240944 ps
CPU time 18.1 seconds
Started Mar 03 02:06:10 PM PST 24
Finished Mar 03 02:06:29 PM PST 24
Peak memory 217340 kb
Host smart-7600ccf5-7e59-4975-8a4d-6ffbd27a4217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225811783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.225811783
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1441485877
Short name T882
Test name
Test status
Simulation time 18033171 ps
CPU time 0.8 seconds
Started Mar 03 02:06:06 PM PST 24
Finished Mar 03 02:06:07 PM PST 24
Peak memory 216064 kb
Host smart-5a89fff5-341e-4764-8133-a687a7f02082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441485877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1441485877
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2333470731
Short name T375
Test name
Test status
Simulation time 398921276 ps
CPU time 3.38 seconds
Started Mar 03 02:06:12 PM PST 24
Finished Mar 03 02:06:15 PM PST 24
Peak memory 222132 kb
Host smart-53ec5ee9-1bcc-4517-9ae0-902946c3447d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2333470731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2333470731
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1846224121
Short name T973
Test name
Test status
Simulation time 37707870 ps
CPU time 0.96 seconds
Started Mar 03 02:06:19 PM PST 24
Finished Mar 03 02:06:20 PM PST 24
Peak memory 206180 kb
Host smart-9416ceef-0f21-4723-8965-3886626fe60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846224121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1846224121
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1995069758
Short name T420
Test name
Test status
Simulation time 34286931707 ps
CPU time 45.43 seconds
Started Mar 03 02:06:05 PM PST 24
Finished Mar 03 02:06:50 PM PST 24
Peak memory 216320 kb
Host smart-a5c7f398-0179-411a-93f0-3ef2bec40678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995069758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1995069758
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1593236499
Short name T20
Test name
Test status
Simulation time 6737443193 ps
CPU time 11.29 seconds
Started Mar 03 02:06:08 PM PST 24
Finished Mar 03 02:06:19 PM PST 24
Peak memory 216256 kb
Host smart-f252b3a4-e04b-47fd-ad96-6ff5bafc2250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593236499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1593236499
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1064885386
Short name T378
Test name
Test status
Simulation time 63702459 ps
CPU time 1.57 seconds
Started Mar 03 02:06:10 PM PST 24
Finished Mar 03 02:06:12 PM PST 24
Peak memory 216264 kb
Host smart-f3ad2c0d-7323-4084-8077-b5717708f7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064885386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1064885386
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.210252734
Short name T777
Test name
Test status
Simulation time 279566310 ps
CPU time 1.02 seconds
Started Mar 03 02:06:07 PM PST 24
Finished Mar 03 02:06:08 PM PST 24
Peak memory 206364 kb
Host smart-933d0224-1f3c-42fb-8de8-c67ca535abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210252734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.210252734
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2442946930
Short name T473
Test name
Test status
Simulation time 3600440932 ps
CPU time 4.39 seconds
Started Mar 03 02:06:17 PM PST 24
Finished Mar 03 02:06:21 PM PST 24
Peak memory 224408 kb
Host smart-170773ff-9106-4e85-a79a-9481c08da0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442946930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2442946930
Directory /workspace/9.spi_device_upload/latest
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