| T807 |
/workspace/coverage/default/5.spi_device_read_buffer_direct.2413405397 |
|
|
Mar 05 01:37:02 PM PST 24 |
Mar 05 01:37:07 PM PST 24 |
1119848585 ps |
| T808 |
/workspace/coverage/default/9.spi_device_csb_read.1530033294 |
|
|
Mar 05 01:37:36 PM PST 24 |
Mar 05 01:37:37 PM PST 24 |
67744538 ps |
| T278 |
/workspace/coverage/default/43.spi_device_stress_all.4030551629 |
|
|
Mar 05 01:43:02 PM PST 24 |
Mar 05 01:47:34 PM PST 24 |
69958450696 ps |
| T809 |
/workspace/coverage/default/12.spi_device_stress_all.732259625 |
|
|
Mar 05 01:38:20 PM PST 24 |
Mar 05 01:45:53 PM PST 24 |
282555509104 ps |
| T810 |
/workspace/coverage/default/36.spi_device_flash_all.3384631955 |
|
|
Mar 05 01:41:59 PM PST 24 |
Mar 05 01:42:42 PM PST 24 |
8743890452 ps |
| T811 |
/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.848988976 |
|
|
Mar 05 01:41:11 PM PST 24 |
Mar 05 01:41:25 PM PST 24 |
7353114048 ps |
| T275 |
/workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4008847342 |
|
|
Mar 05 01:40:49 PM PST 24 |
Mar 05 01:42:09 PM PST 24 |
14397143317 ps |
| T812 |
/workspace/coverage/default/37.spi_device_alert_test.2730888121 |
|
|
Mar 05 01:42:15 PM PST 24 |
Mar 05 01:42:15 PM PST 24 |
43299991 ps |
| T813 |
/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2898023729 |
|
|
Mar 05 01:40:02 PM PST 24 |
Mar 05 01:40:10 PM PST 24 |
2576511420 ps |
| T814 |
/workspace/coverage/default/47.spi_device_tpm_rw.2074784035 |
|
|
Mar 05 01:43:32 PM PST 24 |
Mar 05 01:43:35 PM PST 24 |
39848832 ps |
| T815 |
/workspace/coverage/default/45.spi_device_mailbox.262039414 |
|
|
Mar 05 01:43:17 PM PST 24 |
Mar 05 01:43:45 PM PST 24 |
45665011844 ps |
| T816 |
/workspace/coverage/default/7.spi_device_flash_and_tpm.706764062 |
|
|
Mar 05 01:37:24 PM PST 24 |
Mar 05 01:39:00 PM PST 24 |
76066298249 ps |
| T817 |
/workspace/coverage/default/3.spi_device_flash_mode.1425218982 |
|
|
Mar 05 01:36:39 PM PST 24 |
Mar 05 01:37:05 PM PST 24 |
11023536941 ps |
| T42 |
/workspace/coverage/default/7.spi_device_stress_all.2380143024 |
|
|
Mar 05 01:37:24 PM PST 24 |
Mar 05 01:47:01 PM PST 24 |
72149652382 ps |
| T818 |
/workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.27627466 |
|
|
Mar 05 01:37:57 PM PST 24 |
Mar 05 01:39:14 PM PST 24 |
37046778825 ps |
| T819 |
/workspace/coverage/default/19.spi_device_flash_mode.3526892617 |
|
|
Mar 05 01:39:23 PM PST 24 |
Mar 05 01:39:42 PM PST 24 |
1796577612 ps |
| T820 |
/workspace/coverage/default/43.spi_device_mailbox.3602994269 |
|
|
Mar 05 01:43:02 PM PST 24 |
Mar 05 01:43:11 PM PST 24 |
985585434 ps |
| T821 |
/workspace/coverage/default/6.spi_device_tpm_sts_read.3777411649 |
|
|
Mar 05 01:37:11 PM PST 24 |
Mar 05 01:37:12 PM PST 24 |
167585218 ps |
| T822 |
/workspace/coverage/default/47.spi_device_intercept.115970348 |
|
|
Mar 05 01:43:33 PM PST 24 |
Mar 05 01:43:38 PM PST 24 |
838450059 ps |
| T823 |
/workspace/coverage/default/47.spi_device_tpm_all.3823985427 |
|
|
Mar 05 01:43:33 PM PST 24 |
Mar 05 01:44:08 PM PST 24 |
37952327288 ps |
| T824 |
/workspace/coverage/default/32.spi_device_pass_cmd_filtering.2505882014 |
|
|
Mar 05 01:41:20 PM PST 24 |
Mar 05 01:41:25 PM PST 24 |
2494966809 ps |
| T81 |
/workspace/coverage/default/45.spi_device_stress_all.461171051 |
|
|
Mar 05 01:43:23 PM PST 24 |
Mar 05 01:50:39 PM PST 24 |
284235233790 ps |
| T825 |
/workspace/coverage/default/17.spi_device_flash_all.3716822115 |
|
|
Mar 05 01:39:01 PM PST 24 |
Mar 05 01:39:47 PM PST 24 |
7469885819 ps |
| T826 |
/workspace/coverage/default/33.spi_device_cfg_cmd.2030325648 |
|
|
Mar 05 01:41:35 PM PST 24 |
Mar 05 01:41:39 PM PST 24 |
688321688 ps |
| T827 |
/workspace/coverage/default/15.spi_device_ram_cfg.1466440698 |
|
|
Mar 05 01:38:40 PM PST 24 |
Mar 05 01:38:41 PM PST 24 |
17870930 ps |
| T828 |
/workspace/coverage/default/46.spi_device_csb_read.3787281121 |
|
|
Mar 05 01:43:24 PM PST 24 |
Mar 05 01:43:25 PM PST 24 |
41114580 ps |
| T829 |
/workspace/coverage/default/17.spi_device_csb_read.3651237299 |
|
|
Mar 05 01:38:55 PM PST 24 |
Mar 05 01:38:57 PM PST 24 |
52067460 ps |
| T830 |
/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2346828080 |
|
|
Mar 05 01:42:38 PM PST 24 |
Mar 05 01:42:46 PM PST 24 |
1850352093 ps |
| T831 |
/workspace/coverage/default/4.spi_device_tpm_rw.1555829499 |
|
|
Mar 05 01:36:45 PM PST 24 |
Mar 05 01:36:47 PM PST 24 |
68389652 ps |
| T832 |
/workspace/coverage/default/12.spi_device_flash_and_tpm.1814120193 |
|
|
Mar 05 01:38:13 PM PST 24 |
Mar 05 01:45:49 PM PST 24 |
71020751928 ps |
| T833 |
/workspace/coverage/default/24.spi_device_upload.1238266144 |
|
|
Mar 05 01:40:13 PM PST 24 |
Mar 05 01:40:18 PM PST 24 |
396872828 ps |
| T834 |
/workspace/coverage/default/11.spi_device_mem_parity.2202199694 |
|
|
Mar 05 01:37:58 PM PST 24 |
Mar 05 01:37:59 PM PST 24 |
194419829 ps |
| T835 |
/workspace/coverage/default/37.spi_device_upload.952155479 |
|
|
Mar 05 01:42:09 PM PST 24 |
Mar 05 01:42:15 PM PST 24 |
563052825 ps |
| T836 |
/workspace/coverage/default/4.spi_device_flash_mode.1202799208 |
|
|
Mar 05 01:36:55 PM PST 24 |
Mar 05 01:37:21 PM PST 24 |
9526204534 ps |
| T837 |
/workspace/coverage/default/26.spi_device_flash_mode.4157515426 |
|
|
Mar 05 01:40:31 PM PST 24 |
Mar 05 01:40:38 PM PST 24 |
302059525 ps |
| T838 |
/workspace/coverage/default/22.spi_device_mailbox.2543119303 |
|
|
Mar 05 01:39:57 PM PST 24 |
Mar 05 01:40:25 PM PST 24 |
7829008022 ps |
| T839 |
/workspace/coverage/default/6.spi_device_mailbox.2427186446 |
|
|
Mar 05 01:37:09 PM PST 24 |
Mar 05 01:37:18 PM PST 24 |
3321435806 ps |
| T840 |
/workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1995945626 |
|
|
Mar 05 01:41:21 PM PST 24 |
Mar 05 01:41:30 PM PST 24 |
1543363321 ps |
| T841 |
/workspace/coverage/default/25.spi_device_tpm_rw.1627134979 |
|
|
Mar 05 01:40:10 PM PST 24 |
Mar 05 01:40:13 PM PST 24 |
133839487 ps |
| T842 |
/workspace/coverage/default/49.spi_device_tpm_sts_read.3649866445 |
|
|
Mar 05 01:43:38 PM PST 24 |
Mar 05 01:43:39 PM PST 24 |
105925388 ps |
| T843 |
/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.253238975 |
|
|
Mar 05 01:40:09 PM PST 24 |
Mar 05 01:40:19 PM PST 24 |
36316593435 ps |
| T844 |
/workspace/coverage/default/27.spi_device_tpm_rw.2258973895 |
|
|
Mar 05 01:40:35 PM PST 24 |
Mar 05 01:40:39 PM PST 24 |
243505890 ps |
| T845 |
/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1616899603 |
|
|
Mar 05 01:39:05 PM PST 24 |
Mar 05 01:41:16 PM PST 24 |
13277204308 ps |
| T846 |
/workspace/coverage/default/31.spi_device_stress_all.2677674161 |
|
|
Mar 05 01:41:22 PM PST 24 |
Mar 05 01:45:09 PM PST 24 |
35412336581 ps |
| T285 |
/workspace/coverage/default/10.spi_device_flash_and_tpm.3382529464 |
|
|
Mar 05 01:37:56 PM PST 24 |
Mar 05 01:39:29 PM PST 24 |
13981362512 ps |
| T847 |
/workspace/coverage/default/3.spi_device_flash_and_tpm.1649850999 |
|
|
Mar 05 01:36:39 PM PST 24 |
Mar 05 01:42:50 PM PST 24 |
217946059717 ps |
| T848 |
/workspace/coverage/default/39.spi_device_pass_cmd_filtering.4113118575 |
|
|
Mar 05 01:42:20 PM PST 24 |
Mar 05 01:43:05 PM PST 24 |
18102192765 ps |
| T849 |
/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2926117466 |
|
|
Mar 05 01:37:07 PM PST 24 |
Mar 05 01:37:24 PM PST 24 |
6324817377 ps |
| T850 |
/workspace/coverage/default/32.spi_device_csb_read.1206942630 |
|
|
Mar 05 01:41:19 PM PST 24 |
Mar 05 01:41:20 PM PST 24 |
52865365 ps |
| T851 |
/workspace/coverage/default/9.spi_device_intercept.2702114947 |
|
|
Mar 05 01:37:44 PM PST 24 |
Mar 05 01:37:49 PM PST 24 |
63224296 ps |
| T852 |
/workspace/coverage/default/6.spi_device_intercept.3947475583 |
|
|
Mar 05 01:37:13 PM PST 24 |
Mar 05 01:37:16 PM PST 24 |
124710822 ps |
| T853 |
/workspace/coverage/default/29.spi_device_csb_read.247520701 |
|
|
Mar 05 01:40:50 PM PST 24 |
Mar 05 01:40:51 PM PST 24 |
28719971 ps |
| T854 |
/workspace/coverage/default/41.spi_device_mailbox.2303742349 |
|
|
Mar 05 01:42:44 PM PST 24 |
Mar 05 01:43:18 PM PST 24 |
27424736252 ps |
| T82 |
/workspace/coverage/default/28.spi_device_tpm_all.3043889581 |
|
|
Mar 05 01:40:51 PM PST 24 |
Mar 05 01:41:03 PM PST 24 |
11513229015 ps |
| T855 |
/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1613197005 |
|
|
Mar 05 01:43:43 PM PST 24 |
Mar 05 01:43:57 PM PST 24 |
4955772988 ps |
| T856 |
/workspace/coverage/default/45.spi_device_upload.3350009914 |
|
|
Mar 05 01:43:18 PM PST 24 |
Mar 05 01:43:30 PM PST 24 |
3886688647 ps |
| T857 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.391664626 |
|
|
Mar 05 01:38:50 PM PST 24 |
Mar 05 01:38:58 PM PST 24 |
647693852 ps |
| T858 |
/workspace/coverage/default/28.spi_device_cfg_cmd.500134268 |
|
|
Mar 05 01:40:50 PM PST 24 |
Mar 05 01:40:57 PM PST 24 |
4860879377 ps |
| T859 |
/workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3692914050 |
|
|
Mar 05 01:38:56 PM PST 24 |
Mar 05 01:39:13 PM PST 24 |
2974871299 ps |
| T860 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.4145749921 |
|
|
Mar 05 01:36:33 PM PST 24 |
Mar 05 01:36:38 PM PST 24 |
1186156407 ps |
| T861 |
/workspace/coverage/default/47.spi_device_flash_and_tpm.2618948582 |
|
|
Mar 05 01:43:32 PM PST 24 |
Mar 05 01:44:54 PM PST 24 |
54712094623 ps |
| T862 |
/workspace/coverage/default/23.spi_device_tpm_sts_read.3286104067 |
|
|
Mar 05 01:39:58 PM PST 24 |
Mar 05 01:40:04 PM PST 24 |
81172031 ps |
| T863 |
/workspace/coverage/default/7.spi_device_tpm_rw.3019457995 |
|
|
Mar 05 01:37:16 PM PST 24 |
Mar 05 01:37:18 PM PST 24 |
461100785 ps |
| T864 |
/workspace/coverage/default/15.spi_device_read_buffer_direct.3944623386 |
|
|
Mar 05 01:38:46 PM PST 24 |
Mar 05 01:38:50 PM PST 24 |
232625542 ps |
| T865 |
/workspace/coverage/default/23.spi_device_pass_cmd_filtering.2198576357 |
|
|
Mar 05 01:40:02 PM PST 24 |
Mar 05 01:40:13 PM PST 24 |
7646945362 ps |
| T866 |
/workspace/coverage/default/14.spi_device_flash_and_tpm.2981676664 |
|
|
Mar 05 01:38:38 PM PST 24 |
Mar 05 01:41:11 PM PST 24 |
69750095672 ps |
| T867 |
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3302653431 |
|
|
Mar 05 01:37:44 PM PST 24 |
Mar 05 01:37:54 PM PST 24 |
1522577681 ps |
| T868 |
/workspace/coverage/default/32.spi_device_upload.1314955287 |
|
|
Mar 05 01:41:20 PM PST 24 |
Mar 05 01:41:24 PM PST 24 |
913073739 ps |
| T869 |
/workspace/coverage/default/49.spi_device_tpm_all.198695866 |
|
|
Mar 05 01:43:37 PM PST 24 |
Mar 05 01:44:05 PM PST 24 |
2870349261 ps |
| T870 |
/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.183129179 |
|
|
Mar 05 01:38:34 PM PST 24 |
Mar 05 01:39:04 PM PST 24 |
20280235171 ps |
| T871 |
/workspace/coverage/default/39.spi_device_mailbox.4025437432 |
|
|
Mar 05 01:42:25 PM PST 24 |
Mar 05 01:42:28 PM PST 24 |
88134633 ps |
| T872 |
/workspace/coverage/default/46.spi_device_tpm_sts_read.5504791 |
|
|
Mar 05 01:43:24 PM PST 24 |
Mar 05 01:43:25 PM PST 24 |
95194825 ps |
| T873 |
/workspace/coverage/default/29.spi_device_intercept.2217568190 |
|
|
Mar 05 01:40:51 PM PST 24 |
Mar 05 01:40:55 PM PST 24 |
1028836884 ps |
| T874 |
/workspace/coverage/default/31.spi_device_tpm_rw.2923920119 |
|
|
Mar 05 01:41:08 PM PST 24 |
Mar 05 01:41:16 PM PST 24 |
673540887 ps |
| T875 |
/workspace/coverage/default/19.spi_device_intercept.410564749 |
|
|
Mar 05 01:39:26 PM PST 24 |
Mar 05 01:39:31 PM PST 24 |
964906013 ps |
| T876 |
/workspace/coverage/default/33.spi_device_tpm_all.3096559343 |
|
|
Mar 05 01:41:29 PM PST 24 |
Mar 05 01:42:01 PM PST 24 |
10598770465 ps |
| T877 |
/workspace/coverage/default/49.spi_device_upload.4215459757 |
|
|
Mar 05 01:43:47 PM PST 24 |
Mar 05 01:43:58 PM PST 24 |
3122051689 ps |
| T878 |
/workspace/coverage/default/25.spi_device_csb_read.2281455702 |
|
|
Mar 05 01:40:16 PM PST 24 |
Mar 05 01:40:17 PM PST 24 |
24827346 ps |
| T879 |
/workspace/coverage/default/33.spi_device_mailbox.2627375916 |
|
|
Mar 05 01:41:30 PM PST 24 |
Mar 05 01:41:43 PM PST 24 |
2527903509 ps |
| T880 |
/workspace/coverage/default/34.spi_device_intercept.932700159 |
|
|
Mar 05 01:41:36 PM PST 24 |
Mar 05 01:41:41 PM PST 24 |
520804918 ps |
| T881 |
/workspace/coverage/default/29.spi_device_tpm_rw.1908877822 |
|
|
Mar 05 01:40:52 PM PST 24 |
Mar 05 01:41:02 PM PST 24 |
228709303 ps |
| T882 |
/workspace/coverage/default/37.spi_device_tpm_all.3777887879 |
|
|
Mar 05 01:42:08 PM PST 24 |
Mar 05 01:42:24 PM PST 24 |
23472126958 ps |
| T883 |
/workspace/coverage/default/17.spi_device_tpm_sts_read.3833948985 |
|
|
Mar 05 01:38:55 PM PST 24 |
Mar 05 01:38:57 PM PST 24 |
66198636 ps |
| T884 |
/workspace/coverage/default/13.spi_device_mem_parity.1277801448 |
|
|
Mar 05 01:38:16 PM PST 24 |
Mar 05 01:38:18 PM PST 24 |
130885011 ps |
| T885 |
/workspace/coverage/default/5.spi_device_flash_mode.1508574816 |
|
|
Mar 05 01:37:03 PM PST 24 |
Mar 05 01:37:41 PM PST 24 |
9655511322 ps |
| T886 |
/workspace/coverage/default/4.spi_device_flash_all.144999335 |
|
|
Mar 05 01:36:53 PM PST 24 |
Mar 05 01:37:40 PM PST 24 |
27699256989 ps |
| T887 |
/workspace/coverage/default/46.spi_device_pass_addr_payload_swap.143009589 |
|
|
Mar 05 01:43:26 PM PST 24 |
Mar 05 01:43:34 PM PST 24 |
1699004463 ps |
| T888 |
/workspace/coverage/default/49.spi_device_csb_read.1782428620 |
|
|
Mar 05 01:43:38 PM PST 24 |
Mar 05 01:43:39 PM PST 24 |
22377270 ps |
| T889 |
/workspace/coverage/default/16.spi_device_intercept.2128795416 |
|
|
Mar 05 01:38:50 PM PST 24 |
Mar 05 01:38:55 PM PST 24 |
244905646 ps |
| T890 |
/workspace/coverage/default/48.spi_device_flash_mode.1380953608 |
|
|
Mar 05 01:43:37 PM PST 24 |
Mar 05 01:43:46 PM PST 24 |
3235291545 ps |
| T891 |
/workspace/coverage/default/14.spi_device_tpm_sts_read.1355451795 |
|
|
Mar 05 01:38:34 PM PST 24 |
Mar 05 01:38:35 PM PST 24 |
127524510 ps |
| T892 |
/workspace/coverage/default/29.spi_device_tpm_all.2963009753 |
|
|
Mar 05 01:40:49 PM PST 24 |
Mar 05 01:40:55 PM PST 24 |
503082964 ps |
| T893 |
/workspace/coverage/default/23.spi_device_tpm_all.434318194 |
|
|
Mar 05 01:40:00 PM PST 24 |
Mar 05 01:40:30 PM PST 24 |
7437583873 ps |
| T894 |
/workspace/coverage/default/18.spi_device_read_buffer_direct.1325024798 |
|
|
Mar 05 01:39:07 PM PST 24 |
Mar 05 01:39:13 PM PST 24 |
861506871 ps |
| T895 |
/workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.578581095 |
|
|
Mar 05 01:38:05 PM PST 24 |
Mar 05 01:42:23 PM PST 24 |
32753230476 ps |
| T896 |
/workspace/coverage/default/30.spi_device_tpm_rw.2204772677 |
|
|
Mar 05 01:40:55 PM PST 24 |
Mar 05 01:40:56 PM PST 24 |
161639573 ps |
| T897 |
/workspace/coverage/default/25.spi_device_alert_test.4217780476 |
|
|
Mar 05 01:40:21 PM PST 24 |
Mar 05 01:40:22 PM PST 24 |
11622198 ps |
| T898 |
/workspace/coverage/default/33.spi_device_tpm_rw.1856727617 |
|
|
Mar 05 01:41:33 PM PST 24 |
Mar 05 01:41:36 PM PST 24 |
668895105 ps |
| T899 |
/workspace/coverage/default/36.spi_device_flash_mode.842433638 |
|
|
Mar 05 01:42:00 PM PST 24 |
Mar 05 01:42:26 PM PST 24 |
4627002326 ps |
| T900 |
/workspace/coverage/default/37.spi_device_flash_all.4200479835 |
|
|
Mar 05 01:42:05 PM PST 24 |
Mar 05 01:47:01 PM PST 24 |
246731352727 ps |
| T901 |
/workspace/coverage/default/7.spi_device_ram_cfg.2074173680 |
|
|
Mar 05 01:37:19 PM PST 24 |
Mar 05 01:37:20 PM PST 24 |
16352488 ps |
| T902 |
/workspace/coverage/default/21.spi_device_tpm_rw.2789058987 |
|
|
Mar 05 01:39:38 PM PST 24 |
Mar 05 01:39:41 PM PST 24 |
159187532 ps |
| T903 |
/workspace/coverage/default/29.spi_device_tpm_sts_read.2060591576 |
|
|
Mar 05 01:40:48 PM PST 24 |
Mar 05 01:40:49 PM PST 24 |
139079267 ps |
| T904 |
/workspace/coverage/default/11.spi_device_ram_cfg.3849757232 |
|
|
Mar 05 01:38:01 PM PST 24 |
Mar 05 01:38:02 PM PST 24 |
32219311 ps |
| T905 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1626017187 |
|
|
Mar 05 01:40:48 PM PST 24 |
Mar 05 01:41:13 PM PST 24 |
5470429740 ps |
| T906 |
/workspace/coverage/default/42.spi_device_read_buffer_direct.2745966652 |
|
|
Mar 05 01:42:54 PM PST 24 |
Mar 05 01:42:58 PM PST 24 |
540366728 ps |
| T907 |
/workspace/coverage/default/32.spi_device_intercept.3235258395 |
|
|
Mar 05 01:41:21 PM PST 24 |
Mar 05 01:41:27 PM PST 24 |
6576587031 ps |
| T908 |
/workspace/coverage/default/45.spi_device_alert_test.3532215042 |
|
|
Mar 05 01:43:23 PM PST 24 |
Mar 05 01:43:24 PM PST 24 |
124410250 ps |
| T909 |
/workspace/coverage/default/2.spi_device_upload.1492768281 |
|
|
Mar 05 01:36:21 PM PST 24 |
Mar 05 01:36:28 PM PST 24 |
929887512 ps |
| T910 |
/workspace/coverage/default/4.spi_device_mem_parity.1957143946 |
|
|
Mar 05 01:36:43 PM PST 24 |
Mar 05 01:36:45 PM PST 24 |
15440751 ps |
| T911 |
/workspace/coverage/default/40.spi_device_csb_read.1664231642 |
|
|
Mar 05 01:42:33 PM PST 24 |
Mar 05 01:42:35 PM PST 24 |
55148649 ps |
| T912 |
/workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2763244283 |
|
|
Mar 05 01:42:07 PM PST 24 |
Mar 05 01:43:52 PM PST 24 |
23322648968 ps |
| T913 |
/workspace/coverage/default/38.spi_device_tpm_all.2373648724 |
|
|
Mar 05 01:42:19 PM PST 24 |
Mar 05 01:42:56 PM PST 24 |
3525666271 ps |
| T269 |
/workspace/coverage/default/46.spi_device_flash_all.1493052581 |
|
|
Mar 05 01:43:25 PM PST 24 |
Mar 05 01:44:42 PM PST 24 |
25970569758 ps |
| T914 |
/workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.330021656 |
|
|
Mar 05 01:36:39 PM PST 24 |
Mar 05 01:38:28 PM PST 24 |
9230153553 ps |
| T915 |
/workspace/coverage/default/23.spi_device_flash_all.3302672911 |
|
|
Mar 05 01:40:04 PM PST 24 |
Mar 05 01:41:02 PM PST 24 |
9655385598 ps |
| T916 |
/workspace/coverage/default/10.spi_device_alert_test.2039664437 |
|
|
Mar 05 01:37:59 PM PST 24 |
Mar 05 01:38:00 PM PST 24 |
46226259 ps |
| T917 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.3336616349 |
|
|
Mar 05 01:42:19 PM PST 24 |
Mar 05 01:42:20 PM PST 24 |
176062509 ps |
| T918 |
/workspace/coverage/default/15.spi_device_csb_read.2591992078 |
|
|
Mar 05 01:38:40 PM PST 24 |
Mar 05 01:38:40 PM PST 24 |
31783174 ps |
| T919 |
/workspace/coverage/default/36.spi_device_read_buffer_direct.2418719594 |
|
|
Mar 05 01:42:04 PM PST 24 |
Mar 05 01:42:08 PM PST 24 |
115533914 ps |
| T920 |
/workspace/coverage/default/18.spi_device_tpm_rw.4127569875 |
|
|
Mar 05 01:39:08 PM PST 24 |
Mar 05 01:39:09 PM PST 24 |
105854239 ps |
| T921 |
/workspace/coverage/default/8.spi_device_cfg_cmd.1014518201 |
|
|
Mar 05 01:37:29 PM PST 24 |
Mar 05 01:37:33 PM PST 24 |
522206050 ps |
| T922 |
/workspace/coverage/default/42.spi_device_upload.2822183534 |
|
|
Mar 05 01:42:54 PM PST 24 |
Mar 05 01:43:03 PM PST 24 |
1662871569 ps |
| T65 |
/workspace/coverage/default/0.spi_device_sec_cm.4167860485 |
|
|
Mar 05 01:35:58 PM PST 24 |
Mar 05 01:36:00 PM PST 24 |
70826914 ps |
| T923 |
/workspace/coverage/default/35.spi_device_stress_all.3795008954 |
|
|
Mar 05 01:41:54 PM PST 24 |
Mar 05 01:41:55 PM PST 24 |
950601621 ps |
| T924 |
/workspace/coverage/default/5.spi_device_upload.2939029076 |
|
|
Mar 05 01:37:03 PM PST 24 |
Mar 05 01:37:30 PM PST 24 |
118642600570 ps |
| T925 |
/workspace/coverage/default/34.spi_device_tpm_sts_read.3282284498 |
|
|
Mar 05 01:41:43 PM PST 24 |
Mar 05 01:41:45 PM PST 24 |
137839313 ps |
| T926 |
/workspace/coverage/default/27.spi_device_intercept.1303500526 |
|
|
Mar 05 01:40:46 PM PST 24 |
Mar 05 01:40:50 PM PST 24 |
1806512677 ps |
| T927 |
/workspace/coverage/default/41.spi_device_tpm_sts_read.1095315814 |
|
|
Mar 05 01:42:48 PM PST 24 |
Mar 05 01:42:49 PM PST 24 |
403937958 ps |
| T928 |
/workspace/coverage/default/2.spi_device_tpm_sts_read.1070813681 |
|
|
Mar 05 01:36:23 PM PST 24 |
Mar 05 01:36:25 PM PST 24 |
48648411 ps |
| T282 |
/workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2739222699 |
|
|
Mar 05 01:42:47 PM PST 24 |
Mar 05 01:48:17 PM PST 24 |
95315530190 ps |
| T929 |
/workspace/coverage/default/4.spi_device_ram_cfg.1658557631 |
|
|
Mar 05 01:36:44 PM PST 24 |
Mar 05 01:36:46 PM PST 24 |
19252489 ps |
| T930 |
/workspace/coverage/default/2.spi_device_tpm_rw.4261167408 |
|
|
Mar 05 01:36:39 PM PST 24 |
Mar 05 01:36:45 PM PST 24 |
469887550 ps |
| T931 |
/workspace/coverage/default/20.spi_device_mailbox.2114678086 |
|
|
Mar 05 01:39:32 PM PST 24 |
Mar 05 01:40:05 PM PST 24 |
104549411547 ps |
| T256 |
/workspace/coverage/default/26.spi_device_stress_all.2889176406 |
|
|
Mar 05 01:40:33 PM PST 24 |
Mar 05 01:54:14 PM PST 24 |
135708167337 ps |
| T932 |
/workspace/coverage/default/13.spi_device_read_buffer_direct.3510618134 |
|
|
Mar 05 01:38:26 PM PST 24 |
Mar 05 01:38:34 PM PST 24 |
6314739093 ps |
| T933 |
/workspace/coverage/default/21.spi_device_alert_test.3890529694 |
|
|
Mar 05 01:39:49 PM PST 24 |
Mar 05 01:39:50 PM PST 24 |
18679009 ps |
| T934 |
/workspace/coverage/default/45.spi_device_flash_all.1229144730 |
|
|
Mar 05 01:43:20 PM PST 24 |
Mar 05 01:43:37 PM PST 24 |
13420377296 ps |
| T935 |
/workspace/coverage/default/40.spi_device_pass_cmd_filtering.1807912576 |
|
|
Mar 05 01:42:38 PM PST 24 |
Mar 05 01:42:48 PM PST 24 |
2886152307 ps |
| T936 |
/workspace/coverage/default/0.spi_device_upload.1974130530 |
|
|
Mar 05 01:35:49 PM PST 24 |
Mar 05 01:36:34 PM PST 24 |
46451119807 ps |
| T937 |
/workspace/coverage/default/9.spi_device_tpm_rw.3579964352 |
|
|
Mar 05 01:37:38 PM PST 24 |
Mar 05 01:37:40 PM PST 24 |
56132725 ps |
| T938 |
/workspace/coverage/default/39.spi_device_flash_mode.583062521 |
|
|
Mar 05 01:42:33 PM PST 24 |
Mar 05 01:42:42 PM PST 24 |
2648678848 ps |
| T939 |
/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4098501274 |
|
|
Mar 05 01:39:10 PM PST 24 |
Mar 05 01:39:24 PM PST 24 |
7686690262 ps |
| T940 |
/workspace/coverage/default/33.spi_device_flash_all.2183348237 |
|
|
Mar 05 01:41:35 PM PST 24 |
Mar 05 01:42:23 PM PST 24 |
18183483927 ps |
| T941 |
/workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2817820817 |
|
|
Mar 05 01:39:38 PM PST 24 |
Mar 05 01:41:30 PM PST 24 |
22413272374 ps |
| T942 |
/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.410342924 |
|
|
Mar 05 01:40:56 PM PST 24 |
Mar 05 01:41:04 PM PST 24 |
714316602 ps |
| T943 |
/workspace/coverage/default/46.spi_device_pass_cmd_filtering.3715049389 |
|
|
Mar 05 01:43:24 PM PST 24 |
Mar 05 01:43:32 PM PST 24 |
665745674 ps |
| T944 |
/workspace/coverage/default/38.spi_device_cfg_cmd.703478362 |
|
|
Mar 05 01:42:23 PM PST 24 |
Mar 05 01:42:26 PM PST 24 |
89364714 ps |
| T945 |
/workspace/coverage/default/40.spi_device_read_buffer_direct.2391635573 |
|
|
Mar 05 01:42:43 PM PST 24 |
Mar 05 01:42:47 PM PST 24 |
821582841 ps |
| T946 |
/workspace/coverage/default/41.spi_device_upload.932227761 |
|
|
Mar 05 01:42:46 PM PST 24 |
Mar 05 01:42:50 PM PST 24 |
418459789 ps |
| T947 |
/workspace/coverage/default/43.spi_device_cfg_cmd.2810134154 |
|
|
Mar 05 01:43:00 PM PST 24 |
Mar 05 01:43:05 PM PST 24 |
484646727 ps |
| T948 |
/workspace/coverage/default/2.spi_device_flash_and_tpm.765713900 |
|
|
Mar 05 01:36:33 PM PST 24 |
Mar 05 01:37:25 PM PST 24 |
9114501321 ps |
| T949 |
/workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3296505398 |
|
|
Mar 05 01:41:59 PM PST 24 |
Mar 05 01:43:31 PM PST 24 |
7261919011 ps |
| T950 |
/workspace/coverage/default/1.spi_device_flash_and_tpm.1517416009 |
|
|
Mar 05 01:36:14 PM PST 24 |
Mar 05 01:36:45 PM PST 24 |
1470456835 ps |
| T951 |
/workspace/coverage/default/42.spi_device_flash_all.1851041203 |
|
|
Mar 05 01:42:54 PM PST 24 |
Mar 05 01:43:29 PM PST 24 |
4294465989 ps |
| T952 |
/workspace/coverage/default/1.spi_device_tpm_all.2243280097 |
|
|
Mar 05 01:36:09 PM PST 24 |
Mar 05 01:37:08 PM PST 24 |
9162616413 ps |
| T953 |
/workspace/coverage/default/17.spi_device_alert_test.1948088113 |
|
|
Mar 05 01:39:05 PM PST 24 |
Mar 05 01:39:06 PM PST 24 |
13427426 ps |
| T954 |
/workspace/coverage/default/4.spi_device_flash_and_tpm.3194584064 |
|
|
Mar 05 01:36:53 PM PST 24 |
Mar 05 01:37:32 PM PST 24 |
2094162479 ps |
| T955 |
/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.787052283 |
|
|
Mar 05 01:43:02 PM PST 24 |
Mar 05 01:43:26 PM PST 24 |
7639821570 ps |
| T956 |
/workspace/coverage/default/10.spi_device_tpm_sts_read.2787870189 |
|
|
Mar 05 01:37:49 PM PST 24 |
Mar 05 01:37:50 PM PST 24 |
488298794 ps |
| T957 |
/workspace/coverage/default/36.spi_device_pass_cmd_filtering.2618989129 |
|
|
Mar 05 01:41:57 PM PST 24 |
Mar 05 01:42:20 PM PST 24 |
6674850744 ps |
| T958 |
/workspace/coverage/default/49.spi_device_cfg_cmd.1519242178 |
|
|
Mar 05 01:43:47 PM PST 24 |
Mar 05 01:43:51 PM PST 24 |
659804905 ps |
| T959 |
/workspace/coverage/default/43.spi_device_flash_all.1978921528 |
|
|
Mar 05 01:43:05 PM PST 24 |
Mar 05 01:45:16 PM PST 24 |
84653448846 ps |
| T960 |
/workspace/coverage/default/22.spi_device_cfg_cmd.4164210557 |
|
|
Mar 05 01:39:57 PM PST 24 |
Mar 05 01:40:08 PM PST 24 |
1749396016 ps |
| T961 |
/workspace/coverage/default/12.spi_device_tpm_all.63130523 |
|
|
Mar 05 01:38:08 PM PST 24 |
Mar 05 01:38:13 PM PST 24 |
266664900 ps |
| T962 |
/workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3776827564 |
|
|
Mar 05 01:39:57 PM PST 24 |
Mar 05 01:40:09 PM PST 24 |
4103035250 ps |
| T963 |
/workspace/coverage/default/22.spi_device_tpm_sts_read.2665370664 |
|
|
Mar 05 01:39:56 PM PST 24 |
Mar 05 01:40:02 PM PST 24 |
83536514 ps |
| T964 |
/workspace/coverage/default/43.spi_device_flash_mode.3965892375 |
|
|
Mar 05 01:43:06 PM PST 24 |
Mar 05 01:43:32 PM PST 24 |
8594008687 ps |
| T965 |
/workspace/coverage/default/11.spi_device_mailbox.2113648325 |
|
|
Mar 05 01:38:02 PM PST 24 |
Mar 05 01:38:35 PM PST 24 |
40337215573 ps |
| T966 |
/workspace/coverage/default/18.spi_device_tpm_sts_read.116743541 |
|
|
Mar 05 01:39:07 PM PST 24 |
Mar 05 01:39:08 PM PST 24 |
27798219 ps |
| T967 |
/workspace/coverage/default/2.spi_device_intercept.3875840236 |
|
|
Mar 05 01:36:24 PM PST 24 |
Mar 05 01:36:36 PM PST 24 |
32635390975 ps |
| T968 |
/workspace/coverage/default/10.spi_device_upload.739828669 |
|
|
Mar 05 01:37:56 PM PST 24 |
Mar 05 01:38:08 PM PST 24 |
1537161168 ps |
| T969 |
/workspace/coverage/default/0.spi_device_intercept.1886857446 |
|
|
Mar 05 01:35:49 PM PST 24 |
Mar 05 01:35:57 PM PST 24 |
9050750432 ps |
| T970 |
/workspace/coverage/default/10.spi_device_ram_cfg.1975834221 |
|
|
Mar 05 01:37:52 PM PST 24 |
Mar 05 01:37:53 PM PST 24 |
90505200 ps |
| T971 |
/workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1711276410 |
|
|
Mar 05 01:41:36 PM PST 24 |
Mar 05 01:41:46 PM PST 24 |
5305311626 ps |
| T972 |
/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2477576915 |
|
|
Mar 05 01:43:23 PM PST 24 |
Mar 05 01:43:41 PM PST 24 |
10506910933 ps |
| T973 |
/workspace/coverage/default/35.spi_device_alert_test.962355139 |
|
|
Mar 05 01:41:53 PM PST 24 |
Mar 05 01:41:54 PM PST 24 |
13108375 ps |
| T974 |
/workspace/coverage/default/10.spi_device_csb_read.988113105 |
|
|
Mar 05 01:37:50 PM PST 24 |
Mar 05 01:37:52 PM PST 24 |
58590750 ps |
| T975 |
/workspace/coverage/default/40.spi_device_flash_all.4000353719 |
|
|
Mar 05 01:42:39 PM PST 24 |
Mar 05 01:45:28 PM PST 24 |
148903478031 ps |
| T976 |
/workspace/coverage/default/0.spi_device_flash_all.3489912621 |
|
|
Mar 05 01:36:01 PM PST 24 |
Mar 05 01:36:50 PM PST 24 |
3082550900 ps |
| T977 |
/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3914976302 |
|
|
Mar 05 01:37:23 PM PST 24 |
Mar 05 01:41:00 PM PST 24 |
61738049195 ps |
| T978 |
/workspace/coverage/default/47.spi_device_tpm_sts_read.2745534310 |
|
|
Mar 05 01:43:32 PM PST 24 |
Mar 05 01:43:33 PM PST 24 |
443165477 ps |
| T979 |
/workspace/coverage/default/27.spi_device_flash_mode.1925345857 |
|
|
Mar 05 01:40:48 PM PST 24 |
Mar 05 01:41:14 PM PST 24 |
5073670463 ps |
| T980 |
/workspace/coverage/default/14.spi_device_read_buffer_direct.3062267748 |
|
|
Mar 05 01:38:32 PM PST 24 |
Mar 05 01:38:38 PM PST 24 |
1814640048 ps |
| T981 |
/workspace/coverage/default/48.spi_device_alert_test.556819430 |
|
|
Mar 05 01:43:46 PM PST 24 |
Mar 05 01:43:47 PM PST 24 |
12593781 ps |
| T265 |
/workspace/coverage/default/36.spi_device_stress_all.1830077106 |
|
|
Mar 05 01:42:08 PM PST 24 |
Mar 05 01:46:36 PM PST 24 |
82110433402 ps |
| T982 |
/workspace/coverage/default/42.spi_device_flash_and_tpm.2314248197 |
|
|
Mar 05 01:42:56 PM PST 24 |
Mar 05 01:44:17 PM PST 24 |
14107853130 ps |
| T983 |
/workspace/coverage/default/3.spi_device_tpm_all.3954454457 |
|
|
Mar 05 01:36:31 PM PST 24 |
Mar 05 01:36:53 PM PST 24 |
36706424559 ps |
| T984 |
/workspace/coverage/default/10.spi_device_mem_parity.4232413998 |
|
|
Mar 05 01:38:03 PM PST 24 |
Mar 05 01:38:05 PM PST 24 |
50850602 ps |
| T985 |
/workspace/coverage/default/34.spi_device_upload.3400593509 |
|
|
Mar 05 01:41:37 PM PST 24 |
Mar 05 01:42:07 PM PST 24 |
9027349053 ps |
| T986 |
/workspace/coverage/default/0.spi_device_tpm_all.3333615700 |
|
|
Mar 05 01:35:47 PM PST 24 |
Mar 05 01:36:00 PM PST 24 |
1007817607 ps |
| T987 |
/workspace/coverage/default/5.spi_device_tpm_rw.2394187464 |
|
|
Mar 05 01:37:01 PM PST 24 |
Mar 05 01:37:05 PM PST 24 |
214029790 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1007787791 |
|
|
Mar 05 12:39:45 PM PST 24 |
Mar 05 12:39:52 PM PST 24 |
33274541 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2305308213 |
|
|
Mar 05 12:39:49 PM PST 24 |
Mar 05 12:40:07 PM PST 24 |
592047622 ps |
| T87 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1218806361 |
|
|
Mar 05 12:39:58 PM PST 24 |
Mar 05 12:40:03 PM PST 24 |
102560282 ps |
| T130 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.142305744 |
|
|
Mar 05 12:39:47 PM PST 24 |
Mar 05 12:39:50 PM PST 24 |
1527983645 ps |
| T989 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.1736056464 |
|
|
Mar 05 12:40:17 PM PST 24 |
Mar 05 12:40:18 PM PST 24 |
30094570 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1977346980 |
|
|
Mar 05 12:39:51 PM PST 24 |
Mar 05 12:39:59 PM PST 24 |
2070205373 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3537555005 |
|
|
Mar 05 12:39:50 PM PST 24 |
Mar 05 12:39:51 PM PST 24 |
13842567 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1439753795 |
|
|
Mar 05 12:40:04 PM PST 24 |
Mar 05 12:40:07 PM PST 24 |
169322465 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.318103781 |
|
|
Mar 05 12:40:14 PM PST 24 |
Mar 05 12:40:15 PM PST 24 |
32424426 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2089620599 |
|
|
Mar 05 12:39:47 PM PST 24 |
Mar 05 12:39:48 PM PST 24 |
132515740 ps |
| T994 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.4194081362 |
|
|
Mar 05 12:41:15 PM PST 24 |
Mar 05 12:41:17 PM PST 24 |
32623772 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.536016704 |
|
|
Mar 05 12:39:51 PM PST 24 |
Mar 05 12:39:53 PM PST 24 |
62013125 ps |
| T995 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.2645286395 |
|
|
Mar 05 12:40:09 PM PST 24 |
Mar 05 12:40:10 PM PST 24 |
21373023 ps |
| T996 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1035436374 |
|
|
Mar 05 12:39:50 PM PST 24 |
Mar 05 12:39:50 PM PST 24 |
35854084 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4247691794 |
|
|
Mar 05 12:39:55 PM PST 24 |
Mar 05 12:40:00 PM PST 24 |
204769107 ps |
| T88 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2767024466 |
|
|
Mar 05 12:39:48 PM PST 24 |
Mar 05 12:39:57 PM PST 24 |
4245047618 ps |
| T998 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.4028903592 |
|
|
Mar 05 12:39:58 PM PST 24 |
Mar 05 12:39:59 PM PST 24 |
27447641 ps |
| T104 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4081171151 |
|
|
Mar 05 12:41:32 PM PST 24 |
Mar 05 12:41:34 PM PST 24 |
75434087 ps |
| T89 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1433202845 |
|
|
Mar 05 12:40:01 PM PST 24 |
Mar 05 12:40:07 PM PST 24 |
128552155 ps |
| T999 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.2330569338 |
|
|
Mar 05 12:40:19 PM PST 24 |
Mar 05 12:40:20 PM PST 24 |
17336552 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1338252231 |
|
|
Mar 05 12:39:50 PM PST 24 |
Mar 05 12:40:03 PM PST 24 |
608426020 ps |
| T1001 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.1600028632 |
|
|
Mar 05 12:39:46 PM PST 24 |
Mar 05 12:39:47 PM PST 24 |
49704664 ps |
| T1002 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1472265569 |
|
|
Mar 05 12:40:04 PM PST 24 |
Mar 05 12:40:05 PM PST 24 |
18624040 ps |
| T90 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3785605347 |
|
|
Mar 05 12:40:06 PM PST 24 |
Mar 05 12:40:10 PM PST 24 |
147894350 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1477180733 |
|
|
Mar 05 12:39:44 PM PST 24 |
Mar 05 12:39:46 PM PST 24 |
69106044 ps |
| T94 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1673885378 |
|
|
Mar 05 12:40:12 PM PST 24 |
Mar 05 12:40:16 PM PST 24 |
197689677 ps |
| T99 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.85707498 |
|
|
Mar 05 12:40:01 PM PST 24 |
Mar 05 12:40:06 PM PST 24 |
55702566 ps |
| T1003 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.588832180 |
|
|
Mar 05 12:39:54 PM PST 24 |
Mar 05 12:39:55 PM PST 24 |
15101317 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.3505495007 |
|
|
Mar 05 12:39:42 PM PST 24 |
Mar 05 12:39:44 PM PST 24 |
16165840 ps |
| T1005 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.251258319 |
|
|
Mar 05 12:39:59 PM PST 24 |
Mar 05 12:40:00 PM PST 24 |
10268338 ps |
| T93 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3801571807 |
|
|
Mar 05 12:40:05 PM PST 24 |
Mar 05 12:40:09 PM PST 24 |
329350552 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1704902657 |
|
|
Mar 05 12:40:16 PM PST 24 |
Mar 05 12:40:33 PM PST 24 |
1470352927 ps |
| T100 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2025279345 |
|
|
Mar 05 12:39:45 PM PST 24 |
Mar 05 12:40:09 PM PST 24 |
600974093 ps |
| T1006 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1511024759 |
|
|
Mar 05 12:39:51 PM PST 24 |
Mar 05 12:39:59 PM PST 24 |
120862944 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2834053272 |
|
|
Mar 05 12:39:39 PM PST 24 |
Mar 05 12:39:40 PM PST 24 |
43972551 ps |
| T1007 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.1416508679 |
|
|
Mar 05 12:40:16 PM PST 24 |
Mar 05 12:40:17 PM PST 24 |
50621553 ps |
| T1008 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.128758510 |
|
|
Mar 05 12:40:04 PM PST 24 |
Mar 05 12:40:13 PM PST 24 |
1041923838 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1892315623 |
|
|
Mar 05 12:39:38 PM PST 24 |
Mar 05 12:39:40 PM PST 24 |
52189821 ps |
| T1009 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.441815466 |
|
|
Mar 05 12:40:08 PM PST 24 |
Mar 05 12:40:09 PM PST 24 |
61691518 ps |
| T131 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2136892205 |
|
|
Mar 05 12:39:50 PM PST 24 |
Mar 05 12:40:07 PM PST 24 |
14234721691 ps |
| T1010 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.1181452944 |
|
|
Mar 05 12:41:28 PM PST 24 |
Mar 05 12:41:29 PM PST 24 |
16672218 ps |
| T107 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1288987470 |
|
|
Mar 05 12:39:45 PM PST 24 |
Mar 05 12:39:47 PM PST 24 |
290356400 ps |
| T1011 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3987690769 |
|
|
Mar 05 12:39:43 PM PST 24 |
Mar 05 12:39:46 PM PST 24 |
142259977 ps |
| T96 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.760295952 |
|
|
Mar 05 12:39:53 PM PST 24 |
Mar 05 12:39:56 PM PST 24 |
71694317 ps |
| T1012 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.2915623122 |
|
|
Mar 05 12:40:11 PM PST 24 |
Mar 05 12:40:12 PM PST 24 |
38490554 ps |
| T1013 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.974372564 |
|
|
Mar 05 12:40:09 PM PST 24 |
Mar 05 12:40:10 PM PST 24 |
11479717 ps |
| T132 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.515356088 |
|
|
Mar 05 12:39:47 PM PST 24 |
Mar 05 12:39:50 PM PST 24 |
133079276 ps |
| T133 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1033121502 |
|
|
Mar 05 12:39:50 PM PST 24 |
Mar 05 12:39:53 PM PST 24 |
1652141591 ps |
| T134 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2190199853 |
|
|
Mar 05 12:39:56 PM PST 24 |
Mar 05 12:40:17 PM PST 24 |
3804036509 ps |
| T1014 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2857332228 |
|
|
Mar 05 12:40:23 PM PST 24 |
Mar 05 12:40:25 PM PST 24 |
103005296 ps |
| T1015 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.525606444 |
|
|
Mar 05 12:39:56 PM PST 24 |
Mar 05 12:39:57 PM PST 24 |
21704847 ps |
| T1016 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.11900816 |
|
|
Mar 05 12:40:13 PM PST 24 |
Mar 05 12:40:14 PM PST 24 |
17771927 ps |
| T98 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4142911058 |
|
|
Mar 05 12:40:05 PM PST 24 |
Mar 05 12:40:08 PM PST 24 |
124014320 ps |
| T108 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.44459161 |
|
|
Mar 05 12:39:48 PM PST 24 |
Mar 05 12:39:49 PM PST 24 |
64248618 ps |
| T1017 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1542315241 |
|
|
Mar 05 12:39:51 PM PST 24 |
Mar 05 12:39:57 PM PST 24 |
126551917 ps |
| T97 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2598270494 |
|
|
Mar 05 12:39:57 PM PST 24 |
Mar 05 12:40:02 PM PST 24 |
157561583 ps |
| T1018 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1499164892 |
|
|
Mar 05 12:39:53 PM PST 24 |
Mar 05 12:39:55 PM PST 24 |
133874617 ps |
| T1019 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.480609403 |
|
|
Mar 05 12:39:46 PM PST 24 |
Mar 05 12:39:48 PM PST 24 |
81341407 ps |