| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.99 | 98.39 | 94.44 | 98.61 | 89.36 | 97.10 | 95.82 | 98.22 |
| T1020 | /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.464364530 | Mar 05 12:39:52 PM PST 24 | Mar 05 12:39:54 PM PST 24 | 55148376 ps | ||
| T1021 | /workspace/coverage/cover_reg_top/31.spi_device_intr_test.77071531 | Mar 05 12:40:06 PM PST 24 | Mar 05 12:40:07 PM PST 24 | 55859873 ps | ||
| T1022 | /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3031543692 | Mar 05 12:41:34 PM PST 24 | Mar 05 12:41:34 PM PST 24 | 26365291 ps | ||
| T1023 | /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2693138676 | Mar 05 12:39:50 PM PST 24 | Mar 05 12:39:52 PM PST 24 | 199159458 ps | ||
| T109 | /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1642468883 | Mar 05 12:40:15 PM PST 24 | Mar 05 12:40:17 PM PST 24 | 227990153 ps | ||
| T1024 | /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1898643620 | Mar 05 12:39:45 PM PST 24 | Mar 05 12:39:46 PM PST 24 | 177590577 ps | ||
| T1025 | /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3066520088 | Mar 05 12:40:02 PM PST 24 | Mar 05 12:40:08 PM PST 24 | 16168684 ps | ||
| T110 | /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1891799410 | Mar 05 12:39:43 PM PST 24 | Mar 05 12:40:11 PM PST 24 | 7471449518 ps | ||
| T1026 | /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2010208772 | Mar 05 12:39:54 PM PST 24 | Mar 05 12:39:56 PM PST 24 | 337154668 ps | ||
| T1027 | /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3562097149 | Mar 05 12:39:58 PM PST 24 | Mar 05 12:40:06 PM PST 24 | 320030787 ps | ||
| T111 | /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4031038023 | Mar 05 12:39:57 PM PST 24 | Mar 05 12:40:28 PM PST 24 | 535636382 ps | ||
| T1028 | /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3678768759 | Mar 05 12:39:53 PM PST 24 | Mar 05 12:39:55 PM PST 24 | 47929453 ps | ||
| T1029 | /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1635388498 | Mar 05 12:40:03 PM PST 24 | Mar 05 12:40:04 PM PST 24 | 22449889 ps | ||
| T1030 | /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1289908359 | Mar 05 12:39:53 PM PST 24 | Mar 05 12:39:56 PM PST 24 | 175084027 ps | ||
| T1031 | /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3688775961 | Mar 05 12:40:01 PM PST 24 | Mar 05 12:40:05 PM PST 24 | 210092495 ps | ||
| T112 | /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.338544123 | Mar 05 12:39:57 PM PST 24 | Mar 05 12:40:00 PM PST 24 | 144269070 ps | ||
| T1032 | /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2674491295 | Mar 05 12:39:50 PM PST 24 | Mar 05 12:39:58 PM PST 24 | 111141177 ps | ||
| T1033 | /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3580072178 | Mar 05 12:39:51 PM PST 24 | Mar 05 12:40:00 PM PST 24 | 133387189 ps | ||
| T1034 | /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4264234067 | Mar 05 12:40:17 PM PST 24 | Mar 05 12:40:18 PM PST 24 | 130281166 ps | ||
| T1035 | /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.266346120 | Mar 05 12:39:59 PM PST 24 | Mar 05 12:40:01 PM PST 24 | 28308140 ps | ||
| T1036 | /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.420283195 | Mar 05 12:40:09 PM PST 24 | Mar 05 12:40:11 PM PST 24 | 345809950 ps | ||
| T114 | /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2004356813 | Mar 05 12:39:47 PM PST 24 | Mar 05 12:39:49 PM PST 24 | 98672925 ps | ||
| T1037 | /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1527513042 | Mar 05 12:40:03 PM PST 24 | Mar 05 12:40:10 PM PST 24 | 214939377 ps | ||
| T1038 | /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2005863983 | Mar 05 12:39:51 PM PST 24 | Mar 05 12:39:51 PM PST 24 | 134561821 ps | ||
| T1039 | /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4174599636 | Mar 05 12:40:01 PM PST 24 | Mar 05 12:40:03 PM PST 24 | 38128105 ps | ||
| T1040 | /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.934197243 | Mar 05 12:39:56 PM PST 24 | Mar 05 12:40:00 PM PST 24 | 140358619 ps | ||
| T1041 | /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1310435577 | Mar 05 12:40:16 PM PST 24 | Mar 05 12:40:18 PM PST 24 | 14661504 ps | ||
| T1042 | /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.798758306 | Mar 05 12:40:00 PM PST 24 | Mar 05 12:40:08 PM PST 24 | 1215745285 ps | ||
| T1043 | /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2534675827 | Mar 05 12:40:02 PM PST 24 | Mar 05 12:40:03 PM PST 24 | 12791854 ps | ||
| T1044 | /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.405682903 | Mar 05 12:40:10 PM PST 24 | Mar 05 12:40:13 PM PST 24 | 90456848 ps | ||
| T1045 | /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3581131385 | Mar 05 12:39:57 PM PST 24 | Mar 05 12:40:04 PM PST 24 | 16926039 ps | ||
| T1046 | /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.497534971 | Mar 05 12:40:17 PM PST 24 | Mar 05 12:40:20 PM PST 24 | 122404748 ps | ||
| T1047 | /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1817550191 | Mar 05 12:39:45 PM PST 24 | Mar 05 12:39:48 PM PST 24 | 378245659 ps | ||
| T158 | /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2244352131 | Mar 05 12:40:06 PM PST 24 | Mar 05 12:40:14 PM PST 24 | 293067912 ps | ||
| T113 | /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3508567246 | Mar 05 12:39:52 PM PST 24 | Mar 05 12:39:53 PM PST 24 | 69854617 ps | ||
| T1048 | /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4020245347 | Mar 05 12:39:52 PM PST 24 | Mar 05 12:39:55 PM PST 24 | 212845622 ps | ||
| T1049 | /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1542734984 | Mar 05 12:40:22 PM PST 24 | Mar 05 12:40:29 PM PST 24 | 32450247 ps | ||
| T1050 | /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2794595335 | Mar 05 12:39:53 PM PST 24 | Mar 05 12:39:57 PM PST 24 | 173419352 ps | ||
| T149 | /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3669901050 | Mar 05 12:39:41 PM PST 24 | Mar 05 12:39:46 PM PST 24 | 69741521 ps | ||
| T1051 | /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2861855582 | Mar 05 12:39:50 PM PST 24 | Mar 05 12:39:51 PM PST 24 | 57843445 ps | ||
| T79 | /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1684452460 | Mar 05 12:39:50 PM PST 24 | Mar 05 12:39:51 PM PST 24 | 19012603 ps | ||
| T1052 | /workspace/coverage/cover_reg_top/41.spi_device_intr_test.913403769 | Mar 05 12:40:17 PM PST 24 | Mar 05 12:40:18 PM PST 24 | 58281780 ps | ||
| T1053 | /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2590702093 | Mar 05 12:39:56 PM PST 24 | Mar 05 12:39:59 PM PST 24 | 1790713859 ps | ||
| T1054 | /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2692597763 | Mar 05 12:39:48 PM PST 24 | Mar 05 12:39:50 PM PST 24 | 66069994 ps | ||
| T1055 | /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.251432869 | Mar 05 12:39:46 PM PST 24 | Mar 05 12:39:48 PM PST 24 | 48174396 ps | ||
| T156 | /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3943768773 | Mar 05 12:39:50 PM PST 24 | Mar 05 12:39:58 PM PST 24 | 566625868 ps | ||
| T154 | /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.397861357 | Mar 05 12:39:44 PM PST 24 | Mar 05 12:39:51 PM PST 24 | 443987334 ps | ||
| T1056 | /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1329459129 | Mar 05 12:39:56 PM PST 24 | Mar 05 12:39:59 PM PST 24 | 322804835 ps | ||
| T1057 | /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2665946614 | Mar 05 12:39:53 PM PST 24 | Mar 05 12:40:01 PM PST 24 | 1354415701 ps | ||
| T1058 | /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4115366771 | Mar 05 12:39:58 PM PST 24 | Mar 05 12:40:01 PM PST 24 | 28030897 ps | ||
| T1059 | /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1459025050 | Mar 05 12:39:39 PM PST 24 | Mar 05 12:39:41 PM PST 24 | 156643004 ps | ||
| T1060 | /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3392544546 | Mar 05 12:39:58 PM PST 24 | Mar 05 12:40:00 PM PST 24 | 321073823 ps | ||
| T1061 | /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2205158024 | Mar 05 12:39:58 PM PST 24 | Mar 05 12:40:03 PM PST 24 | 176230083 ps | ||
| T1062 | /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1179046455 | Mar 05 12:39:42 PM PST 24 | Mar 05 12:39:43 PM PST 24 | 16220294 ps | ||
| T1063 | /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3345583951 | Mar 05 12:40:06 PM PST 24 | Mar 05 12:40:07 PM PST 24 | 19504319 ps | ||
| T151 | /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.428078771 | Mar 05 12:39:54 PM PST 24 | Mar 05 12:40:13 PM PST 24 | 1213475284 ps | ||
| T1064 | /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2611334689 | Mar 05 12:40:07 PM PST 24 | Mar 05 12:40:08 PM PST 24 | 24920141 ps | ||
| T80 | /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.914676821 | Mar 05 12:39:37 PM PST 24 | Mar 05 12:39:38 PM PST 24 | 83391380 ps | ||
| T1065 | /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.546881912 | Mar 05 12:39:51 PM PST 24 | Mar 05 12:39:55 PM PST 24 | 154377646 ps | ||
| T1066 | /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1274673426 | Mar 05 12:40:03 PM PST 24 | Mar 05 12:40:06 PM PST 24 | 45328030 ps | ||
| T1067 | /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2519374012 | Mar 05 12:41:30 PM PST 24 | Mar 05 12:41:31 PM PST 24 | 13358603 ps | ||
| T1068 | /workspace/coverage/cover_reg_top/3.spi_device_intr_test.831638238 | Mar 05 12:39:53 PM PST 24 | Mar 05 12:39:54 PM PST 24 | 44505233 ps | ||
| T1069 | /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1156433948 | Mar 05 12:39:53 PM PST 24 | Mar 05 12:39:54 PM PST 24 | 14879391 ps | ||
| T1070 | /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3183640892 | Mar 05 12:40:00 PM PST 24 | Mar 05 12:40:01 PM PST 24 | 16456332 ps | ||
| T1071 | /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4282392087 | Mar 05 12:39:44 PM PST 24 | Mar 05 12:39:48 PM PST 24 | 733393927 ps | ||
| T1072 | /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.737115245 | Mar 05 12:40:19 PM PST 24 | Mar 05 12:40:23 PM PST 24 | 132766505 ps | ||
| T1073 | /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2073444355 | Mar 05 12:39:48 PM PST 24 | Mar 05 12:39:50 PM PST 24 | 201717713 ps | ||
| T1074 | /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2869694811 | Mar 05 12:39:50 PM PST 24 | Mar 05 12:39:54 PM PST 24 | 144932902 ps | ||
| T1075 | /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3854360747 | Mar 05 12:40:05 PM PST 24 | Mar 05 12:40:08 PM PST 24 | 223550627 ps | ||
| T1076 | /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1634540214 | Mar 05 12:40:12 PM PST 24 | Mar 05 12:40:15 PM PST 24 | 135307856 ps | ||
| T1077 | /workspace/coverage/cover_reg_top/23.spi_device_intr_test.527783701 | Mar 05 12:39:58 PM PST 24 | Mar 05 12:40:00 PM PST 24 | 28464375 ps | ||
| T1078 | /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1068170917 | Mar 05 12:40:02 PM PST 24 | Mar 05 12:40:05 PM PST 24 | 896581497 ps | ||
| T1079 | /workspace/coverage/cover_reg_top/4.spi_device_intr_test.289755346 | Mar 05 12:40:05 PM PST 24 | Mar 05 12:40:06 PM PST 24 | 51688490 ps | ||
| T1080 | /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3488801711 | Mar 05 12:39:54 PM PST 24 | Mar 05 12:39:57 PM PST 24 | 276958028 ps | ||
| T155 | /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3360460176 | Mar 05 12:39:53 PM PST 24 | Mar 05 12:40:08 PM PST 24 | 2109096442 ps | ||
| T1081 | /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2227744443 | Mar 05 12:40:04 PM PST 24 | Mar 05 12:40:05 PM PST 24 | 15976432 ps | ||
| T1082 | /workspace/coverage/cover_reg_top/29.spi_device_intr_test.66600404 | Mar 05 12:41:37 PM PST 24 | Mar 05 12:41:38 PM PST 24 | 14617691 ps | ||
| T1083 | /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2152931397 | Mar 05 12:40:06 PM PST 24 | Mar 05 12:40:07 PM PST 24 | 30465780 ps | ||
| T1084 | /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2014895339 | Mar 05 12:39:43 PM PST 24 | Mar 05 12:39:45 PM PST 24 | 22092723 ps | ||
| T1085 | /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.620507775 | Mar 05 12:40:13 PM PST 24 | Mar 05 12:40:18 PM PST 24 | 228537110 ps | ||
| T1086 | /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3346864374 | Mar 05 12:40:01 PM PST 24 | Mar 05 12:40:35 PM PST 24 | 1884794588 ps | ||
| T1087 | /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2479425238 | Mar 05 12:39:48 PM PST 24 | Mar 05 12:40:01 PM PST 24 | 100941645 ps | ||
| T1088 | /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.715167674 | Mar 05 12:40:10 PM PST 24 | Mar 05 12:40:17 PM PST 24 | 496594205 ps | ||
| T157 | /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2330935655 | Mar 05 12:39:59 PM PST 24 | Mar 05 12:40:15 PM PST 24 | 562710347 ps | ||
| T150 | /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.768935496 | Mar 05 12:39:54 PM PST 24 | Mar 05 12:39:56 PM PST 24 | 103789340 ps | ||
| T1089 | /workspace/coverage/cover_reg_top/10.spi_device_intr_test.957173176 | Mar 05 12:40:06 PM PST 24 | Mar 05 12:40:07 PM PST 24 | 189442916 ps | ||
| T1090 | /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.772979338 | Mar 05 12:40:05 PM PST 24 | Mar 05 12:40:10 PM PST 24 | 687625696 ps | ||
| T1091 | /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3758422165 | Mar 05 12:39:41 PM PST 24 | Mar 05 12:39:42 PM PST 24 | 27911133 ps | ||
| T1092 | /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2070476789 | Mar 05 12:39:50 PM PST 24 | Mar 05 12:39:51 PM PST 24 | 31982163 ps | ||
| T1093 | /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.422359386 | Mar 05 12:40:00 PM PST 24 | Mar 05 12:40:06 PM PST 24 | 106356046 ps | ||
| T1094 | /workspace/coverage/cover_reg_top/49.spi_device_intr_test.865314703 | Mar 05 12:40:27 PM PST 24 | Mar 05 12:40:30 PM PST 24 | 173739158 ps | ||
| T1095 | /workspace/coverage/cover_reg_top/16.spi_device_intr_test.288548102 | Mar 05 12:39:52 PM PST 24 | Mar 05 12:39:53 PM PST 24 | 12851666 ps | ||
| T1096 | /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1067973479 | Mar 05 12:40:18 PM PST 24 | Mar 05 12:40:21 PM PST 24 | 147240833 ps | ||
| T1097 | /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2087897294 | Mar 05 12:39:58 PM PST 24 | Mar 05 12:40:01 PM PST 24 | 158905718 ps | ||
| T1098 | /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1842810178 | Mar 05 12:40:22 PM PST 24 | Mar 05 12:40:25 PM PST 24 | 311505838 ps | ||
| T1099 | /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1040132103 | Mar 05 12:39:42 PM PST 24 | Mar 05 12:39:43 PM PST 24 | 56255426 ps | ||
| T152 | /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2246547201 | Mar 05 12:39:49 PM PST 24 | Mar 05 12:40:03 PM PST 24 | 207867495 ps | ||
| T1100 | /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1913189116 | Mar 05 12:39:59 PM PST 24 | Mar 05 12:40:24 PM PST 24 | 6012172115 ps | ||
| T1101 | /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2079464972 | Mar 05 12:39:41 PM PST 24 | Mar 05 12:39:43 PM PST 24 | 179512147 ps | ||
| T1102 | /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2909502029 | Mar 05 12:40:04 PM PST 24 | Mar 05 12:40:06 PM PST 24 | 39728037 ps | ||
| T1103 | /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2535413477 | Mar 05 12:39:58 PM PST 24 | Mar 05 12:40:01 PM PST 24 | 27071215 ps | ||
| T1104 | /workspace/coverage/cover_reg_top/33.spi_device_intr_test.640346771 | Mar 05 12:40:04 PM PST 24 | Mar 05 12:40:05 PM PST 24 | 35078392 ps | ||
| T1105 | /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3666697519 | Mar 05 12:39:57 PM PST 24 | Mar 05 12:39:58 PM PST 24 | 15029972 ps | ||
| T1106 | /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1277572354 | Mar 05 12:39:53 PM PST 24 | Mar 05 12:39:55 PM PST 24 | 111711881 ps | ||
| T153 | /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2731891211 | Mar 05 12:39:42 PM PST 24 | Mar 05 12:40:02 PM PST 24 | 808035251 ps | ||
| T1107 | /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.811852687 | Mar 05 12:39:55 PM PST 24 | Mar 05 12:39:58 PM PST 24 | 2871321438 ps | ||
| T1108 | /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2689876738 | Mar 05 12:40:03 PM PST 24 | Mar 05 12:40:06 PM PST 24 | 59522100 ps | ||
| T1109 | /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2966014236 | Mar 05 12:39:39 PM PST 24 | Mar 05 12:39:40 PM PST 24 | 17465758 ps | ||
| T1110 | /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3430339793 | Mar 05 12:39:48 PM PST 24 | Mar 05 12:39:51 PM PST 24 | 475523116 ps | ||
| T1111 | /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4009646982 | Mar 05 12:39:48 PM PST 24 | Mar 05 12:39:50 PM PST 24 | 75220834 ps | ||
| T1112 | /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2959420322 | Mar 05 12:39:49 PM PST 24 | Mar 05 12:39:53 PM PST 24 | 541026585 ps | ||
| T1113 | /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4051225589 | Mar 05 12:39:55 PM PST 24 | Mar 05 12:40:03 PM PST 24 | 244813187 ps | ||
| T1114 | /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2773473194 | Mar 05 12:40:03 PM PST 24 | Mar 05 12:40:07 PM PST 24 | 271670410 ps | ||
| T95 | /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2165985206 | Mar 05 12:39:49 PM PST 24 | Mar 05 12:40:06 PM PST 24 | 2563582905 ps | ||
| T1115 | /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.274770994 | Mar 05 12:39:50 PM PST 24 | Mar 05 12:39:54 PM PST 24 | 216751321 ps | ||
| T1116 | /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.276801761 | Mar 05 12:39:48 PM PST 24 | Mar 05 12:39:50 PM PST 24 | 40365113 ps | ||
| T1117 | /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3897517337 | Mar 05 12:40:05 PM PST 24 | Mar 05 12:40:06 PM PST 24 | 32357541 ps |
| Test location | /workspace/coverage/default/18.spi_device_flash_all.1696346207 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 20936686912 ps |
| CPU time | 21.96 seconds |
| Started | Mar 05 01:39:19 PM PST 24 |
| Finished | Mar 05 01:39:44 PM PST 24 |
| Peak memory | 240820 kb |
| Host | smart-fed73967-8129-4c05-9687-cb1208297699 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696346207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1696346207 |
| Directory | /workspace/18.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/22.spi_device_flash_and_tpm.2625492581 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 46258155570 ps |
| CPU time | 219.42 seconds |
| Started | Mar 05 01:39:56 PM PST 24 |
| Finished | Mar 05 01:43:38 PM PST 24 |
| Peak memory | 263544 kb |
| Host | smart-cef615e1-55f9-4a49-a5c0-19ddc2d143dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625492581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2625492581 |
| Directory | /workspace/22.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/39.spi_device_stress_all.3867222730 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 90700008975 ps |
| CPU time | 574.28 seconds |
| Started | Mar 05 01:42:28 PM PST 24 |
| Finished | Mar 05 01:52:02 PM PST 24 |
| Peak memory | 298308 kb |
| Host | smart-c0f71757-5e5c-4c00-96c1-c1df723b30a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867222730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre ss_all.3867222730 |
| Directory | /workspace/39.spi_device_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1704902657 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1470352927 ps |
| CPU time | 15.73 seconds |
| Started | Mar 05 12:40:16 PM PST 24 |
| Finished | Mar 05 12:40:33 PM PST 24 |
| Peak memory | 215744 kb |
| Host | smart-4d14ca1d-c124-4396-8925-ec55d079f423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704902657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic e_tl_intg_err.1704902657 |
| Directory | /workspace/18.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2216700404 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 23402071032 ps |
| CPU time | 190.69 seconds |
| Started | Mar 05 01:36:31 PM PST 24 |
| Finished | Mar 05 01:39:42 PM PST 24 |
| Peak memory | 265232 kb |
| Host | smart-f1e9db2f-b664-4a41-b3df-ee695bcef919 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2216700404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle .2216700404 |
| Directory | /workspace/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3196893971 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 19263457584 ps |
| CPU time | 162.7 seconds |
| Started | Mar 05 01:40:34 PM PST 24 |
| Finished | Mar 05 01:43:17 PM PST 24 |
| Peak memory | 253352 kb |
| Host | smart-46ca9e9e-b4fc-4770-b8ec-fce848ce3639 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196893971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl e.3196893971 |
| Directory | /workspace/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/18.spi_device_stress_all.132588057 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 55967506786 ps |
| CPU time | 417.81 seconds |
| Started | Mar 05 01:39:21 PM PST 24 |
| Finished | Mar 05 01:46:20 PM PST 24 |
| Peak memory | 297256 kb |
| Host | smart-daaadd7e-fd77-4a17-a62e-09f7babee3af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132588057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres s_all.132588057 |
| Directory | /workspace/18.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/1.spi_device_ram_cfg.4283953294 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 17523568 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:35:58 PM PST 24 |
| Finished | Mar 05 01:35:59 PM PST 24 |
| Peak memory | 216064 kb |
| Host | smart-dcae54bb-f863-45c5-9590-a59bb93326e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283953294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.4283953294 |
| Directory | /workspace/1.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/15.spi_device_stress_all.1673486876 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 27764390185 ps |
| CPU time | 125.39 seconds |
| Started | Mar 05 01:38:49 PM PST 24 |
| Finished | Mar 05 01:40:54 PM PST 24 |
| Peak memory | 251928 kb |
| Host | smart-742aef73-7b22-4bfa-a77d-9f28f0d44550 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673486876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre ss_all.1673486876 |
| Directory | /workspace/15.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/13.spi_device_stress_all.604557254 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 44191580619 ps |
| CPU time | 345.12 seconds |
| Started | Mar 05 01:38:24 PM PST 24 |
| Finished | Mar 05 01:44:10 PM PST 24 |
| Peak memory | 255228 kb |
| Host | smart-88082fa3-9e7c-41b5-9e07-a65fee6b5ccb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604557254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres s_all.604557254 |
| Directory | /workspace/13.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/0.spi_device_alert_test.1875683052 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 13267384 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:35:58 PM PST 24 |
| Finished | Mar 05 01:35:59 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-a71a5e13-a2e3-431a-b7bc-4fe905665585 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875683052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1 875683052 |
| Directory | /workspace/0.spi_device_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1433202845 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 128552155 ps |
| CPU time | 4.75 seconds |
| Started | Mar 05 12:40:01 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 214628 kb |
| Host | smart-610fe14a-b603-4e74-a268-28786fd3065e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433202845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors. 1433202845 |
| Directory | /workspace/10.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/default/12.spi_device_flash_mode.462575449 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 461322496 ps |
| CPU time | 9.84 seconds |
| Started | Mar 05 01:38:11 PM PST 24 |
| Finished | Mar 05 01:38:21 PM PST 24 |
| Peak memory | 233628 kb |
| Host | smart-9ba615b0-3ca2-48bb-9b21-e17009daee11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462575449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.462575449 |
| Directory | /workspace/12.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/2.spi_device_stress_all.1493297259 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 24137696454 ps |
| CPU time | 154.78 seconds |
| Started | Mar 05 01:36:32 PM PST 24 |
| Finished | Mar 05 01:39:07 PM PST 24 |
| Peak memory | 273152 kb |
| Host | smart-618488d8-4a6a-4ee3-a4c5-86a6ca3d8a83 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493297259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres s_all.1493297259 |
| Directory | /workspace/2.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/39.spi_device_flash_and_tpm.2658762896 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 32997432800 ps |
| CPU time | 102.33 seconds |
| Started | Mar 05 01:42:33 PM PST 24 |
| Finished | Mar 05 01:44:16 PM PST 24 |
| Peak memory | 263652 kb |
| Host | smart-fd5d8f5f-0392-485f-988c-ff95ec89bcd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658762896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2658762896 |
| Directory | /workspace/39.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2089620599 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 132515740 ps |
| CPU time | 1.14 seconds |
| Started | Mar 05 12:39:47 PM PST 24 |
| Finished | Mar 05 12:39:48 PM PST 24 |
| Peak memory | 206196 kb |
| Host | smart-27729817-bcb2-4466-b607-30fd9084fe1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089620599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_hw_reset.2089620599 |
| Directory | /workspace/4.spi_device_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/48.spi_device_stress_all.154252308 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 84010628862 ps |
| CPU time | 221.23 seconds |
| Started | Mar 05 01:43:41 PM PST 24 |
| Finished | Mar 05 01:47:22 PM PST 24 |
| Peak memory | 240884 kb |
| Host | smart-cfdf2311-5772-4df0-b3b8-b53d9551b024 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154252308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres s_all.154252308 |
| Directory | /workspace/48.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/12.spi_device_mem_parity.4051814797 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 15174814 ps |
| CPU time | 1.02 seconds |
| Started | Mar 05 01:38:06 PM PST 24 |
| Finished | Mar 05 01:38:08 PM PST 24 |
| Peak memory | 216516 kb |
| Host | smart-6f7adb70-c64c-4f29-a04b-30f9795b437e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051814797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.spi_device_mem_parity.4051814797 |
| Directory | /workspace/12.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/43.spi_device_flash_and_tpm.1870225337 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 48771727407 ps |
| CPU time | 129.16 seconds |
| Started | Mar 05 01:43:00 PM PST 24 |
| Finished | Mar 05 01:45:10 PM PST 24 |
| Peak memory | 268924 kb |
| Host | smart-048ed4b3-6806-477d-b222-c021b2b2b672 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870225337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1870225337 |
| Directory | /workspace/43.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/47.spi_device_flash_all.189076706 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 105542302324 ps |
| CPU time | 99.84 seconds |
| Started | Mar 05 01:43:33 PM PST 24 |
| Finished | Mar 05 01:45:13 PM PST 24 |
| Peak memory | 273480 kb |
| Host | smart-e20dae74-53b2-4e40-8b91-6800545f6e84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189076706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.189076706 |
| Directory | /workspace/47.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/0.spi_device_sec_cm.4167860485 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 70826914 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:35:58 PM PST 24 |
| Finished | Mar 05 01:36:00 PM PST 24 |
| Peak memory | 234640 kb |
| Host | smart-02f55d46-15f4-4a32-8d8a-34474405fc24 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167860485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4167860485 |
| Directory | /workspace/0.spi_device_sec_cm/latest |
| Test location | /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3569481306 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 83005363547 ps |
| CPU time | 36.35 seconds |
| Started | Mar 05 01:38:52 PM PST 24 |
| Finished | Mar 05 01:39:28 PM PST 24 |
| Peak memory | 216224 kb |
| Host | smart-892c5835-93e2-43f4-973c-1cec540fcc19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569481306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3569481306 |
| Directory | /workspace/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/17.spi_device_flash_and_tpm.2313244337 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8312403128 ps |
| CPU time | 88.34 seconds |
| Started | Mar 05 01:39:05 PM PST 24 |
| Finished | Mar 05 01:40:36 PM PST 24 |
| Peak memory | 255000 kb |
| Host | smart-2d3c1625-ffee-419b-af83-569a00963a82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313244337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2313244337 |
| Directory | /workspace/17.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/7.spi_device_stress_all.2380143024 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 72149652382 ps |
| CPU time | 577.23 seconds |
| Started | Mar 05 01:37:24 PM PST 24 |
| Finished | Mar 05 01:47:01 PM PST 24 |
| Peak memory | 281888 kb |
| Host | smart-70ab52e2-d47e-460e-abf5-db64e62a8ecb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380143024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres s_all.2380143024 |
| Directory | /workspace/7.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4008847342 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 14397143317 ps |
| CPU time | 79.83 seconds |
| Started | Mar 05 01:40:49 PM PST 24 |
| Finished | Mar 05 01:42:09 PM PST 24 |
| Peak memory | 256508 kb |
| Host | smart-300c8f22-3b1e-43af-8813-f2f145a3d417 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008847342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl e.4008847342 |
| Directory | /workspace/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/11.spi_device_stress_all.1058768450 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 112348021921 ps |
| CPU time | 329.7 seconds |
| Started | Mar 05 01:38:05 PM PST 24 |
| Finished | Mar 05 01:43:36 PM PST 24 |
| Peak memory | 269876 kb |
| Host | smart-aaaf4752-7305-4828-b538-ff7ec3d600c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058768450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre ss_all.1058768450 |
| Directory | /workspace/11.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/17.spi_device_flash_mode.2857738918 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 17290597806 ps |
| CPU time | 47.83 seconds |
| Started | Mar 05 01:39:06 PM PST 24 |
| Finished | Mar 05 01:39:55 PM PST 24 |
| Peak memory | 239268 kb |
| Host | smart-952a761e-60bb-4af9-8c36-53016e8ddcf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857738918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2857738918 |
| Directory | /workspace/17.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/46.spi_device_stress_all.2066629505 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 24955738348 ps |
| CPU time | 206.39 seconds |
| Started | Mar 05 01:43:27 PM PST 24 |
| Finished | Mar 05 01:46:54 PM PST 24 |
| Peak memory | 279328 kb |
| Host | smart-8f9c239c-bded-4e09-948f-79f30927cdd0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066629505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre ss_all.2066629505 |
| Directory | /workspace/46.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/25.spi_device_stress_all.1639934280 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 26181780694 ps |
| CPU time | 174.22 seconds |
| Started | Mar 05 01:40:17 PM PST 24 |
| Finished | Mar 05 01:43:11 PM PST 24 |
| Peak memory | 249960 kb |
| Host | smart-22d8e3e2-72c0-4d0d-ae97-8f6b87e27331 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639934280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre ss_all.1639934280 |
| Directory | /workspace/25.spi_device_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2330935655 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 562710347 ps |
| CPU time | 16.07 seconds |
| Started | Mar 05 12:39:59 PM PST 24 |
| Finished | Mar 05 12:40:15 PM PST 24 |
| Peak memory | 214556 kb |
| Host | smart-b1210b22-6876-4ab5-989b-f42de16d468d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330935655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.2330935655 |
| Directory | /workspace/0.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2305308213 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 592047622 ps |
| CPU time | 17.88 seconds |
| Started | Mar 05 12:39:49 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 214692 kb |
| Host | smart-b7acbd6a-1bf5-4785-bdfc-3162b09e456c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305308213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device _tl_intg_err.2305308213 |
| Directory | /workspace/7.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/default/36.spi_device_stress_all.1830077106 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 82110433402 ps |
| CPU time | 268.42 seconds |
| Started | Mar 05 01:42:08 PM PST 24 |
| Finished | Mar 05 01:46:36 PM PST 24 |
| Peak memory | 281352 kb |
| Host | smart-593b6aad-bcf7-4bf7-aa3b-7ca013fec5d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830077106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre ss_all.1830077106 |
| Directory | /workspace/36.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/44.spi_device_stress_all.1675510603 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 198521099085 ps |
| CPU time | 89.93 seconds |
| Started | Mar 05 01:43:08 PM PST 24 |
| Finished | Mar 05 01:44:39 PM PST 24 |
| Peak memory | 254608 kb |
| Host | smart-d8a04d24-473a-47b5-83ff-b727b73c7d67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675510603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre ss_all.1675510603 |
| Directory | /workspace/44.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/45.spi_device_stress_all.461171051 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 284235233790 ps |
| CPU time | 435.64 seconds |
| Started | Mar 05 01:43:23 PM PST 24 |
| Finished | Mar 05 01:50:39 PM PST 24 |
| Peak memory | 283280 kb |
| Host | smart-46af18cd-ab4a-4578-a4e6-a79ed439fb21 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461171051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres s_all.461171051 |
| Directory | /workspace/45.spi_device_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3801571807 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 329350552 ps |
| CPU time | 4.02 seconds |
| Started | Mar 05 12:40:05 PM PST 24 |
| Finished | Mar 05 12:40:09 PM PST 24 |
| Peak memory | 214692 kb |
| Host | smart-a6687034-dd82-4369-8ed5-92d632e64ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801571807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 3801571807 |
| Directory | /workspace/18.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/default/14.spi_device_stress_all.1681472620 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 30197742295 ps |
| CPU time | 307.79 seconds |
| Started | Mar 05 01:38:43 PM PST 24 |
| Finished | Mar 05 01:43:50 PM PST 24 |
| Peak memory | 270324 kb |
| Host | smart-585c6521-e355-4fb5-b715-253c03060bac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681472620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre ss_all.1681472620 |
| Directory | /workspace/14.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/16.spi_device_stress_all.2931629106 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10969197141 ps |
| CPU time | 227.16 seconds |
| Started | Mar 05 01:38:57 PM PST 24 |
| Finished | Mar 05 01:42:44 PM PST 24 |
| Peak memory | 289996 kb |
| Host | smart-630a46c5-8e06-4089-a093-fe64811d2e55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931629106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre ss_all.2931629106 |
| Directory | /workspace/16.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.613726019 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 528811145 ps |
| CPU time | 8.99 seconds |
| Started | Mar 05 01:36:31 PM PST 24 |
| Finished | Mar 05 01:36:40 PM PST 24 |
| Peak memory | 229228 kb |
| Host | smart-8709cba2-8e11-4734-92eb-7bc5dc1567b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=613726019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap. 613726019 |
| Directory | /workspace/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.600418691 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 34498208432 ps |
| CPU time | 128.94 seconds |
| Started | Mar 05 01:42:32 PM PST 24 |
| Finished | Mar 05 01:44:41 PM PST 24 |
| Peak memory | 267552 kb |
| Host | smart-748b50b5-4a19-43c3-af0a-af701f450e8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=600418691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle .600418691 |
| Directory | /workspace/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/45.spi_device_flash_mode.3872642756 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5355757814 ps |
| CPU time | 21.89 seconds |
| Started | Mar 05 01:43:20 PM PST 24 |
| Finished | Mar 05 01:43:43 PM PST 24 |
| Peak memory | 240588 kb |
| Host | smart-33a7c7e5-07db-42ef-8147-0c665da9f19e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872642756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3872642756 |
| Directory | /workspace/45.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/10.spi_device_flash_and_tpm.3382529464 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 13981362512 ps |
| CPU time | 92.68 seconds |
| Started | Mar 05 01:37:56 PM PST 24 |
| Finished | Mar 05 01:39:29 PM PST 24 |
| Peak memory | 251496 kb |
| Host | smart-1d91ec2c-bc55-48f6-935f-791721e908f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382529464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3382529464 |
| Directory | /workspace/10.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/12.spi_device_flash_all.675608171 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 77774854715 ps |
| CPU time | 302.97 seconds |
| Started | Mar 05 01:38:13 PM PST 24 |
| Finished | Mar 05 01:43:16 PM PST 24 |
| Peak memory | 256624 kb |
| Host | smart-acb4cbc8-f8d8-424d-b2de-3546a4c050c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675608171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.675608171 |
| Directory | /workspace/12.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/2.spi_device_flash_all.922686335 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 77270041321 ps |
| CPU time | 135.45 seconds |
| Started | Mar 05 01:36:32 PM PST 24 |
| Finished | Mar 05 01:38:47 PM PST 24 |
| Peak memory | 256816 kb |
| Host | smart-4be9f396-9e04-494b-9396-f24697f789a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922686335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.922686335 |
| Directory | /workspace/2.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1608694449 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 100227094927 ps |
| CPU time | 371.23 seconds |
| Started | Mar 05 01:40:12 PM PST 24 |
| Finished | Mar 05 01:46:23 PM PST 24 |
| Peak memory | 256704 kb |
| Host | smart-5b66027c-f5ed-4429-accf-572c4fa48da6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608694449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl e.1608694449 |
| Directory | /workspace/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2871973228 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 152012744840 ps |
| CPU time | 308.97 seconds |
| Started | Mar 05 01:41:39 PM PST 24 |
| Finished | Mar 05 01:46:48 PM PST 24 |
| Peak memory | 254512 kb |
| Host | smart-85ddc65b-f118-426b-9e32-98470eb47c11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871973228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl e.2871973228 |
| Directory | /workspace/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/49.spi_device_flash_all.3530204298 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 103386179815 ps |
| CPU time | 131.06 seconds |
| Started | Mar 05 01:43:46 PM PST 24 |
| Finished | Mar 05 01:45:58 PM PST 24 |
| Peak memory | 248932 kb |
| Host | smart-5f1b6cc5-4e58-4f92-abbf-796abcd0d3b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530204298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3530204298 |
| Directory | /workspace/49.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1037880866 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1338479795 ps |
| CPU time | 4.09 seconds |
| Started | Mar 05 01:38:45 PM PST 24 |
| Finished | Mar 05 01:38:49 PM PST 24 |
| Peak memory | 233480 kb |
| Host | smart-aec7fc48-7d3d-4781-baff-1b74e1af03a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037880866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1037880866 |
| Directory | /workspace/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2959420322 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 541026585 ps |
| CPU time | 4.51 seconds |
| Started | Mar 05 12:39:49 PM PST 24 |
| Finished | Mar 05 12:39:53 PM PST 24 |
| Peak memory | 214584 kb |
| Host | smart-a061a22d-804c-46c7-a6b0-cd3315a82d25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959420322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2 959420322 |
| Directory | /workspace/0.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.914676821 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 83391380 ps |
| CPU time | 1 seconds |
| Started | Mar 05 12:39:37 PM PST 24 |
| Finished | Mar 05 12:39:38 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-70e2ed98-fabb-4149-a5c9-9f77e97230e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914676821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _hw_reset.914676821 |
| Directory | /workspace/1.spi_device_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2165985206 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2563582905 ps |
| CPU time | 16.97 seconds |
| Started | Mar 05 12:39:49 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 214640 kb |
| Host | smart-dc7348fa-c771-4c4f-a9df-6671486bdbed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165985206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic e_tl_intg_err.2165985206 |
| Directory | /workspace/10.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1977346980 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2070205373 ps |
| CPU time | 8.36 seconds |
| Started | Mar 05 12:39:51 PM PST 24 |
| Finished | Mar 05 12:39:59 PM PST 24 |
| Peak memory | 206392 kb |
| Host | smart-be2bf74b-8b1e-456f-815b-d1f7e847c905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977346980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_aliasing.1977346980 |
| Directory | /workspace/0.spi_device_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1891799410 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 7471449518 ps |
| CPU time | 27.25 seconds |
| Started | Mar 05 12:39:43 PM PST 24 |
| Finished | Mar 05 12:40:11 PM PST 24 |
| Peak memory | 206420 kb |
| Host | smart-d3686f30-923a-45f8-82af-8cc9255d5aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891799410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_bit_bash.1891799410 |
| Directory | /workspace/0.spi_device_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1684452460 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 19012603 ps |
| CPU time | 1.15 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:51 PM PST 24 |
| Peak memory | 206360 kb |
| Host | smart-09c38aed-02b3-4366-b5c3-b9dd586c0df9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684452460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_hw_reset.1684452460 |
| Directory | /workspace/0.spi_device_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2869694811 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 144932902 ps |
| CPU time | 3.91 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:54 PM PST 24 |
| Peak memory | 215736 kb |
| Host | smart-fa118897-3377-4f79-9407-edd7e80619d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869694811 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2869694811 |
| Directory | /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4009646982 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 75220834 ps |
| CPU time | 1.99 seconds |
| Started | Mar 05 12:39:48 PM PST 24 |
| Finished | Mar 05 12:39:50 PM PST 24 |
| Peak memory | 206556 kb |
| Host | smart-2cf0b492-d7b9-4013-b334-37aadf2c8839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009646982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4 009646982 |
| Directory | /workspace/0.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1040132103 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 56255426 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 12:39:42 PM PST 24 |
| Finished | Mar 05 12:39:43 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-ed076fff-4eab-40e4-ab12-7a72a77f5262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040132103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1 040132103 |
| Directory | /workspace/0.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2014895339 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 22092723 ps |
| CPU time | 1.75 seconds |
| Started | Mar 05 12:39:43 PM PST 24 |
| Finished | Mar 05 12:39:45 PM PST 24 |
| Peak memory | 214456 kb |
| Host | smart-e57a3abb-6f83-4848-ac07-b9dc85961aa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014895339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.2014895339 |
| Directory | /workspace/0.spi_device_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.588832180 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 15101317 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 12:39:54 PM PST 24 |
| Finished | Mar 05 12:39:55 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-bb2ae154-bfe5-45e2-85f9-25d01aa5af20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588832180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem _walk.588832180 |
| Directory | /workspace/0.spi_device_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.546881912 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 154377646 ps |
| CPU time | 3.98 seconds |
| Started | Mar 05 12:39:51 PM PST 24 |
| Finished | Mar 05 12:39:55 PM PST 24 |
| Peak memory | 214564 kb |
| Host | smart-5a144152-a9c1-47ac-b804-993f0e8fc0e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546881912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp i_device_same_csr_outstanding.546881912 |
| Directory | /workspace/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1511024759 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 120862944 ps |
| CPU time | 8.19 seconds |
| Started | Mar 05 12:39:51 PM PST 24 |
| Finished | Mar 05 12:39:59 PM PST 24 |
| Peak memory | 206332 kb |
| Host | smart-4e9cb4b6-996b-405b-801a-73001b278e34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511024759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_aliasing.1511024759 |
| Directory | /workspace/1.spi_device_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4031038023 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 535636382 ps |
| CPU time | 30.65 seconds |
| Started | Mar 05 12:39:57 PM PST 24 |
| Finished | Mar 05 12:40:28 PM PST 24 |
| Peak memory | 206308 kb |
| Host | smart-43e91f65-5802-44eb-a8db-56f02cc9af74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031038023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_bit_bash.4031038023 |
| Directory | /workspace/1.spi_device_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2079464972 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 179512147 ps |
| CPU time | 1.55 seconds |
| Started | Mar 05 12:39:41 PM PST 24 |
| Finished | Mar 05 12:39:43 PM PST 24 |
| Peak memory | 214720 kb |
| Host | smart-16a37035-33b2-46c0-bd5c-f3a8f5beb7cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079464972 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2079464972 |
| Directory | /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.338544123 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 144269070 ps |
| CPU time | 2.44 seconds |
| Started | Mar 05 12:39:57 PM PST 24 |
| Finished | Mar 05 12:40:00 PM PST 24 |
| Peak memory | 214528 kb |
| Host | smart-85d232de-77c2-4031-b62d-6420131248d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338544123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.338544123 |
| Directory | /workspace/1.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2861855582 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 57843445 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:51 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-9162b5d0-9fa5-4d78-906c-e94b0e707234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861855582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2 861855582 |
| Directory | /workspace/1.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2073444355 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 201717713 ps |
| CPU time | 1.8 seconds |
| Started | Mar 05 12:39:48 PM PST 24 |
| Finished | Mar 05 12:39:50 PM PST 24 |
| Peak memory | 214500 kb |
| Host | smart-82e275b0-e8af-430a-9e90-e92da7a4663e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073444355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi _device_mem_partial_access.2073444355 |
| Directory | /workspace/1.spi_device_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1179046455 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 16220294 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 12:39:42 PM PST 24 |
| Finished | Mar 05 12:39:43 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-d8188243-1f3f-4c24-bf42-615823747c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179046455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me m_walk.1179046455 |
| Directory | /workspace/1.spi_device_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3987690769 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 142259977 ps |
| CPU time | 2.81 seconds |
| Started | Mar 05 12:39:43 PM PST 24 |
| Finished | Mar 05 12:39:46 PM PST 24 |
| Peak memory | 206288 kb |
| Host | smart-035aecbc-49b9-40da-89c0-1d174b9ba58f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987690769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s pi_device_same_csr_outstanding.3987690769 |
| Directory | /workspace/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3669901050 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 69741521 ps |
| CPU time | 5.05 seconds |
| Started | Mar 05 12:39:41 PM PST 24 |
| Finished | Mar 05 12:39:46 PM PST 24 |
| Peak memory | 214788 kb |
| Host | smart-1c41940d-de7b-401c-977b-9552d05a10cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669901050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3 669901050 |
| Directory | /workspace/1.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2190199853 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3804036509 ps |
| CPU time | 21.34 seconds |
| Started | Mar 05 12:39:56 PM PST 24 |
| Finished | Mar 05 12:40:17 PM PST 24 |
| Peak memory | 214648 kb |
| Host | smart-06f474a4-0946-487e-9dae-45dc219b4073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190199853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device _tl_intg_err.2190199853 |
| Directory | /workspace/1.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1817550191 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 378245659 ps |
| CPU time | 2.52 seconds |
| Started | Mar 05 12:39:45 PM PST 24 |
| Finished | Mar 05 12:39:48 PM PST 24 |
| Peak memory | 215072 kb |
| Host | smart-7f77b1be-e2c2-4451-8e11-6aa475d0b1d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817550191 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1817550191 |
| Directory | /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3854360747 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 223550627 ps |
| CPU time | 1.9 seconds |
| Started | Mar 05 12:40:05 PM PST 24 |
| Finished | Mar 05 12:40:08 PM PST 24 |
| Peak memory | 206464 kb |
| Host | smart-2830cc8f-6734-4995-bcf4-8253a66a44f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854360747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw. 3854360747 |
| Directory | /workspace/10.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.spi_device_intr_test.957173176 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 189442916 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 12:40:06 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-c4432799-b3af-4633-8d7c-c369121ea034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957173176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.957173176 |
| Directory | /workspace/10.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4115366771 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 28030897 ps |
| CPU time | 1.75 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:40:01 PM PST 24 |
| Peak memory | 214372 kb |
| Host | smart-3a54aa59-fe83-4d17-8947-f20a31f29709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115366771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. spi_device_same_csr_outstanding.4115366771 |
| Directory | /workspace/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3488801711 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 276958028 ps |
| CPU time | 2.86 seconds |
| Started | Mar 05 12:39:54 PM PST 24 |
| Finished | Mar 05 12:39:57 PM PST 24 |
| Peak memory | 215668 kb |
| Host | smart-c84671d6-4b17-4b02-b506-b5b706631b89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488801711 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3488801711 |
| Directory | /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.44459161 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 64248618 ps |
| CPU time | 1.27 seconds |
| Started | Mar 05 12:39:48 PM PST 24 |
| Finished | Mar 05 12:39:49 PM PST 24 |
| Peak memory | 206464 kb |
| Host | smart-f3e30556-b70d-40f5-99c4-51c59adbd42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44459161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.44459161 |
| Directory | /workspace/11.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.spi_device_intr_test.318103781 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 32424426 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:40:14 PM PST 24 |
| Finished | Mar 05 12:40:15 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-8256115d-e75d-4458-81b9-eb13144161d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318103781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.318103781 |
| Directory | /workspace/11.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1842810178 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 311505838 ps |
| CPU time | 2.85 seconds |
| Started | Mar 05 12:40:22 PM PST 24 |
| Finished | Mar 05 12:40:25 PM PST 24 |
| Peak memory | 214568 kb |
| Host | smart-061cb202-9b92-4e7b-b4b7-fd4c74ed4641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842810178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. spi_device_same_csr_outstanding.1842810178 |
| Directory | /workspace/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1218806361 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 102560282 ps |
| CPU time | 3.64 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:40:03 PM PST 24 |
| Peak memory | 214700 kb |
| Host | smart-a6ac5941-0937-4de8-93e3-725451e91921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218806361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors. 1218806361 |
| Directory | /workspace/11.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3943768773 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 566625868 ps |
| CPU time | 7.45 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:58 PM PST 24 |
| Peak memory | 220944 kb |
| Host | smart-71c2381f-5ca2-4003-a75c-553928f0a78e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943768773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic e_tl_intg_err.3943768773 |
| Directory | /workspace/11.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2773473194 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 271670410 ps |
| CPU time | 3.67 seconds |
| Started | Mar 05 12:40:03 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 214668 kb |
| Host | smart-31c8ac91-4fc4-4c6a-b24a-1961ca2b9ffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773473194 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2773473194 |
| Directory | /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1277572354 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 111711881 ps |
| CPU time | 1.9 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:39:55 PM PST 24 |
| Peak memory | 206356 kb |
| Host | smart-2fd9c899-4be6-4fcf-8e1a-f14b1e726cf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277572354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw. 1277572354 |
| Directory | /workspace/12.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3666697519 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 15029972 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 12:39:57 PM PST 24 |
| Finished | Mar 05 12:39:58 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-1689f113-8399-4ea5-96d2-15319d8245e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666697519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 3666697519 |
| Directory | /workspace/12.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.620507775 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 228537110 ps |
| CPU time | 4.13 seconds |
| Started | Mar 05 12:40:13 PM PST 24 |
| Finished | Mar 05 12:40:18 PM PST 24 |
| Peak memory | 206240 kb |
| Host | smart-14bffb17-51a7-4911-9188-1e18d117d431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620507775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s pi_device_same_csr_outstanding.620507775 |
| Directory | /workspace/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2689876738 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 59522100 ps |
| CPU time | 1.92 seconds |
| Started | Mar 05 12:40:03 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 213320 kb |
| Host | smart-4f728b6a-e093-4821-ad1f-46e9e48b236e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689876738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors. 2689876738 |
| Directory | /workspace/12.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1527513042 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 214939377 ps |
| CPU time | 6.58 seconds |
| Started | Mar 05 12:40:03 PM PST 24 |
| Finished | Mar 05 12:40:10 PM PST 24 |
| Peak memory | 214564 kb |
| Host | smart-9e22311c-0762-48a4-997a-d9c25ea9eeec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527513042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic e_tl_intg_err.1527513042 |
| Directory | /workspace/12.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.737115245 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 132766505 ps |
| CPU time | 3.67 seconds |
| Started | Mar 05 12:40:19 PM PST 24 |
| Finished | Mar 05 12:40:23 PM PST 24 |
| Peak memory | 216768 kb |
| Host | smart-2f6c530e-d831-40db-86f9-044fece1d9bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737115245 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.737115245 |
| Directory | /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3508567246 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 69854617 ps |
| CPU time | 1.27 seconds |
| Started | Mar 05 12:39:52 PM PST 24 |
| Finished | Mar 05 12:39:53 PM PST 24 |
| Peak memory | 206340 kb |
| Host | smart-e4368098-b0e5-42fd-9a5e-0afeca803484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508567246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw. 3508567246 |
| Directory | /workspace/13.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.spi_device_intr_test.525606444 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 21704847 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 12:39:56 PM PST 24 |
| Finished | Mar 05 12:39:57 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-32acae9b-9da1-4e1d-9208-a3987505dd5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525606444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.525606444 |
| Directory | /workspace/13.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1067973479 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 147240833 ps |
| CPU time | 2.53 seconds |
| Started | Mar 05 12:40:18 PM PST 24 |
| Finished | Mar 05 12:40:21 PM PST 24 |
| Peak memory | 214272 kb |
| Host | smart-125afe64-24ef-4cca-8004-01d04f458980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067973479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. spi_device_same_csr_outstanding.1067973479 |
| Directory | /workspace/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.497534971 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 122404748 ps |
| CPU time | 2.16 seconds |
| Started | Mar 05 12:40:17 PM PST 24 |
| Finished | Mar 05 12:40:20 PM PST 24 |
| Peak memory | 214540 kb |
| Host | smart-89f9bf68-abd3-4e13-9c12-a1c1e8a249b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497534971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.497534971 |
| Directory | /workspace/13.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.715167674 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 496594205 ps |
| CPU time | 6.74 seconds |
| Started | Mar 05 12:40:10 PM PST 24 |
| Finished | Mar 05 12:40:17 PM PST 24 |
| Peak memory | 214600 kb |
| Host | smart-25997a05-cecd-4dd8-964d-ffaa9c2ce494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715167674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device _tl_intg_err.715167674 |
| Directory | /workspace/13.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.420283195 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 345809950 ps |
| CPU time | 1.91 seconds |
| Started | Mar 05 12:40:09 PM PST 24 |
| Finished | Mar 05 12:40:11 PM PST 24 |
| Peak memory | 214648 kb |
| Host | smart-43415fd7-e9af-4757-a7b6-b5a64bc44e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420283195 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.420283195 |
| Directory | /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1542315241 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 126551917 ps |
| CPU time | 1.24 seconds |
| Started | Mar 05 12:39:51 PM PST 24 |
| Finished | Mar 05 12:39:57 PM PST 24 |
| Peak memory | 206344 kb |
| Host | smart-3cb3e3ca-6e36-4e4d-bb10-3f8a18045e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542315241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw. 1542315241 |
| Directory | /workspace/14.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3345583951 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 19504319 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 12:40:06 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-03d3cffc-a0bc-4a5d-92a2-ad9fe5e2b209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345583951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 3345583951 |
| Directory | /workspace/14.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3678768759 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 47929453 ps |
| CPU time | 1.67 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:39:55 PM PST 24 |
| Peak memory | 206296 kb |
| Host | smart-4d43a0b9-2069-46ee-ac13-75a94e244ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678768759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. spi_device_same_csr_outstanding.3678768759 |
| Directory | /workspace/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3785605347 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 147894350 ps |
| CPU time | 3.2 seconds |
| Started | Mar 05 12:40:06 PM PST 24 |
| Finished | Mar 05 12:40:10 PM PST 24 |
| Peak memory | 215736 kb |
| Host | smart-9d5a4a56-807d-47ff-826b-2a004b8ef9e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785605347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors. 3785605347 |
| Directory | /workspace/14.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2767024466 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4245047618 ps |
| CPU time | 8.28 seconds |
| Started | Mar 05 12:39:48 PM PST 24 |
| Finished | Mar 05 12:39:57 PM PST 24 |
| Peak memory | 214628 kb |
| Host | smart-be8c315a-d6f6-46bc-bd39-e0e45c9240c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767024466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic e_tl_intg_err.2767024466 |
| Directory | /workspace/14.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.85707498 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 55702566 ps |
| CPU time | 3.95 seconds |
| Started | Mar 05 12:40:01 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 215908 kb |
| Host | smart-cbfb7448-b12f-4db8-a63f-e4da2b3b1967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85707498 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.85707498 |
| Directory | /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1329459129 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 322804835 ps |
| CPU time | 2.13 seconds |
| Started | Mar 05 12:39:56 PM PST 24 |
| Finished | Mar 05 12:39:59 PM PST 24 |
| Peak memory | 214532 kb |
| Host | smart-3c8ff41d-2681-4e4c-a5da-c5eefd6e1d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329459129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw. 1329459129 |
| Directory | /workspace/15.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1635388498 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 22449889 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 12:40:03 PM PST 24 |
| Finished | Mar 05 12:40:04 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-36bb09a3-7e3e-431c-a920-f00ba2c1640d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635388498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test. 1635388498 |
| Directory | /workspace/15.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1439753795 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 169322465 ps |
| CPU time | 2.85 seconds |
| Started | Mar 05 12:40:04 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 214596 kb |
| Host | smart-f82d9d8b-39d9-4472-905b-3471cc1e641f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439753795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. spi_device_same_csr_outstanding.1439753795 |
| Directory | /workspace/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.464364530 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 55148376 ps |
| CPU time | 2.03 seconds |
| Started | Mar 05 12:39:52 PM PST 24 |
| Finished | Mar 05 12:39:54 PM PST 24 |
| Peak memory | 214640 kb |
| Host | smart-165661d1-c6ba-4e42-a833-e366497b8359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464364530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.464364530 |
| Directory | /workspace/15.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2244352131 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 293067912 ps |
| CPU time | 7.91 seconds |
| Started | Mar 05 12:40:06 PM PST 24 |
| Finished | Mar 05 12:40:14 PM PST 24 |
| Peak memory | 214456 kb |
| Host | smart-835eef7f-472e-4b43-9218-2132dded352d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244352131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic e_tl_intg_err.2244352131 |
| Directory | /workspace/15.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2857332228 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 103005296 ps |
| CPU time | 2.61 seconds |
| Started | Mar 05 12:40:23 PM PST 24 |
| Finished | Mar 05 12:40:25 PM PST 24 |
| Peak memory | 215696 kb |
| Host | smart-3a7c0711-e9e3-47af-8451-6f7225d0190d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857332228 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2857332228 |
| Directory | /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4081171151 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 75434087 ps |
| CPU time | 1.87 seconds |
| Started | Mar 05 12:41:32 PM PST 24 |
| Finished | Mar 05 12:41:34 PM PST 24 |
| Peak memory | 206208 kb |
| Host | smart-8c8bc225-34f0-46ff-941a-ba616c5251ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081171151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw. 4081171151 |
| Directory | /workspace/16.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.spi_device_intr_test.288548102 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 12851666 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 12:39:52 PM PST 24 |
| Finished | Mar 05 12:39:53 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-614c4b9d-fdb0-490a-96cd-ac2e3a107821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288548102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.288548102 |
| Directory | /workspace/16.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2535413477 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 27071215 ps |
| CPU time | 1.83 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:40:01 PM PST 24 |
| Peak memory | 214472 kb |
| Host | smart-1a8e14b4-23b7-41b1-ade9-94894309e6bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535413477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. spi_device_same_csr_outstanding.2535413477 |
| Directory | /workspace/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4142911058 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 124014320 ps |
| CPU time | 3.05 seconds |
| Started | Mar 05 12:40:05 PM PST 24 |
| Finished | Mar 05 12:40:08 PM PST 24 |
| Peak memory | 214656 kb |
| Host | smart-5f1d239a-fec8-4c6f-96fc-4715a18fdddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142911058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors. 4142911058 |
| Directory | /workspace/16.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3562097149 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 320030787 ps |
| CPU time | 7.53 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 214532 kb |
| Host | smart-afd439a5-f0a0-42a2-a3f5-90bc406cc2a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562097149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic e_tl_intg_err.3562097149 |
| Directory | /workspace/16.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3430339793 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 475523116 ps |
| CPU time | 3.49 seconds |
| Started | Mar 05 12:39:48 PM PST 24 |
| Finished | Mar 05 12:39:51 PM PST 24 |
| Peak memory | 215952 kb |
| Host | smart-3c049718-5834-4040-af75-7be9962f0388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430339793 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3430339793 |
| Directory | /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2909502029 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 39728037 ps |
| CPU time | 1.32 seconds |
| Started | Mar 05 12:40:04 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 206244 kb |
| Host | smart-6b7c390c-d522-4a3d-903d-99f584e6ef02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909502029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw. 2909502029 |
| Directory | /workspace/17.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.spi_device_intr_test.251258319 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 10268338 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 12:39:59 PM PST 24 |
| Finished | Mar 05 12:40:00 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-ab3cb970-683f-45e2-bc5f-fc5e88fe17dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251258319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.251258319 |
| Directory | /workspace/17.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1068170917 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 896581497 ps |
| CPU time | 3.14 seconds |
| Started | Mar 05 12:40:02 PM PST 24 |
| Finished | Mar 05 12:40:05 PM PST 24 |
| Peak memory | 214528 kb |
| Host | smart-6e317d68-780d-43cb-8458-7a9a41c4f984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068170917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. spi_device_same_csr_outstanding.1068170917 |
| Directory | /workspace/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.768935496 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 103789340 ps |
| CPU time | 1.72 seconds |
| Started | Mar 05 12:39:54 PM PST 24 |
| Finished | Mar 05 12:39:56 PM PST 24 |
| Peak memory | 214584 kb |
| Host | smart-ae49b31b-a2a1-4d0d-b837-2beca472144f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768935496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.768935496 |
| Directory | /workspace/17.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.422359386 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 106356046 ps |
| CPU time | 6.27 seconds |
| Started | Mar 05 12:40:00 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 220020 kb |
| Host | smart-d51a2b96-f949-4884-ac11-fda8c8ab294b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422359386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device _tl_intg_err.422359386 |
| Directory | /workspace/17.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.266346120 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 28308140 ps |
| CPU time | 1.88 seconds |
| Started | Mar 05 12:39:59 PM PST 24 |
| Finished | Mar 05 12:40:01 PM PST 24 |
| Peak memory | 214652 kb |
| Host | smart-6705803a-6a23-4716-a3b8-12dfcbdaf3f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266346120 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.266346120 |
| Directory | /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.276801761 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 40365113 ps |
| CPU time | 1.43 seconds |
| Started | Mar 05 12:39:48 PM PST 24 |
| Finished | Mar 05 12:39:50 PM PST 24 |
| Peak memory | 206400 kb |
| Host | smart-78cd7456-b59a-499f-b5f1-30accc6d36b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276801761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.276801761 |
| Directory | /workspace/18.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1156433948 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 14879391 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:39:54 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-65d0bdbb-f61d-4e81-8b02-fc1e45cc02c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156433948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 1156433948 |
| Directory | /workspace/18.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.128758510 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 1041923838 ps |
| CPU time | 3.87 seconds |
| Started | Mar 05 12:40:04 PM PST 24 |
| Finished | Mar 05 12:40:13 PM PST 24 |
| Peak memory | 206180 kb |
| Host | smart-547645df-9c8c-4bda-9580-dc0759848503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128758510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s pi_device_same_csr_outstanding.128758510 |
| Directory | /workspace/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1673885378 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 197689677 ps |
| CPU time | 3.51 seconds |
| Started | Mar 05 12:40:12 PM PST 24 |
| Finished | Mar 05 12:40:16 PM PST 24 |
| Peak memory | 217400 kb |
| Host | smart-01702d80-d3ad-4a11-9bd2-0824799ea4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673885378 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1673885378 |
| Directory | /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1642468883 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 227990153 ps |
| CPU time | 1.85 seconds |
| Started | Mar 05 12:40:15 PM PST 24 |
| Finished | Mar 05 12:40:17 PM PST 24 |
| Peak memory | 214480 kb |
| Host | smart-6a8bdd49-a33c-4361-95eb-0ab9acf5e368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642468883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw. 1642468883 |
| Directory | /workspace/19.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1472265569 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 18624040 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:40:04 PM PST 24 |
| Finished | Mar 05 12:40:05 PM PST 24 |
| Peak memory | 202000 kb |
| Host | smart-17f29a01-74fd-4994-b72c-2cd0179a0dc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472265569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 1472265569 |
| Directory | /workspace/19.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1274673426 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 45328030 ps |
| CPU time | 2.72 seconds |
| Started | Mar 05 12:40:03 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 214584 kb |
| Host | smart-9faee5a7-0de1-4529-b443-eb833e4d3038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274673426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. spi_device_same_csr_outstanding.1274673426 |
| Directory | /workspace/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2010208772 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 337154668 ps |
| CPU time | 2.19 seconds |
| Started | Mar 05 12:39:54 PM PST 24 |
| Finished | Mar 05 12:39:56 PM PST 24 |
| Peak memory | 214696 kb |
| Host | smart-0cd4fe6c-c205-4c1b-9b60-6d663087d6eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010208772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors. 2010208772 |
| Directory | /workspace/19.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.798758306 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 1215745285 ps |
| CPU time | 7.75 seconds |
| Started | Mar 05 12:40:00 PM PST 24 |
| Finished | Mar 05 12:40:08 PM PST 24 |
| Peak memory | 214512 kb |
| Host | smart-14872593-7c7c-4ca9-a130-7c11fd38f53e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798758306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device _tl_intg_err.798758306 |
| Directory | /workspace/19.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2665946614 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 1354415701 ps |
| CPU time | 7.84 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:40:01 PM PST 24 |
| Peak memory | 214476 kb |
| Host | smart-e16bde88-7d31-4a4a-9884-ed3c09341703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665946614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.2665946614 |
| Directory | /workspace/2.spi_device_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1913189116 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 6012172115 ps |
| CPU time | 25.18 seconds |
| Started | Mar 05 12:39:59 PM PST 24 |
| Finished | Mar 05 12:40:24 PM PST 24 |
| Peak memory | 206588 kb |
| Host | smart-eef585f4-b432-481f-852d-4c20c5cd7d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913189116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_bit_bash.1913189116 |
| Directory | /workspace/2.spi_device_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2070476789 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 31982163 ps |
| CPU time | 1.09 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:51 PM PST 24 |
| Peak memory | 214576 kb |
| Host | smart-fdc64b74-6b71-4085-b21b-6c5ae6fa5853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070476789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_hw_reset.2070476789 |
| Directory | /workspace/2.spi_device_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.405682903 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 90456848 ps |
| CPU time | 2.74 seconds |
| Started | Mar 05 12:40:10 PM PST 24 |
| Finished | Mar 05 12:40:13 PM PST 24 |
| Peak memory | 215632 kb |
| Host | smart-9fc5db7f-03f4-4062-aa78-ff82c6fd43f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405682903 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.405682903 |
| Directory | /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2834053272 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 43972551 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 12:39:39 PM PST 24 |
| Finished | Mar 05 12:39:40 PM PST 24 |
| Peak memory | 206304 kb |
| Host | smart-7209feb9-ba65-49ca-898d-66c915a16bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834053272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2 834053272 |
| Directory | /workspace/2.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3505495007 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 16165840 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 12:39:42 PM PST 24 |
| Finished | Mar 05 12:39:44 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-02ec2c1c-a69c-481e-9a49-ae6df9ae150d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505495007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3 505495007 |
| Directory | /workspace/2.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.536016704 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 62013125 ps |
| CPU time | 1.32 seconds |
| Started | Mar 05 12:39:51 PM PST 24 |
| Finished | Mar 05 12:39:53 PM PST 24 |
| Peak memory | 214476 kb |
| Host | smart-1ad38c70-e464-4a90-a082-b980e2f31b5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536016704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_ device_mem_partial_access.536016704 |
| Directory | /workspace/2.spi_device_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1035436374 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 35854084 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:50 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-9d556787-b456-4161-a49c-3a570a69fe61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035436374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me m_walk.1035436374 |
| Directory | /workspace/2.spi_device_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4247691794 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 204769107 ps |
| CPU time | 4.12 seconds |
| Started | Mar 05 12:39:55 PM PST 24 |
| Finished | Mar 05 12:40:00 PM PST 24 |
| Peak memory | 214528 kb |
| Host | smart-0452aed7-2fbe-4078-9f73-09d6bf757664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247691794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s pi_device_same_csr_outstanding.4247691794 |
| Directory | /workspace/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1892315623 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 52189821 ps |
| CPU time | 1.57 seconds |
| Started | Mar 05 12:39:38 PM PST 24 |
| Finished | Mar 05 12:39:40 PM PST 24 |
| Peak memory | 214584 kb |
| Host | smart-fce44268-8894-4f65-8cd6-1ee66cb8b65c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892315623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1 892315623 |
| Directory | /workspace/2.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.397861357 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 443987334 ps |
| CPU time | 6.94 seconds |
| Started | Mar 05 12:39:44 PM PST 24 |
| Finished | Mar 05 12:39:51 PM PST 24 |
| Peak memory | 214532 kb |
| Host | smart-87d0e215-b8ac-44bd-a2b6-92ab10ae1542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397861357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_ tl_intg_err.397861357 |
| Directory | /workspace/2.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.spi_device_intr_test.11900816 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 17771927 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 12:40:13 PM PST 24 |
| Finished | Mar 05 12:40:14 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-b6ede10f-604b-42e0-870f-fd1d71803b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11900816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.11900816 |
| Directory | /workspace/20.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2330569338 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 17336552 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 12:40:19 PM PST 24 |
| Finished | Mar 05 12:40:20 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-85472bf6-71f8-4826-8fe1-fcdb2f179802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330569338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test. 2330569338 |
| Directory | /workspace/21.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3183640892 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 16456332 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 12:40:00 PM PST 24 |
| Finished | Mar 05 12:40:01 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-b18aa074-f043-4e6b-849f-a562c002f795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183640892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 3183640892 |
| Directory | /workspace/22.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.spi_device_intr_test.527783701 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 28464375 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:40:00 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-444a3c97-8b10-462f-8fc3-db8408c9d636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527783701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.527783701 |
| Directory | /workspace/23.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1181452944 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 16672218 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 12:41:28 PM PST 24 |
| Finished | Mar 05 12:41:29 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-47f65f1f-8f32-48d4-8197-8a2defec5f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181452944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test. 1181452944 |
| Directory | /workspace/24.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3031543692 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 26365291 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 12:41:34 PM PST 24 |
| Finished | Mar 05 12:41:34 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-7eddc19b-305e-4fa6-9ce5-1eff76a2010c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031543692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test. 3031543692 |
| Directory | /workspace/25.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2519374012 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 13358603 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 12:41:30 PM PST 24 |
| Finished | Mar 05 12:41:31 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-d5eb75ec-9418-4706-8067-b20211f3804b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519374012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test. 2519374012 |
| Directory | /workspace/26.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3066520088 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 16168684 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 12:40:02 PM PST 24 |
| Finished | Mar 05 12:40:08 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-a29c3cd7-5755-4e12-b833-b15ed99e9192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066520088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test. 3066520088 |
| Directory | /workspace/27.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4194081362 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 32623772 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:41:15 PM PST 24 |
| Finished | Mar 05 12:41:17 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-208f0513-2341-4423-9ea0-c42aaac82767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194081362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 4194081362 |
| Directory | /workspace/28.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.spi_device_intr_test.66600404 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 14617691 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:41:37 PM PST 24 |
| Finished | Mar 05 12:41:38 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-13ed6895-fe69-4d41-ab91-68a9fc620f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66600404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.66600404 |
| Directory | /workspace/29.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2674491295 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 111141177 ps |
| CPU time | 7.66 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:58 PM PST 24 |
| Peak memory | 206392 kb |
| Host | smart-7bc9cb99-fdf6-4b26-8199-dd334223b4a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674491295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_aliasing.2674491295 |
| Directory | /workspace/3.spi_device_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1338252231 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 608426020 ps |
| CPU time | 12.81 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:40:03 PM PST 24 |
| Peak memory | 205940 kb |
| Host | smart-addb01c7-fbd5-441e-9b44-ef12d6ba54ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338252231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_bit_bash.1338252231 |
| Directory | /workspace/3.spi_device_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1898643620 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 177590577 ps |
| CPU time | 0.97 seconds |
| Started | Mar 05 12:39:45 PM PST 24 |
| Finished | Mar 05 12:39:46 PM PST 24 |
| Peak memory | 205804 kb |
| Host | smart-1271a5d2-f80f-4681-9a07-0950162586ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898643620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_hw_reset.1898643620 |
| Directory | /workspace/3.spi_device_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2794595335 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 173419352 ps |
| CPU time | 3.99 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:39:57 PM PST 24 |
| Peak memory | 216064 kb |
| Host | smart-d086bd46-5952-458c-9f31-7395fb4d4845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794595335 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2794595335 |
| Directory | /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.251432869 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 48174396 ps |
| CPU time | 1.43 seconds |
| Started | Mar 05 12:39:46 PM PST 24 |
| Finished | Mar 05 12:39:48 PM PST 24 |
| Peak memory | 206400 kb |
| Host | smart-bc12b0e9-5f0e-4b25-a514-a3559edbb27d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251432869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.251432869 |
| Directory | /workspace/3.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_intr_test.831638238 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 44505233 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:39:54 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-228f7081-9a9c-4f33-ac95-f375497314b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831638238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.831638238 |
| Directory | /workspace/3.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2004356813 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 98672925 ps |
| CPU time | 1.29 seconds |
| Started | Mar 05 12:39:47 PM PST 24 |
| Finished | Mar 05 12:39:49 PM PST 24 |
| Peak memory | 214532 kb |
| Host | smart-501a1b00-8963-46e5-8239-92d6a33f8132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004356813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi _device_mem_partial_access.2004356813 |
| Directory | /workspace/3.spi_device_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1007787791 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 33274541 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 12:39:45 PM PST 24 |
| Finished | Mar 05 12:39:52 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-b267e247-4058-47f4-aae7-007500af7db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007787791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me m_walk.1007787791 |
| Directory | /workspace/3.spi_device_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.772979338 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 687625696 ps |
| CPU time | 3.79 seconds |
| Started | Mar 05 12:40:05 PM PST 24 |
| Finished | Mar 05 12:40:10 PM PST 24 |
| Peak memory | 214564 kb |
| Host | smart-d89f1f95-e242-4df2-86f0-d4a0092c91d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772979338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp i_device_same_csr_outstanding.772979338 |
| Directory | /workspace/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2205158024 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 176230083 ps |
| CPU time | 5.33 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:40:03 PM PST 24 |
| Peak memory | 215620 kb |
| Host | smart-3a80d0e1-0698-402b-bc59-b091762cd8e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205158024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2 205158024 |
| Directory | /workspace/3.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2136892205 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 14234721691 ps |
| CPU time | 16.74 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 214616 kb |
| Host | smart-d3f1fd93-77b4-4897-bf6f-21304108f321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136892205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device _tl_intg_err.2136892205 |
| Directory | /workspace/3.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2611334689 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 24920141 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 12:40:07 PM PST 24 |
| Finished | Mar 05 12:40:08 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-b091e655-4bcf-4026-8a6b-ae929d3ac653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611334689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test. 2611334689 |
| Directory | /workspace/30.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.spi_device_intr_test.77071531 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 55859873 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 12:40:06 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-fd18aac6-8604-46ff-9f16-212ea97cab07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77071531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.77071531 |
| Directory | /workspace/31.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1416508679 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 50621553 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 12:40:16 PM PST 24 |
| Finished | Mar 05 12:40:17 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-ae852586-9747-4711-805d-fe981195d836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416508679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test. 1416508679 |
| Directory | /workspace/32.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.spi_device_intr_test.640346771 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 35078392 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:40:04 PM PST 24 |
| Finished | Mar 05 12:40:05 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-499b2fb0-f1de-40d4-bc0f-521191393a35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640346771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.640346771 |
| Directory | /workspace/33.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.spi_device_intr_test.974372564 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 11479717 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 12:40:09 PM PST 24 |
| Finished | Mar 05 12:40:10 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-bf271f0c-898b-4ef4-b2a7-a2968e3ebd91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974372564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.974372564 |
| Directory | /workspace/34.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3581131385 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 16926039 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 12:39:57 PM PST 24 |
| Finished | Mar 05 12:40:04 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-dffaf2d2-62ab-4142-a215-893bbbb3fc6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581131385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test. 3581131385 |
| Directory | /workspace/35.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2915623122 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 38490554 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 12:40:11 PM PST 24 |
| Finished | Mar 05 12:40:12 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-c7ee97e9-5eef-40d8-95f0-7e6e55593640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915623122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test. 2915623122 |
| Directory | /workspace/36.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4174599636 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 38128105 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:40:01 PM PST 24 |
| Finished | Mar 05 12:40:03 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-3b61ef20-6458-43ff-8423-f7e326fde97d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174599636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test. 4174599636 |
| Directory | /workspace/37.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4028903592 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 27447641 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:39:59 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-854504ef-cda7-4ec8-8bf6-dffc2f1da753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028903592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test. 4028903592 |
| Directory | /workspace/38.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1310435577 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 14661504 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 12:40:16 PM PST 24 |
| Finished | Mar 05 12:40:18 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-ca38fec9-0053-4ca8-8b50-f60ec2ba8baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310435577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test. 1310435577 |
| Directory | /workspace/39.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4051225589 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 244813187 ps |
| CPU time | 7.95 seconds |
| Started | Mar 05 12:39:55 PM PST 24 |
| Finished | Mar 05 12:40:03 PM PST 24 |
| Peak memory | 206260 kb |
| Host | smart-d8e25b87-aee5-45e1-98b4-19a8fb01e031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051225589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_aliasing.4051225589 |
| Directory | /workspace/4.spi_device_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3346864374 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 1884794588 ps |
| CPU time | 33.66 seconds |
| Started | Mar 05 12:40:01 PM PST 24 |
| Finished | Mar 05 12:40:35 PM PST 24 |
| Peak memory | 206352 kb |
| Host | smart-81f7cdc5-0db4-413b-8921-21565e7980bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346864374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_bit_bash.3346864374 |
| Directory | /workspace/4.spi_device_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1634540214 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 135307856 ps |
| CPU time | 2.57 seconds |
| Started | Mar 05 12:40:12 PM PST 24 |
| Finished | Mar 05 12:40:15 PM PST 24 |
| Peak memory | 214800 kb |
| Host | smart-5f1a143d-1906-46ec-8d79-fd9e8e2f49ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634540214 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1634540214 |
| Directory | /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2590702093 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 1790713859 ps |
| CPU time | 2.7 seconds |
| Started | Mar 05 12:39:56 PM PST 24 |
| Finished | Mar 05 12:39:59 PM PST 24 |
| Peak memory | 206400 kb |
| Host | smart-24536bd1-20e9-45ed-b42c-395f179d4e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590702093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2 590702093 |
| Directory | /workspace/4.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_intr_test.289755346 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 51688490 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 12:40:05 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-551112dd-db75-4b85-8b79-df39534f0f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289755346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.289755346 |
| Directory | /workspace/4.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1477180733 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 69106044 ps |
| CPU time | 2.16 seconds |
| Started | Mar 05 12:39:44 PM PST 24 |
| Finished | Mar 05 12:39:46 PM PST 24 |
| Peak memory | 214428 kb |
| Host | smart-bae2524c-1045-4983-869b-78f9a4050282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477180733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.1477180733 |
| Directory | /workspace/4.spi_device_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3537555005 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 13842567 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:51 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-3b553863-ca52-470f-9731-61f255b0a347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537555005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.3537555005 |
| Directory | /workspace/4.spi_device_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1033121502 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1652141591 ps |
| CPU time | 2.95 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:53 PM PST 24 |
| Peak memory | 206260 kb |
| Host | smart-43db22a8-5c38-46e7-a003-50c2117ae731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033121502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s pi_device_same_csr_outstanding.1033121502 |
| Directory | /workspace/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2598270494 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 157561583 ps |
| CPU time | 4.27 seconds |
| Started | Mar 05 12:39:57 PM PST 24 |
| Finished | Mar 05 12:40:02 PM PST 24 |
| Peak memory | 215640 kb |
| Host | smart-00c88768-e978-47e0-930b-b3defa384b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598270494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2 598270494 |
| Directory | /workspace/4.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2025279345 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 600974093 ps |
| CPU time | 18.48 seconds |
| Started | Mar 05 12:39:45 PM PST 24 |
| Finished | Mar 05 12:40:09 PM PST 24 |
| Peak memory | 214524 kb |
| Host | smart-acce885b-f30f-4b14-8783-e7ef91cce62b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025279345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device _tl_intg_err.2025279345 |
| Directory | /workspace/4.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.spi_device_intr_test.441815466 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 61691518 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 12:40:08 PM PST 24 |
| Finished | Mar 05 12:40:09 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-45668c9b-136c-4816-a2f0-041b1788fde4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441815466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.441815466 |
| Directory | /workspace/40.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.spi_device_intr_test.913403769 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 58281780 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:40:17 PM PST 24 |
| Finished | Mar 05 12:40:18 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-ac6fd066-8938-448f-9f90-052e4e14a05d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913403769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.913403769 |
| Directory | /workspace/41.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1542734984 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 32450247 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 12:40:22 PM PST 24 |
| Finished | Mar 05 12:40:29 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-dd239b69-5325-441d-9353-c3c6ac332e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542734984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test. 1542734984 |
| Directory | /workspace/42.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2227744443 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 15976432 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 12:40:04 PM PST 24 |
| Finished | Mar 05 12:40:05 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-e66c861f-fb45-4297-ab18-1bd89508001a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227744443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test. 2227744443 |
| Directory | /workspace/43.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2645286395 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 21373023 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:40:09 PM PST 24 |
| Finished | Mar 05 12:40:10 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-76f10604-aeb4-4f30-9a2a-875636e3e864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645286395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test. 2645286395 |
| Directory | /workspace/44.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3897517337 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 32357541 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 12:40:05 PM PST 24 |
| Finished | Mar 05 12:40:06 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-aa19760d-712b-47d3-9895-1b3120ca7c8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897517337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test. 3897517337 |
| Directory | /workspace/45.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4264234067 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 130281166 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 12:40:17 PM PST 24 |
| Finished | Mar 05 12:40:18 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-ee17a039-9e50-4bf0-bd37-7958d5a0da51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264234067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test. 4264234067 |
| Directory | /workspace/46.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1736056464 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 30094570 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 12:40:17 PM PST 24 |
| Finished | Mar 05 12:40:18 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-6781717a-cf2e-4db7-818c-f8d1ff533d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736056464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test. 1736056464 |
| Directory | /workspace/47.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2534675827 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 12791854 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 12:40:02 PM PST 24 |
| Finished | Mar 05 12:40:03 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-710195c2-d9bf-4ecd-b692-18098af3d064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534675827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test. 2534675827 |
| Directory | /workspace/48.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.spi_device_intr_test.865314703 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 173739158 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 12:40:27 PM PST 24 |
| Finished | Mar 05 12:40:30 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-52f8cee7-e7d1-4870-a46e-1b356e000a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865314703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.865314703 |
| Directory | /workspace/49.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.934197243 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 140358619 ps |
| CPU time | 3.49 seconds |
| Started | Mar 05 12:39:56 PM PST 24 |
| Finished | Mar 05 12:40:00 PM PST 24 |
| Peak memory | 216260 kb |
| Host | smart-88ba160a-2caa-40db-b577-2a7496cc0907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934197243 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.934197243 |
| Directory | /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4020245347 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 212845622 ps |
| CPU time | 2.62 seconds |
| Started | Mar 05 12:39:52 PM PST 24 |
| Finished | Mar 05 12:39:55 PM PST 24 |
| Peak memory | 206332 kb |
| Host | smart-bb32a534-051a-4cb5-aaec-9cd30af55315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020245347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4 020245347 |
| Directory | /workspace/5.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2152931397 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 30465780 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 12:40:06 PM PST 24 |
| Finished | Mar 05 12:40:07 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-a94c207b-adf8-4d99-b6f2-eb4501e152db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152931397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2 152931397 |
| Directory | /workspace/5.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.480609403 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 81341407 ps |
| CPU time | 1.89 seconds |
| Started | Mar 05 12:39:46 PM PST 24 |
| Finished | Mar 05 12:39:48 PM PST 24 |
| Peak memory | 214552 kb |
| Host | smart-dacfe078-bc30-413e-9e6e-ac55d88cd368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480609403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp i_device_same_csr_outstanding.480609403 |
| Directory | /workspace/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4282392087 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 733393927 ps |
| CPU time | 4.04 seconds |
| Started | Mar 05 12:39:44 PM PST 24 |
| Finished | Mar 05 12:39:48 PM PST 24 |
| Peak memory | 214724 kb |
| Host | smart-38c5025f-e104-4edb-b3c8-ec021add9339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282392087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4 282392087 |
| Directory | /workspace/5.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2246547201 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 207867495 ps |
| CPU time | 13.2 seconds |
| Started | Mar 05 12:39:49 PM PST 24 |
| Finished | Mar 05 12:40:03 PM PST 24 |
| Peak memory | 214592 kb |
| Host | smart-451c5740-f3a7-4a4c-8fa2-39d15dd978a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246547201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device _tl_intg_err.2246547201 |
| Directory | /workspace/5.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.274770994 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 216751321 ps |
| CPU time | 3.63 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:54 PM PST 24 |
| Peak memory | 215752 kb |
| Host | smart-5ac2b7a8-6b58-44af-858d-62a0685e2dd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274770994 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.274770994 |
| Directory | /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1288987470 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 290356400 ps |
| CPU time | 2.21 seconds |
| Started | Mar 05 12:39:45 PM PST 24 |
| Finished | Mar 05 12:39:47 PM PST 24 |
| Peak memory | 214536 kb |
| Host | smart-bfa35f6c-c0b9-4813-b569-4fa92c9c04a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288987470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1 288987470 |
| Directory | /workspace/6.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2966014236 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 17465758 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 12:39:39 PM PST 24 |
| Finished | Mar 05 12:39:40 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-86355fe6-948a-47d5-859b-5687a854b8bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966014236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2 966014236 |
| Directory | /workspace/6.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.142305744 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1527983645 ps |
| CPU time | 3 seconds |
| Started | Mar 05 12:39:47 PM PST 24 |
| Finished | Mar 05 12:39:50 PM PST 24 |
| Peak memory | 214724 kb |
| Host | smart-3d3d3f22-ef3d-49d1-8198-451920fa34bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142305744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp i_device_same_csr_outstanding.142305744 |
| Directory | /workspace/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.760295952 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 71694317 ps |
| CPU time | 2.45 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:39:56 PM PST 24 |
| Peak memory | 214644 kb |
| Host | smart-d8dd5e2b-057d-4aee-86cc-40b6da79df6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760295952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.760295952 |
| Directory | /workspace/6.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2731891211 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 808035251 ps |
| CPU time | 19.75 seconds |
| Started | Mar 05 12:39:42 PM PST 24 |
| Finished | Mar 05 12:40:02 PM PST 24 |
| Peak memory | 214548 kb |
| Host | smart-c38d6384-6213-4e43-af2e-9f44a4b8e098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731891211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.2731891211 |
| Directory | /workspace/6.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.811852687 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2871321438 ps |
| CPU time | 3.72 seconds |
| Started | Mar 05 12:39:55 PM PST 24 |
| Finished | Mar 05 12:39:58 PM PST 24 |
| Peak memory | 216064 kb |
| Host | smart-30018791-fa37-433f-bafa-50180d8f5bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811852687 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.811852687 |
| Directory | /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2692597763 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 66069994 ps |
| CPU time | 1.99 seconds |
| Started | Mar 05 12:39:48 PM PST 24 |
| Finished | Mar 05 12:39:50 PM PST 24 |
| Peak memory | 214484 kb |
| Host | smart-d4ec765e-f841-4f34-83c0-7f88b38ecfe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692597763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2 692597763 |
| Directory | /workspace/7.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1600028632 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 49704664 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 12:39:46 PM PST 24 |
| Finished | Mar 05 12:39:47 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-a4afc8d2-49b5-4dfc-b267-40e3a7b01515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600028632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1 600028632 |
| Directory | /workspace/7.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3392544546 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 321073823 ps |
| CPU time | 2 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:40:00 PM PST 24 |
| Peak memory | 214536 kb |
| Host | smart-a9d990d5-a4f1-4892-b86c-7630cb2ea48d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392544546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s pi_device_same_csr_outstanding.3392544546 |
| Directory | /workspace/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1499164892 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 133874617 ps |
| CPU time | 2.63 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:39:55 PM PST 24 |
| Peak memory | 214696 kb |
| Host | smart-f56ddcb7-1026-42e4-8dad-f1e2b65a7529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499164892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1 499164892 |
| Directory | /workspace/7.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1289908359 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 175084027 ps |
| CPU time | 2.67 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:39:56 PM PST 24 |
| Peak memory | 214836 kb |
| Host | smart-1f49900e-6d1c-499a-957d-f206755fe218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289908359 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1289908359 |
| Directory | /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2479425238 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 100941645 ps |
| CPU time | 2.6 seconds |
| Started | Mar 05 12:39:48 PM PST 24 |
| Finished | Mar 05 12:40:01 PM PST 24 |
| Peak memory | 214620 kb |
| Host | smart-2f0fc235-1245-45fe-a316-3bd23c918e45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479425238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2 479425238 |
| Directory | /workspace/8.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3758422165 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 27911133 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 12:39:41 PM PST 24 |
| Finished | Mar 05 12:39:42 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-6a3c089e-fb68-4537-9679-0f95a7c3372c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758422165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3 758422165 |
| Directory | /workspace/8.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3688775961 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 210092495 ps |
| CPU time | 4.02 seconds |
| Started | Mar 05 12:40:01 PM PST 24 |
| Finished | Mar 05 12:40:05 PM PST 24 |
| Peak memory | 214260 kb |
| Host | smart-765f3f21-04fe-4002-81a7-7b60a4252772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688775961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s pi_device_same_csr_outstanding.3688775961 |
| Directory | /workspace/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1459025050 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 156643004 ps |
| CPU time | 1.76 seconds |
| Started | Mar 05 12:39:39 PM PST 24 |
| Finished | Mar 05 12:39:41 PM PST 24 |
| Peak memory | 214600 kb |
| Host | smart-471f1f69-de60-4aed-9fc2-81418e484434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459025050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1 459025050 |
| Directory | /workspace/8.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3360460176 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2109096442 ps |
| CPU time | 15.16 seconds |
| Started | Mar 05 12:39:53 PM PST 24 |
| Finished | Mar 05 12:40:08 PM PST 24 |
| Peak memory | 214520 kb |
| Host | smart-a50d47ae-0491-4b30-a786-2ebd1c48ef06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360460176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device _tl_intg_err.3360460176 |
| Directory | /workspace/8.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3580072178 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 133387189 ps |
| CPU time | 3.91 seconds |
| Started | Mar 05 12:39:51 PM PST 24 |
| Finished | Mar 05 12:40:00 PM PST 24 |
| Peak memory | 215748 kb |
| Host | smart-b7d5943e-e19c-4edf-b7ab-610f8cb72404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580072178 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3580072178 |
| Directory | /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2087897294 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 158905718 ps |
| CPU time | 2.21 seconds |
| Started | Mar 05 12:39:58 PM PST 24 |
| Finished | Mar 05 12:40:01 PM PST 24 |
| Peak memory | 206444 kb |
| Host | smart-25ac88eb-01ab-4638-8a26-1f2f5339779d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087897294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2 087897294 |
| Directory | /workspace/9.spi_device_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2005863983 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 134561821 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 12:39:51 PM PST 24 |
| Finished | Mar 05 12:39:51 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-2a66440c-756e-47f7-97c7-5835b4a50fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005863983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2 005863983 |
| Directory | /workspace/9.spi_device_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.515356088 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 133079276 ps |
| CPU time | 2.91 seconds |
| Started | Mar 05 12:39:47 PM PST 24 |
| Finished | Mar 05 12:39:50 PM PST 24 |
| Peak memory | 214504 kb |
| Host | smart-c0cd2612-4806-4f7f-ab56-29a5cb3dbb91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515356088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp i_device_same_csr_outstanding.515356088 |
| Directory | /workspace/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2693138676 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 199159458 ps |
| CPU time | 1.89 seconds |
| Started | Mar 05 12:39:50 PM PST 24 |
| Finished | Mar 05 12:39:52 PM PST 24 |
| Peak memory | 214652 kb |
| Host | smart-7ed3484b-c4ea-42c1-9e93-abeeb0352097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693138676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2 693138676 |
| Directory | /workspace/9.spi_device_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.428078771 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1213475284 ps |
| CPU time | 18.83 seconds |
| Started | Mar 05 12:39:54 PM PST 24 |
| Finished | Mar 05 12:40:13 PM PST 24 |
| Peak memory | 214568 kb |
| Host | smart-2c88ec24-bc30-4f26-bf42-1c83eba0b1b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428078771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_ tl_intg_err.428078771 |
| Directory | /workspace/9.spi_device_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.spi_device_cfg_cmd.3609715277 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3309991572 ps |
| CPU time | 6.8 seconds |
| Started | Mar 05 01:35:53 PM PST 24 |
| Finished | Mar 05 01:36:00 PM PST 24 |
| Peak memory | 224332 kb |
| Host | smart-c36a6fa3-96a1-4bed-9bca-f65079fcc62f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3609715277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3609715277 |
| Directory | /workspace/0.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/0.spi_device_csb_read.1000160480 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 62776097 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:35:50 PM PST 24 |
| Finished | Mar 05 01:35:51 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-524e7a8c-abe9-46db-ab60-7145fd25011a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000160480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1000160480 |
| Directory | /workspace/0.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/0.spi_device_flash_all.3489912621 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3082550900 ps |
| CPU time | 49.69 seconds |
| Started | Mar 05 01:36:01 PM PST 24 |
| Finished | Mar 05 01:36:50 PM PST 24 |
| Peak memory | 250312 kb |
| Host | smart-da4a4a03-a325-4225-bc08-bf233f63ca7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489912621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3489912621 |
| Directory | /workspace/0.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/0.spi_device_flash_and_tpm.926820779 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6391463459 ps |
| CPU time | 75.21 seconds |
| Started | Mar 05 01:35:57 PM PST 24 |
| Finished | Mar 05 01:37:12 PM PST 24 |
| Peak memory | 249184 kb |
| Host | smart-a1d82a65-82d5-454d-8fc4-039cde316b8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926820779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.926820779 |
| Directory | /workspace/0.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2493481392 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 42360476876 ps |
| CPU time | 35.5 seconds |
| Started | Mar 05 01:35:58 PM PST 24 |
| Finished | Mar 05 01:36:34 PM PST 24 |
| Peak memory | 222132 kb |
| Host | smart-a231dc49-a017-4ef0-878f-7ecf481cd83b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493481392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle .2493481392 |
| Directory | /workspace/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/0.spi_device_flash_mode.2437066846 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 8288356895 ps |
| CPU time | 36.39 seconds |
| Started | Mar 05 01:36:01 PM PST 24 |
| Finished | Mar 05 01:36:38 PM PST 24 |
| Peak memory | 240888 kb |
| Host | smart-951bc014-bcd1-4233-952d-11fef01f4798 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437066846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2437066846 |
| Directory | /workspace/0.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/0.spi_device_intercept.1886857446 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 9050750432 ps |
| CPU time | 8.67 seconds |
| Started | Mar 05 01:35:49 PM PST 24 |
| Finished | Mar 05 01:35:57 PM PST 24 |
| Peak memory | 233520 kb |
| Host | smart-df6921a2-3e1f-457c-821c-bbb094214cda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886857446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1886857446 |
| Directory | /workspace/0.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/0.spi_device_mailbox.278007587 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 7705825825 ps |
| CPU time | 6.94 seconds |
| Started | Mar 05 01:35:50 PM PST 24 |
| Finished | Mar 05 01:35:57 PM PST 24 |
| Peak memory | 232624 kb |
| Host | smart-6fd9b5e7-a089-44ca-ac69-e95b0791ea6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=278007587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.278007587 |
| Directory | /workspace/0.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/0.spi_device_mem_parity.1949976982 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 117780793 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:35:49 PM PST 24 |
| Finished | Mar 05 01:35:50 PM PST 24 |
| Peak memory | 216528 kb |
| Host | smart-6167098a-d529-4168-96f5-9eab91522494 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949976982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.spi_device_mem_parity.1949976982 |
| Directory | /workspace/0.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1362756706 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 311024719 ps |
| CPU time | 4.62 seconds |
| Started | Mar 05 01:35:51 PM PST 24 |
| Finished | Mar 05 01:35:56 PM PST 24 |
| Peak memory | 233392 kb |
| Host | smart-ad458689-759e-43bb-8005-102f8c43bb5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362756706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap .1362756706 |
| Directory | /workspace/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2196158279 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1082195409 ps |
| CPU time | 7.53 seconds |
| Started | Mar 05 01:35:50 PM PST 24 |
| Finished | Mar 05 01:35:57 PM PST 24 |
| Peak memory | 217592 kb |
| Host | smart-31e12f56-d5c9-4a98-a817-615bbf4a0cae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196158279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2196158279 |
| Directory | /workspace/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/0.spi_device_ram_cfg.3343245042 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 41013162 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:35:50 PM PST 24 |
| Finished | Mar 05 01:35:51 PM PST 24 |
| Peak memory | 216044 kb |
| Host | smart-c8d0835c-0817-4d58-a9e8-52986ee4572c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3343245042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3343245042 |
| Directory | /workspace/0.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/0.spi_device_read_buffer_direct.2897031029 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 5326390743 ps |
| CPU time | 6.75 seconds |
| Started | Mar 05 01:35:59 PM PST 24 |
| Finished | Mar 05 01:36:07 PM PST 24 |
| Peak memory | 222508 kb |
| Host | smart-1da28242-ffd7-48db-bb5a-38cc4a946ae3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2897031029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire ct.2897031029 |
| Directory | /workspace/0.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/0.spi_device_stress_all.979655400 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 465921426 ps |
| CPU time | 1.14 seconds |
| Started | Mar 05 01:35:58 PM PST 24 |
| Finished | Mar 05 01:35:59 PM PST 24 |
| Peak memory | 206656 kb |
| Host | smart-37d30a91-e3c5-4e4a-a53a-fdb00cf64b7e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979655400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress _all.979655400 |
| Directory | /workspace/0.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/0.spi_device_tpm_all.3333615700 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 1007817607 ps |
| CPU time | 12.02 seconds |
| Started | Mar 05 01:35:47 PM PST 24 |
| Finished | Mar 05 01:36:00 PM PST 24 |
| Peak memory | 216272 kb |
| Host | smart-18f34ada-47a2-4144-ae36-dd64beb93ea5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333615700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3333615700 |
| Directory | /workspace/0.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2664431337 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 878466432 ps |
| CPU time | 5.61 seconds |
| Started | Mar 05 01:35:49 PM PST 24 |
| Finished | Mar 05 01:35:54 PM PST 24 |
| Peak memory | 216104 kb |
| Host | smart-54b61241-f30c-4052-b2f7-8924b6924350 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664431337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2664431337 |
| Directory | /workspace/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/0.spi_device_tpm_rw.592517664 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 179555649 ps |
| CPU time | 0.92 seconds |
| Started | Mar 05 01:35:49 PM PST 24 |
| Finished | Mar 05 01:35:50 PM PST 24 |
| Peak memory | 206840 kb |
| Host | smart-030a443f-577a-4c70-8e68-25c14cd40c0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592517664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.592517664 |
| Directory | /workspace/0.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/0.spi_device_tpm_sts_read.112881785 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 28477889 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 01:35:48 PM PST 24 |
| Finished | Mar 05 01:35:49 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-ada9bab2-17ea-4fd5-8924-6998fbcb4626 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112881785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.112881785 |
| Directory | /workspace/0.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/0.spi_device_upload.1974130530 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 46451119807 ps |
| CPU time | 45.43 seconds |
| Started | Mar 05 01:35:49 PM PST 24 |
| Finished | Mar 05 01:36:34 PM PST 24 |
| Peak memory | 230016 kb |
| Host | smart-f45eb4ef-480b-42ac-8a98-ad93c0d2406d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974130530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1974130530 |
| Directory | /workspace/0.spi_device_upload/latest |
| Test location | /workspace/coverage/default/1.spi_device_alert_test.1882145768 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 14684148 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:36:17 PM PST 24 |
| Finished | Mar 05 01:36:18 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-96ba4d17-d009-4eea-be1d-f572f738ccf7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882145768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1 882145768 |
| Directory | /workspace/1.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/1.spi_device_cfg_cmd.2058994762 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 16951369115 ps |
| CPU time | 5.63 seconds |
| Started | Mar 05 01:36:08 PM PST 24 |
| Finished | Mar 05 01:36:14 PM PST 24 |
| Peak memory | 234120 kb |
| Host | smart-d071d702-a82d-4c48-80d2-5ee88f9fc255 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058994762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2058994762 |
| Directory | /workspace/1.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/1.spi_device_csb_read.2222609235 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 14871927 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:35:58 PM PST 24 |
| Finished | Mar 05 01:35:59 PM PST 24 |
| Peak memory | 206004 kb |
| Host | smart-3b2e32f0-a231-4f3b-b65a-128c6bf7538f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222609235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2222609235 |
| Directory | /workspace/1.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/1.spi_device_flash_all.3828452943 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 7984823260 ps |
| CPU time | 29.08 seconds |
| Started | Mar 05 01:36:16 PM PST 24 |
| Finished | Mar 05 01:36:45 PM PST 24 |
| Peak memory | 248624 kb |
| Host | smart-1c612f48-5b02-4f98-bc42-38691d1a0562 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828452943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3828452943 |
| Directory | /workspace/1.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/1.spi_device_flash_and_tpm.1517416009 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 1470456835 ps |
| CPU time | 30.53 seconds |
| Started | Mar 05 01:36:14 PM PST 24 |
| Finished | Mar 05 01:36:45 PM PST 24 |
| Peak memory | 224544 kb |
| Host | smart-0d2e3778-d7f8-4a60-87fd-cc04d775038f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517416009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1517416009 |
| Directory | /workspace/1.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.936027574 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3767764018 ps |
| CPU time | 78.17 seconds |
| Started | Mar 05 01:36:17 PM PST 24 |
| Finished | Mar 05 01:37:35 PM PST 24 |
| Peak memory | 252228 kb |
| Host | smart-22e990cd-ed99-4543-a125-65888993edd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936027574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle. 936027574 |
| Directory | /workspace/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/1.spi_device_flash_mode.2101940432 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1956692190 ps |
| CPU time | 17.4 seconds |
| Started | Mar 05 01:36:11 PM PST 24 |
| Finished | Mar 05 01:36:29 PM PST 24 |
| Peak memory | 249840 kb |
| Host | smart-fbb89663-c3f2-4f12-b27b-85d59c5961c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101940432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2101940432 |
| Directory | /workspace/1.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/1.spi_device_intercept.3730849336 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 36257675 ps |
| CPU time | 2.62 seconds |
| Started | Mar 05 01:36:09 PM PST 24 |
| Finished | Mar 05 01:36:12 PM PST 24 |
| Peak memory | 232604 kb |
| Host | smart-5751b1d9-328c-4b4f-8e1f-48bbfbbcbff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730849336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3730849336 |
| Directory | /workspace/1.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/1.spi_device_mailbox.409925060 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 11071423533 ps |
| CPU time | 18.68 seconds |
| Started | Mar 05 01:36:08 PM PST 24 |
| Finished | Mar 05 01:36:28 PM PST 24 |
| Peak memory | 239508 kb |
| Host | smart-b179f0f7-e69f-4098-9d05-2c3bc6341108 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409925060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.409925060 |
| Directory | /workspace/1.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/1.spi_device_mem_parity.529634200 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 16005742 ps |
| CPU time | 1.03 seconds |
| Started | Mar 05 01:35:58 PM PST 24 |
| Finished | Mar 05 01:35:59 PM PST 24 |
| Peak memory | 217756 kb |
| Host | smart-0c8af8d9-1973-42a1-b80c-a993fb2d8edc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529634200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.529634200 |
| Directory | /workspace/1.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.203142828 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 23662504185 ps |
| CPU time | 15.22 seconds |
| Started | Mar 05 01:36:08 PM PST 24 |
| Finished | Mar 05 01:36:24 PM PST 24 |
| Peak memory | 226984 kb |
| Host | smart-6e7bdcef-d1c3-4ddb-89dd-10394c747340 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203142828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap. 203142828 |
| Directory | /workspace/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1596662279 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1191027409 ps |
| CPU time | 3.81 seconds |
| Started | Mar 05 01:36:08 PM PST 24 |
| Finished | Mar 05 01:36:12 PM PST 24 |
| Peak memory | 232624 kb |
| Host | smart-3d3eb148-3a08-4655-8f09-2e24ac0f0110 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596662279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1596662279 |
| Directory | /workspace/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/1.spi_device_read_buffer_direct.3436344826 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1145155291 ps |
| CPU time | 6.19 seconds |
| Started | Mar 05 01:36:12 PM PST 24 |
| Finished | Mar 05 01:36:19 PM PST 24 |
| Peak memory | 221916 kb |
| Host | smart-7bacba51-fc1a-41c4-93fd-cee19b85a514 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3436344826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire ct.3436344826 |
| Directory | /workspace/1.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/1.spi_device_sec_cm.1203493049 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 110465864 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:36:15 PM PST 24 |
| Finished | Mar 05 01:36:16 PM PST 24 |
| Peak memory | 234564 kb |
| Host | smart-9327c580-3944-42fc-a9cc-632f853f52a0 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203493049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1203493049 |
| Directory | /workspace/1.spi_device_sec_cm/latest |
| Test location | /workspace/coverage/default/1.spi_device_stress_all.2234342573 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 37842256946 ps |
| CPU time | 183.3 seconds |
| Started | Mar 05 01:36:12 PM PST 24 |
| Finished | Mar 05 01:39:16 PM PST 24 |
| Peak memory | 249168 kb |
| Host | smart-e81fceb2-4cf9-4dfc-9d78-9cb4041ba0af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234342573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres s_all.2234342573 |
| Directory | /workspace/1.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/1.spi_device_tpm_all.2243280097 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 9162616413 ps |
| CPU time | 59.01 seconds |
| Started | Mar 05 01:36:09 PM PST 24 |
| Finished | Mar 05 01:37:08 PM PST 24 |
| Peak memory | 216276 kb |
| Host | smart-3f4040ce-d2a4-4bee-9d76-a449609bcdf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243280097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2243280097 |
| Directory | /workspace/1.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.205650107 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2642858378 ps |
| CPU time | 7.39 seconds |
| Started | Mar 05 01:36:09 PM PST 24 |
| Finished | Mar 05 01:36:18 PM PST 24 |
| Peak memory | 216240 kb |
| Host | smart-6db66c47-dcfc-42f2-8782-37b18e198c3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205650107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.205650107 |
| Directory | /workspace/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/1.spi_device_tpm_rw.2485083986 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 44337097 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:36:09 PM PST 24 |
| Finished | Mar 05 01:36:11 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-ef7aac6f-a484-4634-8e18-12ec04652bf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485083986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2485083986 |
| Directory | /workspace/1.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/1.spi_device_tpm_sts_read.111212668 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 137299778 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:36:09 PM PST 24 |
| Finished | Mar 05 01:36:11 PM PST 24 |
| Peak memory | 205340 kb |
| Host | smart-5eadfd1a-a37a-4468-b7ea-5e4f6b39ba2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111212668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.111212668 |
| Directory | /workspace/1.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/1.spi_device_upload.1542506756 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1910768182 ps |
| CPU time | 7.26 seconds |
| Started | Mar 05 01:36:10 PM PST 24 |
| Finished | Mar 05 01:36:17 PM PST 24 |
| Peak memory | 237576 kb |
| Host | smart-254dd132-e038-4a67-af78-3bc589b07ee8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1542506756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1542506756 |
| Directory | /workspace/1.spi_device_upload/latest |
| Test location | /workspace/coverage/default/10.spi_device_alert_test.2039664437 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 46226259 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:37:59 PM PST 24 |
| Finished | Mar 05 01:38:00 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-02f1d2d8-fb42-43a1-98d8-395aa996b8ba |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039664437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test. 2039664437 |
| Directory | /workspace/10.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/10.spi_device_cfg_cmd.4227448407 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 523645603 ps |
| CPU time | 3.95 seconds |
| Started | Mar 05 01:37:58 PM PST 24 |
| Finished | Mar 05 01:38:02 PM PST 24 |
| Peak memory | 232724 kb |
| Host | smart-73daa0fc-878b-4bc2-9984-305f16d18c43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4227448407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4227448407 |
| Directory | /workspace/10.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/10.spi_device_csb_read.988113105 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 58590750 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:37:50 PM PST 24 |
| Finished | Mar 05 01:37:52 PM PST 24 |
| Peak memory | 206304 kb |
| Host | smart-eddc24d0-69e0-408e-8f03-8ddcf9fbfdf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988113105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.988113105 |
| Directory | /workspace/10.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/10.spi_device_flash_all.2668829014 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 33114316839 ps |
| CPU time | 164.83 seconds |
| Started | Mar 05 01:38:02 PM PST 24 |
| Finished | Mar 05 01:40:47 PM PST 24 |
| Peak memory | 264288 kb |
| Host | smart-4ec9d52d-94f4-49ae-9dc4-c324ef5303cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668829014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2668829014 |
| Directory | /workspace/10.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.27627466 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 37046778825 ps |
| CPU time | 76.57 seconds |
| Started | Mar 05 01:37:57 PM PST 24 |
| Finished | Mar 05 01:39:14 PM PST 24 |
| Peak memory | 254792 kb |
| Host | smart-9a92b915-e23d-482e-9235-11788ece24c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27627466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.27627466 |
| Directory | /workspace/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/10.spi_device_flash_mode.3224261573 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 787248558 ps |
| CPU time | 16.32 seconds |
| Started | Mar 05 01:37:59 PM PST 24 |
| Finished | Mar 05 01:38:15 PM PST 24 |
| Peak memory | 233116 kb |
| Host | smart-a0cc3e89-4cd5-41c1-9aa5-84012ad8a446 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3224261573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3224261573 |
| Directory | /workspace/10.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/10.spi_device_intercept.2377322637 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1400270598 ps |
| CPU time | 5.65 seconds |
| Started | Mar 05 01:37:50 PM PST 24 |
| Finished | Mar 05 01:37:56 PM PST 24 |
| Peak memory | 237984 kb |
| Host | smart-dbf8d9f5-1d9a-4960-9c0e-0083fa746a3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377322637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2377322637 |
| Directory | /workspace/10.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/10.spi_device_mailbox.4215215703 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 2463187095 ps |
| CPU time | 7.99 seconds |
| Started | Mar 05 01:37:59 PM PST 24 |
| Finished | Mar 05 01:38:07 PM PST 24 |
| Peak memory | 233300 kb |
| Host | smart-b072cfef-6d49-4280-a6d6-fdf18fcdc6e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215215703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4215215703 |
| Directory | /workspace/10.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/10.spi_device_mem_parity.4232413998 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 50850602 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:38:03 PM PST 24 |
| Finished | Mar 05 01:38:05 PM PST 24 |
| Peak memory | 216488 kb |
| Host | smart-6e7e0d3f-b225-4d8d-b280-2ca9bdbed3b2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232413998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.spi_device_mem_parity.4232413998 |
| Directory | /workspace/10.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3238073676 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 647489468 ps |
| CPU time | 7.24 seconds |
| Started | Mar 05 01:37:53 PM PST 24 |
| Finished | Mar 05 01:38:01 PM PST 24 |
| Peak memory | 236572 kb |
| Host | smart-a9e1d3bb-3bc4-4a53-b8c1-a0891bd1ae6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238073676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa p.3238073676 |
| Directory | /workspace/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/10.spi_device_pass_cmd_filtering.967588021 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1594269194 ps |
| CPU time | 6.6 seconds |
| Started | Mar 05 01:37:50 PM PST 24 |
| Finished | Mar 05 01:37:57 PM PST 24 |
| Peak memory | 224340 kb |
| Host | smart-04248226-d647-444d-9882-d0580c503c01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967588021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.967588021 |
| Directory | /workspace/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/10.spi_device_ram_cfg.1975834221 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 90505200 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:37:52 PM PST 24 |
| Finished | Mar 05 01:37:53 PM PST 24 |
| Peak memory | 216072 kb |
| Host | smart-58cb2b13-8ffa-484d-8200-5888a7608e47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975834221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1975834221 |
| Directory | /workspace/10.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/10.spi_device_read_buffer_direct.138475449 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 140856491 ps |
| CPU time | 3.78 seconds |
| Started | Mar 05 01:37:57 PM PST 24 |
| Finished | Mar 05 01:38:01 PM PST 24 |
| Peak memory | 221824 kb |
| Host | smart-0d38d0c9-1936-4898-bb00-1c3a965068dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=138475449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire ct.138475449 |
| Directory | /workspace/10.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/10.spi_device_stress_all.880175162 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 7021904839 ps |
| CPU time | 18.46 seconds |
| Started | Mar 05 01:38:01 PM PST 24 |
| Finished | Mar 05 01:38:20 PM PST 24 |
| Peak memory | 234120 kb |
| Host | smart-de324e70-d810-45ee-8dfc-0e92b2e1bea1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880175162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres s_all.880175162 |
| Directory | /workspace/10.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/10.spi_device_tpm_all.3462795747 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1027786398 ps |
| CPU time | 8.13 seconds |
| Started | Mar 05 01:37:50 PM PST 24 |
| Finished | Mar 05 01:37:59 PM PST 24 |
| Peak memory | 216192 kb |
| Host | smart-31101f55-a776-4423-a8fa-2da267ac118c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462795747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3462795747 |
| Directory | /workspace/10.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3676112877 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2314180946 ps |
| CPU time | 2.69 seconds |
| Started | Mar 05 01:37:51 PM PST 24 |
| Finished | Mar 05 01:37:54 PM PST 24 |
| Peak memory | 207880 kb |
| Host | smart-4bf337c5-6470-45a3-a2d1-058200c3c4d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676112877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3676112877 |
| Directory | /workspace/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/10.spi_device_tpm_rw.3701504316 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 67905655 ps |
| CPU time | 0.95 seconds |
| Started | Mar 05 01:37:50 PM PST 24 |
| Finished | Mar 05 01:37:52 PM PST 24 |
| Peak memory | 206740 kb |
| Host | smart-08f3247d-1ae2-4011-bd53-1ea523f4f5d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701504316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3701504316 |
| Directory | /workspace/10.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/10.spi_device_tpm_sts_read.2787870189 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 488298794 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:37:49 PM PST 24 |
| Finished | Mar 05 01:37:50 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-56e25b77-3dd6-4885-b4ac-027e88266ebc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2787870189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2787870189 |
| Directory | /workspace/10.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/10.spi_device_upload.739828669 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 1537161168 ps |
| CPU time | 11.75 seconds |
| Started | Mar 05 01:37:56 PM PST 24 |
| Finished | Mar 05 01:38:08 PM PST 24 |
| Peak memory | 218696 kb |
| Host | smart-db6c8199-dae2-4218-a805-fd2bbe14b49a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739828669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.739828669 |
| Directory | /workspace/10.spi_device_upload/latest |
| Test location | /workspace/coverage/default/11.spi_device_alert_test.932528176 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 12971547 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:38:04 PM PST 24 |
| Finished | Mar 05 01:38:06 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-2cf8a40c-16da-4495-95d7-e05bb1be4af4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932528176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.932528176 |
| Directory | /workspace/11.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/11.spi_device_cfg_cmd.3113089187 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 566073517 ps |
| CPU time | 4.19 seconds |
| Started | Mar 05 01:38:06 PM PST 24 |
| Finished | Mar 05 01:38:12 PM PST 24 |
| Peak memory | 236524 kb |
| Host | smart-0b2b9a83-6787-40ef-9faf-39b08028b098 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113089187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3113089187 |
| Directory | /workspace/11.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/11.spi_device_csb_read.3946731562 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 113061299 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:37:58 PM PST 24 |
| Finished | Mar 05 01:37:59 PM PST 24 |
| Peak memory | 206332 kb |
| Host | smart-4b6574a5-2084-4199-b7c4-fa750eb70c2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946731562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3946731562 |
| Directory | /workspace/11.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/11.spi_device_flash_all.152718184 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 55952854217 ps |
| CPU time | 112.8 seconds |
| Started | Mar 05 01:38:05 PM PST 24 |
| Finished | Mar 05 01:39:59 PM PST 24 |
| Peak memory | 267544 kb |
| Host | smart-7b6abeca-562d-4115-9527-eb6773a13224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152718184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.152718184 |
| Directory | /workspace/11.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/11.spi_device_flash_and_tpm.3137761789 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 6099830985 ps |
| CPU time | 50.01 seconds |
| Started | Mar 05 01:38:04 PM PST 24 |
| Finished | Mar 05 01:38:56 PM PST 24 |
| Peak memory | 249280 kb |
| Host | smart-eeacd457-72a6-4e29-ad73-db928c2270ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137761789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3137761789 |
| Directory | /workspace/11.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.578581095 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 32753230476 ps |
| CPU time | 256.72 seconds |
| Started | Mar 05 01:38:05 PM PST 24 |
| Finished | Mar 05 01:42:23 PM PST 24 |
| Peak memory | 256032 kb |
| Host | smart-68dc5846-914c-42f0-9d22-b721e9d4c3b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578581095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle .578581095 |
| Directory | /workspace/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/11.spi_device_flash_mode.2013031819 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3080253899 ps |
| CPU time | 20.13 seconds |
| Started | Mar 05 01:38:06 PM PST 24 |
| Finished | Mar 05 01:38:28 PM PST 24 |
| Peak memory | 248320 kb |
| Host | smart-2fa3008c-17c1-4ee3-8d60-dc5c04d9f5f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013031819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2013031819 |
| Directory | /workspace/11.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/11.spi_device_intercept.82897061 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2996272834 ps |
| CPU time | 5.36 seconds |
| Started | Mar 05 01:37:59 PM PST 24 |
| Finished | Mar 05 01:38:05 PM PST 24 |
| Peak memory | 233212 kb |
| Host | smart-9d3cf7cd-0e7b-4b63-a740-04fc6abdf193 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82897061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.82897061 |
| Directory | /workspace/11.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/11.spi_device_mailbox.2113648325 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 40337215573 ps |
| CPU time | 32.34 seconds |
| Started | Mar 05 01:38:02 PM PST 24 |
| Finished | Mar 05 01:38:35 PM PST 24 |
| Peak memory | 230580 kb |
| Host | smart-cd04185c-acd0-4a48-a731-130057576ad2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113648325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2113648325 |
| Directory | /workspace/11.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/11.spi_device_mem_parity.2202199694 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 194419829 ps |
| CPU time | 1.01 seconds |
| Started | Mar 05 01:37:58 PM PST 24 |
| Finished | Mar 05 01:37:59 PM PST 24 |
| Peak memory | 217736 kb |
| Host | smart-1389826a-f5be-467f-b27e-6edf1d403955 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202199694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.spi_device_mem_parity.2202199694 |
| Directory | /workspace/11.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2024076264 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 25524523577 ps |
| CPU time | 10.08 seconds |
| Started | Mar 05 01:38:01 PM PST 24 |
| Finished | Mar 05 01:38:11 PM PST 24 |
| Peak memory | 236180 kb |
| Host | smart-4bac10ba-950e-4328-bf29-253c4e697e41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024076264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa p.2024076264 |
| Directory | /workspace/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2062203562 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 13554356459 ps |
| CPU time | 23 seconds |
| Started | Mar 05 01:38:03 PM PST 24 |
| Finished | Mar 05 01:38:26 PM PST 24 |
| Peak memory | 238436 kb |
| Host | smart-dc9efb62-1163-4627-874b-0b524679d029 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062203562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2062203562 |
| Directory | /workspace/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/11.spi_device_ram_cfg.3849757232 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 32219311 ps |
| CPU time | 0.84 seconds |
| Started | Mar 05 01:38:01 PM PST 24 |
| Finished | Mar 05 01:38:02 PM PST 24 |
| Peak memory | 216052 kb |
| Host | smart-65b2c8bb-5884-4bb5-a00e-070512ec78d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849757232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3849757232 |
| Directory | /workspace/11.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/11.spi_device_read_buffer_direct.2471022203 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 139622447 ps |
| CPU time | 3.75 seconds |
| Started | Mar 05 01:38:07 PM PST 24 |
| Finished | Mar 05 01:38:13 PM PST 24 |
| Peak memory | 222544 kb |
| Host | smart-72fa8768-b1c1-4725-ae36-2f5d4bd90943 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2471022203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir ect.2471022203 |
| Directory | /workspace/11.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/11.spi_device_tpm_all.921075492 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4733787712 ps |
| CPU time | 37.95 seconds |
| Started | Mar 05 01:37:58 PM PST 24 |
| Finished | Mar 05 01:38:36 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-29acb69d-e4b9-4b98-8d63-e58f2d1eebe5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921075492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.921075492 |
| Directory | /workspace/11.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2298306516 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5260254943 ps |
| CPU time | 8.71 seconds |
| Started | Mar 05 01:37:59 PM PST 24 |
| Finished | Mar 05 01:38:08 PM PST 24 |
| Peak memory | 216344 kb |
| Host | smart-320f77ce-2cff-4064-8e28-136f2f435bbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298306516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2298306516 |
| Directory | /workspace/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/11.spi_device_tpm_rw.4178267366 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 59103592 ps |
| CPU time | 1.79 seconds |
| Started | Mar 05 01:38:03 PM PST 24 |
| Finished | Mar 05 01:38:06 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-6def1f2b-bb82-47bd-a4bf-65b7ee3a8aca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178267366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4178267366 |
| Directory | /workspace/11.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/11.spi_device_tpm_sts_read.175216680 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 476012135 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:37:58 PM PST 24 |
| Finished | Mar 05 01:37:59 PM PST 24 |
| Peak memory | 206376 kb |
| Host | smart-8b4f8e61-3200-477a-8702-55f64c62603c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175216680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.175216680 |
| Directory | /workspace/11.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/11.spi_device_upload.404714698 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 974406870 ps |
| CPU time | 7.65 seconds |
| Started | Mar 05 01:38:06 PM PST 24 |
| Finished | Mar 05 01:38:17 PM PST 24 |
| Peak memory | 220604 kb |
| Host | smart-389bae10-9ab5-47f2-bcdd-ca87bb407e99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404714698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.404714698 |
| Directory | /workspace/11.spi_device_upload/latest |
| Test location | /workspace/coverage/default/12.spi_device_alert_test.1547781866 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 42396215 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:38:18 PM PST 24 |
| Finished | Mar 05 01:38:19 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-a1f93ee0-0b6c-4322-8e6c-2564f494ca59 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547781866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test. 1547781866 |
| Directory | /workspace/12.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/12.spi_device_cfg_cmd.2786589941 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 257474505 ps |
| CPU time | 3.3 seconds |
| Started | Mar 05 01:38:11 PM PST 24 |
| Finished | Mar 05 01:38:14 PM PST 24 |
| Peak memory | 233092 kb |
| Host | smart-283642b7-a33b-46f4-82b5-aa492b8a5463 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786589941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2786589941 |
| Directory | /workspace/12.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/12.spi_device_csb_read.4159927135 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 16681594 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:38:06 PM PST 24 |
| Finished | Mar 05 01:38:07 PM PST 24 |
| Peak memory | 204968 kb |
| Host | smart-7b0ffcb6-1c8c-44d7-a908-68b028fe3580 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4159927135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4159927135 |
| Directory | /workspace/12.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/12.spi_device_flash_and_tpm.1814120193 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 71020751928 ps |
| CPU time | 455.26 seconds |
| Started | Mar 05 01:38:13 PM PST 24 |
| Finished | Mar 05 01:45:49 PM PST 24 |
| Peak memory | 249248 kb |
| Host | smart-1a0a89a6-b678-4bcd-8d77-281fb2b42f84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814120193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1814120193 |
| Directory | /workspace/12.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1856379266 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 18770584519 ps |
| CPU time | 63.33 seconds |
| Started | Mar 05 01:38:13 PM PST 24 |
| Finished | Mar 05 01:39:16 PM PST 24 |
| Peak memory | 236964 kb |
| Host | smart-a764b057-7f0b-48b6-ab13-608348a76d61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856379266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl e.1856379266 |
| Directory | /workspace/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/12.spi_device_intercept.912561940 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1098763907 ps |
| CPU time | 6.04 seconds |
| Started | Mar 05 01:38:11 PM PST 24 |
| Finished | Mar 05 01:38:17 PM PST 24 |
| Peak memory | 235644 kb |
| Host | smart-bfb44039-7e89-4acd-985f-a970625cce68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912561940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.912561940 |
| Directory | /workspace/12.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/12.spi_device_mailbox.1406213174 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 12613333773 ps |
| CPU time | 11.99 seconds |
| Started | Mar 05 01:38:16 PM PST 24 |
| Finished | Mar 05 01:38:28 PM PST 24 |
| Peak memory | 237900 kb |
| Host | smart-15744670-9a8f-4ec6-872c-146807880432 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1406213174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1406213174 |
| Directory | /workspace/12.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1396526224 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 354715417 ps |
| CPU time | 5.96 seconds |
| Started | Mar 05 01:38:17 PM PST 24 |
| Finished | Mar 05 01:38:24 PM PST 24 |
| Peak memory | 234404 kb |
| Host | smart-ea2491fc-f353-430e-9d88-9e0b1d0437f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396526224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa p.1396526224 |
| Directory | /workspace/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4220318425 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 8074684403 ps |
| CPU time | 18.9 seconds |
| Started | Mar 05 01:38:12 PM PST 24 |
| Finished | Mar 05 01:38:31 PM PST 24 |
| Peak memory | 238264 kb |
| Host | smart-da00e69e-4bd4-4a76-af5f-cfbd37be2c46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220318425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4220318425 |
| Directory | /workspace/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/12.spi_device_ram_cfg.3638479999 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 18570646 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:38:05 PM PST 24 |
| Finished | Mar 05 01:38:07 PM PST 24 |
| Peak memory | 216040 kb |
| Host | smart-3539627e-e95a-43ea-b6cf-618cbc805da8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638479999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3638479999 |
| Directory | /workspace/12.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/12.spi_device_read_buffer_direct.239463039 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 15979403795 ps |
| CPU time | 4.79 seconds |
| Started | Mar 05 01:38:17 PM PST 24 |
| Finished | Mar 05 01:38:22 PM PST 24 |
| Peak memory | 218504 kb |
| Host | smart-e510d14f-c599-4191-9610-87e69bec5527 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=239463039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire ct.239463039 |
| Directory | /workspace/12.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/12.spi_device_stress_all.732259625 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 282555509104 ps |
| CPU time | 453.02 seconds |
| Started | Mar 05 01:38:20 PM PST 24 |
| Finished | Mar 05 01:45:53 PM PST 24 |
| Peak memory | 255924 kb |
| Host | smart-8b84e72e-3163-4686-9fca-e80eb685c86c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732259625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres s_all.732259625 |
| Directory | /workspace/12.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/12.spi_device_tpm_all.63130523 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 266664900 ps |
| CPU time | 2.94 seconds |
| Started | Mar 05 01:38:08 PM PST 24 |
| Finished | Mar 05 01:38:13 PM PST 24 |
| Peak memory | 216252 kb |
| Host | smart-52add756-7a6d-4654-acae-089e21e687fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63130523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.63130523 |
| Directory | /workspace/12.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3080201028 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3772476196 ps |
| CPU time | 3.54 seconds |
| Started | Mar 05 01:38:07 PM PST 24 |
| Finished | Mar 05 01:38:14 PM PST 24 |
| Peak memory | 216296 kb |
| Host | smart-8fd2a864-5846-4a42-806c-3c6748d90c14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3080201028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3080201028 |
| Directory | /workspace/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/12.spi_device_tpm_rw.3036701905 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 105030205 ps |
| CPU time | 1.04 seconds |
| Started | Mar 05 01:38:09 PM PST 24 |
| Finished | Mar 05 01:38:11 PM PST 24 |
| Peak memory | 207224 kb |
| Host | smart-9a85f1f8-68a3-4d2f-8c65-d338b1a77fa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036701905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3036701905 |
| Directory | /workspace/12.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/12.spi_device_tpm_sts_read.1430333073 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 152682639 ps |
| CPU time | 0.91 seconds |
| Started | Mar 05 01:38:07 PM PST 24 |
| Finished | Mar 05 01:38:11 PM PST 24 |
| Peak memory | 206372 kb |
| Host | smart-e5939c4d-8090-44c0-9dc2-65e35057951d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430333073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1430333073 |
| Directory | /workspace/12.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/12.spi_device_upload.1644776767 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1254488947 ps |
| CPU time | 5.82 seconds |
| Started | Mar 05 01:38:12 PM PST 24 |
| Finished | Mar 05 01:38:18 PM PST 24 |
| Peak memory | 217104 kb |
| Host | smart-e9144ee1-e0ea-4c11-a8eb-e19e8f130c14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644776767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1644776767 |
| Directory | /workspace/12.spi_device_upload/latest |
| Test location | /workspace/coverage/default/13.spi_device_alert_test.2435468340 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 11735165 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 01:38:27 PM PST 24 |
| Finished | Mar 05 01:38:28 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-11b1af81-b2f4-425c-a35c-28ab084b341f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435468340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test. 2435468340 |
| Directory | /workspace/13.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/13.spi_device_cfg_cmd.4123138444 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 11135763528 ps |
| CPU time | 7.17 seconds |
| Started | Mar 05 01:38:26 PM PST 24 |
| Finished | Mar 05 01:38:33 PM PST 24 |
| Peak memory | 224432 kb |
| Host | smart-9a0b7037-c4d8-415c-8bb1-1176ae1e745b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123138444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4123138444 |
| Directory | /workspace/13.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/13.spi_device_csb_read.855033830 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 17662072 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:38:19 PM PST 24 |
| Finished | Mar 05 01:38:20 PM PST 24 |
| Peak memory | 206344 kb |
| Host | smart-3d9e32fd-d709-4703-9f4d-2620e4818aae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855033830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.855033830 |
| Directory | /workspace/13.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/13.spi_device_flash_all.3803933474 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 14283427708 ps |
| CPU time | 38.56 seconds |
| Started | Mar 05 01:38:25 PM PST 24 |
| Finished | Mar 05 01:39:03 PM PST 24 |
| Peak memory | 240676 kb |
| Host | smart-3a7e1850-12a5-416d-86b3-a596ae2deabb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803933474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3803933474 |
| Directory | /workspace/13.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/13.spi_device_flash_and_tpm.915306283 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 53879936471 ps |
| CPU time | 93.77 seconds |
| Started | Mar 05 01:38:27 PM PST 24 |
| Finished | Mar 05 01:40:01 PM PST 24 |
| Peak memory | 235508 kb |
| Host | smart-76c205d8-52b1-422d-8498-b4f32b42ebb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915306283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.915306283 |
| Directory | /workspace/13.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3358593541 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 29198663149 ps |
| CPU time | 199.31 seconds |
| Started | Mar 05 01:38:26 PM PST 24 |
| Finished | Mar 05 01:41:46 PM PST 24 |
| Peak memory | 254236 kb |
| Host | smart-76073d84-e3ab-4202-9b5d-dde221f2bdad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358593541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl e.3358593541 |
| Directory | /workspace/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/13.spi_device_flash_mode.2795848558 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1203637988 ps |
| CPU time | 13.47 seconds |
| Started | Mar 05 01:38:27 PM PST 24 |
| Finished | Mar 05 01:38:40 PM PST 24 |
| Peak memory | 245944 kb |
| Host | smart-d2166a8f-0aa9-428b-816b-b2d8eb469980 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795848558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2795848558 |
| Directory | /workspace/13.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/13.spi_device_intercept.1138837687 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 922245839 ps |
| CPU time | 2.69 seconds |
| Started | Mar 05 01:38:19 PM PST 24 |
| Finished | Mar 05 01:38:22 PM PST 24 |
| Peak memory | 216372 kb |
| Host | smart-a2c8a0f6-5a88-41f9-999a-47741fbb7b3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138837687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1138837687 |
| Directory | /workspace/13.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/13.spi_device_mailbox.2532508683 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 540854854 ps |
| CPU time | 9.56 seconds |
| Started | Mar 05 01:38:16 PM PST 24 |
| Finished | Mar 05 01:38:26 PM PST 24 |
| Peak memory | 220432 kb |
| Host | smart-db34fbeb-7ea5-441b-bb82-d8bde2b0feb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532508683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2532508683 |
| Directory | /workspace/13.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/13.spi_device_mem_parity.1277801448 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 130885011 ps |
| CPU time | 1.04 seconds |
| Started | Mar 05 01:38:16 PM PST 24 |
| Finished | Mar 05 01:38:18 PM PST 24 |
| Peak memory | 216488 kb |
| Host | smart-822c5a4c-92cb-4a54-8c1b-1278f1cf2bd0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277801448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.spi_device_mem_parity.1277801448 |
| Directory | /workspace/13.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1441746086 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1887220473 ps |
| CPU time | 9.36 seconds |
| Started | Mar 05 01:38:19 PM PST 24 |
| Finished | Mar 05 01:38:28 PM PST 24 |
| Peak memory | 229180 kb |
| Host | smart-feee2a2b-b408-440f-9645-85c3368611c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441746086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa p.1441746086 |
| Directory | /workspace/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2128327204 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2004749309 ps |
| CPU time | 6.85 seconds |
| Started | Mar 05 01:38:20 PM PST 24 |
| Finished | Mar 05 01:38:27 PM PST 24 |
| Peak memory | 234040 kb |
| Host | smart-b90bcdc7-9938-44da-9451-ed8ebbbd3171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128327204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2128327204 |
| Directory | /workspace/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/13.spi_device_ram_cfg.2863461029 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 20113911 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:38:21 PM PST 24 |
| Finished | Mar 05 01:38:22 PM PST 24 |
| Peak memory | 216056 kb |
| Host | smart-b5dc2ca7-c437-44ae-a1c8-e9b5ed605e41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863461029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2863461029 |
| Directory | /workspace/13.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/13.spi_device_read_buffer_direct.3510618134 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 6314739093 ps |
| CPU time | 7.37 seconds |
| Started | Mar 05 01:38:26 PM PST 24 |
| Finished | Mar 05 01:38:34 PM PST 24 |
| Peak memory | 222632 kb |
| Host | smart-536a6f78-453b-41cb-a9e2-c4bebcb76fd2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3510618134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir ect.3510618134 |
| Directory | /workspace/13.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/13.spi_device_tpm_all.73837181 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 32468883318 ps |
| CPU time | 29.84 seconds |
| Started | Mar 05 01:38:19 PM PST 24 |
| Finished | Mar 05 01:38:49 PM PST 24 |
| Peak memory | 216112 kb |
| Host | smart-e2e25141-aad1-412f-a202-075b54a35f03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73837181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.73837181 |
| Directory | /workspace/13.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2661802015 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1478242374 ps |
| CPU time | 4.31 seconds |
| Started | Mar 05 01:38:17 PM PST 24 |
| Finished | Mar 05 01:38:21 PM PST 24 |
| Peak memory | 216076 kb |
| Host | smart-a00f0b38-64c8-47ac-8b40-a2cdd65de1da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661802015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2661802015 |
| Directory | /workspace/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/13.spi_device_tpm_rw.3101139428 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 29202451 ps |
| CPU time | 1.85 seconds |
| Started | Mar 05 01:38:19 PM PST 24 |
| Finished | Mar 05 01:38:22 PM PST 24 |
| Peak memory | 216456 kb |
| Host | smart-735afc67-906c-40ea-9a90-4f940b29f41c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101139428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3101139428 |
| Directory | /workspace/13.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/13.spi_device_tpm_sts_read.371393032 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 131265769 ps |
| CPU time | 0.98 seconds |
| Started | Mar 05 01:38:18 PM PST 24 |
| Finished | Mar 05 01:38:19 PM PST 24 |
| Peak memory | 206400 kb |
| Host | smart-05b6dced-d965-4060-a1fd-86d80fed495c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371393032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.371393032 |
| Directory | /workspace/13.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/13.spi_device_upload.1639140166 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1383674769 ps |
| CPU time | 7.6 seconds |
| Started | Mar 05 01:38:25 PM PST 24 |
| Finished | Mar 05 01:38:32 PM PST 24 |
| Peak memory | 233496 kb |
| Host | smart-6df68ca7-3290-42a6-a29c-53d6eeb4512f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639140166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1639140166 |
| Directory | /workspace/13.spi_device_upload/latest |
| Test location | /workspace/coverage/default/14.spi_device_alert_test.2256904946 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 16261412 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 01:38:43 PM PST 24 |
| Finished | Mar 05 01:38:43 PM PST 24 |
| Peak memory | 204812 kb |
| Host | smart-bd9bfc20-1dbd-486f-a439-0b18d847ea38 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256904946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test. 2256904946 |
| Directory | /workspace/14.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/14.spi_device_cfg_cmd.4116182664 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1428348687 ps |
| CPU time | 3.56 seconds |
| Started | Mar 05 01:38:31 PM PST 24 |
| Finished | Mar 05 01:38:35 PM PST 24 |
| Peak memory | 233136 kb |
| Host | smart-d1a5f18d-ccc6-4972-ac23-0ef52ec517f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116182664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4116182664 |
| Directory | /workspace/14.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/14.spi_device_csb_read.2159726910 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 47081551 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:38:27 PM PST 24 |
| Finished | Mar 05 01:38:28 PM PST 24 |
| Peak memory | 206320 kb |
| Host | smart-9ac854d2-6b71-444d-9cd3-ffa32cddb3a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159726910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2159726910 |
| Directory | /workspace/14.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/14.spi_device_flash_all.3073731531 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1586631203 ps |
| CPU time | 6.95 seconds |
| Started | Mar 05 01:38:36 PM PST 24 |
| Finished | Mar 05 01:38:43 PM PST 24 |
| Peak memory | 232592 kb |
| Host | smart-5ad79e5a-5e2f-45d5-be8c-69da5014eb3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073731531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3073731531 |
| Directory | /workspace/14.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/14.spi_device_flash_and_tpm.2981676664 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 69750095672 ps |
| CPU time | 152.14 seconds |
| Started | Mar 05 01:38:38 PM PST 24 |
| Finished | Mar 05 01:41:11 PM PST 24 |
| Peak memory | 257356 kb |
| Host | smart-11cde93f-545f-47b0-a8f8-26d3185c9248 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981676664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2981676664 |
| Directory | /workspace/14.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/14.spi_device_flash_mode.3206801307 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13566502169 ps |
| CPU time | 25.94 seconds |
| Started | Mar 05 01:38:33 PM PST 24 |
| Finished | Mar 05 01:38:59 PM PST 24 |
| Peak memory | 247388 kb |
| Host | smart-b31512c3-8f60-43f4-b503-4e994b5f3925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206801307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3206801307 |
| Directory | /workspace/14.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/14.spi_device_intercept.1772032907 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 4822341810 ps |
| CPU time | 7.47 seconds |
| Started | Mar 05 01:38:35 PM PST 24 |
| Finished | Mar 05 01:38:43 PM PST 24 |
| Peak memory | 224420 kb |
| Host | smart-6a675df8-9522-4b66-8b79-e3b6f16f9c51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772032907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1772032907 |
| Directory | /workspace/14.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/14.spi_device_mailbox.2474665924 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 51963670 ps |
| CPU time | 2.82 seconds |
| Started | Mar 05 01:38:38 PM PST 24 |
| Finished | Mar 05 01:38:41 PM PST 24 |
| Peak memory | 232552 kb |
| Host | smart-a3579bcc-36a9-43a3-9e4a-1a1bacdd0a82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474665924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2474665924 |
| Directory | /workspace/14.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/14.spi_device_mem_parity.3091377045 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 60643700 ps |
| CPU time | 1.03 seconds |
| Started | Mar 05 01:38:27 PM PST 24 |
| Finished | Mar 05 01:38:28 PM PST 24 |
| Peak memory | 216488 kb |
| Host | smart-d558ee14-3e76-44f1-b363-f2bc5dd76962 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091377045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.spi_device_mem_parity.3091377045 |
| Directory | /workspace/14.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1236552002 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 15847578936 ps |
| CPU time | 18.4 seconds |
| Started | Mar 05 01:38:33 PM PST 24 |
| Finished | Mar 05 01:38:51 PM PST 24 |
| Peak memory | 228480 kb |
| Host | smart-10fb8c72-9c63-458b-b9d2-1193155c61ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236552002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa p.1236552002 |
| Directory | /workspace/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1002218286 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2961186102 ps |
| CPU time | 6.34 seconds |
| Started | Mar 05 01:38:36 PM PST 24 |
| Finished | Mar 05 01:38:42 PM PST 24 |
| Peak memory | 217292 kb |
| Host | smart-c5544f38-7823-4ba0-8578-533f873f43e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002218286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1002218286 |
| Directory | /workspace/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/14.spi_device_ram_cfg.3925111450 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 30178969 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:38:35 PM PST 24 |
| Finished | Mar 05 01:38:36 PM PST 24 |
| Peak memory | 216048 kb |
| Host | smart-ceb8efcb-9b12-4c90-8391-aaa87461e03c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3925111450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.3925111450 |
| Directory | /workspace/14.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/14.spi_device_read_buffer_direct.3062267748 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 1814640048 ps |
| CPU time | 4.66 seconds |
| Started | Mar 05 01:38:32 PM PST 24 |
| Finished | Mar 05 01:38:38 PM PST 24 |
| Peak memory | 217256 kb |
| Host | smart-60069f91-c389-4b66-a52b-9f67c258b423 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3062267748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir ect.3062267748 |
| Directory | /workspace/14.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/14.spi_device_tpm_all.3897293567 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2753543897 ps |
| CPU time | 14.9 seconds |
| Started | Mar 05 01:38:32 PM PST 24 |
| Finished | Mar 05 01:38:48 PM PST 24 |
| Peak memory | 216172 kb |
| Host | smart-bb36a7da-4d2b-4b26-9560-c86025d5a22a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897293567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3897293567 |
| Directory | /workspace/14.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.183129179 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 20280235171 ps |
| CPU time | 30.11 seconds |
| Started | Mar 05 01:38:34 PM PST 24 |
| Finished | Mar 05 01:39:04 PM PST 24 |
| Peak memory | 217396 kb |
| Host | smart-24748ca5-b997-4021-a6cd-8727b326533c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183129179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.183129179 |
| Directory | /workspace/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/14.spi_device_tpm_rw.3479627397 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 102380055 ps |
| CPU time | 1.44 seconds |
| Started | Mar 05 01:38:33 PM PST 24 |
| Finished | Mar 05 01:38:34 PM PST 24 |
| Peak memory | 216156 kb |
| Host | smart-c3120b70-1b87-4f0e-a251-e633bbdd0e95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3479627397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3479627397 |
| Directory | /workspace/14.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/14.spi_device_tpm_sts_read.1355451795 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 127524510 ps |
| CPU time | 0.85 seconds |
| Started | Mar 05 01:38:34 PM PST 24 |
| Finished | Mar 05 01:38:35 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-71599a17-0395-400e-8737-ce7d0a1e3c79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355451795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1355451795 |
| Directory | /workspace/14.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/14.spi_device_upload.3926368766 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4155846083 ps |
| CPU time | 19.79 seconds |
| Started | Mar 05 01:38:36 PM PST 24 |
| Finished | Mar 05 01:38:55 PM PST 24 |
| Peak memory | 248136 kb |
| Host | smart-f85b0dba-1c68-4484-821e-ea08ef44b50c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926368766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3926368766 |
| Directory | /workspace/14.spi_device_upload/latest |
| Test location | /workspace/coverage/default/15.spi_device_alert_test.3640129804 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 39286113 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:38:49 PM PST 24 |
| Finished | Mar 05 01:38:49 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-c39c530a-0a90-4335-bf9b-f63d11a121ec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640129804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test. 3640129804 |
| Directory | /workspace/15.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/15.spi_device_cfg_cmd.2228865129 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 571022167 ps |
| CPU time | 3.19 seconds |
| Started | Mar 05 01:38:43 PM PST 24 |
| Finished | Mar 05 01:38:46 PM PST 24 |
| Peak memory | 216872 kb |
| Host | smart-4a1a4be2-f9bc-43ba-ac54-d430053bad9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228865129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2228865129 |
| Directory | /workspace/15.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/15.spi_device_csb_read.2591992078 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 31783174 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:38:40 PM PST 24 |
| Finished | Mar 05 01:38:40 PM PST 24 |
| Peak memory | 204964 kb |
| Host | smart-b91d81d8-7476-4e8b-966b-f19851906472 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591992078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2591992078 |
| Directory | /workspace/15.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/15.spi_device_flash_all.2182500569 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 987066845 ps |
| CPU time | 10.59 seconds |
| Started | Mar 05 01:38:42 PM PST 24 |
| Finished | Mar 05 01:38:53 PM PST 24 |
| Peak memory | 234632 kb |
| Host | smart-5983d2b4-792c-4642-8dca-ffda5e4e162d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182500569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2182500569 |
| Directory | /workspace/15.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/15.spi_device_flash_and_tpm.3611711338 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 4640498253 ps |
| CPU time | 90.5 seconds |
| Started | Mar 05 01:38:47 PM PST 24 |
| Finished | Mar 05 01:40:17 PM PST 24 |
| Peak memory | 256708 kb |
| Host | smart-0139dd88-178c-4168-b1de-2fd71ff6624f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611711338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3611711338 |
| Directory | /workspace/15.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3368341711 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 33342795183 ps |
| CPU time | 93.82 seconds |
| Started | Mar 05 01:38:48 PM PST 24 |
| Finished | Mar 05 01:40:22 PM PST 24 |
| Peak memory | 251436 kb |
| Host | smart-fe51a20a-1f8c-412d-b8d2-fdd9cddfc7c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368341711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl e.3368341711 |
| Directory | /workspace/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/15.spi_device_flash_mode.2525396261 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 14336443952 ps |
| CPU time | 23.85 seconds |
| Started | Mar 05 01:38:43 PM PST 24 |
| Finished | Mar 05 01:39:07 PM PST 24 |
| Peak memory | 233508 kb |
| Host | smart-ec8013d9-4e19-4bed-967f-40631eeb6e65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525396261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2525396261 |
| Directory | /workspace/15.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/15.spi_device_intercept.3570741566 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 11739421344 ps |
| CPU time | 9.41 seconds |
| Started | Mar 05 01:38:45 PM PST 24 |
| Finished | Mar 05 01:38:54 PM PST 24 |
| Peak memory | 224392 kb |
| Host | smart-45d69674-ca9c-430f-8ef3-7979d2c9a5d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570741566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3570741566 |
| Directory | /workspace/15.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/15.spi_device_mailbox.2753028625 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 30265050464 ps |
| CPU time | 47.22 seconds |
| Started | Mar 05 01:38:42 PM PST 24 |
| Finished | Mar 05 01:39:29 PM PST 24 |
| Peak memory | 232640 kb |
| Host | smart-3cccb661-bbe6-4191-b17f-4b7e3624a76f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753028625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2753028625 |
| Directory | /workspace/15.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/15.spi_device_mem_parity.894926524 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 331632835 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:38:40 PM PST 24 |
| Finished | Mar 05 01:38:41 PM PST 24 |
| Peak memory | 216516 kb |
| Host | smart-0de7b707-6fd1-4080-be09-c27e00be03b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894926524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.894926524 |
| Directory | /workspace/15.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3182217826 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 507495896 ps |
| CPU time | 2.66 seconds |
| Started | Mar 05 01:38:51 PM PST 24 |
| Finished | Mar 05 01:38:54 PM PST 24 |
| Peak memory | 223432 kb |
| Host | smart-e68f8080-7d8b-4b1c-87cb-7753405b6885 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3182217826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa p.3182217826 |
| Directory | /workspace/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/15.spi_device_ram_cfg.1466440698 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 17870930 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:38:40 PM PST 24 |
| Finished | Mar 05 01:38:41 PM PST 24 |
| Peak memory | 216044 kb |
| Host | smart-29c827a6-b500-4919-b474-4af9174e728b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466440698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.1466440698 |
| Directory | /workspace/15.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/15.spi_device_read_buffer_direct.3944623386 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 232625542 ps |
| CPU time | 3.93 seconds |
| Started | Mar 05 01:38:46 PM PST 24 |
| Finished | Mar 05 01:38:50 PM PST 24 |
| Peak memory | 222624 kb |
| Host | smart-f70ca241-4c72-4dde-928c-e94b0230f662 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3944623386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir ect.3944623386 |
| Directory | /workspace/15.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/15.spi_device_tpm_all.591126191 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2449910600 ps |
| CPU time | 13.57 seconds |
| Started | Mar 05 01:38:43 PM PST 24 |
| Finished | Mar 05 01:38:56 PM PST 24 |
| Peak memory | 216296 kb |
| Host | smart-f92672f1-c3c7-473a-af57-f9360b178028 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591126191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.591126191 |
| Directory | /workspace/15.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/15.spi_device_tpm_rw.1048187829 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 34186780 ps |
| CPU time | 1.65 seconds |
| Started | Mar 05 01:38:46 PM PST 24 |
| Finished | Mar 05 01:38:48 PM PST 24 |
| Peak memory | 216216 kb |
| Host | smart-1dba7676-3ba9-4685-91dc-016b84c3a85b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048187829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1048187829 |
| Directory | /workspace/15.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/15.spi_device_tpm_sts_read.4279427987 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 123211858 ps |
| CPU time | 0.95 seconds |
| Started | Mar 05 01:38:51 PM PST 24 |
| Finished | Mar 05 01:38:52 PM PST 24 |
| Peak memory | 205260 kb |
| Host | smart-8e819f57-0cc5-4b5f-b6f6-6af41263a6bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279427987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4279427987 |
| Directory | /workspace/15.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/15.spi_device_upload.1325985071 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 3040761105 ps |
| CPU time | 9.41 seconds |
| Started | Mar 05 01:38:40 PM PST 24 |
| Finished | Mar 05 01:38:50 PM PST 24 |
| Peak memory | 230204 kb |
| Host | smart-3a21cf9f-9751-4d18-b4be-5898f7e8f2f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325985071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1325985071 |
| Directory | /workspace/15.spi_device_upload/latest |
| Test location | /workspace/coverage/default/16.spi_device_alert_test.2979317447 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 11064356 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:38:58 PM PST 24 |
| Finished | Mar 05 01:38:59 PM PST 24 |
| Peak memory | 204844 kb |
| Host | smart-9c447e7e-e590-4da6-ab26-4ffd8b450c98 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979317447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test. 2979317447 |
| Directory | /workspace/16.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/16.spi_device_cfg_cmd.248538655 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 231229413 ps |
| CPU time | 3.41 seconds |
| Started | Mar 05 01:38:55 PM PST 24 |
| Finished | Mar 05 01:39:00 PM PST 24 |
| Peak memory | 220176 kb |
| Host | smart-ab34a706-dc20-460f-8ecb-1b274141296f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248538655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.248538655 |
| Directory | /workspace/16.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/16.spi_device_csb_read.796730630 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 21226032 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:38:47 PM PST 24 |
| Finished | Mar 05 01:38:48 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-13d4b1a3-1cc4-46e6-8645-aa4cdffe7757 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796730630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.796730630 |
| Directory | /workspace/16.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/16.spi_device_flash_all.1367257667 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 25627821402 ps |
| CPU time | 67.24 seconds |
| Started | Mar 05 01:38:57 PM PST 24 |
| Finished | Mar 05 01:40:04 PM PST 24 |
| Peak memory | 238428 kb |
| Host | smart-aebc762d-9f65-4cc3-a0b3-b64ae94e1d27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367257667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1367257667 |
| Directory | /workspace/16.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/16.spi_device_flash_and_tpm.3448478762 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 61670327998 ps |
| CPU time | 253.76 seconds |
| Started | Mar 05 01:38:55 PM PST 24 |
| Finished | Mar 05 01:43:10 PM PST 24 |
| Peak memory | 271588 kb |
| Host | smart-805db6a6-75a7-4eba-b5df-843fe82b8bbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448478762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3448478762 |
| Directory | /workspace/16.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2716947638 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 29423736263 ps |
| CPU time | 187.54 seconds |
| Started | Mar 05 01:38:54 PM PST 24 |
| Finished | Mar 05 01:42:04 PM PST 24 |
| Peak memory | 236736 kb |
| Host | smart-c4c01b99-24ec-4fc0-988e-a092f3d9bec8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716947638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl e.2716947638 |
| Directory | /workspace/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/16.spi_device_flash_mode.759095629 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 63908925099 ps |
| CPU time | 26.63 seconds |
| Started | Mar 05 01:38:51 PM PST 24 |
| Finished | Mar 05 01:39:18 PM PST 24 |
| Peak memory | 238136 kb |
| Host | smart-d00fedf4-04b5-417b-989b-ced6eb0fdfd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759095629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.759095629 |
| Directory | /workspace/16.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/16.spi_device_intercept.2128795416 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 244905646 ps |
| CPU time | 4.6 seconds |
| Started | Mar 05 01:38:50 PM PST 24 |
| Finished | Mar 05 01:38:55 PM PST 24 |
| Peak memory | 233036 kb |
| Host | smart-f2b442d6-0540-4f11-a34f-e17fe2f43d30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128795416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2128795416 |
| Directory | /workspace/16.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/16.spi_device_mailbox.2930837014 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 13555219283 ps |
| CPU time | 16.9 seconds |
| Started | Mar 05 01:38:51 PM PST 24 |
| Finished | Mar 05 01:39:08 PM PST 24 |
| Peak memory | 249024 kb |
| Host | smart-88682501-190c-4f42-8344-6478da6c4785 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930837014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2930837014 |
| Directory | /workspace/16.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/16.spi_device_mem_parity.295334113 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 17993767 ps |
| CPU time | 1.04 seconds |
| Started | Mar 05 01:38:50 PM PST 24 |
| Finished | Mar 05 01:38:51 PM PST 24 |
| Peak memory | 217748 kb |
| Host | smart-ea97204a-b6ff-4a57-9ae0-cb29d58f4384 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295334113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.295334113 |
| Directory | /workspace/16.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.289782144 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 8393162469 ps |
| CPU time | 22.55 seconds |
| Started | Mar 05 01:38:50 PM PST 24 |
| Finished | Mar 05 01:39:12 PM PST 24 |
| Peak memory | 233248 kb |
| Host | smart-52c11111-7b64-4b28-a082-a8edece24943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289782144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap .289782144 |
| Directory | /workspace/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/16.spi_device_pass_cmd_filtering.391664626 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 647693852 ps |
| CPU time | 7.33 seconds |
| Started | Mar 05 01:38:50 PM PST 24 |
| Finished | Mar 05 01:38:58 PM PST 24 |
| Peak memory | 223500 kb |
| Host | smart-265cecff-2f57-4113-8250-a6894f662e5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391664626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.391664626 |
| Directory | /workspace/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/16.spi_device_ram_cfg.2210266095 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 51270444 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:38:52 PM PST 24 |
| Finished | Mar 05 01:38:52 PM PST 24 |
| Peak memory | 215952 kb |
| Host | smart-f052a9fd-aa3e-41a2-9eb6-9ef40740b27d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210266095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2210266095 |
| Directory | /workspace/16.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/16.spi_device_read_buffer_direct.3327866802 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2095426896 ps |
| CPU time | 4.59 seconds |
| Started | Mar 05 01:38:57 PM PST 24 |
| Finished | Mar 05 01:39:02 PM PST 24 |
| Peak memory | 221924 kb |
| Host | smart-fe2debb9-9a59-4e0f-be38-8ffb817482cc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3327866802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir ect.3327866802 |
| Directory | /workspace/16.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/16.spi_device_tpm_all.1889918384 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 4299703746 ps |
| CPU time | 10.57 seconds |
| Started | Mar 05 01:38:50 PM PST 24 |
| Finished | Mar 05 01:39:00 PM PST 24 |
| Peak memory | 216448 kb |
| Host | smart-883ef5a8-3763-4870-9e34-baf1bd1cc629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889918384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1889918384 |
| Directory | /workspace/16.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.354300403 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 159312288 ps |
| CPU time | 1.99 seconds |
| Started | Mar 05 01:38:49 PM PST 24 |
| Finished | Mar 05 01:38:51 PM PST 24 |
| Peak memory | 207768 kb |
| Host | smart-01b85508-4fff-4b0b-99e8-fd6d1fc1fa33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354300403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.354300403 |
| Directory | /workspace/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/16.spi_device_tpm_rw.2354140153 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 81296187 ps |
| CPU time | 1.93 seconds |
| Started | Mar 05 01:38:53 PM PST 24 |
| Finished | Mar 05 01:38:55 PM PST 24 |
| Peak memory | 217364 kb |
| Host | smart-b637e8f9-c1b3-4efa-9cbd-dea524887542 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354140153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2354140153 |
| Directory | /workspace/16.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/16.spi_device_tpm_sts_read.2221058642 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 744120456 ps |
| CPU time | 0.99 seconds |
| Started | Mar 05 01:38:55 PM PST 24 |
| Finished | Mar 05 01:38:57 PM PST 24 |
| Peak memory | 205676 kb |
| Host | smart-056259a3-6aa3-45a6-a328-9ba013906e01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221058642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2221058642 |
| Directory | /workspace/16.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/16.spi_device_upload.4101060624 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6341098244 ps |
| CPU time | 7.75 seconds |
| Started | Mar 05 01:38:52 PM PST 24 |
| Finished | Mar 05 01:39:01 PM PST 24 |
| Peak memory | 236448 kb |
| Host | smart-9293375b-8e8d-47c8-8287-3c2eae045c71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101060624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4101060624 |
| Directory | /workspace/16.spi_device_upload/latest |
| Test location | /workspace/coverage/default/17.spi_device_alert_test.1948088113 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 13427426 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:39:05 PM PST 24 |
| Finished | Mar 05 01:39:06 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-6fffecfc-fa99-4e3a-b012-1d853da171dc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948088113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test. 1948088113 |
| Directory | /workspace/17.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/17.spi_device_cfg_cmd.3809866024 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 370571800 ps |
| CPU time | 3.34 seconds |
| Started | Mar 05 01:39:08 PM PST 24 |
| Finished | Mar 05 01:39:12 PM PST 24 |
| Peak memory | 233696 kb |
| Host | smart-fe24c38c-438d-4c96-a0cc-b69162c5e5d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809866024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3809866024 |
| Directory | /workspace/17.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/17.spi_device_csb_read.3651237299 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 52067460 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 01:38:55 PM PST 24 |
| Finished | Mar 05 01:38:57 PM PST 24 |
| Peak memory | 205288 kb |
| Host | smart-02bf0682-b5ed-484f-a032-4c2bed918492 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651237299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3651237299 |
| Directory | /workspace/17.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/17.spi_device_flash_all.3716822115 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 7469885819 ps |
| CPU time | 45.32 seconds |
| Started | Mar 05 01:39:01 PM PST 24 |
| Finished | Mar 05 01:39:47 PM PST 24 |
| Peak memory | 249048 kb |
| Host | smart-232730f3-c146-4259-aed5-504b3fb5c3f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716822115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3716822115 |
| Directory | /workspace/17.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1616899603 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 13277204308 ps |
| CPU time | 131.36 seconds |
| Started | Mar 05 01:39:05 PM PST 24 |
| Finished | Mar 05 01:41:16 PM PST 24 |
| Peak memory | 257296 kb |
| Host | smart-f5ea3a33-47ee-47c1-868c-70f00a82eab8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616899603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl e.1616899603 |
| Directory | /workspace/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/17.spi_device_intercept.2818447848 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 865644099 ps |
| CPU time | 5.29 seconds |
| Started | Mar 05 01:38:59 PM PST 24 |
| Finished | Mar 05 01:39:05 PM PST 24 |
| Peak memory | 233776 kb |
| Host | smart-26bff8f9-cbff-4da5-a607-6a1513ed9f77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818447848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2818447848 |
| Directory | /workspace/17.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/17.spi_device_mailbox.2228931669 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 22084972966 ps |
| CPU time | 29.53 seconds |
| Started | Mar 05 01:39:09 PM PST 24 |
| Finished | Mar 05 01:39:39 PM PST 24 |
| Peak memory | 221624 kb |
| Host | smart-a0f9d93b-456c-4a30-bfdb-81fecf12c4f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228931669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2228931669 |
| Directory | /workspace/17.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/17.spi_device_mem_parity.1134470991 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 50915015 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:38:58 PM PST 24 |
| Finished | Mar 05 01:39:00 PM PST 24 |
| Peak memory | 216524 kb |
| Host | smart-ca1414ed-0ec6-4f4f-9270-3a308ce12c10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134470991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.spi_device_mem_parity.1134470991 |
| Directory | /workspace/17.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3556574506 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 4583860138 ps |
| CPU time | 11.81 seconds |
| Started | Mar 05 01:38:59 PM PST 24 |
| Finished | Mar 05 01:39:11 PM PST 24 |
| Peak memory | 236428 kb |
| Host | smart-62eea25b-28ee-40e6-a950-aa8854c06958 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556574506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa p.3556574506 |
| Directory | /workspace/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/17.spi_device_pass_cmd_filtering.4135232175 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3193028388 ps |
| CPU time | 9.86 seconds |
| Started | Mar 05 01:38:59 PM PST 24 |
| Finished | Mar 05 01:39:09 PM PST 24 |
| Peak memory | 232472 kb |
| Host | smart-1687bb15-45a7-48ea-9504-68d3ab5b528e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135232175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.4135232175 |
| Directory | /workspace/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/17.spi_device_ram_cfg.983528509 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 22044280 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:38:57 PM PST 24 |
| Finished | Mar 05 01:38:58 PM PST 24 |
| Peak memory | 216080 kb |
| Host | smart-d4fc170d-0908-4876-82be-92ee31e70511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983528509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.983528509 |
| Directory | /workspace/17.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/17.spi_device_read_buffer_direct.1158220127 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 446751301 ps |
| CPU time | 3.75 seconds |
| Started | Mar 05 01:39:03 PM PST 24 |
| Finished | Mar 05 01:39:07 PM PST 24 |
| Peak memory | 222092 kb |
| Host | smart-310dbc2b-94fe-4dc9-9206-4bb9517079d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1158220127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir ect.1158220127 |
| Directory | /workspace/17.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/17.spi_device_stress_all.3165169592 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 12945896991 ps |
| CPU time | 77.93 seconds |
| Started | Mar 05 01:39:03 PM PST 24 |
| Finished | Mar 05 01:40:21 PM PST 24 |
| Peak memory | 250904 kb |
| Host | smart-da9b205e-2b4b-442d-b9df-f12c1500290b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165169592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre ss_all.3165169592 |
| Directory | /workspace/17.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/17.spi_device_tpm_all.2689998278 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 7302143618 ps |
| CPU time | 39.39 seconds |
| Started | Mar 05 01:38:55 PM PST 24 |
| Finished | Mar 05 01:39:36 PM PST 24 |
| Peak memory | 216220 kb |
| Host | smart-29df78fb-53c7-4ee5-896d-27e79f4bb8f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2689998278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2689998278 |
| Directory | /workspace/17.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3692914050 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2974871299 ps |
| CPU time | 16.2 seconds |
| Started | Mar 05 01:38:56 PM PST 24 |
| Finished | Mar 05 01:39:13 PM PST 24 |
| Peak memory | 216272 kb |
| Host | smart-113c2122-a1b9-4173-a468-26f1ba5cb283 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692914050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3692914050 |
| Directory | /workspace/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/17.spi_device_tpm_rw.132155338 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 63548435 ps |
| CPU time | 1.88 seconds |
| Started | Mar 05 01:38:58 PM PST 24 |
| Finished | Mar 05 01:39:00 PM PST 24 |
| Peak memory | 216284 kb |
| Host | smart-3a999d77-2f10-4baa-8915-f0603b6727af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132155338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.132155338 |
| Directory | /workspace/17.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/17.spi_device_tpm_sts_read.3833948985 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 66198636 ps |
| CPU time | 0.91 seconds |
| Started | Mar 05 01:38:55 PM PST 24 |
| Finished | Mar 05 01:38:57 PM PST 24 |
| Peak memory | 206396 kb |
| Host | smart-9afb7efe-6f94-4159-b5b4-3b66bf07496b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833948985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3833948985 |
| Directory | /workspace/17.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/17.spi_device_upload.2186973735 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 24916270807 ps |
| CPU time | 23.35 seconds |
| Started | Mar 05 01:39:02 PM PST 24 |
| Finished | Mar 05 01:39:26 PM PST 24 |
| Peak memory | 233772 kb |
| Host | smart-a8d1a361-5929-4142-a505-ae0f3b76c104 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186973735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2186973735 |
| Directory | /workspace/17.spi_device_upload/latest |
| Test location | /workspace/coverage/default/18.spi_device_alert_test.4101126502 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 49432715 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:39:16 PM PST 24 |
| Finished | Mar 05 01:39:19 PM PST 24 |
| Peak memory | 204880 kb |
| Host | smart-3fc324ba-ba50-411d-81f9-5cf507f95b5c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101126502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test. 4101126502 |
| Directory | /workspace/18.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/18.spi_device_cfg_cmd.1297636549 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1959759280 ps |
| CPU time | 7.03 seconds |
| Started | Mar 05 01:39:19 PM PST 24 |
| Finished | Mar 05 01:39:29 PM PST 24 |
| Peak memory | 217532 kb |
| Host | smart-0ccfec88-8739-4aa9-b325-f9269a8b4c71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297636549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1297636549 |
| Directory | /workspace/18.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/18.spi_device_csb_read.1808803990 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 56699261 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:39:05 PM PST 24 |
| Finished | Mar 05 01:39:05 PM PST 24 |
| Peak memory | 206296 kb |
| Host | smart-a381faac-5355-4cf5-bde7-75c8feae51d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808803990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1808803990 |
| Directory | /workspace/18.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/18.spi_device_flash_and_tpm.1498959005 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 283965621001 ps |
| CPU time | 243.31 seconds |
| Started | Mar 05 01:39:23 PM PST 24 |
| Finished | Mar 05 01:43:29 PM PST 24 |
| Peak memory | 260156 kb |
| Host | smart-ae81d888-f0bf-434e-8007-ff7afca90195 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498959005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1498959005 |
| Directory | /workspace/18.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1775607236 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3780786192 ps |
| CPU time | 39.55 seconds |
| Started | Mar 05 01:39:15 PM PST 24 |
| Finished | Mar 05 01:39:56 PM PST 24 |
| Peak memory | 236428 kb |
| Host | smart-01f74b88-9a91-481f-ba02-81c9511f0b02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775607236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl e.1775607236 |
| Directory | /workspace/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/18.spi_device_flash_mode.1213442175 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1625219954 ps |
| CPU time | 16.52 seconds |
| Started | Mar 05 01:39:11 PM PST 24 |
| Finished | Mar 05 01:39:28 PM PST 24 |
| Peak memory | 252972 kb |
| Host | smart-e0a2e69d-a70b-4a93-a31d-ca9fdef3a447 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213442175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1213442175 |
| Directory | /workspace/18.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/18.spi_device_intercept.1130868948 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 211442417 ps |
| CPU time | 3.43 seconds |
| Started | Mar 05 01:39:11 PM PST 24 |
| Finished | Mar 05 01:39:15 PM PST 24 |
| Peak memory | 234060 kb |
| Host | smart-1a474b84-a334-4cdd-9e44-ddfec790a446 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130868948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1130868948 |
| Directory | /workspace/18.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/18.spi_device_mailbox.707364012 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 9362841379 ps |
| CPU time | 11.81 seconds |
| Started | Mar 05 01:39:09 PM PST 24 |
| Finished | Mar 05 01:39:21 PM PST 24 |
| Peak memory | 248336 kb |
| Host | smart-b84530ce-1829-4208-b68f-d15affba9f8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707364012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.707364012 |
| Directory | /workspace/18.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/18.spi_device_mem_parity.2060788478 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 15091207 ps |
| CPU time | 1.04 seconds |
| Started | Mar 05 01:39:06 PM PST 24 |
| Finished | Mar 05 01:39:09 PM PST 24 |
| Peak memory | 217764 kb |
| Host | smart-dbf8ef55-32f7-41fa-9736-9597be79ae9d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060788478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.spi_device_mem_parity.2060788478 |
| Directory | /workspace/18.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4098501274 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 7686690262 ps |
| CPU time | 14.28 seconds |
| Started | Mar 05 01:39:10 PM PST 24 |
| Finished | Mar 05 01:39:24 PM PST 24 |
| Peak memory | 235852 kb |
| Host | smart-d2161f38-9748-4537-85f3-7899e0f778eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098501274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa p.4098501274 |
| Directory | /workspace/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2182209543 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 28696195631 ps |
| CPU time | 24.13 seconds |
| Started | Mar 05 01:39:10 PM PST 24 |
| Finished | Mar 05 01:39:35 PM PST 24 |
| Peak memory | 218988 kb |
| Host | smart-a26611f9-6a5d-4a3a-9ec0-cda8c0d61dfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182209543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2182209543 |
| Directory | /workspace/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/18.spi_device_ram_cfg.3378040161 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 26016489 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:39:06 PM PST 24 |
| Finished | Mar 05 01:39:08 PM PST 24 |
| Peak memory | 216056 kb |
| Host | smart-3634bbb9-ac12-4e0d-b4aa-785fd3aa8152 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378040161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3378040161 |
| Directory | /workspace/18.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/18.spi_device_read_buffer_direct.1325024798 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 861506871 ps |
| CPU time | 5.12 seconds |
| Started | Mar 05 01:39:07 PM PST 24 |
| Finished | Mar 05 01:39:13 PM PST 24 |
| Peak memory | 216424 kb |
| Host | smart-90f46873-9078-48cd-aee4-2642b85c9ea6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1325024798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir ect.1325024798 |
| Directory | /workspace/18.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/18.spi_device_tpm_all.4138320799 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 20716879614 ps |
| CPU time | 29.63 seconds |
| Started | Mar 05 01:39:11 PM PST 24 |
| Finished | Mar 05 01:39:41 PM PST 24 |
| Peak memory | 216316 kb |
| Host | smart-6931057d-ccb6-4d5e-9f8f-dabda809838d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138320799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4138320799 |
| Directory | /workspace/18.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1022811348 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3998368181 ps |
| CPU time | 3.41 seconds |
| Started | Mar 05 01:39:03 PM PST 24 |
| Finished | Mar 05 01:39:07 PM PST 24 |
| Peak memory | 216168 kb |
| Host | smart-53d18733-413b-4b58-8fa3-faf6f7da71cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022811348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1022811348 |
| Directory | /workspace/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/18.spi_device_tpm_rw.4127569875 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 105854239 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:39:08 PM PST 24 |
| Finished | Mar 05 01:39:09 PM PST 24 |
| Peak memory | 207644 kb |
| Host | smart-497a70ee-9b97-48e2-87ed-1de48282d998 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127569875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4127569875 |
| Directory | /workspace/18.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/18.spi_device_tpm_sts_read.116743541 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 27798219 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:39:07 PM PST 24 |
| Finished | Mar 05 01:39:08 PM PST 24 |
| Peak memory | 205304 kb |
| Host | smart-f01b2a78-083d-4c73-8915-e1e0a22af3a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=116743541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.116743541 |
| Directory | /workspace/18.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/18.spi_device_upload.1236409093 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 8714936626 ps |
| CPU time | 15.73 seconds |
| Started | Mar 05 01:39:08 PM PST 24 |
| Finished | Mar 05 01:39:24 PM PST 24 |
| Peak memory | 240016 kb |
| Host | smart-160b043e-3e3b-47ec-8d3f-0e9c09ee43d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236409093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1236409093 |
| Directory | /workspace/18.spi_device_upload/latest |
| Test location | /workspace/coverage/default/19.spi_device_alert_test.3524473716 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 14461127 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:39:24 PM PST 24 |
| Finished | Mar 05 01:39:27 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-9f410998-9988-446e-a6d8-1655651f5952 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524473716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test. 3524473716 |
| Directory | /workspace/19.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/19.spi_device_cfg_cmd.1217330872 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 44066368 ps |
| CPU time | 2.64 seconds |
| Started | Mar 05 01:39:24 PM PST 24 |
| Finished | Mar 05 01:39:29 PM PST 24 |
| Peak memory | 233164 kb |
| Host | smart-434d0687-c4eb-44bc-844e-af450d26efb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217330872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1217330872 |
| Directory | /workspace/19.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/19.spi_device_csb_read.157281072 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 36158875 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:39:18 PM PST 24 |
| Finished | Mar 05 01:39:21 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-cba0b422-102d-4323-8c08-801c5564992c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157281072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.157281072 |
| Directory | /workspace/19.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/19.spi_device_flash_all.3358469337 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 73367522836 ps |
| CPU time | 111.73 seconds |
| Started | Mar 05 01:39:32 PM PST 24 |
| Finished | Mar 05 01:41:25 PM PST 24 |
| Peak memory | 249036 kb |
| Host | smart-4a5f8a41-ed62-45bd-96b0-18b4c9fc6114 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358469337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3358469337 |
| Directory | /workspace/19.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/19.spi_device_flash_and_tpm.3414100382 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 14031422052 ps |
| CPU time | 24.18 seconds |
| Started | Mar 05 01:39:29 PM PST 24 |
| Finished | Mar 05 01:39:53 PM PST 24 |
| Peak memory | 249164 kb |
| Host | smart-efe3ebe1-704e-4067-93f1-a78f5245e7b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414100382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3414100382 |
| Directory | /workspace/19.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.98010882 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 10926122318 ps |
| CPU time | 146.99 seconds |
| Started | Mar 05 01:39:26 PM PST 24 |
| Finished | Mar 05 01:41:54 PM PST 24 |
| Peak memory | 259236 kb |
| Host | smart-61c3b598-905c-4d24-a52f-86e1b9961505 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98010882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.98010882 |
| Directory | /workspace/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/19.spi_device_flash_mode.3526892617 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1796577612 ps |
| CPU time | 16.15 seconds |
| Started | Mar 05 01:39:23 PM PST 24 |
| Finished | Mar 05 01:39:42 PM PST 24 |
| Peak memory | 232536 kb |
| Host | smart-db17db6a-9e4f-4e00-adb0-419d63432db8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526892617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3526892617 |
| Directory | /workspace/19.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/19.spi_device_intercept.410564749 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 964906013 ps |
| CPU time | 4.17 seconds |
| Started | Mar 05 01:39:26 PM PST 24 |
| Finished | Mar 05 01:39:31 PM PST 24 |
| Peak memory | 218304 kb |
| Host | smart-f6619088-ec91-45b7-9aee-9390d109b373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410564749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.410564749 |
| Directory | /workspace/19.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/19.spi_device_mailbox.4057216159 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 112296014 ps |
| CPU time | 2.28 seconds |
| Started | Mar 05 01:39:25 PM PST 24 |
| Finished | Mar 05 01:39:29 PM PST 24 |
| Peak memory | 216796 kb |
| Host | smart-3128b4a6-3117-44b2-9168-b07af760338b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057216159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4057216159 |
| Directory | /workspace/19.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/19.spi_device_mem_parity.4279820755 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 112251162 ps |
| CPU time | 1.03 seconds |
| Started | Mar 05 01:39:18 PM PST 24 |
| Finished | Mar 05 01:39:22 PM PST 24 |
| Peak memory | 216516 kb |
| Host | smart-873332e9-71ae-4dcd-829b-3c5b60389885 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279820755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.spi_device_mem_parity.4279820755 |
| Directory | /workspace/19.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.366677709 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 17160921642 ps |
| CPU time | 8.16 seconds |
| Started | Mar 05 01:39:27 PM PST 24 |
| Finished | Mar 05 01:39:36 PM PST 24 |
| Peak memory | 217680 kb |
| Host | smart-92a11f84-e802-4278-9a8b-5a9c790f1822 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366677709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap .366677709 |
| Directory | /workspace/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2013539944 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1819800452 ps |
| CPU time | 9.78 seconds |
| Started | Mar 05 01:39:14 PM PST 24 |
| Finished | Mar 05 01:39:25 PM PST 24 |
| Peak memory | 233440 kb |
| Host | smart-79418c81-902b-437a-bce8-cd37f4d54513 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013539944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2013539944 |
| Directory | /workspace/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/19.spi_device_ram_cfg.2789121637 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 17316695 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:39:19 PM PST 24 |
| Finished | Mar 05 01:39:22 PM PST 24 |
| Peak memory | 216052 kb |
| Host | smart-64eb9eda-fb03-497b-a795-1775a744fef6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789121637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2789121637 |
| Directory | /workspace/19.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/19.spi_device_read_buffer_direct.578418803 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 714603147 ps |
| CPU time | 5.69 seconds |
| Started | Mar 05 01:39:34 PM PST 24 |
| Finished | Mar 05 01:39:39 PM PST 24 |
| Peak memory | 222324 kb |
| Host | smart-3d42c325-c8f8-439e-9993-585016cd800e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=578418803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire ct.578418803 |
| Directory | /workspace/19.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/19.spi_device_stress_all.1932903025 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 11619170592 ps |
| CPU time | 59.2 seconds |
| Started | Mar 05 01:39:26 PM PST 24 |
| Finished | Mar 05 01:40:26 PM PST 24 |
| Peak memory | 251876 kb |
| Host | smart-798156ec-3084-4a57-bb54-c228c85c2e2b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932903025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre ss_all.1932903025 |
| Directory | /workspace/19.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/19.spi_device_tpm_all.2292356164 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 46747166423 ps |
| CPU time | 26.29 seconds |
| Started | Mar 05 01:39:17 PM PST 24 |
| Finished | Mar 05 01:39:45 PM PST 24 |
| Peak memory | 216232 kb |
| Host | smart-71a3648b-3aca-4b3e-8c20-8cc8a3a78761 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2292356164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2292356164 |
| Directory | /workspace/19.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3192852343 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 195868717 ps |
| CPU time | 1.78 seconds |
| Started | Mar 05 01:39:18 PM PST 24 |
| Finished | Mar 05 01:39:22 PM PST 24 |
| Peak memory | 207816 kb |
| Host | smart-a2318011-d033-49e1-b9dc-83b414fbd340 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192852343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3192852343 |
| Directory | /workspace/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/19.spi_device_tpm_rw.1416155582 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 100320088 ps |
| CPU time | 1.4 seconds |
| Started | Mar 05 01:39:16 PM PST 24 |
| Finished | Mar 05 01:39:19 PM PST 24 |
| Peak memory | 216584 kb |
| Host | smart-2e59aaa6-63fb-4669-ade5-6d558e64a360 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416155582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1416155582 |
| Directory | /workspace/19.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/19.spi_device_tpm_sts_read.1882701871 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1158662124 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:39:17 PM PST 24 |
| Finished | Mar 05 01:39:20 PM PST 24 |
| Peak memory | 206380 kb |
| Host | smart-b9330e26-8edb-4899-a86e-c0f3e687e9f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882701871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1882701871 |
| Directory | /workspace/19.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/19.spi_device_upload.828520742 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3019206603 ps |
| CPU time | 11.11 seconds |
| Started | Mar 05 01:39:24 PM PST 24 |
| Finished | Mar 05 01:39:38 PM PST 24 |
| Peak memory | 234768 kb |
| Host | smart-40bb3b44-f026-4970-ab56-a0aed8058609 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=828520742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.828520742 |
| Directory | /workspace/19.spi_device_upload/latest |
| Test location | /workspace/coverage/default/2.spi_device_alert_test.2413376364 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 15788811 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:36:30 PM PST 24 |
| Finished | Mar 05 01:36:31 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-bafb4a35-ea14-434e-a801-289f89eb889e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413376364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2 413376364 |
| Directory | /workspace/2.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/2.spi_device_cfg_cmd.58814907 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 353304642 ps |
| CPU time | 2.85 seconds |
| Started | Mar 05 01:36:20 PM PST 24 |
| Finished | Mar 05 01:36:23 PM PST 24 |
| Peak memory | 217408 kb |
| Host | smart-e32025e7-fbd0-4244-87f9-02d6df6e1d77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58814907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.58814907 |
| Directory | /workspace/2.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/2.spi_device_csb_read.1671558886 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 14719732 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:36:15 PM PST 24 |
| Finished | Mar 05 01:36:16 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-5aca2764-4a97-48b8-9019-472acf96ff67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671558886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1671558886 |
| Directory | /workspace/2.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/2.spi_device_flash_and_tpm.765713900 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 9114501321 ps |
| CPU time | 51.32 seconds |
| Started | Mar 05 01:36:33 PM PST 24 |
| Finished | Mar 05 01:37:25 PM PST 24 |
| Peak memory | 255660 kb |
| Host | smart-95e74157-3fab-4da1-9e92-59b3ee5511ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=765713900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.765713900 |
| Directory | /workspace/2.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/2.spi_device_flash_mode.2709282737 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1410646203 ps |
| CPU time | 13.12 seconds |
| Started | Mar 05 01:36:23 PM PST 24 |
| Finished | Mar 05 01:36:37 PM PST 24 |
| Peak memory | 238468 kb |
| Host | smart-eec640a2-0c01-4b28-a4ef-3882c91e1899 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709282737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2709282737 |
| Directory | /workspace/2.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/2.spi_device_intercept.3875840236 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 32635390975 ps |
| CPU time | 11.71 seconds |
| Started | Mar 05 01:36:24 PM PST 24 |
| Finished | Mar 05 01:36:36 PM PST 24 |
| Peak memory | 233304 kb |
| Host | smart-e9ea94ea-04fb-4ddd-ac66-92fcb4e3125c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875840236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3875840236 |
| Directory | /workspace/2.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/2.spi_device_mailbox.4160381625 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 365207105 ps |
| CPU time | 2.7 seconds |
| Started | Mar 05 01:36:24 PM PST 24 |
| Finished | Mar 05 01:36:28 PM PST 24 |
| Peak memory | 232592 kb |
| Host | smart-d88dd23e-ac27-4606-a15f-f622ef50d50c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160381625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4160381625 |
| Directory | /workspace/2.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/2.spi_device_mem_parity.2635778103 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 65367766 ps |
| CPU time | 1.03 seconds |
| Started | Mar 05 01:36:15 PM PST 24 |
| Finished | Mar 05 01:36:16 PM PST 24 |
| Peak memory | 216572 kb |
| Host | smart-375c9dce-2c74-476f-b6d3-95f915782b17 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635778103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.spi_device_mem_parity.2635778103 |
| Directory | /workspace/2.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2570819791 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4000176505 ps |
| CPU time | 12.33 seconds |
| Started | Mar 05 01:36:24 PM PST 24 |
| Finished | Mar 05 01:36:38 PM PST 24 |
| Peak memory | 217980 kb |
| Host | smart-82effa50-8cb0-4337-a2ef-440fbc947c34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2570819791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap .2570819791 |
| Directory | /workspace/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/2.spi_device_pass_cmd_filtering.435422555 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1474627903 ps |
| CPU time | 4.38 seconds |
| Started | Mar 05 01:36:22 PM PST 24 |
| Finished | Mar 05 01:36:27 PM PST 24 |
| Peak memory | 217556 kb |
| Host | smart-3e41430d-db8e-4426-b0ef-a222dd61ac7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435422555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.435422555 |
| Directory | /workspace/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/2.spi_device_ram_cfg.3729293208 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 15355621 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:36:15 PM PST 24 |
| Finished | Mar 05 01:36:16 PM PST 24 |
| Peak memory | 216068 kb |
| Host | smart-6e982bc3-3b6c-4f81-8ab2-026b62d96e8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729293208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.3729293208 |
| Directory | /workspace/2.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/2.spi_device_read_buffer_direct.3197396709 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1630043450 ps |
| CPU time | 4.79 seconds |
| Started | Mar 05 01:36:24 PM PST 24 |
| Finished | Mar 05 01:36:30 PM PST 24 |
| Peak memory | 218324 kb |
| Host | smart-e8c94bbe-c39a-42fd-bf73-40b61ed6bff9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3197396709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire ct.3197396709 |
| Directory | /workspace/2.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/2.spi_device_sec_cm.2271208040 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 922769670 ps |
| CPU time | 1.38 seconds |
| Started | Mar 05 01:36:31 PM PST 24 |
| Finished | Mar 05 01:36:33 PM PST 24 |
| Peak memory | 235068 kb |
| Host | smart-27f312cb-e123-4029-ba8b-5fa9e1a854fd |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271208040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2271208040 |
| Directory | /workspace/2.spi_device_sec_cm/latest |
| Test location | /workspace/coverage/default/2.spi_device_tpm_all.1982897346 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 10568049427 ps |
| CPU time | 16.32 seconds |
| Started | Mar 05 01:36:22 PM PST 24 |
| Finished | Mar 05 01:36:39 PM PST 24 |
| Peak memory | 216308 kb |
| Host | smart-f6a203db-79b0-4549-804e-fb2d370e576c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982897346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1982897346 |
| Directory | /workspace/2.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1304720266 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5672549332 ps |
| CPU time | 19.6 seconds |
| Started | Mar 05 01:36:23 PM PST 24 |
| Finished | Mar 05 01:36:42 PM PST 24 |
| Peak memory | 216328 kb |
| Host | smart-c4081897-fc54-4906-b89b-7868d1b3bbd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304720266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1304720266 |
| Directory | /workspace/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/2.spi_device_tpm_rw.4261167408 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 469887550 ps |
| CPU time | 6.13 seconds |
| Started | Mar 05 01:36:39 PM PST 24 |
| Finished | Mar 05 01:36:45 PM PST 24 |
| Peak memory | 216404 kb |
| Host | smart-5720151e-89af-4f4b-a82f-21e58cd2e74f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261167408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4261167408 |
| Directory | /workspace/2.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/2.spi_device_tpm_sts_read.1070813681 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 48648411 ps |
| CPU time | 0.94 seconds |
| Started | Mar 05 01:36:23 PM PST 24 |
| Finished | Mar 05 01:36:25 PM PST 24 |
| Peak memory | 206392 kb |
| Host | smart-7f87c9dd-512f-4de1-abdf-9fd94e9d069e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070813681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1070813681 |
| Directory | /workspace/2.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/2.spi_device_upload.1492768281 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 929887512 ps |
| CPU time | 7.55 seconds |
| Started | Mar 05 01:36:21 PM PST 24 |
| Finished | Mar 05 01:36:28 PM PST 24 |
| Peak memory | 229308 kb |
| Host | smart-60d8475b-84a6-4a00-980d-3c201e52438a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492768281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1492768281 |
| Directory | /workspace/2.spi_device_upload/latest |
| Test location | /workspace/coverage/default/20.spi_device_alert_test.692050732 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 23200400 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:39:32 PM PST 24 |
| Finished | Mar 05 01:39:34 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-03bf95fd-1362-4c92-99b9-f21eb4c211bd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692050732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.692050732 |
| Directory | /workspace/20.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/20.spi_device_cfg_cmd.2422275511 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 764404544 ps |
| CPU time | 4.78 seconds |
| Started | Mar 05 01:39:36 PM PST 24 |
| Finished | Mar 05 01:39:41 PM PST 24 |
| Peak memory | 234152 kb |
| Host | smart-67e21f12-18b5-477d-ae6f-977e95e90666 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422275511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2422275511 |
| Directory | /workspace/20.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/20.spi_device_csb_read.3928975841 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 21318435 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:39:29 PM PST 24 |
| Finished | Mar 05 01:39:30 PM PST 24 |
| Peak memory | 204948 kb |
| Host | smart-e7237c94-3be4-4912-b9aa-f1e5955f972b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928975841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3928975841 |
| Directory | /workspace/20.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/20.spi_device_flash_all.4166744151 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 15495136281 ps |
| CPU time | 73.2 seconds |
| Started | Mar 05 01:39:30 PM PST 24 |
| Finished | Mar 05 01:40:44 PM PST 24 |
| Peak memory | 237988 kb |
| Host | smart-e4f0ca31-4d16-4f1c-a0db-01acb3ad80ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166744151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4166744151 |
| Directory | /workspace/20.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/20.spi_device_flash_and_tpm.1388506199 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 913969290048 ps |
| CPU time | 457.62 seconds |
| Started | Mar 05 01:39:32 PM PST 24 |
| Finished | Mar 05 01:47:11 PM PST 24 |
| Peak memory | 266160 kb |
| Host | smart-75bcd0a2-f96a-4ef3-8b49-4c7a278936e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1388506199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1388506199 |
| Directory | /workspace/20.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2449184690 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 6587812966 ps |
| CPU time | 86.18 seconds |
| Started | Mar 05 01:39:34 PM PST 24 |
| Finished | Mar 05 01:41:01 PM PST 24 |
| Peak memory | 260972 kb |
| Host | smart-96b32bd2-a5cb-48fd-9d0f-5dd2c05315e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2449184690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl e.2449184690 |
| Directory | /workspace/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/20.spi_device_flash_mode.3157858389 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 9886222135 ps |
| CPU time | 18.12 seconds |
| Started | Mar 05 01:39:30 PM PST 24 |
| Finished | Mar 05 01:39:49 PM PST 24 |
| Peak memory | 238100 kb |
| Host | smart-307b5411-5054-4032-bce8-148e54c2b46a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157858389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3157858389 |
| Directory | /workspace/20.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/20.spi_device_intercept.1090841832 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2505378978 ps |
| CPU time | 6.15 seconds |
| Started | Mar 05 01:39:30 PM PST 24 |
| Finished | Mar 05 01:39:37 PM PST 24 |
| Peak memory | 224460 kb |
| Host | smart-3adccb1d-71a8-42e4-be63-3fcfeb5eb2f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090841832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1090841832 |
| Directory | /workspace/20.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/20.spi_device_mailbox.2114678086 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 104549411547 ps |
| CPU time | 32.31 seconds |
| Started | Mar 05 01:39:32 PM PST 24 |
| Finished | Mar 05 01:40:05 PM PST 24 |
| Peak memory | 233636 kb |
| Host | smart-61ace126-cf69-40be-8762-d433c43565c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114678086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2114678086 |
| Directory | /workspace/20.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2967266641 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 30470225381 ps |
| CPU time | 20.63 seconds |
| Started | Mar 05 01:39:31 PM PST 24 |
| Finished | Mar 05 01:39:52 PM PST 24 |
| Peak memory | 224348 kb |
| Host | smart-b084f4c4-fd93-407b-8bcf-90d85a5e503d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967266641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa p.2967266641 |
| Directory | /workspace/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1882373163 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2677948649 ps |
| CPU time | 10.75 seconds |
| Started | Mar 05 01:39:32 PM PST 24 |
| Finished | Mar 05 01:39:44 PM PST 24 |
| Peak memory | 234880 kb |
| Host | smart-b41aec7d-1fa1-406a-8530-83134f8372b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882373163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1882373163 |
| Directory | /workspace/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/20.spi_device_read_buffer_direct.3671259106 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 7614020802 ps |
| CPU time | 6.78 seconds |
| Started | Mar 05 01:39:30 PM PST 24 |
| Finished | Mar 05 01:39:37 PM PST 24 |
| Peak memory | 222524 kb |
| Host | smart-b9ceb677-9160-44ea-b54d-5d1c01f1186e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3671259106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir ect.3671259106 |
| Directory | /workspace/20.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/20.spi_device_stress_all.2874160595 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 7167231104 ps |
| CPU time | 36.46 seconds |
| Started | Mar 05 01:39:34 PM PST 24 |
| Finished | Mar 05 01:40:10 PM PST 24 |
| Peak memory | 249232 kb |
| Host | smart-c6680ea6-b7b2-4929-baf4-e7260129aaae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874160595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre ss_all.2874160595 |
| Directory | /workspace/20.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/20.spi_device_tpm_all.2765243916 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2808022761 ps |
| CPU time | 17 seconds |
| Started | Mar 05 01:39:23 PM PST 24 |
| Finished | Mar 05 01:39:43 PM PST 24 |
| Peak memory | 216268 kb |
| Host | smart-361a1950-b3c2-456a-aac8-a697927b1ec1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765243916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2765243916 |
| Directory | /workspace/20.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2314790131 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 32810069251 ps |
| CPU time | 24.51 seconds |
| Started | Mar 05 01:39:26 PM PST 24 |
| Finished | Mar 05 01:39:52 PM PST 24 |
| Peak memory | 216272 kb |
| Host | smart-2722932f-d7da-488e-9221-880288f5aeae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314790131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2314790131 |
| Directory | /workspace/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/20.spi_device_tpm_rw.147257733 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 878810384 ps |
| CPU time | 13.82 seconds |
| Started | Mar 05 01:39:30 PM PST 24 |
| Finished | Mar 05 01:39:44 PM PST 24 |
| Peak memory | 216288 kb |
| Host | smart-7edd6e4d-634f-4c94-ad0b-de2afc94dc2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147257733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.147257733 |
| Directory | /workspace/20.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/20.spi_device_tpm_sts_read.3403492244 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 56729297 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:39:30 PM PST 24 |
| Finished | Mar 05 01:39:31 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-081eff25-7915-47af-9e56-39e64b41a184 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403492244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3403492244 |
| Directory | /workspace/20.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/20.spi_device_upload.1143617579 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 9956655778 ps |
| CPU time | 29.87 seconds |
| Started | Mar 05 01:39:32 PM PST 24 |
| Finished | Mar 05 01:40:03 PM PST 24 |
| Peak memory | 233796 kb |
| Host | smart-4a46e8df-ddb4-40af-8ccf-48629698dc31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143617579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1143617579 |
| Directory | /workspace/20.spi_device_upload/latest |
| Test location | /workspace/coverage/default/21.spi_device_alert_test.3890529694 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 18679009 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:39:49 PM PST 24 |
| Finished | Mar 05 01:39:50 PM PST 24 |
| Peak memory | 205184 kb |
| Host | smart-b7b5071e-6344-4ace-9c41-f7391f355138 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890529694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test. 3890529694 |
| Directory | /workspace/21.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/21.spi_device_cfg_cmd.2903280968 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 513406701 ps |
| CPU time | 3.37 seconds |
| Started | Mar 05 01:39:43 PM PST 24 |
| Finished | Mar 05 01:39:46 PM PST 24 |
| Peak memory | 217524 kb |
| Host | smart-9cda4282-c999-4db0-82fc-eef7f76b9ed2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903280968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2903280968 |
| Directory | /workspace/21.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/21.spi_device_csb_read.3247979082 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 18412903 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:39:37 PM PST 24 |
| Finished | Mar 05 01:39:38 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-fa0c7077-4aa7-45a0-9264-ee4f6190f49f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247979082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3247979082 |
| Directory | /workspace/21.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/21.spi_device_flash_all.1835882750 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 11839834297 ps |
| CPU time | 60.9 seconds |
| Started | Mar 05 01:39:43 PM PST 24 |
| Finished | Mar 05 01:40:45 PM PST 24 |
| Peak memory | 240832 kb |
| Host | smart-8045fac3-d489-4c3f-8dd3-13a38ff43cc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835882750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1835882750 |
| Directory | /workspace/21.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/21.spi_device_flash_and_tpm.3936102367 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 59302592609 ps |
| CPU time | 251.49 seconds |
| Started | Mar 05 01:39:43 PM PST 24 |
| Finished | Mar 05 01:43:55 PM PST 24 |
| Peak memory | 254172 kb |
| Host | smart-96b56980-359c-4d89-b19c-04c9f869fee7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936102367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3936102367 |
| Directory | /workspace/21.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2817820817 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 22413272374 ps |
| CPU time | 111.69 seconds |
| Started | Mar 05 01:39:38 PM PST 24 |
| Finished | Mar 05 01:41:30 PM PST 24 |
| Peak memory | 256160 kb |
| Host | smart-9cbe4c24-e023-4bf1-86f1-447a8cf6534b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817820817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl e.2817820817 |
| Directory | /workspace/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/21.spi_device_flash_mode.3542219771 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5044188381 ps |
| CPU time | 18.16 seconds |
| Started | Mar 05 01:39:40 PM PST 24 |
| Finished | Mar 05 01:39:59 PM PST 24 |
| Peak memory | 248656 kb |
| Host | smart-ee8b62f9-2051-4c66-8f61-c30a8eca43ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542219771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3542219771 |
| Directory | /workspace/21.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/21.spi_device_intercept.1399451363 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 448720617 ps |
| CPU time | 4.68 seconds |
| Started | Mar 05 01:39:46 PM PST 24 |
| Finished | Mar 05 01:39:51 PM PST 24 |
| Peak memory | 224328 kb |
| Host | smart-da806962-873e-4ebd-88fd-850ce20a8233 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399451363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1399451363 |
| Directory | /workspace/21.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/21.spi_device_mailbox.2218310358 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 79921458499 ps |
| CPU time | 44.48 seconds |
| Started | Mar 05 01:39:42 PM PST 24 |
| Finished | Mar 05 01:40:26 PM PST 24 |
| Peak memory | 237256 kb |
| Host | smart-9d0b8e05-efd9-48d2-a242-f3fcde8591f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2218310358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2218310358 |
| Directory | /workspace/21.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.888254057 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1185420003 ps |
| CPU time | 3.22 seconds |
| Started | Mar 05 01:39:46 PM PST 24 |
| Finished | Mar 05 01:39:50 PM PST 24 |
| Peak memory | 232880 kb |
| Host | smart-1564d037-e834-4bea-8ac9-857f822f97b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888254057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap .888254057 |
| Directory | /workspace/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/21.spi_device_pass_cmd_filtering.782922785 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1378311383 ps |
| CPU time | 5.24 seconds |
| Started | Mar 05 01:39:41 PM PST 24 |
| Finished | Mar 05 01:39:47 PM PST 24 |
| Peak memory | 218504 kb |
| Host | smart-d962c756-7e7b-4568-b3a9-7e3a845e46fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782922785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.782922785 |
| Directory | /workspace/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/21.spi_device_read_buffer_direct.4114698008 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6499292568 ps |
| CPU time | 6.89 seconds |
| Started | Mar 05 01:39:44 PM PST 24 |
| Finished | Mar 05 01:39:51 PM PST 24 |
| Peak memory | 222036 kb |
| Host | smart-30a9f46d-800b-4837-9c5d-548e04e9990a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4114698008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir ect.4114698008 |
| Directory | /workspace/21.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/21.spi_device_stress_all.686017960 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 96929222 ps |
| CPU time | 0.98 seconds |
| Started | Mar 05 01:39:42 PM PST 24 |
| Finished | Mar 05 01:39:44 PM PST 24 |
| Peak memory | 205168 kb |
| Host | smart-166fd8aa-6ff5-4829-a2c3-c0c9fd0710e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686017960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres s_all.686017960 |
| Directory | /workspace/21.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/21.spi_device_tpm_all.87656698 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 16214767830 ps |
| CPU time | 46.41 seconds |
| Started | Mar 05 01:39:43 PM PST 24 |
| Finished | Mar 05 01:40:30 PM PST 24 |
| Peak memory | 216280 kb |
| Host | smart-47b44cee-fa39-404e-8c2e-2ceb4365eb13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87656698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.87656698 |
| Directory | /workspace/21.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1802385973 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2461563779 ps |
| CPU time | 7.74 seconds |
| Started | Mar 05 01:39:33 PM PST 24 |
| Finished | Mar 05 01:39:41 PM PST 24 |
| Peak memory | 216284 kb |
| Host | smart-7a7ffde8-7a2a-4a6e-a960-3ed48173ea84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802385973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1802385973 |
| Directory | /workspace/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/21.spi_device_tpm_rw.2789058987 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 159187532 ps |
| CPU time | 2.14 seconds |
| Started | Mar 05 01:39:38 PM PST 24 |
| Finished | Mar 05 01:39:41 PM PST 24 |
| Peak memory | 216476 kb |
| Host | smart-eb2ef807-26b5-4ff6-8ccd-a6f861a292bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789058987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2789058987 |
| Directory | /workspace/21.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/21.spi_device_tpm_sts_read.1303114093 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 76033626 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 01:39:40 PM PST 24 |
| Finished | Mar 05 01:39:41 PM PST 24 |
| Peak memory | 205324 kb |
| Host | smart-e1fb4ab6-008b-4cb3-bcb4-9dfc66fc9b6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303114093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1303114093 |
| Directory | /workspace/21.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/21.spi_device_upload.328708435 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1328854551 ps |
| CPU time | 2.83 seconds |
| Started | Mar 05 01:39:42 PM PST 24 |
| Finished | Mar 05 01:39:45 PM PST 24 |
| Peak memory | 218352 kb |
| Host | smart-8db56658-84bd-4fee-b200-6e896c6e6851 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328708435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.328708435 |
| Directory | /workspace/21.spi_device_upload/latest |
| Test location | /workspace/coverage/default/22.spi_device_alert_test.1671915241 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 20774842 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:40:03 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-d48ad1bc-6375-443f-9f5a-4ea0ec4f9503 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671915241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test. 1671915241 |
| Directory | /workspace/22.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/22.spi_device_cfg_cmd.4164210557 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 1749396016 ps |
| CPU time | 5.12 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:40:08 PM PST 24 |
| Peak memory | 236772 kb |
| Host | smart-d8f21104-e78c-4a44-a934-bc20e2d9e6a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164210557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4164210557 |
| Directory | /workspace/22.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/22.spi_device_csb_read.3498230589 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 22538599 ps |
| CPU time | 0.82 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:40:04 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-da49a496-bdad-4b79-a867-3729fb3758fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498230589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3498230589 |
| Directory | /workspace/22.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.305479718 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 74081991089 ps |
| CPU time | 237.03 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:44:00 PM PST 24 |
| Peak memory | 249280 kb |
| Host | smart-7111b9e8-f9e9-40ef-89a3-26301df50de8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=305479718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle .305479718 |
| Directory | /workspace/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/22.spi_device_flash_mode.1515052396 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 11410558234 ps |
| CPU time | 24.28 seconds |
| Started | Mar 05 01:39:50 PM PST 24 |
| Finished | Mar 05 01:40:15 PM PST 24 |
| Peak memory | 238616 kb |
| Host | smart-702526f4-4bb3-4972-b8d2-eaed80ac4bbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515052396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1515052396 |
| Directory | /workspace/22.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/22.spi_device_intercept.3748703686 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 8959828960 ps |
| CPU time | 14.71 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:40:17 PM PST 24 |
| Peak memory | 233204 kb |
| Host | smart-54dfcc7b-d949-487e-952c-bd2dd1d5a6ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748703686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3748703686 |
| Directory | /workspace/22.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/22.spi_device_mailbox.2543119303 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 7829008022 ps |
| CPU time | 22.76 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:40:25 PM PST 24 |
| Peak memory | 232548 kb |
| Host | smart-b12355fa-d562-4903-bfb6-4684f50644f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543119303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2543119303 |
| Directory | /workspace/22.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.839046382 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 704281182 ps |
| CPU time | 4.3 seconds |
| Started | Mar 05 01:39:54 PM PST 24 |
| Finished | Mar 05 01:40:01 PM PST 24 |
| Peak memory | 217280 kb |
| Host | smart-9ee0f01d-8c70-4097-80a0-7e99246e9b82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839046382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap .839046382 |
| Directory | /workspace/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2530164054 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 946157714 ps |
| CPU time | 6.99 seconds |
| Started | Mar 05 01:39:55 PM PST 24 |
| Finished | Mar 05 01:40:05 PM PST 24 |
| Peak memory | 232780 kb |
| Host | smart-69e5957e-7b20-485f-99fe-b6b08054e30b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530164054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2530164054 |
| Directory | /workspace/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/22.spi_device_read_buffer_direct.1404155880 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 774136328 ps |
| CPU time | 3.76 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:40:06 PM PST 24 |
| Peak memory | 218264 kb |
| Host | smart-bf65a477-3e52-49f5-bf2b-414a0bd2cb0d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1404155880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir ect.1404155880 |
| Directory | /workspace/22.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/22.spi_device_stress_all.2587101506 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 5940807497 ps |
| CPU time | 31.02 seconds |
| Started | Mar 05 01:39:55 PM PST 24 |
| Finished | Mar 05 01:40:30 PM PST 24 |
| Peak memory | 239272 kb |
| Host | smart-682a0f42-2e8e-4911-8b72-b1236b529680 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587101506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre ss_all.2587101506 |
| Directory | /workspace/22.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/22.spi_device_tpm_all.1629219462 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1900352619 ps |
| CPU time | 17.21 seconds |
| Started | Mar 05 01:39:58 PM PST 24 |
| Finished | Mar 05 01:40:21 PM PST 24 |
| Peak memory | 216172 kb |
| Host | smart-e37a0c82-3a2b-4d30-a340-78e2e236524f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629219462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1629219462 |
| Directory | /workspace/22.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3776827564 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 4103035250 ps |
| CPU time | 7.31 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:40:09 PM PST 24 |
| Peak memory | 216316 kb |
| Host | smart-1b5375e6-01fd-4cfd-864c-68a02f50bf86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776827564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3776827564 |
| Directory | /workspace/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/22.spi_device_tpm_rw.3083964130 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 305852299 ps |
| CPU time | 2.82 seconds |
| Started | Mar 05 01:39:56 PM PST 24 |
| Finished | Mar 05 01:40:01 PM PST 24 |
| Peak memory | 216208 kb |
| Host | smart-35e057d9-5022-41fe-9d76-fde38032332a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083964130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3083964130 |
| Directory | /workspace/22.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/22.spi_device_tpm_sts_read.2665370664 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 83536514 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:39:56 PM PST 24 |
| Finished | Mar 05 01:40:02 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-a9032ff7-c29b-44cc-bb12-c84d280dda6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665370664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2665370664 |
| Directory | /workspace/22.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/22.spi_device_upload.3167727243 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1111052545 ps |
| CPU time | 3.74 seconds |
| Started | Mar 05 01:39:57 PM PST 24 |
| Finished | Mar 05 01:40:07 PM PST 24 |
| Peak memory | 235444 kb |
| Host | smart-1de83d3f-6056-40d1-8966-68bee1a89ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3167727243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3167727243 |
| Directory | /workspace/22.spi_device_upload/latest |
| Test location | /workspace/coverage/default/23.spi_device_alert_test.3391960661 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 59476866 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:40:04 PM PST 24 |
| Finished | Mar 05 01:40:07 PM PST 24 |
| Peak memory | 204304 kb |
| Host | smart-f3c97be6-e763-4f42-9f1c-be29d409e5c9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391960661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test. 3391960661 |
| Directory | /workspace/23.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/23.spi_device_cfg_cmd.1674126088 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4366978502 ps |
| CPU time | 5.22 seconds |
| Started | Mar 05 01:40:02 PM PST 24 |
| Finished | Mar 05 01:40:10 PM PST 24 |
| Peak memory | 236688 kb |
| Host | smart-e704da34-c104-4772-984d-9fe68bbb2e5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674126088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1674126088 |
| Directory | /workspace/23.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/23.spi_device_csb_read.3638212381 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 14768223 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:40:01 PM PST 24 |
| Finished | Mar 05 01:40:06 PM PST 24 |
| Peak memory | 206152 kb |
| Host | smart-78fbd1bd-73fe-487c-b5e2-df5513fc9470 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638212381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3638212381 |
| Directory | /workspace/23.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/23.spi_device_flash_all.3302672911 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 9655385598 ps |
| CPU time | 55.77 seconds |
| Started | Mar 05 01:40:04 PM PST 24 |
| Finished | Mar 05 01:41:02 PM PST 24 |
| Peak memory | 240828 kb |
| Host | smart-4b5ca7a5-19c1-4e94-8095-9d68387ebf17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302672911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3302672911 |
| Directory | /workspace/23.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/23.spi_device_flash_and_tpm.3458899437 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 52474551715 ps |
| CPU time | 360.35 seconds |
| Started | Mar 05 01:40:07 PM PST 24 |
| Finished | Mar 05 01:46:07 PM PST 24 |
| Peak memory | 248604 kb |
| Host | smart-fb4a56fd-751d-4814-bbcf-40b3b563b2fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458899437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3458899437 |
| Directory | /workspace/23.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3986138369 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 110446093049 ps |
| CPU time | 418.37 seconds |
| Started | Mar 05 01:40:03 PM PST 24 |
| Finished | Mar 05 01:47:04 PM PST 24 |
| Peak memory | 255896 kb |
| Host | smart-17e336f1-8890-49f8-913f-049fb8bffac3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986138369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl e.3986138369 |
| Directory | /workspace/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/23.spi_device_flash_mode.2887285771 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1646867216 ps |
| CPU time | 13.9 seconds |
| Started | Mar 05 01:40:05 PM PST 24 |
| Finished | Mar 05 01:40:20 PM PST 24 |
| Peak memory | 246856 kb |
| Host | smart-dcdfc6f3-4336-45ca-82f5-9e8346f3391b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2887285771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2887285771 |
| Directory | /workspace/23.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/23.spi_device_intercept.3919763514 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 8874819059 ps |
| CPU time | 9.74 seconds |
| Started | Mar 05 01:40:01 PM PST 24 |
| Finished | Mar 05 01:40:15 PM PST 24 |
| Peak memory | 220772 kb |
| Host | smart-f2a47d0a-168f-4ec8-84a8-8104d7f7f7f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3919763514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3919763514 |
| Directory | /workspace/23.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/23.spi_device_mailbox.253718742 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 32729041086 ps |
| CPU time | 32.85 seconds |
| Started | Mar 05 01:40:00 PM PST 24 |
| Finished | Mar 05 01:40:37 PM PST 24 |
| Peak memory | 240584 kb |
| Host | smart-27f1ee6a-f149-44fe-b0df-b8f138a19fc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253718742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.253718742 |
| Directory | /workspace/23.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.722477904 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 5641461038 ps |
| CPU time | 16.67 seconds |
| Started | Mar 05 01:40:00 PM PST 24 |
| Finished | Mar 05 01:40:20 PM PST 24 |
| Peak memory | 218220 kb |
| Host | smart-6632da1d-33c7-4069-8bc7-1036ccfe46ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722477904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap .722477904 |
| Directory | /workspace/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2198576357 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 7646945362 ps |
| CPU time | 8.26 seconds |
| Started | Mar 05 01:40:02 PM PST 24 |
| Finished | Mar 05 01:40:13 PM PST 24 |
| Peak memory | 229112 kb |
| Host | smart-ce5b4343-9259-468f-a4c9-8d9e089d5903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2198576357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2198576357 |
| Directory | /workspace/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/23.spi_device_read_buffer_direct.3156216512 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 189504052 ps |
| CPU time | 3.41 seconds |
| Started | Mar 05 01:40:05 PM PST 24 |
| Finished | Mar 05 01:40:10 PM PST 24 |
| Peak memory | 220484 kb |
| Host | smart-969c5438-a383-4f39-b686-7d39b59d45b2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3156216512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir ect.3156216512 |
| Directory | /workspace/23.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/23.spi_device_stress_all.1459538904 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 135853021 ps |
| CPU time | 0.9 seconds |
| Started | Mar 05 01:40:03 PM PST 24 |
| Finished | Mar 05 01:40:07 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-5094d38d-6162-435e-9cc6-3492c65d74c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459538904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre ss_all.1459538904 |
| Directory | /workspace/23.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/23.spi_device_tpm_all.434318194 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 7437583873 ps |
| CPU time | 25.78 seconds |
| Started | Mar 05 01:40:00 PM PST 24 |
| Finished | Mar 05 01:40:30 PM PST 24 |
| Peak memory | 216332 kb |
| Host | smart-d0bc3cd6-2c2a-4ec9-b9fe-2529d7afc29c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=434318194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.434318194 |
| Directory | /workspace/23.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2898023729 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2576511420 ps |
| CPU time | 5.67 seconds |
| Started | Mar 05 01:40:02 PM PST 24 |
| Finished | Mar 05 01:40:10 PM PST 24 |
| Peak memory | 216184 kb |
| Host | smart-f6621ff7-febd-49a6-8501-440d15502fdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898023729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2898023729 |
| Directory | /workspace/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/23.spi_device_tpm_rw.3205874818 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 131486935 ps |
| CPU time | 2.16 seconds |
| Started | Mar 05 01:40:00 PM PST 24 |
| Finished | Mar 05 01:40:07 PM PST 24 |
| Peak memory | 216292 kb |
| Host | smart-66c138e5-434f-410f-a462-d36be7325713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205874818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3205874818 |
| Directory | /workspace/23.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/23.spi_device_tpm_sts_read.3286104067 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 81172031 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:39:58 PM PST 24 |
| Finished | Mar 05 01:40:04 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-9e667820-8f9a-4eb7-8adf-6e864e6d774e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286104067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3286104067 |
| Directory | /workspace/23.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/23.spi_device_upload.1732272494 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 8612215358 ps |
| CPU time | 8.67 seconds |
| Started | Mar 05 01:40:02 PM PST 24 |
| Finished | Mar 05 01:40:14 PM PST 24 |
| Peak memory | 236300 kb |
| Host | smart-58f78a88-8800-4cf7-8b5d-d86bed0a8eda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732272494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1732272494 |
| Directory | /workspace/23.spi_device_upload/latest |
| Test location | /workspace/coverage/default/24.spi_device_alert_test.1314473977 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 12436841 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 01:40:12 PM PST 24 |
| Finished | Mar 05 01:40:13 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-ec240072-2190-4910-a572-83f1e153d73b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314473977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test. 1314473977 |
| Directory | /workspace/24.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/24.spi_device_cfg_cmd.3100221194 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 486532560 ps |
| CPU time | 2.45 seconds |
| Started | Mar 05 01:40:13 PM PST 24 |
| Finished | Mar 05 01:40:16 PM PST 24 |
| Peak memory | 224368 kb |
| Host | smart-ed6f04ed-122e-4aa6-b947-f74a7fbf567a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100221194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3100221194 |
| Directory | /workspace/24.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/24.spi_device_csb_read.1634377995 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 73372495 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:40:03 PM PST 24 |
| Finished | Mar 05 01:40:06 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-6055b812-96b3-4dc7-93e7-eb52f5ddd0e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634377995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1634377995 |
| Directory | /workspace/24.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/24.spi_device_flash_all.3935415270 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 120296138992 ps |
| CPU time | 110.8 seconds |
| Started | Mar 05 01:40:13 PM PST 24 |
| Finished | Mar 05 01:42:04 PM PST 24 |
| Peak memory | 249032 kb |
| Host | smart-8a728dc3-ef9a-4103-b2df-6d77b2c29e87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935415270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3935415270 |
| Directory | /workspace/24.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/24.spi_device_flash_and_tpm.3355930603 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 144230111928 ps |
| CPU time | 240.29 seconds |
| Started | Mar 05 01:40:15 PM PST 24 |
| Finished | Mar 05 01:44:16 PM PST 24 |
| Peak memory | 253892 kb |
| Host | smart-b0948d91-3513-46c0-b2de-cd784f313dbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355930603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3355930603 |
| Directory | /workspace/24.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/24.spi_device_flash_mode.4003086205 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 12129527835 ps |
| CPU time | 30.15 seconds |
| Started | Mar 05 01:40:10 PM PST 24 |
| Finished | Mar 05 01:40:41 PM PST 24 |
| Peak memory | 239492 kb |
| Host | smart-439a635a-fd64-4ca9-9a7d-c351569b17ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003086205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4003086205 |
| Directory | /workspace/24.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/24.spi_device_intercept.3030932629 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 13462168700 ps |
| CPU time | 7.24 seconds |
| Started | Mar 05 01:40:07 PM PST 24 |
| Finished | Mar 05 01:40:15 PM PST 24 |
| Peak memory | 218128 kb |
| Host | smart-fc9a29b3-40ed-4fca-8eaf-5780c92950e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3030932629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3030932629 |
| Directory | /workspace/24.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/24.spi_device_mailbox.2913487015 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4147530031 ps |
| CPU time | 16.72 seconds |
| Started | Mar 05 01:40:09 PM PST 24 |
| Finished | Mar 05 01:40:27 PM PST 24 |
| Peak memory | 233228 kb |
| Host | smart-8a7801b2-5d44-458c-96c1-f2751a8d3eb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913487015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2913487015 |
| Directory | /workspace/24.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1286464232 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 809261579 ps |
| CPU time | 3.98 seconds |
| Started | Mar 05 01:40:10 PM PST 24 |
| Finished | Mar 05 01:40:14 PM PST 24 |
| Peak memory | 233508 kb |
| Host | smart-3b170e2a-39be-468c-9b02-c729192b915f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286464232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa p.1286464232 |
| Directory | /workspace/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/24.spi_device_pass_cmd_filtering.829393773 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1434075561 ps |
| CPU time | 4.79 seconds |
| Started | Mar 05 01:40:06 PM PST 24 |
| Finished | Mar 05 01:40:12 PM PST 24 |
| Peak memory | 224320 kb |
| Host | smart-bffe79d3-77db-470c-aaea-fcc4f3333265 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829393773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.829393773 |
| Directory | /workspace/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/24.spi_device_read_buffer_direct.1552051894 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1182082906 ps |
| CPU time | 5.91 seconds |
| Started | Mar 05 01:40:13 PM PST 24 |
| Finished | Mar 05 01:40:19 PM PST 24 |
| Peak memory | 218468 kb |
| Host | smart-abc76a8d-bc3e-415a-8c25-0f1e38d2d460 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1552051894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir ect.1552051894 |
| Directory | /workspace/24.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/24.spi_device_stress_all.3933350898 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 130299382024 ps |
| CPU time | 552.56 seconds |
| Started | Mar 05 01:40:15 PM PST 24 |
| Finished | Mar 05 01:49:28 PM PST 24 |
| Peak memory | 257328 kb |
| Host | smart-a4ae4df9-f240-456d-a479-4aaf01577fef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933350898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre ss_all.3933350898 |
| Directory | /workspace/24.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/24.spi_device_tpm_all.517081309 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3468159924 ps |
| CPU time | 25.81 seconds |
| Started | Mar 05 01:40:06 PM PST 24 |
| Finished | Mar 05 01:40:32 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-959946ea-c6e0-41a5-af1e-2aef192d8a75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517081309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.517081309 |
| Directory | /workspace/24.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.253238975 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 36316593435 ps |
| CPU time | 8.7 seconds |
| Started | Mar 05 01:40:09 PM PST 24 |
| Finished | Mar 05 01:40:19 PM PST 24 |
| Peak memory | 216304 kb |
| Host | smart-f3db2dec-7451-4dcb-ba96-9bd30d111894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253238975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.253238975 |
| Directory | /workspace/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/24.spi_device_tpm_rw.2243484173 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 36780988 ps |
| CPU time | 1.14 seconds |
| Started | Mar 05 01:40:04 PM PST 24 |
| Finished | Mar 05 01:40:07 PM PST 24 |
| Peak memory | 216076 kb |
| Host | smart-65db5dc0-6100-48dc-8e5d-61917add569a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243484173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2243484173 |
| Directory | /workspace/24.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/24.spi_device_tpm_sts_read.2520604596 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 47353494 ps |
| CPU time | 0.98 seconds |
| Started | Mar 05 01:40:03 PM PST 24 |
| Finished | Mar 05 01:40:07 PM PST 24 |
| Peak memory | 206388 kb |
| Host | smart-2e3e9574-efce-46b5-a790-b5c9236b65c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520604596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2520604596 |
| Directory | /workspace/24.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/24.spi_device_upload.1238266144 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 396872828 ps |
| CPU time | 4.74 seconds |
| Started | Mar 05 01:40:13 PM PST 24 |
| Finished | Mar 05 01:40:18 PM PST 24 |
| Peak memory | 216348 kb |
| Host | smart-042e20f5-1468-4946-b8d8-d93f46fe0979 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238266144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1238266144 |
| Directory | /workspace/24.spi_device_upload/latest |
| Test location | /workspace/coverage/default/25.spi_device_alert_test.4217780476 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 11622198 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:40:21 PM PST 24 |
| Finished | Mar 05 01:40:22 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-594b41b9-9f03-4f0e-8ba9-b23350a271e1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217780476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test. 4217780476 |
| Directory | /workspace/25.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/25.spi_device_cfg_cmd.153818470 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3965807452 ps |
| CPU time | 12.75 seconds |
| Started | Mar 05 01:40:16 PM PST 24 |
| Finished | Mar 05 01:40:28 PM PST 24 |
| Peak memory | 232944 kb |
| Host | smart-cee62c10-78dd-4f78-ab02-15e4fabed2b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153818470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.153818470 |
| Directory | /workspace/25.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/25.spi_device_csb_read.2281455702 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 24827346 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:40:16 PM PST 24 |
| Finished | Mar 05 01:40:17 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-39f12a60-62e3-4bb4-8c47-ddf51098e2c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281455702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2281455702 |
| Directory | /workspace/25.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/25.spi_device_flash_all.1385445850 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 9572606568 ps |
| CPU time | 24.62 seconds |
| Started | Mar 05 01:40:19 PM PST 24 |
| Finished | Mar 05 01:40:44 PM PST 24 |
| Peak memory | 221052 kb |
| Host | smart-28a1251f-ab01-4c65-b495-9a1d269fd0d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385445850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1385445850 |
| Directory | /workspace/25.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/25.spi_device_flash_and_tpm.1175112688 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 151541037399 ps |
| CPU time | 261.53 seconds |
| Started | Mar 05 01:40:22 PM PST 24 |
| Finished | Mar 05 01:44:43 PM PST 24 |
| Peak memory | 254320 kb |
| Host | smart-2d83aec5-2661-48d4-a8b0-b2b3f6b14e85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1175112688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1175112688 |
| Directory | /workspace/25.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2913417150 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 15941981750 ps |
| CPU time | 92.87 seconds |
| Started | Mar 05 01:40:18 PM PST 24 |
| Finished | Mar 05 01:41:51 PM PST 24 |
| Peak memory | 249156 kb |
| Host | smart-e98994c2-1c6e-4081-b0f6-33159c85da61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913417150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl e.2913417150 |
| Directory | /workspace/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/25.spi_device_flash_mode.4276838029 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2133604914 ps |
| CPU time | 17.94 seconds |
| Started | Mar 05 01:40:19 PM PST 24 |
| Finished | Mar 05 01:40:38 PM PST 24 |
| Peak memory | 237548 kb |
| Host | smart-bbf50031-ad1b-49d3-93a6-2495a0e9f8c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276838029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4276838029 |
| Directory | /workspace/25.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/25.spi_device_intercept.2719099968 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 206409382 ps |
| CPU time | 2.5 seconds |
| Started | Mar 05 01:40:10 PM PST 24 |
| Finished | Mar 05 01:40:13 PM PST 24 |
| Peak memory | 232584 kb |
| Host | smart-99acc115-a797-489a-aa48-87c11b79033c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719099968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2719099968 |
| Directory | /workspace/25.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/25.spi_device_mailbox.1865447430 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 852548395 ps |
| CPU time | 8.45 seconds |
| Started | Mar 05 01:40:15 PM PST 24 |
| Finished | Mar 05 01:40:24 PM PST 24 |
| Peak memory | 224280 kb |
| Host | smart-62a6533a-9710-4510-8f96-5924e6ec060d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865447430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1865447430 |
| Directory | /workspace/25.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1491371779 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 603335683 ps |
| CPU time | 5.06 seconds |
| Started | Mar 05 01:40:10 PM PST 24 |
| Finished | Mar 05 01:40:15 PM PST 24 |
| Peak memory | 217300 kb |
| Host | smart-1a6c5067-3e77-484f-902d-ad88df590d96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491371779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa p.1491371779 |
| Directory | /workspace/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/25.spi_device_pass_cmd_filtering.590192498 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 12326716860 ps |
| CPU time | 29.11 seconds |
| Started | Mar 05 01:40:14 PM PST 24 |
| Finished | Mar 05 01:40:43 PM PST 24 |
| Peak memory | 235152 kb |
| Host | smart-6253e724-6869-4487-adf4-781373f7b44c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=590192498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.590192498 |
| Directory | /workspace/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/25.spi_device_read_buffer_direct.1412031291 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 460860091 ps |
| CPU time | 3.82 seconds |
| Started | Mar 05 01:40:19 PM PST 24 |
| Finished | Mar 05 01:40:23 PM PST 24 |
| Peak memory | 222616 kb |
| Host | smart-66f0ddb5-698f-4cf7-936c-eedb27f0860a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1412031291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir ect.1412031291 |
| Directory | /workspace/25.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/25.spi_device_tpm_all.3957386543 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 20133430267 ps |
| CPU time | 29.19 seconds |
| Started | Mar 05 01:40:15 PM PST 24 |
| Finished | Mar 05 01:40:44 PM PST 24 |
| Peak memory | 219600 kb |
| Host | smart-4cabe92b-1023-4775-a677-b26ad484fdb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3957386543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3957386543 |
| Directory | /workspace/25.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1464500247 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2155186391 ps |
| CPU time | 5.38 seconds |
| Started | Mar 05 01:40:11 PM PST 24 |
| Finished | Mar 05 01:40:17 PM PST 24 |
| Peak memory | 216300 kb |
| Host | smart-3e371da3-981d-400c-a0a3-725b09100af9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464500247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1464500247 |
| Directory | /workspace/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/25.spi_device_tpm_rw.1627134979 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 133839487 ps |
| CPU time | 2.35 seconds |
| Started | Mar 05 01:40:10 PM PST 24 |
| Finished | Mar 05 01:40:13 PM PST 24 |
| Peak memory | 216220 kb |
| Host | smart-1bbb256f-1a13-4232-a3e4-7efc0e233363 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627134979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1627134979 |
| Directory | /workspace/25.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/25.spi_device_tpm_sts_read.2758576640 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 123974677 ps |
| CPU time | 0.93 seconds |
| Started | Mar 05 01:40:15 PM PST 24 |
| Finished | Mar 05 01:40:16 PM PST 24 |
| Peak memory | 206360 kb |
| Host | smart-08178c6c-1e36-4b8b-8bac-355de7e20959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758576640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2758576640 |
| Directory | /workspace/25.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/25.spi_device_upload.634832018 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 10718322919 ps |
| CPU time | 14.23 seconds |
| Started | Mar 05 01:40:15 PM PST 24 |
| Finished | Mar 05 01:40:30 PM PST 24 |
| Peak memory | 219528 kb |
| Host | smart-69d3b7ce-0489-4947-91ed-50b026f73a60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=634832018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.634832018 |
| Directory | /workspace/25.spi_device_upload/latest |
| Test location | /workspace/coverage/default/26.spi_device_alert_test.1054155560 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 23018414 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:40:33 PM PST 24 |
| Finished | Mar 05 01:40:34 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-3ab50919-9aa3-4dba-b962-17d078e3bc6f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054155560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test. 1054155560 |
| Directory | /workspace/26.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/26.spi_device_cfg_cmd.3940359470 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 319248750 ps |
| CPU time | 3.2 seconds |
| Started | Mar 05 01:40:37 PM PST 24 |
| Finished | Mar 05 01:40:40 PM PST 24 |
| Peak memory | 224324 kb |
| Host | smart-0c25fb06-eae0-41f6-a044-61dce15d82e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940359470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3940359470 |
| Directory | /workspace/26.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/26.spi_device_csb_read.2856985333 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 28214740 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:40:18 PM PST 24 |
| Finished | Mar 05 01:40:19 PM PST 24 |
| Peak memory | 206288 kb |
| Host | smart-b9762a58-89a5-4ba7-a15a-625d14fcbdaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856985333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2856985333 |
| Directory | /workspace/26.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/26.spi_device_flash_all.4136047442 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 65278429400 ps |
| CPU time | 80.98 seconds |
| Started | Mar 05 01:40:31 PM PST 24 |
| Finished | Mar 05 01:41:52 PM PST 24 |
| Peak memory | 240716 kb |
| Host | smart-aaf6b48b-73eb-4e91-8394-17a6921a367d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136047442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4136047442 |
| Directory | /workspace/26.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/26.spi_device_flash_and_tpm.33905346 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 84231813491 ps |
| CPU time | 346.05 seconds |
| Started | Mar 05 01:40:35 PM PST 24 |
| Finished | Mar 05 01:46:21 PM PST 24 |
| Peak memory | 262236 kb |
| Host | smart-ad0bc840-8860-4b7f-90df-131529af9165 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33905346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.33905346 |
| Directory | /workspace/26.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/26.spi_device_flash_mode.4157515426 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 302059525 ps |
| CPU time | 7.03 seconds |
| Started | Mar 05 01:40:31 PM PST 24 |
| Finished | Mar 05 01:40:38 PM PST 24 |
| Peak memory | 237472 kb |
| Host | smart-f8c3d7e1-4446-4abc-943d-1970ce500246 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157515426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4157515426 |
| Directory | /workspace/26.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/26.spi_device_intercept.3811179905 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 793653238 ps |
| CPU time | 3.7 seconds |
| Started | Mar 05 01:40:33 PM PST 24 |
| Finished | Mar 05 01:40:36 PM PST 24 |
| Peak memory | 234024 kb |
| Host | smart-9214f135-c203-4b5b-81fd-6e2028e82518 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3811179905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3811179905 |
| Directory | /workspace/26.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/26.spi_device_mailbox.3655663774 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 72955564473 ps |
| CPU time | 54.79 seconds |
| Started | Mar 05 01:40:34 PM PST 24 |
| Finished | Mar 05 01:41:29 PM PST 24 |
| Peak memory | 240680 kb |
| Host | smart-a1fe8660-8c43-4a94-b8ec-b94f64de0cab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655663774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3655663774 |
| Directory | /workspace/26.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2958198505 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 5845365457 ps |
| CPU time | 18.23 seconds |
| Started | Mar 05 01:40:34 PM PST 24 |
| Finished | Mar 05 01:40:52 PM PST 24 |
| Peak memory | 232576 kb |
| Host | smart-0d825a9a-6c8b-4b6f-b493-41d20a3d439c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958198505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa p.2958198505 |
| Directory | /workspace/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1249637215 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 13728877195 ps |
| CPU time | 11.04 seconds |
| Started | Mar 05 01:40:33 PM PST 24 |
| Finished | Mar 05 01:40:44 PM PST 24 |
| Peak memory | 217480 kb |
| Host | smart-fbcc6673-3f5b-42d5-85af-3b0a5afba985 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249637215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1249637215 |
| Directory | /workspace/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/26.spi_device_read_buffer_direct.2848429771 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 353167896 ps |
| CPU time | 3.94 seconds |
| Started | Mar 05 01:40:34 PM PST 24 |
| Finished | Mar 05 01:40:38 PM PST 24 |
| Peak memory | 221824 kb |
| Host | smart-926cdf6c-735c-4c06-8f24-f178e0e23466 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2848429771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir ect.2848429771 |
| Directory | /workspace/26.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/26.spi_device_stress_all.2889176406 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 135708167337 ps |
| CPU time | 821.39 seconds |
| Started | Mar 05 01:40:33 PM PST 24 |
| Finished | Mar 05 01:54:14 PM PST 24 |
| Peak memory | 273728 kb |
| Host | smart-9a5d8aa8-8014-4295-9769-0cca39a764a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889176406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre ss_all.2889176406 |
| Directory | /workspace/26.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/26.spi_device_tpm_all.4266852047 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3652632496 ps |
| CPU time | 38.79 seconds |
| Started | Mar 05 01:40:23 PM PST 24 |
| Finished | Mar 05 01:41:02 PM PST 24 |
| Peak memory | 216276 kb |
| Host | smart-55cad95d-9e6d-4699-9db5-eba6e12c2a63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266852047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4266852047 |
| Directory | /workspace/26.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1303204109 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 7446591616 ps |
| CPU time | 10.97 seconds |
| Started | Mar 05 01:40:18 PM PST 24 |
| Finished | Mar 05 01:40:29 PM PST 24 |
| Peak memory | 216260 kb |
| Host | smart-1235290b-af5a-40ce-8062-eaae685fdaa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303204109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1303204109 |
| Directory | /workspace/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/26.spi_device_tpm_rw.1102474498 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 892219966 ps |
| CPU time | 3.36 seconds |
| Started | Mar 05 01:40:20 PM PST 24 |
| Finished | Mar 05 01:40:24 PM PST 24 |
| Peak memory | 216172 kb |
| Host | smart-39d1e872-09b6-4e0b-8c84-ec89937bb900 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102474498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1102474498 |
| Directory | /workspace/26.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/26.spi_device_tpm_sts_read.272470660 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 32655554 ps |
| CPU time | 0.86 seconds |
| Started | Mar 05 01:40:19 PM PST 24 |
| Finished | Mar 05 01:40:20 PM PST 24 |
| Peak memory | 205508 kb |
| Host | smart-9234e917-2177-4526-a587-0cdc4fc78b94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272470660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.272470660 |
| Directory | /workspace/26.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/26.spi_device_upload.3541204329 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4442470515 ps |
| CPU time | 15.32 seconds |
| Started | Mar 05 01:40:38 PM PST 24 |
| Finished | Mar 05 01:40:53 PM PST 24 |
| Peak memory | 220716 kb |
| Host | smart-5a26ac9e-2c81-4b0e-aa0c-8209ff8b9658 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541204329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3541204329 |
| Directory | /workspace/26.spi_device_upload/latest |
| Test location | /workspace/coverage/default/27.spi_device_alert_test.893307314 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 15084239 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 01:40:51 PM PST 24 |
| Finished | Mar 05 01:40:52 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-7586fa78-fc78-45c8-a0b4-5b188484839d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893307314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.893307314 |
| Directory | /workspace/27.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/27.spi_device_cfg_cmd.4198215747 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 530111788 ps |
| CPU time | 2.98 seconds |
| Started | Mar 05 01:40:39 PM PST 24 |
| Finished | Mar 05 01:40:42 PM PST 24 |
| Peak memory | 216572 kb |
| Host | smart-677c2b5b-e4bb-4ced-994c-e9441f310d8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198215747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4198215747 |
| Directory | /workspace/27.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/27.spi_device_csb_read.943074292 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 51759041 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:40:34 PM PST 24 |
| Finished | Mar 05 01:40:35 PM PST 24 |
| Peak memory | 206020 kb |
| Host | smart-fa3016c3-0c41-497e-bafd-54f9c8f3671e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943074292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.943074292 |
| Directory | /workspace/27.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/27.spi_device_flash_all.1661520385 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2606032264 ps |
| CPU time | 45.41 seconds |
| Started | Mar 05 01:40:41 PM PST 24 |
| Finished | Mar 05 01:41:27 PM PST 24 |
| Peak memory | 249028 kb |
| Host | smart-8150bbb8-d21e-4fef-b9d7-93eb0bf89aad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661520385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1661520385 |
| Directory | /workspace/27.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/27.spi_device_flash_and_tpm.1051918278 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 49374374863 ps |
| CPU time | 172.09 seconds |
| Started | Mar 05 01:40:39 PM PST 24 |
| Finished | Mar 05 01:43:32 PM PST 24 |
| Peak memory | 261496 kb |
| Host | smart-ea002fcc-017e-4cf0-959a-060d6a93d96c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051918278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1051918278 |
| Directory | /workspace/27.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2832559570 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 81205193515 ps |
| CPU time | 74.32 seconds |
| Started | Mar 05 01:40:44 PM PST 24 |
| Finished | Mar 05 01:41:58 PM PST 24 |
| Peak memory | 252364 kb |
| Host | smart-656f9607-ea87-402d-847c-e7c597743b2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832559570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl e.2832559570 |
| Directory | /workspace/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/27.spi_device_flash_mode.1925345857 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 5073670463 ps |
| CPU time | 26.25 seconds |
| Started | Mar 05 01:40:48 PM PST 24 |
| Finished | Mar 05 01:41:14 PM PST 24 |
| Peak memory | 238452 kb |
| Host | smart-055d548a-08ac-4aa2-a17d-6c6ff8293fa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925345857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1925345857 |
| Directory | /workspace/27.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/27.spi_device_intercept.1303500526 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 1806512677 ps |
| CPU time | 3.75 seconds |
| Started | Mar 05 01:40:46 PM PST 24 |
| Finished | Mar 05 01:40:50 PM PST 24 |
| Peak memory | 233456 kb |
| Host | smart-b59d7c6b-f209-46ec-b77c-19130a820a58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303500526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1303500526 |
| Directory | /workspace/27.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/27.spi_device_mailbox.2492676909 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 185973242 ps |
| CPU time | 3.91 seconds |
| Started | Mar 05 01:40:46 PM PST 24 |
| Finished | Mar 05 01:40:50 PM PST 24 |
| Peak memory | 233132 kb |
| Host | smart-4b548a64-e8e2-4878-a75b-490afe3237d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492676909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2492676909 |
| Directory | /workspace/27.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3362028609 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1353150852 ps |
| CPU time | 5.62 seconds |
| Started | Mar 05 01:40:35 PM PST 24 |
| Finished | Mar 05 01:40:41 PM PST 24 |
| Peak memory | 234324 kb |
| Host | smart-2ffcbc8a-66ac-4b13-bd94-30743051e22d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362028609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa p.3362028609 |
| Directory | /workspace/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1150539639 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4803336695 ps |
| CPU time | 17.32 seconds |
| Started | Mar 05 01:40:36 PM PST 24 |
| Finished | Mar 05 01:40:53 PM PST 24 |
| Peak memory | 242524 kb |
| Host | smart-5307c826-8367-4d18-b916-c2937e7e5497 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150539639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1150539639 |
| Directory | /workspace/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/27.spi_device_read_buffer_direct.3792522258 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 762764998 ps |
| CPU time | 3.89 seconds |
| Started | Mar 05 01:40:47 PM PST 24 |
| Finished | Mar 05 01:40:51 PM PST 24 |
| Peak memory | 216480 kb |
| Host | smart-5365b8dc-872c-4736-9599-18e814a8961c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3792522258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir ect.3792522258 |
| Directory | /workspace/27.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/27.spi_device_stress_all.1912322049 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 41438539 ps |
| CPU time | 0.91 seconds |
| Started | Mar 05 01:40:52 PM PST 24 |
| Finished | Mar 05 01:40:53 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-88974051-fe4a-40d8-88a8-0bcef0a7d4a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912322049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre ss_all.1912322049 |
| Directory | /workspace/27.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/27.spi_device_tpm_all.3495961924 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 22061743426 ps |
| CPU time | 66.82 seconds |
| Started | Mar 05 01:40:31 PM PST 24 |
| Finished | Mar 05 01:41:38 PM PST 24 |
| Peak memory | 216328 kb |
| Host | smart-c772fb87-a9b9-4bb4-b5ab-ea9c6348b2fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495961924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3495961924 |
| Directory | /workspace/27.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2029666878 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3344496727 ps |
| CPU time | 8.36 seconds |
| Started | Mar 05 01:40:34 PM PST 24 |
| Finished | Mar 05 01:40:42 PM PST 24 |
| Peak memory | 216308 kb |
| Host | smart-7c816f84-131f-4f93-8a4c-26569dfde9f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029666878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2029666878 |
| Directory | /workspace/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/27.spi_device_tpm_rw.2258973895 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 243505890 ps |
| CPU time | 3.36 seconds |
| Started | Mar 05 01:40:35 PM PST 24 |
| Finished | Mar 05 01:40:39 PM PST 24 |
| Peak memory | 216300 kb |
| Host | smart-4a5ca1fa-8b64-4e73-8f30-ad30ecf7d34b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258973895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2258973895 |
| Directory | /workspace/27.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/27.spi_device_tpm_sts_read.3417178352 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 29216289 ps |
| CPU time | 0.82 seconds |
| Started | Mar 05 01:40:33 PM PST 24 |
| Finished | Mar 05 01:40:34 PM PST 24 |
| Peak memory | 205256 kb |
| Host | smart-4814aa12-22d5-4869-8262-4e7f82757912 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417178352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3417178352 |
| Directory | /workspace/27.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/27.spi_device_upload.483778838 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5064562030 ps |
| CPU time | 13.61 seconds |
| Started | Mar 05 01:40:48 PM PST 24 |
| Finished | Mar 05 01:41:02 PM PST 24 |
| Peak memory | 239780 kb |
| Host | smart-8fad0bfb-1e27-452f-a55b-88b69473751c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=483778838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.483778838 |
| Directory | /workspace/27.spi_device_upload/latest |
| Test location | /workspace/coverage/default/28.spi_device_alert_test.1357517534 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 16915973 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:40:56 PM PST 24 |
| Finished | Mar 05 01:40:57 PM PST 24 |
| Peak memory | 205172 kb |
| Host | smart-3323d516-f747-4e33-ac69-9440b257c0c0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357517534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test. 1357517534 |
| Directory | /workspace/28.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/28.spi_device_cfg_cmd.500134268 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 4860879377 ps |
| CPU time | 6.68 seconds |
| Started | Mar 05 01:40:50 PM PST 24 |
| Finished | Mar 05 01:40:57 PM PST 24 |
| Peak memory | 233660 kb |
| Host | smart-b020e8b1-6a1e-4b51-baab-79746fe0b930 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500134268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.500134268 |
| Directory | /workspace/28.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/28.spi_device_csb_read.3476940929 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 26963435 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:40:52 PM PST 24 |
| Finished | Mar 05 01:40:53 PM PST 24 |
| Peak memory | 206004 kb |
| Host | smart-8f4cb802-a655-49b9-aa55-e077312020af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476940929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3476940929 |
| Directory | /workspace/28.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/28.spi_device_flash_all.1395214009 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 8438747081 ps |
| CPU time | 45.71 seconds |
| Started | Mar 05 01:40:47 PM PST 24 |
| Finished | Mar 05 01:41:33 PM PST 24 |
| Peak memory | 257212 kb |
| Host | smart-5681f88e-c2ff-4c5c-bd0f-4613d9483cca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395214009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1395214009 |
| Directory | /workspace/28.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/28.spi_device_flash_and_tpm.4076759032 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4803283851 ps |
| CPU time | 35.69 seconds |
| Started | Mar 05 01:40:52 PM PST 24 |
| Finished | Mar 05 01:41:28 PM PST 24 |
| Peak memory | 223540 kb |
| Host | smart-f5287253-00e6-4a89-968a-016e048de7fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076759032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4076759032 |
| Directory | /workspace/28.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/28.spi_device_flash_mode.160776272 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 28483317993 ps |
| CPU time | 36.06 seconds |
| Started | Mar 05 01:40:52 PM PST 24 |
| Finished | Mar 05 01:41:28 PM PST 24 |
| Peak memory | 249032 kb |
| Host | smart-c6bb838b-dff6-4e9d-8aba-8225b5aac868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160776272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.160776272 |
| Directory | /workspace/28.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/28.spi_device_intercept.3325975350 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 10550041798 ps |
| CPU time | 8.07 seconds |
| Started | Mar 05 01:40:50 PM PST 24 |
| Finished | Mar 05 01:40:58 PM PST 24 |
| Peak memory | 218320 kb |
| Host | smart-a2e33a42-b046-4d7d-af55-169042818697 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325975350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3325975350 |
| Directory | /workspace/28.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/28.spi_device_mailbox.4266754437 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1685946239 ps |
| CPU time | 6.79 seconds |
| Started | Mar 05 01:40:51 PM PST 24 |
| Finished | Mar 05 01:40:58 PM PST 24 |
| Peak memory | 233052 kb |
| Host | smart-8d13fc33-0f3b-4991-a3b2-bc038e5eb684 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266754437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4266754437 |
| Directory | /workspace/28.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3557454093 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 551707000 ps |
| CPU time | 10.11 seconds |
| Started | Mar 05 01:40:48 PM PST 24 |
| Finished | Mar 05 01:40:58 PM PST 24 |
| Peak memory | 240496 kb |
| Host | smart-227ba4d1-2878-4614-9faa-bb5cd1140c79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557454093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa p.3557454093 |
| Directory | /workspace/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2425004741 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 10446534919 ps |
| CPU time | 15.65 seconds |
| Started | Mar 05 01:40:51 PM PST 24 |
| Finished | Mar 05 01:41:07 PM PST 24 |
| Peak memory | 217212 kb |
| Host | smart-ad1e50c8-8874-4a3c-87e3-f9a2d59f0e86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425004741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2425004741 |
| Directory | /workspace/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/28.spi_device_read_buffer_direct.1749330551 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1369851492 ps |
| CPU time | 3.82 seconds |
| Started | Mar 05 01:40:52 PM PST 24 |
| Finished | Mar 05 01:40:56 PM PST 24 |
| Peak memory | 222504 kb |
| Host | smart-4a49d61d-479b-4f8c-a994-4b0abb079a7a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1749330551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir ect.1749330551 |
| Directory | /workspace/28.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/28.spi_device_stress_all.2445719770 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 39061438018 ps |
| CPU time | 104.37 seconds |
| Started | Mar 05 01:40:48 PM PST 24 |
| Finished | Mar 05 01:42:32 PM PST 24 |
| Peak memory | 253572 kb |
| Host | smart-f950803e-371b-4140-98b4-ce451c14c637 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445719770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre ss_all.2445719770 |
| Directory | /workspace/28.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/28.spi_device_tpm_all.3043889581 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 11513229015 ps |
| CPU time | 11.63 seconds |
| Started | Mar 05 01:40:51 PM PST 24 |
| Finished | Mar 05 01:41:03 PM PST 24 |
| Peak memory | 217344 kb |
| Host | smart-f6f907e8-c88b-46da-9470-b0cb21885eac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3043889581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3043889581 |
| Directory | /workspace/28.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3028662252 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 514970064 ps |
| CPU time | 4.49 seconds |
| Started | Mar 05 01:40:50 PM PST 24 |
| Finished | Mar 05 01:40:54 PM PST 24 |
| Peak memory | 216244 kb |
| Host | smart-39da33b8-9b95-4fa6-9b1b-cb8b35f1a28f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028662252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3028662252 |
| Directory | /workspace/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/28.spi_device_tpm_rw.949925707 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 111545935 ps |
| CPU time | 1.88 seconds |
| Started | Mar 05 01:40:54 PM PST 24 |
| Finished | Mar 05 01:40:56 PM PST 24 |
| Peak memory | 216180 kb |
| Host | smart-04147181-44c7-4386-89e4-d4bf66560e53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949925707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.949925707 |
| Directory | /workspace/28.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/28.spi_device_tpm_sts_read.2479753269 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 18005262 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:40:50 PM PST 24 |
| Finished | Mar 05 01:40:51 PM PST 24 |
| Peak memory | 205356 kb |
| Host | smart-964ec8c9-7083-427f-ba66-0866ac43d9f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479753269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2479753269 |
| Directory | /workspace/28.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/28.spi_device_upload.3208450385 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 914077337 ps |
| CPU time | 5.09 seconds |
| Started | Mar 05 01:40:52 PM PST 24 |
| Finished | Mar 05 01:40:57 PM PST 24 |
| Peak memory | 249400 kb |
| Host | smart-2dc4b039-c01a-4f94-b2a2-19be6d5753cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208450385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3208450385 |
| Directory | /workspace/28.spi_device_upload/latest |
| Test location | /workspace/coverage/default/29.spi_device_alert_test.3663896135 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 43559432 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 01:40:54 PM PST 24 |
| Finished | Mar 05 01:40:55 PM PST 24 |
| Peak memory | 205192 kb |
| Host | smart-01bdbe06-0d4f-4d3f-b3d9-2bb5dcce9f20 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663896135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test. 3663896135 |
| Directory | /workspace/29.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/29.spi_device_cfg_cmd.2819420722 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1033939354 ps |
| CPU time | 5.31 seconds |
| Started | Mar 05 01:40:54 PM PST 24 |
| Finished | Mar 05 01:41:00 PM PST 24 |
| Peak memory | 234320 kb |
| Host | smart-92d37f96-21e4-4d46-90f0-a8ed2921ee41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819420722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2819420722 |
| Directory | /workspace/29.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/29.spi_device_csb_read.247520701 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 28719971 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:40:50 PM PST 24 |
| Finished | Mar 05 01:40:51 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-cef7b714-0335-45ae-a19b-55d042f6dce1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=247520701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.247520701 |
| Directory | /workspace/29.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/29.spi_device_flash_all.2804237228 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 6045103540 ps |
| CPU time | 21.23 seconds |
| Started | Mar 05 01:40:54 PM PST 24 |
| Finished | Mar 05 01:41:16 PM PST 24 |
| Peak memory | 249884 kb |
| Host | smart-42777aab-a0bd-49b9-ad5d-34f2083e48af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804237228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2804237228 |
| Directory | /workspace/29.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/29.spi_device_flash_and_tpm.2336908257 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15834692970 ps |
| CPU time | 98.92 seconds |
| Started | Mar 05 01:40:54 PM PST 24 |
| Finished | Mar 05 01:42:33 PM PST 24 |
| Peak memory | 258156 kb |
| Host | smart-684fc23b-5dd0-460d-a16b-c3603b7666fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336908257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2336908257 |
| Directory | /workspace/29.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.39324747 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3042125953 ps |
| CPU time | 63.45 seconds |
| Started | Mar 05 01:40:56 PM PST 24 |
| Finished | Mar 05 01:41:59 PM PST 24 |
| Peak memory | 252692 kb |
| Host | smart-1db1d784-d71e-4c96-bf60-7a140a97e504 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39324747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.39324747 |
| Directory | /workspace/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/29.spi_device_flash_mode.2711328999 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 29428397416 ps |
| CPU time | 17.53 seconds |
| Started | Mar 05 01:40:55 PM PST 24 |
| Finished | Mar 05 01:41:12 PM PST 24 |
| Peak memory | 246380 kb |
| Host | smart-4e0b1717-cbc6-40aa-9b8f-18a1dfddbbf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711328999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2711328999 |
| Directory | /workspace/29.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/29.spi_device_intercept.2217568190 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1028836884 ps |
| CPU time | 4.24 seconds |
| Started | Mar 05 01:40:51 PM PST 24 |
| Finished | Mar 05 01:40:55 PM PST 24 |
| Peak memory | 224324 kb |
| Host | smart-a5e48687-3204-4fb4-9cbe-7c0b73001ee8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217568190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2217568190 |
| Directory | /workspace/29.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/29.spi_device_mailbox.4214111699 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 11655613389 ps |
| CPU time | 18.1 seconds |
| Started | Mar 05 01:40:57 PM PST 24 |
| Finished | Mar 05 01:41:15 PM PST 24 |
| Peak memory | 218408 kb |
| Host | smart-4a00ce22-de4b-44ee-86ba-1757f6c50652 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214111699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4214111699 |
| Directory | /workspace/29.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1626017187 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 5470429740 ps |
| CPU time | 24.05 seconds |
| Started | Mar 05 01:40:48 PM PST 24 |
| Finished | Mar 05 01:41:13 PM PST 24 |
| Peak memory | 230684 kb |
| Host | smart-8a0f2024-f0a1-4025-bfc0-1535a0c91eaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626017187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa p.1626017187 |
| Directory | /workspace/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3771230151 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 19975016999 ps |
| CPU time | 27.51 seconds |
| Started | Mar 05 01:40:51 PM PST 24 |
| Finished | Mar 05 01:41:19 PM PST 24 |
| Peak memory | 217436 kb |
| Host | smart-b7eb0526-c8d7-4f8d-8d21-698f124483f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771230151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3771230151 |
| Directory | /workspace/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/29.spi_device_read_buffer_direct.1363418637 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 143854369 ps |
| CPU time | 3.73 seconds |
| Started | Mar 05 01:40:55 PM PST 24 |
| Finished | Mar 05 01:40:59 PM PST 24 |
| Peak memory | 222372 kb |
| Host | smart-1116dcd8-e2bb-4112-91a4-98f64cb3f7cf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1363418637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir ect.1363418637 |
| Directory | /workspace/29.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/29.spi_device_stress_all.2225413220 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 162626929425 ps |
| CPU time | 356.37 seconds |
| Started | Mar 05 01:40:56 PM PST 24 |
| Finished | Mar 05 01:46:52 PM PST 24 |
| Peak memory | 272948 kb |
| Host | smart-a31e733c-a112-4005-96ae-1f70aaab0999 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225413220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre ss_all.2225413220 |
| Directory | /workspace/29.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/29.spi_device_tpm_all.2963009753 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 503082964 ps |
| CPU time | 6.67 seconds |
| Started | Mar 05 01:40:49 PM PST 24 |
| Finished | Mar 05 01:40:55 PM PST 24 |
| Peak memory | 216256 kb |
| Host | smart-6972b180-8dc3-4f06-a8e2-05da7b5280f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963009753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2963009753 |
| Directory | /workspace/29.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2808629277 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1790002519 ps |
| CPU time | 4.07 seconds |
| Started | Mar 05 01:40:51 PM PST 24 |
| Finished | Mar 05 01:40:55 PM PST 24 |
| Peak memory | 208076 kb |
| Host | smart-0b1389bf-f716-42b8-bdef-73235de93874 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808629277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2808629277 |
| Directory | /workspace/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/29.spi_device_tpm_rw.1908877822 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 228709303 ps |
| CPU time | 10.3 seconds |
| Started | Mar 05 01:40:52 PM PST 24 |
| Finished | Mar 05 01:41:02 PM PST 24 |
| Peak memory | 216220 kb |
| Host | smart-2a0972f5-8fb9-48bd-b152-85653aad64ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908877822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1908877822 |
| Directory | /workspace/29.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/29.spi_device_tpm_sts_read.2060591576 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 139079267 ps |
| CPU time | 0.89 seconds |
| Started | Mar 05 01:40:48 PM PST 24 |
| Finished | Mar 05 01:40:49 PM PST 24 |
| Peak memory | 206376 kb |
| Host | smart-49881c41-f85e-4145-97da-a6488b19b4f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060591576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2060591576 |
| Directory | /workspace/29.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/29.spi_device_upload.1771053272 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 14798636061 ps |
| CPU time | 23.96 seconds |
| Started | Mar 05 01:40:56 PM PST 24 |
| Finished | Mar 05 01:41:20 PM PST 24 |
| Peak memory | 218724 kb |
| Host | smart-e59389ee-47ea-494e-bff5-bce98f9cf966 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771053272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1771053272 |
| Directory | /workspace/29.spi_device_upload/latest |
| Test location | /workspace/coverage/default/3.spi_device_alert_test.2263526260 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 46125326 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:36:40 PM PST 24 |
| Finished | Mar 05 01:36:41 PM PST 24 |
| Peak memory | 205068 kb |
| Host | smart-3ea2f56c-a522-4440-afdc-ca4d656cfd5a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263526260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2 263526260 |
| Directory | /workspace/3.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/3.spi_device_cfg_cmd.1331928277 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2477004372 ps |
| CPU time | 4.23 seconds |
| Started | Mar 05 01:36:40 PM PST 24 |
| Finished | Mar 05 01:36:45 PM PST 24 |
| Peak memory | 236556 kb |
| Host | smart-78c5303d-a23e-4097-9a9d-9a5e7541e8d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1331928277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1331928277 |
| Directory | /workspace/3.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/3.spi_device_csb_read.1962787084 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 41567237 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:36:32 PM PST 24 |
| Finished | Mar 05 01:36:33 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-7f51ae38-9e20-4fb8-a5bc-1bd561099c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962787084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1962787084 |
| Directory | /workspace/3.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/3.spi_device_flash_all.576366172 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 33964704217 ps |
| CPU time | 162.45 seconds |
| Started | Mar 05 01:36:38 PM PST 24 |
| Finished | Mar 05 01:39:21 PM PST 24 |
| Peak memory | 254672 kb |
| Host | smart-cd6a6d63-7c4d-4aa8-aae1-259f6b72879b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576366172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.576366172 |
| Directory | /workspace/3.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/3.spi_device_flash_and_tpm.1649850999 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 217946059717 ps |
| CPU time | 370.43 seconds |
| Started | Mar 05 01:36:39 PM PST 24 |
| Finished | Mar 05 01:42:50 PM PST 24 |
| Peak memory | 256556 kb |
| Host | smart-18f9be26-e475-4554-978d-df3e7084b5ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649850999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1649850999 |
| Directory | /workspace/3.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.330021656 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 9230153553 ps |
| CPU time | 108.43 seconds |
| Started | Mar 05 01:36:39 PM PST 24 |
| Finished | Mar 05 01:38:28 PM PST 24 |
| Peak memory | 257340 kb |
| Host | smart-5a341eb8-6d68-4f82-9300-8898bfdca5ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330021656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle. 330021656 |
| Directory | /workspace/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/3.spi_device_flash_mode.1425218982 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 11023536941 ps |
| CPU time | 25.46 seconds |
| Started | Mar 05 01:36:39 PM PST 24 |
| Finished | Mar 05 01:37:05 PM PST 24 |
| Peak memory | 251512 kb |
| Host | smart-ecea137b-2f76-4520-be9a-f4c488261b2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425218982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1425218982 |
| Directory | /workspace/3.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/3.spi_device_intercept.2999934500 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 23116938554 ps |
| CPU time | 15.01 seconds |
| Started | Mar 05 01:36:29 PM PST 24 |
| Finished | Mar 05 01:36:44 PM PST 24 |
| Peak memory | 232952 kb |
| Host | smart-603da025-b8db-4f02-9346-cf3d78ea6e91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2999934500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2999934500 |
| Directory | /workspace/3.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/3.spi_device_mailbox.3118714404 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1580878830 ps |
| CPU time | 6.77 seconds |
| Started | Mar 05 01:36:37 PM PST 24 |
| Finished | Mar 05 01:36:45 PM PST 24 |
| Peak memory | 233240 kb |
| Host | smart-f842e949-863c-4621-89f5-2a071192064c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118714404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3118714404 |
| Directory | /workspace/3.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/3.spi_device_mem_parity.2157351755 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 114014606 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:36:32 PM PST 24 |
| Finished | Mar 05 01:36:33 PM PST 24 |
| Peak memory | 217736 kb |
| Host | smart-740e05e5-809b-4a07-b2f6-559e3b2b15fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157351755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.spi_device_mem_parity.2157351755 |
| Directory | /workspace/3.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4145749921 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1186156407 ps |
| CPU time | 4.54 seconds |
| Started | Mar 05 01:36:33 PM PST 24 |
| Finished | Mar 05 01:36:38 PM PST 24 |
| Peak memory | 232580 kb |
| Host | smart-42e5d9cc-6b90-4051-88de-54390031eb32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145749921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4145749921 |
| Directory | /workspace/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/3.spi_device_ram_cfg.3627924331 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 35006498 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:36:29 PM PST 24 |
| Finished | Mar 05 01:36:30 PM PST 24 |
| Peak memory | 216076 kb |
| Host | smart-31896d76-f052-4c16-ae36-9f336e455367 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627924331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3627924331 |
| Directory | /workspace/3.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/3.spi_device_read_buffer_direct.2406806591 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 658050165 ps |
| CPU time | 3.2 seconds |
| Started | Mar 05 01:36:38 PM PST 24 |
| Finished | Mar 05 01:36:42 PM PST 24 |
| Peak memory | 220000 kb |
| Host | smart-30e09b66-7299-42bc-9a21-f3e2ed26f705 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2406806591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire ct.2406806591 |
| Directory | /workspace/3.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/3.spi_device_sec_cm.1220869474 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1011209743 ps |
| CPU time | 1.21 seconds |
| Started | Mar 05 01:36:36 PM PST 24 |
| Finished | Mar 05 01:36:38 PM PST 24 |
| Peak memory | 235048 kb |
| Host | smart-bc3a0640-0ee8-4cfe-8a33-71e6e7dfa2c3 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220869474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1220869474 |
| Directory | /workspace/3.spi_device_sec_cm/latest |
| Test location | /workspace/coverage/default/3.spi_device_stress_all.3050238794 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 56210273049 ps |
| CPU time | 494.02 seconds |
| Started | Mar 05 01:36:39 PM PST 24 |
| Finished | Mar 05 01:44:53 PM PST 24 |
| Peak memory | 284308 kb |
| Host | smart-e7357f8e-1819-42af-b1ff-e34c106ec54d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050238794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres s_all.3050238794 |
| Directory | /workspace/3.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/3.spi_device_tpm_all.3954454457 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 36706424559 ps |
| CPU time | 22.54 seconds |
| Started | Mar 05 01:36:31 PM PST 24 |
| Finished | Mar 05 01:36:53 PM PST 24 |
| Peak memory | 216336 kb |
| Host | smart-3f77a56d-9908-4267-8792-8b07d58dc2f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954454457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3954454457 |
| Directory | /workspace/3.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3105431393 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3946304406 ps |
| CPU time | 3.78 seconds |
| Started | Mar 05 01:36:33 PM PST 24 |
| Finished | Mar 05 01:36:37 PM PST 24 |
| Peak memory | 216332 kb |
| Host | smart-686c2df9-7de6-49ba-87ad-d820c6afcbe3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105431393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3105431393 |
| Directory | /workspace/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/3.spi_device_tpm_rw.2055726808 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 617270104 ps |
| CPU time | 7.71 seconds |
| Started | Mar 05 01:36:33 PM PST 24 |
| Finished | Mar 05 01:36:41 PM PST 24 |
| Peak memory | 216560 kb |
| Host | smart-2c9ec359-9178-4f92-b768-cfb4f2b11a0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055726808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2055726808 |
| Directory | /workspace/3.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/3.spi_device_tpm_sts_read.1367590236 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 35376969 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 01:36:33 PM PST 24 |
| Finished | Mar 05 01:36:34 PM PST 24 |
| Peak memory | 205264 kb |
| Host | smart-9c603086-0838-4768-8cb1-fa04182360da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367590236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1367590236 |
| Directory | /workspace/3.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/3.spi_device_upload.540893549 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 50558177592 ps |
| CPU time | 26.05 seconds |
| Started | Mar 05 01:36:40 PM PST 24 |
| Finished | Mar 05 01:37:06 PM PST 24 |
| Peak memory | 217672 kb |
| Host | smart-1458677e-25e1-4521-85f0-655a12d269cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540893549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.540893549 |
| Directory | /workspace/3.spi_device_upload/latest |
| Test location | /workspace/coverage/default/30.spi_device_alert_test.3399024364 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 10844339 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:40:58 PM PST 24 |
| Finished | Mar 05 01:40:58 PM PST 24 |
| Peak memory | 204832 kb |
| Host | smart-41ddbeed-1ed9-4f53-b85f-c7e3691bfbbd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399024364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test. 3399024364 |
| Directory | /workspace/30.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/30.spi_device_cfg_cmd.830257954 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 55838195 ps |
| CPU time | 2.49 seconds |
| Started | Mar 05 01:41:00 PM PST 24 |
| Finished | Mar 05 01:41:03 PM PST 24 |
| Peak memory | 232532 kb |
| Host | smart-8c5add44-9ab5-4583-8c7f-5f9d08fbddf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830257954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.830257954 |
| Directory | /workspace/30.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/30.spi_device_csb_read.1576959868 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 19578586 ps |
| CPU time | 0.81 seconds |
| Started | Mar 05 01:40:54 PM PST 24 |
| Finished | Mar 05 01:40:55 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-53b630c0-b891-441c-b851-b157cb365a7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576959868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1576959868 |
| Directory | /workspace/30.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/30.spi_device_flash_all.3666258961 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 50900154907 ps |
| CPU time | 247.84 seconds |
| Started | Mar 05 01:41:09 PM PST 24 |
| Finished | Mar 05 01:45:17 PM PST 24 |
| Peak memory | 257244 kb |
| Host | smart-e4bb3a75-968c-45a1-a608-d2518af79bd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666258961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3666258961 |
| Directory | /workspace/30.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/30.spi_device_flash_and_tpm.1416964805 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 21068612129 ps |
| CPU time | 169.2 seconds |
| Started | Mar 05 01:41:02 PM PST 24 |
| Finished | Mar 05 01:43:52 PM PST 24 |
| Peak memory | 249488 kb |
| Host | smart-6d032117-4ae9-48b3-a5ad-d3cb1718805e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416964805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1416964805 |
| Directory | /workspace/30.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3478088998 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 147169404385 ps |
| CPU time | 314.27 seconds |
| Started | Mar 05 01:41:05 PM PST 24 |
| Finished | Mar 05 01:46:19 PM PST 24 |
| Peak memory | 258864 kb |
| Host | smart-b8d26a87-06d4-4381-8ea5-67bd573395f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3478088998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl e.3478088998 |
| Directory | /workspace/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/30.spi_device_flash_mode.2164744039 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 960480851 ps |
| CPU time | 11.47 seconds |
| Started | Mar 05 01:40:59 PM PST 24 |
| Finished | Mar 05 01:41:11 PM PST 24 |
| Peak memory | 233352 kb |
| Host | smart-b11fd66f-12e8-4b67-9297-5b0d4dcedca5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164744039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2164744039 |
| Directory | /workspace/30.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/30.spi_device_intercept.2821180381 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2210079939 ps |
| CPU time | 4.86 seconds |
| Started | Mar 05 01:40:55 PM PST 24 |
| Finished | Mar 05 01:41:00 PM PST 24 |
| Peak memory | 233368 kb |
| Host | smart-6495cae9-2378-4c95-8626-cac213d4e1eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2821180381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2821180381 |
| Directory | /workspace/30.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/30.spi_device_mailbox.1005574308 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2778808135 ps |
| CPU time | 6.53 seconds |
| Started | Mar 05 01:41:02 PM PST 24 |
| Finished | Mar 05 01:41:09 PM PST 24 |
| Peak memory | 234704 kb |
| Host | smart-a6fd28fb-5d81-489b-be1a-10f8a0fbaf22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005574308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1005574308 |
| Directory | /workspace/30.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.410342924 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 714316602 ps |
| CPU time | 8.13 seconds |
| Started | Mar 05 01:40:56 PM PST 24 |
| Finished | Mar 05 01:41:04 PM PST 24 |
| Peak memory | 242044 kb |
| Host | smart-0717b15a-ba10-4df0-98f6-9d94ad698c09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410342924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap .410342924 |
| Directory | /workspace/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2387124297 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 37473837109 ps |
| CPU time | 12.34 seconds |
| Started | Mar 05 01:41:01 PM PST 24 |
| Finished | Mar 05 01:41:14 PM PST 24 |
| Peak memory | 218492 kb |
| Host | smart-89a07d96-7825-4ad0-83bb-393bab95b32c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387124297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2387124297 |
| Directory | /workspace/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/30.spi_device_read_buffer_direct.1110386504 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2119219741 ps |
| CPU time | 4 seconds |
| Started | Mar 05 01:41:00 PM PST 24 |
| Finished | Mar 05 01:41:04 PM PST 24 |
| Peak memory | 218360 kb |
| Host | smart-219af55a-885e-4d4e-9319-5462f5907455 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1110386504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir ect.1110386504 |
| Directory | /workspace/30.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/30.spi_device_stress_all.1345514059 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 51986636413 ps |
| CPU time | 382.51 seconds |
| Started | Mar 05 01:41:06 PM PST 24 |
| Finished | Mar 05 01:47:28 PM PST 24 |
| Peak memory | 257300 kb |
| Host | smart-068d6876-ba77-4763-a96a-6ae83660768f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345514059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre ss_all.1345514059 |
| Directory | /workspace/30.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/30.spi_device_tpm_all.41774025 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1656260353 ps |
| CPU time | 29.04 seconds |
| Started | Mar 05 01:40:55 PM PST 24 |
| Finished | Mar 05 01:41:24 PM PST 24 |
| Peak memory | 216208 kb |
| Host | smart-56091ed7-880e-48e4-a5be-4f2aeda61fbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41774025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.41774025 |
| Directory | /workspace/30.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1804145759 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 6276162974 ps |
| CPU time | 18.22 seconds |
| Started | Mar 05 01:40:57 PM PST 24 |
| Finished | Mar 05 01:41:16 PM PST 24 |
| Peak memory | 217200 kb |
| Host | smart-d4a8f425-38cf-4ef1-8d59-c01d2bd5915c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804145759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1804145759 |
| Directory | /workspace/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/30.spi_device_tpm_rw.2204772677 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 161639573 ps |
| CPU time | 0.97 seconds |
| Started | Mar 05 01:40:55 PM PST 24 |
| Finished | Mar 05 01:40:56 PM PST 24 |
| Peak memory | 206388 kb |
| Host | smart-97eb2428-71ad-4713-8cba-82c0d99a394d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204772677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2204772677 |
| Directory | /workspace/30.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/30.spi_device_tpm_sts_read.2728303242 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 91210080 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:40:58 PM PST 24 |
| Finished | Mar 05 01:41:00 PM PST 24 |
| Peak memory | 206392 kb |
| Host | smart-e86e282f-3c6a-4a68-8b35-3b3197e6a629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728303242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2728303242 |
| Directory | /workspace/30.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/30.spi_device_upload.712989089 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 278537103 ps |
| CPU time | 2.96 seconds |
| Started | Mar 05 01:41:01 PM PST 24 |
| Finished | Mar 05 01:41:04 PM PST 24 |
| Peak memory | 218752 kb |
| Host | smart-db4f2a35-0f09-4696-b838-b5d872b9b0fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712989089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.712989089 |
| Directory | /workspace/30.spi_device_upload/latest |
| Test location | /workspace/coverage/default/31.spi_device_alert_test.577749242 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 17931234 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:41:19 PM PST 24 |
| Finished | Mar 05 01:41:21 PM PST 24 |
| Peak memory | 204772 kb |
| Host | smart-e2fa0a0e-d3cd-40d2-9e18-58215ac16c74 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577749242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.577749242 |
| Directory | /workspace/31.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/31.spi_device_cfg_cmd.1217859985 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3845627298 ps |
| CPU time | 11.65 seconds |
| Started | Mar 05 01:41:08 PM PST 24 |
| Finished | Mar 05 01:41:20 PM PST 24 |
| Peak memory | 224324 kb |
| Host | smart-8939a507-2576-49da-a18f-063737415c82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217859985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1217859985 |
| Directory | /workspace/31.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/31.spi_device_csb_read.3651076187 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 33514947 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:41:04 PM PST 24 |
| Finished | Mar 05 01:41:05 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-66d22c66-e231-4824-84d5-aa2b03ab30dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651076187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3651076187 |
| Directory | /workspace/31.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/31.spi_device_flash_all.4065258434 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 19386358824 ps |
| CPU time | 107.62 seconds |
| Started | Mar 05 01:41:13 PM PST 24 |
| Finished | Mar 05 01:43:02 PM PST 24 |
| Peak memory | 248972 kb |
| Host | smart-8776c883-7417-467b-acb7-8a47ea513a92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065258434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4065258434 |
| Directory | /workspace/31.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/31.spi_device_flash_and_tpm.152822603 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 14335790980 ps |
| CPU time | 34.42 seconds |
| Started | Mar 05 01:41:09 PM PST 24 |
| Finished | Mar 05 01:41:44 PM PST 24 |
| Peak memory | 253232 kb |
| Host | smart-daf7ec3b-5750-41f8-885f-f8805e3103ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152822603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.152822603 |
| Directory | /workspace/31.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.476775240 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 115848371886 ps |
| CPU time | 211.77 seconds |
| Started | Mar 05 01:41:20 PM PST 24 |
| Finished | Mar 05 01:44:52 PM PST 24 |
| Peak memory | 254100 kb |
| Host | smart-7909bad9-e752-43e8-829b-6d37afe92617 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=476775240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle .476775240 |
| Directory | /workspace/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/31.spi_device_intercept.2374058488 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 12540132224 ps |
| CPU time | 6.95 seconds |
| Started | Mar 05 01:41:10 PM PST 24 |
| Finished | Mar 05 01:41:17 PM PST 24 |
| Peak memory | 233600 kb |
| Host | smart-e66d3ae7-9bff-494a-a9ff-57ad2e790fe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374058488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2374058488 |
| Directory | /workspace/31.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/31.spi_device_mailbox.592947681 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 165194385 ps |
| CPU time | 2.57 seconds |
| Started | Mar 05 01:41:08 PM PST 24 |
| Finished | Mar 05 01:41:10 PM PST 24 |
| Peak memory | 224352 kb |
| Host | smart-757faaf2-3034-4a53-954c-8f5599c05fd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592947681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.592947681 |
| Directory | /workspace/31.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.848988976 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7353114048 ps |
| CPU time | 13.71 seconds |
| Started | Mar 05 01:41:11 PM PST 24 |
| Finished | Mar 05 01:41:25 PM PST 24 |
| Peak memory | 217868 kb |
| Host | smart-7d41d41c-fde5-416a-9062-1b95c5c5f811 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848988976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap .848988976 |
| Directory | /workspace/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/31.spi_device_pass_cmd_filtering.528553381 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 5681970242 ps |
| CPU time | 17.18 seconds |
| Started | Mar 05 01:41:08 PM PST 24 |
| Finished | Mar 05 01:41:26 PM PST 24 |
| Peak memory | 232468 kb |
| Host | smart-967d0517-0966-46ec-bb65-ca561403fb55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528553381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.528553381 |
| Directory | /workspace/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/31.spi_device_read_buffer_direct.2863798197 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2151428401 ps |
| CPU time | 4.64 seconds |
| Started | Mar 05 01:41:08 PM PST 24 |
| Finished | Mar 05 01:41:13 PM PST 24 |
| Peak memory | 219704 kb |
| Host | smart-a5042d5c-db41-4053-8317-54a383fb60f3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2863798197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir ect.2863798197 |
| Directory | /workspace/31.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/31.spi_device_stress_all.2677674161 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 35412336581 ps |
| CPU time | 226.92 seconds |
| Started | Mar 05 01:41:22 PM PST 24 |
| Finished | Mar 05 01:45:09 PM PST 24 |
| Peak memory | 239520 kb |
| Host | smart-31146e26-b4e7-41c2-a9c3-c04baf5c7f94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677674161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre ss_all.2677674161 |
| Directory | /workspace/31.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/31.spi_device_tpm_all.2518781012 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 872144553 ps |
| CPU time | 7.03 seconds |
| Started | Mar 05 01:41:01 PM PST 24 |
| Finished | Mar 05 01:41:08 PM PST 24 |
| Peak memory | 216264 kb |
| Host | smart-85439058-e820-4a0a-b6c6-4b52931ad935 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2518781012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2518781012 |
| Directory | /workspace/31.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1732668664 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 5726739333 ps |
| CPU time | 20.84 seconds |
| Started | Mar 05 01:40:59 PM PST 24 |
| Finished | Mar 05 01:41:20 PM PST 24 |
| Peak memory | 217140 kb |
| Host | smart-293f8ab5-6c08-4d99-a146-f7dcd6ec8b1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732668664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1732668664 |
| Directory | /workspace/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/31.spi_device_tpm_rw.2923920119 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 673540887 ps |
| CPU time | 8.16 seconds |
| Started | Mar 05 01:41:08 PM PST 24 |
| Finished | Mar 05 01:41:16 PM PST 24 |
| Peak memory | 216268 kb |
| Host | smart-9b6bb83f-bfdf-468c-9afe-df111401291d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923920119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2923920119 |
| Directory | /workspace/31.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/31.spi_device_tpm_sts_read.2285416924 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 364551082 ps |
| CPU time | 0.93 seconds |
| Started | Mar 05 01:41:09 PM PST 24 |
| Finished | Mar 05 01:41:11 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-d1e83886-1ef6-49ed-9651-467e61143a22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285416924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2285416924 |
| Directory | /workspace/31.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/31.spi_device_upload.1312111032 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 843253438 ps |
| CPU time | 10.6 seconds |
| Started | Mar 05 01:41:09 PM PST 24 |
| Finished | Mar 05 01:41:20 PM PST 24 |
| Peak memory | 233344 kb |
| Host | smart-37c6efb1-fb48-4554-92ae-0eb3a8ed9a29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312111032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1312111032 |
| Directory | /workspace/31.spi_device_upload/latest |
| Test location | /workspace/coverage/default/32.spi_device_alert_test.1395404508 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 47657255 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:41:27 PM PST 24 |
| Finished | Mar 05 01:41:29 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-5e2fa975-a5dc-49f4-a82b-87f9c8baf8c8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395404508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test. 1395404508 |
| Directory | /workspace/32.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/32.spi_device_cfg_cmd.1979773716 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 34270794147 ps |
| CPU time | 10.32 seconds |
| Started | Mar 05 01:41:22 PM PST 24 |
| Finished | Mar 05 01:41:33 PM PST 24 |
| Peak memory | 235216 kb |
| Host | smart-54c2c1a3-e380-42d1-843f-403f0f2a5efb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979773716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1979773716 |
| Directory | /workspace/32.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/32.spi_device_csb_read.1206942630 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 52865365 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 01:41:19 PM PST 24 |
| Finished | Mar 05 01:41:20 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-9e924ca1-e604-4e4c-b704-6b0ba9331881 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206942630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1206942630 |
| Directory | /workspace/32.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/32.spi_device_flash_all.3542155834 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 65042850028 ps |
| CPU time | 55.95 seconds |
| Started | Mar 05 01:41:30 PM PST 24 |
| Finished | Mar 05 01:42:26 PM PST 24 |
| Peak memory | 255000 kb |
| Host | smart-be139409-4746-4a8a-8faf-79384a39a2c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542155834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3542155834 |
| Directory | /workspace/32.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/32.spi_device_flash_and_tpm.2530400664 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 7331735645 ps |
| CPU time | 30.98 seconds |
| Started | Mar 05 01:41:30 PM PST 24 |
| Finished | Mar 05 01:42:01 PM PST 24 |
| Peak memory | 234636 kb |
| Host | smart-78d20fb0-f894-42b3-857a-a4a49474fbfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530400664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2530400664 |
| Directory | /workspace/32.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.268176072 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 138209640301 ps |
| CPU time | 242.25 seconds |
| Started | Mar 05 01:41:27 PM PST 24 |
| Finished | Mar 05 01:45:31 PM PST 24 |
| Peak memory | 273712 kb |
| Host | smart-471d7ce3-4d4a-4718-a42d-902326d26e9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=268176072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle .268176072 |
| Directory | /workspace/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/32.spi_device_flash_mode.4099439833 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1036381563 ps |
| CPU time | 14.54 seconds |
| Started | Mar 05 01:41:21 PM PST 24 |
| Finished | Mar 05 01:41:36 PM PST 24 |
| Peak memory | 248908 kb |
| Host | smart-142bb813-cffe-4e28-b92e-35be455ffb55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4099439833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4099439833 |
| Directory | /workspace/32.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/32.spi_device_intercept.3235258395 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 6576587031 ps |
| CPU time | 6.12 seconds |
| Started | Mar 05 01:41:21 PM PST 24 |
| Finished | Mar 05 01:41:27 PM PST 24 |
| Peak memory | 233608 kb |
| Host | smart-1cc30e74-69f5-4d3e-b259-aabfa397c872 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235258395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3235258395 |
| Directory | /workspace/32.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/32.spi_device_mailbox.3062471239 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 28617659773 ps |
| CPU time | 7.58 seconds |
| Started | Mar 05 01:41:19 PM PST 24 |
| Finished | Mar 05 01:41:27 PM PST 24 |
| Peak memory | 233696 kb |
| Host | smart-6e26b976-d0c8-462b-8a92-ec00697cb86c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062471239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3062471239 |
| Directory | /workspace/32.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3330579589 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27999052218 ps |
| CPU time | 11.92 seconds |
| Started | Mar 05 01:41:23 PM PST 24 |
| Finished | Mar 05 01:41:35 PM PST 24 |
| Peak memory | 235372 kb |
| Host | smart-4c27c53a-887b-4f04-b9ab-a590da2070e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330579589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa p.3330579589 |
| Directory | /workspace/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2505882014 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2494966809 ps |
| CPU time | 4.01 seconds |
| Started | Mar 05 01:41:20 PM PST 24 |
| Finished | Mar 05 01:41:25 PM PST 24 |
| Peak memory | 233236 kb |
| Host | smart-e0669ec1-074a-4644-8e8a-f2c97a2beafd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505882014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2505882014 |
| Directory | /workspace/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/32.spi_device_read_buffer_direct.2028424161 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1433826926 ps |
| CPU time | 6.93 seconds |
| Started | Mar 05 01:41:29 PM PST 24 |
| Finished | Mar 05 01:41:36 PM PST 24 |
| Peak memory | 222476 kb |
| Host | smart-059fe757-f94d-4b6d-9c11-bf5336ece7fb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2028424161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir ect.2028424161 |
| Directory | /workspace/32.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/32.spi_device_stress_all.43571796 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 189852513 ps |
| CPU time | 0.97 seconds |
| Started | Mar 05 01:41:33 PM PST 24 |
| Finished | Mar 05 01:41:34 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-455767d9-1a9c-4430-a483-f1edd87829ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43571796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress _all.43571796 |
| Directory | /workspace/32.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/32.spi_device_tpm_all.1008242341 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 13471871276 ps |
| CPU time | 69.88 seconds |
| Started | Mar 05 01:41:17 PM PST 24 |
| Finished | Mar 05 01:42:27 PM PST 24 |
| Peak memory | 216304 kb |
| Host | smart-1ebc4a6e-a371-4314-b35a-6d2f1db7edca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008242341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1008242341 |
| Directory | /workspace/32.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1995945626 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 1543363321 ps |
| CPU time | 9.55 seconds |
| Started | Mar 05 01:41:21 PM PST 24 |
| Finished | Mar 05 01:41:30 PM PST 24 |
| Peak memory | 208092 kb |
| Host | smart-c55ab3cc-fa9d-4b96-a78f-26281e23f47c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995945626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1995945626 |
| Directory | /workspace/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/32.spi_device_tpm_rw.3128270092 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 324484313 ps |
| CPU time | 2.49 seconds |
| Started | Mar 05 01:41:19 PM PST 24 |
| Finished | Mar 05 01:41:22 PM PST 24 |
| Peak memory | 216232 kb |
| Host | smart-629f08de-0faa-4ae7-808b-57783fa1f42f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128270092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3128270092 |
| Directory | /workspace/32.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/32.spi_device_tpm_sts_read.1137685917 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 107138479 ps |
| CPU time | 1.01 seconds |
| Started | Mar 05 01:41:20 PM PST 24 |
| Finished | Mar 05 01:41:21 PM PST 24 |
| Peak memory | 206372 kb |
| Host | smart-ca26f0fc-4822-4665-842d-e748345ae0b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137685917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1137685917 |
| Directory | /workspace/32.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/32.spi_device_upload.1314955287 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 913073739 ps |
| CPU time | 4.16 seconds |
| Started | Mar 05 01:41:20 PM PST 24 |
| Finished | Mar 05 01:41:24 PM PST 24 |
| Peak memory | 216648 kb |
| Host | smart-575eb183-0616-419b-bbb3-48a02b4afd8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314955287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1314955287 |
| Directory | /workspace/32.spi_device_upload/latest |
| Test location | /workspace/coverage/default/33.spi_device_alert_test.3363615373 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 41660225 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:41:36 PM PST 24 |
| Finished | Mar 05 01:41:38 PM PST 24 |
| Peak memory | 204880 kb |
| Host | smart-b549d0c3-34df-4357-b37d-314afcd05ac6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363615373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test. 3363615373 |
| Directory | /workspace/33.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/33.spi_device_cfg_cmd.2030325648 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 688321688 ps |
| CPU time | 4.19 seconds |
| Started | Mar 05 01:41:35 PM PST 24 |
| Finished | Mar 05 01:41:39 PM PST 24 |
| Peak memory | 224360 kb |
| Host | smart-11fe9965-fb1d-429f-a6d9-f4639b511225 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030325648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2030325648 |
| Directory | /workspace/33.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/33.spi_device_csb_read.749214701 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 30678094 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 01:41:28 PM PST 24 |
| Finished | Mar 05 01:41:29 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-a3a47b2d-50aa-4d49-9dfc-a1ef2b35feb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749214701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.749214701 |
| Directory | /workspace/33.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/33.spi_device_flash_all.2183348237 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 18183483927 ps |
| CPU time | 46.89 seconds |
| Started | Mar 05 01:41:35 PM PST 24 |
| Finished | Mar 05 01:42:23 PM PST 24 |
| Peak memory | 254912 kb |
| Host | smart-c2ec1c85-729d-4aed-8362-cc35a41b99af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183348237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2183348237 |
| Directory | /workspace/33.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/33.spi_device_flash_and_tpm.1603232441 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 14837526987 ps |
| CPU time | 117.85 seconds |
| Started | Mar 05 01:41:35 PM PST 24 |
| Finished | Mar 05 01:43:33 PM PST 24 |
| Peak memory | 259548 kb |
| Host | smart-1058c50b-522f-4f6a-8d8e-6cceba1c39b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1603232441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1603232441 |
| Directory | /workspace/33.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1586146463 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 5289286192 ps |
| CPU time | 27.65 seconds |
| Started | Mar 05 01:41:35 PM PST 24 |
| Finished | Mar 05 01:42:03 PM PST 24 |
| Peak memory | 237020 kb |
| Host | smart-2684d665-87c6-4795-b7de-57acb2110180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586146463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl e.1586146463 |
| Directory | /workspace/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/33.spi_device_flash_mode.758528358 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 3981795101 ps |
| CPU time | 12.85 seconds |
| Started | Mar 05 01:41:35 PM PST 24 |
| Finished | Mar 05 01:41:48 PM PST 24 |
| Peak memory | 240548 kb |
| Host | smart-50902565-316f-4537-becc-cd68cb27a77e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758528358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.758528358 |
| Directory | /workspace/33.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/33.spi_device_intercept.1085601002 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 261852452 ps |
| CPU time | 2.95 seconds |
| Started | Mar 05 01:41:30 PM PST 24 |
| Finished | Mar 05 01:41:33 PM PST 24 |
| Peak memory | 233272 kb |
| Host | smart-1588e0aa-5005-450b-995e-63801c36dede |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085601002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1085601002 |
| Directory | /workspace/33.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/33.spi_device_mailbox.2627375916 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2527903509 ps |
| CPU time | 13.45 seconds |
| Started | Mar 05 01:41:30 PM PST 24 |
| Finished | Mar 05 01:41:43 PM PST 24 |
| Peak memory | 233576 kb |
| Host | smart-fea7b83e-deba-4e81-a0f6-29f40a8547f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627375916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2627375916 |
| Directory | /workspace/33.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2219153586 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2081928740 ps |
| CPU time | 8.22 seconds |
| Started | Mar 05 01:41:31 PM PST 24 |
| Finished | Mar 05 01:41:40 PM PST 24 |
| Peak memory | 222432 kb |
| Host | smart-91c46d9b-36cc-4499-bac8-e279031d344e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219153586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa p.2219153586 |
| Directory | /workspace/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/33.spi_device_pass_cmd_filtering.271911658 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1102718885 ps |
| CPU time | 8.03 seconds |
| Started | Mar 05 01:41:28 PM PST 24 |
| Finished | Mar 05 01:41:37 PM PST 24 |
| Peak memory | 228916 kb |
| Host | smart-951c69bc-f2c1-41fc-afaf-4a372f250f48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271911658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.271911658 |
| Directory | /workspace/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/33.spi_device_read_buffer_direct.3842100939 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 13681634014 ps |
| CPU time | 6.66 seconds |
| Started | Mar 05 01:41:34 PM PST 24 |
| Finished | Mar 05 01:41:40 PM PST 24 |
| Peak memory | 222336 kb |
| Host | smart-0a074f2b-323d-49b1-a80f-a6e615160be4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3842100939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir ect.3842100939 |
| Directory | /workspace/33.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/33.spi_device_stress_all.1622046634 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 70994172420 ps |
| CPU time | 484.97 seconds |
| Started | Mar 05 01:41:43 PM PST 24 |
| Finished | Mar 05 01:49:49 PM PST 24 |
| Peak memory | 270360 kb |
| Host | smart-28ebcf3c-181b-4d23-a586-96915aaa2e5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622046634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre ss_all.1622046634 |
| Directory | /workspace/33.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/33.spi_device_tpm_all.3096559343 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 10598770465 ps |
| CPU time | 31.6 seconds |
| Started | Mar 05 01:41:29 PM PST 24 |
| Finished | Mar 05 01:42:01 PM PST 24 |
| Peak memory | 216264 kb |
| Host | smart-099eeab3-78fc-4e56-9de9-64cbf823a8c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096559343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3096559343 |
| Directory | /workspace/33.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.608892344 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 38722606020 ps |
| CPU time | 23.24 seconds |
| Started | Mar 05 01:41:28 PM PST 24 |
| Finished | Mar 05 01:41:52 PM PST 24 |
| Peak memory | 216348 kb |
| Host | smart-c54eac7a-a3a3-455d-9820-2d7aab83b061 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608892344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.608892344 |
| Directory | /workspace/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/33.spi_device_tpm_rw.1856727617 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 668895105 ps |
| CPU time | 2.42 seconds |
| Started | Mar 05 01:41:33 PM PST 24 |
| Finished | Mar 05 01:41:36 PM PST 24 |
| Peak memory | 216220 kb |
| Host | smart-c1b06163-a483-4996-9793-0ab473af6854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856727617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1856727617 |
| Directory | /workspace/33.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/33.spi_device_tpm_sts_read.2737335543 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 47025840 ps |
| CPU time | 0.81 seconds |
| Started | Mar 05 01:41:30 PM PST 24 |
| Finished | Mar 05 01:41:31 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-96d1d242-aa48-4fa3-a3ee-fada37e546a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737335543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2737335543 |
| Directory | /workspace/33.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/33.spi_device_upload.2912867330 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 280187884 ps |
| CPU time | 5.58 seconds |
| Started | Mar 05 01:41:38 PM PST 24 |
| Finished | Mar 05 01:41:44 PM PST 24 |
| Peak memory | 218236 kb |
| Host | smart-09c03137-a040-4703-911d-c32279be0abf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912867330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2912867330 |
| Directory | /workspace/33.spi_device_upload/latest |
| Test location | /workspace/coverage/default/34.spi_device_alert_test.2374716640 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 120366703 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 01:41:44 PM PST 24 |
| Finished | Mar 05 01:41:47 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-8c20ea79-cb03-4d7c-bb7f-dfb9aaa34839 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374716640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test. 2374716640 |
| Directory | /workspace/34.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/34.spi_device_cfg_cmd.2015435052 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2330810994 ps |
| CPU time | 8.84 seconds |
| Started | Mar 05 01:41:40 PM PST 24 |
| Finished | Mar 05 01:41:50 PM PST 24 |
| Peak memory | 224392 kb |
| Host | smart-b10e8c17-1a4d-4097-a445-0a4fb08fee46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015435052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2015435052 |
| Directory | /workspace/34.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/34.spi_device_csb_read.2923508710 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 18365370 ps |
| CPU time | 0.86 seconds |
| Started | Mar 05 01:41:41 PM PST 24 |
| Finished | Mar 05 01:41:43 PM PST 24 |
| Peak memory | 206028 kb |
| Host | smart-52644d5c-02ca-4b94-84f6-bea07742ccd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923508710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2923508710 |
| Directory | /workspace/34.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/34.spi_device_flash_all.3492785420 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 132830247926 ps |
| CPU time | 175.85 seconds |
| Started | Mar 05 01:41:35 PM PST 24 |
| Finished | Mar 05 01:44:32 PM PST 24 |
| Peak memory | 254408 kb |
| Host | smart-b321bf14-76fc-4a03-8801-6a3b4019f11a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492785420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3492785420 |
| Directory | /workspace/34.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/34.spi_device_flash_and_tpm.1026806871 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 137298258941 ps |
| CPU time | 207.28 seconds |
| Started | Mar 05 01:41:43 PM PST 24 |
| Finished | Mar 05 01:45:11 PM PST 24 |
| Peak memory | 252960 kb |
| Host | smart-7070cdea-c137-43fa-9894-d8c2793e7bfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026806871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1026806871 |
| Directory | /workspace/34.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/34.spi_device_flash_mode.1845626433 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 15058589683 ps |
| CPU time | 40.69 seconds |
| Started | Mar 05 01:41:38 PM PST 24 |
| Finished | Mar 05 01:42:19 PM PST 24 |
| Peak memory | 248716 kb |
| Host | smart-457ebddf-e40b-4bde-9c63-4d0d51260a05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845626433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1845626433 |
| Directory | /workspace/34.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/34.spi_device_intercept.932700159 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 520804918 ps |
| CPU time | 4.45 seconds |
| Started | Mar 05 01:41:36 PM PST 24 |
| Finished | Mar 05 01:41:41 PM PST 24 |
| Peak memory | 217380 kb |
| Host | smart-2fc5a946-d242-4a55-a95d-704c7ef1e87c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932700159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.932700159 |
| Directory | /workspace/34.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/34.spi_device_mailbox.3275876858 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 107298045063 ps |
| CPU time | 27.26 seconds |
| Started | Mar 05 01:41:38 PM PST 24 |
| Finished | Mar 05 01:42:05 PM PST 24 |
| Peak memory | 249164 kb |
| Host | smart-772db309-bf84-4ff4-8396-8fb610336ec0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275876858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3275876858 |
| Directory | /workspace/34.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1711276410 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 5305311626 ps |
| CPU time | 9.15 seconds |
| Started | Mar 05 01:41:36 PM PST 24 |
| Finished | Mar 05 01:41:46 PM PST 24 |
| Peak memory | 233336 kb |
| Host | smart-bcc88ed7-de9c-4f82-983c-73ae796fff19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711276410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa p.1711276410 |
| Directory | /workspace/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3808165016 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3706773998 ps |
| CPU time | 12.04 seconds |
| Started | Mar 05 01:41:37 PM PST 24 |
| Finished | Mar 05 01:41:49 PM PST 24 |
| Peak memory | 232636 kb |
| Host | smart-0e1aa921-bb67-40b1-bc43-6494cc6e50d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808165016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3808165016 |
| Directory | /workspace/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/34.spi_device_read_buffer_direct.3924014436 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 266612587 ps |
| CPU time | 3.24 seconds |
| Started | Mar 05 01:41:39 PM PST 24 |
| Finished | Mar 05 01:41:43 PM PST 24 |
| Peak memory | 218760 kb |
| Host | smart-a0246b97-5f3e-4721-a467-3ef81d5c5c75 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3924014436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir ect.3924014436 |
| Directory | /workspace/34.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/34.spi_device_stress_all.1080539032 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 222779332000 ps |
| CPU time | 284.11 seconds |
| Started | Mar 05 01:41:44 PM PST 24 |
| Finished | Mar 05 01:46:29 PM PST 24 |
| Peak memory | 282864 kb |
| Host | smart-617247b2-51f5-4d1a-9387-400233d78d35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080539032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre ss_all.1080539032 |
| Directory | /workspace/34.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/34.spi_device_tpm_all.1970229933 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 764458725 ps |
| CPU time | 5.66 seconds |
| Started | Mar 05 01:41:36 PM PST 24 |
| Finished | Mar 05 01:41:41 PM PST 24 |
| Peak memory | 216248 kb |
| Host | smart-8f3f712b-f5b2-4f5e-92c4-754077763e09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970229933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1970229933 |
| Directory | /workspace/34.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.269958583 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 31172630461 ps |
| CPU time | 9.49 seconds |
| Started | Mar 05 01:41:36 PM PST 24 |
| Finished | Mar 05 01:41:47 PM PST 24 |
| Peak memory | 216284 kb |
| Host | smart-900485bd-ee65-4e53-950d-9797bd5cf54a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269958583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.269958583 |
| Directory | /workspace/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/34.spi_device_tpm_rw.1471431481 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1427287296 ps |
| CPU time | 3.9 seconds |
| Started | Mar 05 01:41:40 PM PST 24 |
| Finished | Mar 05 01:41:44 PM PST 24 |
| Peak memory | 216412 kb |
| Host | smart-77e43a88-4b5e-4209-87ac-4da47b0a0c70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471431481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1471431481 |
| Directory | /workspace/34.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/34.spi_device_tpm_sts_read.3282284498 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 137839313 ps |
| CPU time | 1.01 seconds |
| Started | Mar 05 01:41:43 PM PST 24 |
| Finished | Mar 05 01:41:45 PM PST 24 |
| Peak memory | 205340 kb |
| Host | smart-5aec2b63-2bc7-4907-939d-09361d6d0f6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282284498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3282284498 |
| Directory | /workspace/34.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/34.spi_device_upload.3400593509 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 9027349053 ps |
| CPU time | 29.38 seconds |
| Started | Mar 05 01:41:37 PM PST 24 |
| Finished | Mar 05 01:42:07 PM PST 24 |
| Peak memory | 233292 kb |
| Host | smart-643cf755-7795-4d87-b593-6de82b8a13e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400593509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3400593509 |
| Directory | /workspace/34.spi_device_upload/latest |
| Test location | /workspace/coverage/default/35.spi_device_alert_test.962355139 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 13108375 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:41:53 PM PST 24 |
| Finished | Mar 05 01:41:54 PM PST 24 |
| Peak memory | 204268 kb |
| Host | smart-67fe145a-1613-4e0e-838d-814b975dbddf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962355139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.962355139 |
| Directory | /workspace/35.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/35.spi_device_cfg_cmd.3195019848 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3908410429 ps |
| CPU time | 8.99 seconds |
| Started | Mar 05 01:41:58 PM PST 24 |
| Finished | Mar 05 01:42:07 PM PST 24 |
| Peak memory | 233464 kb |
| Host | smart-759b39fb-f383-4e20-8b11-714a83229c41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195019848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3195019848 |
| Directory | /workspace/35.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/35.spi_device_csb_read.4253547107 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 67510459 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:41:44 PM PST 24 |
| Finished | Mar 05 01:41:46 PM PST 24 |
| Peak memory | 204960 kb |
| Host | smart-38fa4d3f-b4da-46bb-b36d-f51e32843a17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253547107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4253547107 |
| Directory | /workspace/35.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/35.spi_device_flash_all.2288356684 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 188751340382 ps |
| CPU time | 202.62 seconds |
| Started | Mar 05 01:41:51 PM PST 24 |
| Finished | Mar 05 01:45:14 PM PST 24 |
| Peak memory | 253636 kb |
| Host | smart-27969cf6-cf6c-4477-82f7-07cb0eb12d16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288356684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2288356684 |
| Directory | /workspace/35.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/35.spi_device_flash_and_tpm.272171812 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 14935632919 ps |
| CPU time | 32.65 seconds |
| Started | Mar 05 01:41:54 PM PST 24 |
| Finished | Mar 05 01:42:26 PM PST 24 |
| Peak memory | 221112 kb |
| Host | smart-fc07d789-bf8b-48ab-95ee-56c2ae25237e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272171812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.272171812 |
| Directory | /workspace/35.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.256710084 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 27337304738 ps |
| CPU time | 177.51 seconds |
| Started | Mar 05 01:41:50 PM PST 24 |
| Finished | Mar 05 01:44:48 PM PST 24 |
| Peak memory | 254960 kb |
| Host | smart-7c96209e-5a37-47bf-894e-cc384e37285b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256710084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle .256710084 |
| Directory | /workspace/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/35.spi_device_flash_mode.840997161 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 506626287 ps |
| CPU time | 9.15 seconds |
| Started | Mar 05 01:41:52 PM PST 24 |
| Finished | Mar 05 01:42:01 PM PST 24 |
| Peak memory | 236976 kb |
| Host | smart-222f92d3-0782-4032-aa87-5e87633bb5b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840997161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.840997161 |
| Directory | /workspace/35.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/35.spi_device_intercept.3292963965 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 15667133128 ps |
| CPU time | 12.69 seconds |
| Started | Mar 05 01:41:45 PM PST 24 |
| Finished | Mar 05 01:41:58 PM PST 24 |
| Peak memory | 233416 kb |
| Host | smart-da92824e-e13b-4a92-847a-3af41c8b378f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292963965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3292963965 |
| Directory | /workspace/35.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/35.spi_device_mailbox.2980098113 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4675983644 ps |
| CPU time | 8.81 seconds |
| Started | Mar 05 01:41:46 PM PST 24 |
| Finished | Mar 05 01:41:56 PM PST 24 |
| Peak memory | 224316 kb |
| Host | smart-17686049-b455-4b18-9321-6ba4d8149cd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980098113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2980098113 |
| Directory | /workspace/35.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1452952460 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1764189458 ps |
| CPU time | 4.97 seconds |
| Started | Mar 05 01:41:47 PM PST 24 |
| Finished | Mar 05 01:41:52 PM PST 24 |
| Peak memory | 233060 kb |
| Host | smart-401c7aa9-f6f7-4765-ab10-9630be0863b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452952460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa p.1452952460 |
| Directory | /workspace/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2032948789 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 25327974270 ps |
| CPU time | 21.94 seconds |
| Started | Mar 05 01:41:44 PM PST 24 |
| Finished | Mar 05 01:42:07 PM PST 24 |
| Peak memory | 232672 kb |
| Host | smart-e87598b4-6d54-4f6c-ae93-a6c43545d960 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032948789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2032948789 |
| Directory | /workspace/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/35.spi_device_read_buffer_direct.673481787 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1796473216 ps |
| CPU time | 5.71 seconds |
| Started | Mar 05 01:41:51 PM PST 24 |
| Finished | Mar 05 01:41:57 PM PST 24 |
| Peak memory | 221980 kb |
| Host | smart-b9a2315a-e177-4a77-8871-e4138f486d2c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=673481787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire ct.673481787 |
| Directory | /workspace/35.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/35.spi_device_stress_all.3795008954 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 950601621 ps |
| CPU time | 1.16 seconds |
| Started | Mar 05 01:41:54 PM PST 24 |
| Finished | Mar 05 01:41:55 PM PST 24 |
| Peak memory | 206652 kb |
| Host | smart-ed16f67c-d43f-44f7-b1e1-76c915370323 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795008954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre ss_all.3795008954 |
| Directory | /workspace/35.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/35.spi_device_tpm_all.1758960496 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 7177878654 ps |
| CPU time | 37.48 seconds |
| Started | Mar 05 01:41:41 PM PST 24 |
| Finished | Mar 05 01:42:19 PM PST 24 |
| Peak memory | 216320 kb |
| Host | smart-50f7c2f7-8e94-4eec-9438-206517fac884 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758960496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1758960496 |
| Directory | /workspace/35.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.163381450 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 13114889159 ps |
| CPU time | 24.82 seconds |
| Started | Mar 05 01:41:40 PM PST 24 |
| Finished | Mar 05 01:42:06 PM PST 24 |
| Peak memory | 216292 kb |
| Host | smart-bbd1ef7d-5d29-41df-a668-9d5506eaff35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163381450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.163381450 |
| Directory | /workspace/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/35.spi_device_tpm_rw.351950968 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1720029613 ps |
| CPU time | 4.55 seconds |
| Started | Mar 05 01:41:44 PM PST 24 |
| Finished | Mar 05 01:41:50 PM PST 24 |
| Peak memory | 216164 kb |
| Host | smart-c389ec08-45e0-4e30-8d31-fd9708e11cbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351950968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.351950968 |
| Directory | /workspace/35.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/35.spi_device_tpm_sts_read.535516418 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 499081609 ps |
| CPU time | 1.05 seconds |
| Started | Mar 05 01:41:41 PM PST 24 |
| Finished | Mar 05 01:41:42 PM PST 24 |
| Peak memory | 206388 kb |
| Host | smart-5365d0fb-1bb4-42b2-9922-095a01b5ee7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535516418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.535516418 |
| Directory | /workspace/35.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/35.spi_device_upload.408937741 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 36708233886 ps |
| CPU time | 27.91 seconds |
| Started | Mar 05 01:41:47 PM PST 24 |
| Finished | Mar 05 01:42:15 PM PST 24 |
| Peak memory | 217804 kb |
| Host | smart-8456af3a-bc0f-4e1d-a8d6-c15c102689db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408937741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.408937741 |
| Directory | /workspace/35.spi_device_upload/latest |
| Test location | /workspace/coverage/default/36.spi_device_alert_test.3942548758 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 41518298 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:41:59 PM PST 24 |
| Finished | Mar 05 01:42:00 PM PST 24 |
| Peak memory | 205228 kb |
| Host | smart-fd859f73-bd41-4209-add3-cf622ad18c45 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942548758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test. 3942548758 |
| Directory | /workspace/36.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/36.spi_device_cfg_cmd.1091462516 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 564231401 ps |
| CPU time | 2.77 seconds |
| Started | Mar 05 01:42:08 PM PST 24 |
| Finished | Mar 05 01:42:11 PM PST 24 |
| Peak memory | 233256 kb |
| Host | smart-d87922bb-4cfb-44ed-adec-130250331610 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091462516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1091462516 |
| Directory | /workspace/36.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/36.spi_device_csb_read.407140272 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 57626204 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:41:53 PM PST 24 |
| Finished | Mar 05 01:41:54 PM PST 24 |
| Peak memory | 206220 kb |
| Host | smart-f5dc8237-76bd-4923-bf9d-c6abcebc8bf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407140272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.407140272 |
| Directory | /workspace/36.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/36.spi_device_flash_all.3384631955 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 8743890452 ps |
| CPU time | 43.2 seconds |
| Started | Mar 05 01:41:59 PM PST 24 |
| Finished | Mar 05 01:42:42 PM PST 24 |
| Peak memory | 222544 kb |
| Host | smart-5455efec-555d-488f-b409-9356f674f43a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3384631955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3384631955 |
| Directory | /workspace/36.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/36.spi_device_flash_and_tpm.2033049350 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 11998123272 ps |
| CPU time | 81.14 seconds |
| Started | Mar 05 01:42:02 PM PST 24 |
| Finished | Mar 05 01:43:24 PM PST 24 |
| Peak memory | 249572 kb |
| Host | smart-8fb17432-6f18-4a0b-92fa-1623745468d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033049350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2033049350 |
| Directory | /workspace/36.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3296505398 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 7261919011 ps |
| CPU time | 91.62 seconds |
| Started | Mar 05 01:41:59 PM PST 24 |
| Finished | Mar 05 01:43:31 PM PST 24 |
| Peak memory | 256016 kb |
| Host | smart-508b8634-d19c-4ead-a5dd-95d41217af8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296505398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl e.3296505398 |
| Directory | /workspace/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/36.spi_device_flash_mode.842433638 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 4627002326 ps |
| CPU time | 26.25 seconds |
| Started | Mar 05 01:42:00 PM PST 24 |
| Finished | Mar 05 01:42:26 PM PST 24 |
| Peak memory | 232232 kb |
| Host | smart-471a4dbf-ad3e-406b-8166-b952ca97c232 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842433638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.842433638 |
| Directory | /workspace/36.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/36.spi_device_intercept.2701263685 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2312196866 ps |
| CPU time | 9.31 seconds |
| Started | Mar 05 01:42:01 PM PST 24 |
| Finished | Mar 05 01:42:10 PM PST 24 |
| Peak memory | 217900 kb |
| Host | smart-5d083430-5bf2-4ac6-8453-eb618b76c613 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701263685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2701263685 |
| Directory | /workspace/36.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/36.spi_device_mailbox.835781969 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 16173036459 ps |
| CPU time | 46.35 seconds |
| Started | Mar 05 01:42:05 PM PST 24 |
| Finished | Mar 05 01:42:51 PM PST 24 |
| Peak memory | 222276 kb |
| Host | smart-f1d70918-11ac-48ee-a914-47bc161d130e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835781969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.835781969 |
| Directory | /workspace/36.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2449892483 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2097610768 ps |
| CPU time | 9.17 seconds |
| Started | Mar 05 01:41:56 PM PST 24 |
| Finished | Mar 05 01:42:05 PM PST 24 |
| Peak memory | 224272 kb |
| Host | smart-8ea8ace9-0eab-4c0f-952e-3fed44088a91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2449892483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa p.2449892483 |
| Directory | /workspace/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2618989129 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 6674850744 ps |
| CPU time | 22.69 seconds |
| Started | Mar 05 01:41:57 PM PST 24 |
| Finished | Mar 05 01:42:20 PM PST 24 |
| Peak memory | 224344 kb |
| Host | smart-308c2189-6c7e-4898-ae9e-dbd81e83eee8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618989129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2618989129 |
| Directory | /workspace/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/36.spi_device_read_buffer_direct.2418719594 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 115533914 ps |
| CPU time | 3.42 seconds |
| Started | Mar 05 01:42:04 PM PST 24 |
| Finished | Mar 05 01:42:08 PM PST 24 |
| Peak memory | 219004 kb |
| Host | smart-1be34a33-4002-47c9-a737-230598c13c3b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2418719594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir ect.2418719594 |
| Directory | /workspace/36.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/36.spi_device_tpm_all.686491141 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 32892637901 ps |
| CPU time | 50.95 seconds |
| Started | Mar 05 01:41:52 PM PST 24 |
| Finished | Mar 05 01:42:43 PM PST 24 |
| Peak memory | 216224 kb |
| Host | smart-b4f83c1e-daff-4c1e-a5b4-1b056d7e9195 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686491141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.686491141 |
| Directory | /workspace/36.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2356054820 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2211272854 ps |
| CPU time | 7.32 seconds |
| Started | Mar 05 01:41:56 PM PST 24 |
| Finished | Mar 05 01:42:04 PM PST 24 |
| Peak memory | 208176 kb |
| Host | smart-b8c81887-bc6e-42ad-ae7f-3c91235bff6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356054820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2356054820 |
| Directory | /workspace/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/36.spi_device_tpm_rw.3668417813 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 23786668 ps |
| CPU time | 0.81 seconds |
| Started | Mar 05 01:41:51 PM PST 24 |
| Finished | Mar 05 01:41:52 PM PST 24 |
| Peak memory | 205316 kb |
| Host | smart-a76874f0-a180-4278-8e27-565602eabea6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3668417813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3668417813 |
| Directory | /workspace/36.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/36.spi_device_tpm_sts_read.1768653267 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 25910920 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:41:50 PM PST 24 |
| Finished | Mar 05 01:41:51 PM PST 24 |
| Peak memory | 205372 kb |
| Host | smart-6fa95c5a-0bdd-446d-9111-d21cedbd2fe8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768653267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1768653267 |
| Directory | /workspace/36.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/36.spi_device_upload.3470060503 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 92003092 ps |
| CPU time | 2.5 seconds |
| Started | Mar 05 01:41:59 PM PST 24 |
| Finished | Mar 05 01:42:02 PM PST 24 |
| Peak memory | 217140 kb |
| Host | smart-87e7ec39-3632-4f4f-a666-20553560d8ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470060503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3470060503 |
| Directory | /workspace/36.spi_device_upload/latest |
| Test location | /workspace/coverage/default/37.spi_device_alert_test.2730888121 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 43299991 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:42:15 PM PST 24 |
| Finished | Mar 05 01:42:15 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-cd8c3970-47cb-48b8-bd1a-60c1237704c9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730888121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test. 2730888121 |
| Directory | /workspace/37.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/37.spi_device_cfg_cmd.3758869565 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 607335120 ps |
| CPU time | 3.77 seconds |
| Started | Mar 05 01:42:04 PM PST 24 |
| Finished | Mar 05 01:42:08 PM PST 24 |
| Peak memory | 217560 kb |
| Host | smart-8f00537b-4650-4051-ac29-6d2953267704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3758869565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3758869565 |
| Directory | /workspace/37.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/37.spi_device_csb_read.2531758886 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 128269490 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:42:09 PM PST 24 |
| Finished | Mar 05 01:42:10 PM PST 24 |
| Peak memory | 205264 kb |
| Host | smart-563b1086-2674-45ad-9138-1a9f8bf77edb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531758886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2531758886 |
| Directory | /workspace/37.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/37.spi_device_flash_all.4200479835 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 246731352727 ps |
| CPU time | 295.94 seconds |
| Started | Mar 05 01:42:05 PM PST 24 |
| Finished | Mar 05 01:47:01 PM PST 24 |
| Peak memory | 257068 kb |
| Host | smart-d85d2ced-ba19-4991-a207-be1a79dfc677 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200479835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4200479835 |
| Directory | /workspace/37.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/37.spi_device_flash_and_tpm.3430951513 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 24844709143 ps |
| CPU time | 102.37 seconds |
| Started | Mar 05 01:42:08 PM PST 24 |
| Finished | Mar 05 01:43:51 PM PST 24 |
| Peak memory | 236516 kb |
| Host | smart-0bc647ab-f3b4-4b75-ad9b-a75a7a378183 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430951513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3430951513 |
| Directory | /workspace/37.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2763244283 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 23322648968 ps |
| CPU time | 105.45 seconds |
| Started | Mar 05 01:42:07 PM PST 24 |
| Finished | Mar 05 01:43:52 PM PST 24 |
| Peak memory | 249168 kb |
| Host | smart-0e6aa8e5-de32-41f0-b333-42322d6cd821 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763244283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl e.2763244283 |
| Directory | /workspace/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/37.spi_device_flash_mode.2466123400 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 8469568694 ps |
| CPU time | 40.11 seconds |
| Started | Mar 05 01:42:09 PM PST 24 |
| Finished | Mar 05 01:42:49 PM PST 24 |
| Peak memory | 234956 kb |
| Host | smart-b097e91f-cf30-47fd-80b1-d1a48bed4c79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466123400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2466123400 |
| Directory | /workspace/37.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/37.spi_device_intercept.1788273531 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 991779765 ps |
| CPU time | 7.18 seconds |
| Started | Mar 05 01:42:07 PM PST 24 |
| Finished | Mar 05 01:42:14 PM PST 24 |
| Peak memory | 233004 kb |
| Host | smart-eb6864ce-f1c1-41c4-b65b-e7a7d6a33704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788273531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1788273531 |
| Directory | /workspace/37.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/37.spi_device_mailbox.2655126128 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 495098628 ps |
| CPU time | 7.91 seconds |
| Started | Mar 05 01:42:03 PM PST 24 |
| Finished | Mar 05 01:42:11 PM PST 24 |
| Peak memory | 233512 kb |
| Host | smart-be964330-2227-4afd-9f05-66059673ae14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655126128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2655126128 |
| Directory | /workspace/37.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.786345602 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 4889066418 ps |
| CPU time | 15.29 seconds |
| Started | Mar 05 01:42:09 PM PST 24 |
| Finished | Mar 05 01:42:24 PM PST 24 |
| Peak memory | 224328 kb |
| Host | smart-a8fabb5f-a97f-44ec-a82a-6f150d9847a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786345602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap .786345602 |
| Directory | /workspace/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2283614521 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 709419335 ps |
| CPU time | 4.87 seconds |
| Started | Mar 05 01:42:07 PM PST 24 |
| Finished | Mar 05 01:42:12 PM PST 24 |
| Peak memory | 224316 kb |
| Host | smart-f8399fde-73c4-415b-8f9c-29398d96206e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283614521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2283614521 |
| Directory | /workspace/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/37.spi_device_read_buffer_direct.3190658946 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 856829289 ps |
| CPU time | 5.28 seconds |
| Started | Mar 05 01:42:04 PM PST 24 |
| Finished | Mar 05 01:42:09 PM PST 24 |
| Peak memory | 222656 kb |
| Host | smart-d6690112-3589-475c-946c-d0e38b68cc7e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3190658946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir ect.3190658946 |
| Directory | /workspace/37.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/37.spi_device_stress_all.2528752432 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 25354272395 ps |
| CPU time | 125.97 seconds |
| Started | Mar 05 01:42:19 PM PST 24 |
| Finished | Mar 05 01:44:25 PM PST 24 |
| Peak memory | 255268 kb |
| Host | smart-949f7d7f-25a4-4f87-b157-5dcafea58530 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528752432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre ss_all.2528752432 |
| Directory | /workspace/37.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/37.spi_device_tpm_all.3777887879 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 23472126958 ps |
| CPU time | 15.93 seconds |
| Started | Mar 05 01:42:08 PM PST 24 |
| Finished | Mar 05 01:42:24 PM PST 24 |
| Peak memory | 216256 kb |
| Host | smart-799749db-21fb-4e88-a7ab-6ddb47fae247 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777887879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3777887879 |
| Directory | /workspace/37.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3311004030 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 5992751359 ps |
| CPU time | 4.06 seconds |
| Started | Mar 05 01:42:07 PM PST 24 |
| Finished | Mar 05 01:42:12 PM PST 24 |
| Peak memory | 216312 kb |
| Host | smart-6b7fc2aa-f3a3-4a79-a6d2-90cb09951bbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311004030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3311004030 |
| Directory | /workspace/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/37.spi_device_tpm_rw.1566503977 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 661059630 ps |
| CPU time | 6.32 seconds |
| Started | Mar 05 01:42:03 PM PST 24 |
| Finished | Mar 05 01:42:10 PM PST 24 |
| Peak memory | 216320 kb |
| Host | smart-3a3cd336-1ee6-41ac-9946-01e383986722 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566503977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1566503977 |
| Directory | /workspace/37.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/37.spi_device_tpm_sts_read.4085704890 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 172135735 ps |
| CPU time | 0.96 seconds |
| Started | Mar 05 01:42:07 PM PST 24 |
| Finished | Mar 05 01:42:08 PM PST 24 |
| Peak memory | 206372 kb |
| Host | smart-1bf8e77a-e947-43b6-ae86-ceada06de07d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4085704890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4085704890 |
| Directory | /workspace/37.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/37.spi_device_upload.952155479 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 563052825 ps |
| CPU time | 5.78 seconds |
| Started | Mar 05 01:42:09 PM PST 24 |
| Finished | Mar 05 01:42:15 PM PST 24 |
| Peak memory | 239044 kb |
| Host | smart-2def2dfd-2fbc-450d-af4b-878620ea3d59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952155479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.952155479 |
| Directory | /workspace/37.spi_device_upload/latest |
| Test location | /workspace/coverage/default/38.spi_device_alert_test.903598117 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 48034497 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:42:23 PM PST 24 |
| Finished | Mar 05 01:42:24 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-ba95bcb0-6a05-4f39-adcb-6ffb34852bfb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903598117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.903598117 |
| Directory | /workspace/38.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/38.spi_device_cfg_cmd.703478362 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 89364714 ps |
| CPU time | 2.92 seconds |
| Started | Mar 05 01:42:23 PM PST 24 |
| Finished | Mar 05 01:42:26 PM PST 24 |
| Peak memory | 233544 kb |
| Host | smart-d3c8b939-c133-4298-815f-7156d2f4b5ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703478362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.703478362 |
| Directory | /workspace/38.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/38.spi_device_csb_read.2628406414 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 60712886 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:42:19 PM PST 24 |
| Finished | Mar 05 01:42:20 PM PST 24 |
| Peak memory | 206216 kb |
| Host | smart-9dc87c6c-89b2-479d-919e-f4d2428b48be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628406414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2628406414 |
| Directory | /workspace/38.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/38.spi_device_flash_all.3461191549 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 21597765684 ps |
| CPU time | 114.8 seconds |
| Started | Mar 05 01:42:20 PM PST 24 |
| Finished | Mar 05 01:44:15 PM PST 24 |
| Peak memory | 257048 kb |
| Host | smart-65cd6239-03db-487e-8915-9ead7ec63a61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461191549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3461191549 |
| Directory | /workspace/38.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/38.spi_device_flash_and_tpm.701856709 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4243607413 ps |
| CPU time | 48.74 seconds |
| Started | Mar 05 01:42:21 PM PST 24 |
| Finished | Mar 05 01:43:10 PM PST 24 |
| Peak memory | 249144 kb |
| Host | smart-1c826f8f-318b-4f09-8cc5-2e6d2eed9c6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701856709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.701856709 |
| Directory | /workspace/38.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1049053462 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 38998349129 ps |
| CPU time | 299.64 seconds |
| Started | Mar 05 01:42:20 PM PST 24 |
| Finished | Mar 05 01:47:20 PM PST 24 |
| Peak memory | 266032 kb |
| Host | smart-1166dd85-3e0b-4899-95a3-ae113380c0c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049053462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl e.1049053462 |
| Directory | /workspace/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/38.spi_device_flash_mode.1321969111 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 4583434787 ps |
| CPU time | 25.6 seconds |
| Started | Mar 05 01:42:22 PM PST 24 |
| Finished | Mar 05 01:42:48 PM PST 24 |
| Peak memory | 223316 kb |
| Host | smart-78df19ba-26c1-4d84-854c-374a51b47fb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321969111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1321969111 |
| Directory | /workspace/38.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/38.spi_device_intercept.3948585451 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2711922881 ps |
| CPU time | 9.72 seconds |
| Started | Mar 05 01:42:14 PM PST 24 |
| Finished | Mar 05 01:42:23 PM PST 24 |
| Peak memory | 219292 kb |
| Host | smart-734d7424-fbec-4cda-99b7-0c16b9251b69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948585451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3948585451 |
| Directory | /workspace/38.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/38.spi_device_mailbox.784519190 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4545819523 ps |
| CPU time | 13.48 seconds |
| Started | Mar 05 01:42:11 PM PST 24 |
| Finished | Mar 05 01:42:25 PM PST 24 |
| Peak memory | 224396 kb |
| Host | smart-741d670a-1035-4bc1-9586-4b54a361ee0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784519190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.784519190 |
| Directory | /workspace/38.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1215211498 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 632367802 ps |
| CPU time | 3.01 seconds |
| Started | Mar 05 01:42:15 PM PST 24 |
| Finished | Mar 05 01:42:18 PM PST 24 |
| Peak memory | 224372 kb |
| Host | smart-0267b8f8-f640-4b74-8a38-0f8a03711c6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215211498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa p.1215211498 |
| Directory | /workspace/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/38.spi_device_pass_cmd_filtering.110441042 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1211304601 ps |
| CPU time | 6.65 seconds |
| Started | Mar 05 01:42:17 PM PST 24 |
| Finished | Mar 05 01:42:23 PM PST 24 |
| Peak memory | 233312 kb |
| Host | smart-b0806004-f88d-4acc-8321-9be155f0156d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110441042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.110441042 |
| Directory | /workspace/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/38.spi_device_read_buffer_direct.2207223307 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 21077400004 ps |
| CPU time | 6.28 seconds |
| Started | Mar 05 01:42:22 PM PST 24 |
| Finished | Mar 05 01:42:28 PM PST 24 |
| Peak memory | 222180 kb |
| Host | smart-fdda0bf9-752b-4d40-bad1-fbbd08d772ae |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2207223307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir ect.2207223307 |
| Directory | /workspace/38.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/38.spi_device_stress_all.2026839819 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5598325178 ps |
| CPU time | 69.14 seconds |
| Started | Mar 05 01:42:23 PM PST 24 |
| Finished | Mar 05 01:43:32 PM PST 24 |
| Peak memory | 249168 kb |
| Host | smart-1eacca09-1719-4d21-b97a-fa061cbb0ef4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026839819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre ss_all.2026839819 |
| Directory | /workspace/38.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/38.spi_device_tpm_all.2373648724 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 3525666271 ps |
| CPU time | 36.75 seconds |
| Started | Mar 05 01:42:19 PM PST 24 |
| Finished | Mar 05 01:42:56 PM PST 24 |
| Peak memory | 216312 kb |
| Host | smart-5e58707d-edf5-4a64-a23d-9c65cafb95ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373648724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2373648724 |
| Directory | /workspace/38.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.562317616 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1776929058 ps |
| CPU time | 11.14 seconds |
| Started | Mar 05 01:42:14 PM PST 24 |
| Finished | Mar 05 01:42:25 PM PST 24 |
| Peak memory | 216240 kb |
| Host | smart-40778d2f-2c8b-431e-ab13-9cb1448788bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562317616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.562317616 |
| Directory | /workspace/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/38.spi_device_tpm_rw.1201515278 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 464823818 ps |
| CPU time | 4.41 seconds |
| Started | Mar 05 01:42:15 PM PST 24 |
| Finished | Mar 05 01:42:20 PM PST 24 |
| Peak memory | 216256 kb |
| Host | smart-651d237f-ad8d-4fdb-9b3d-3cbbea42c9e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201515278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1201515278 |
| Directory | /workspace/38.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/38.spi_device_tpm_sts_read.3900116165 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 351119496 ps |
| CPU time | 0.87 seconds |
| Started | Mar 05 01:42:15 PM PST 24 |
| Finished | Mar 05 01:42:16 PM PST 24 |
| Peak memory | 206388 kb |
| Host | smart-4aa699d6-0865-4056-9787-b11bce6fbb72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900116165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3900116165 |
| Directory | /workspace/38.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/38.spi_device_upload.317362814 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1618060852 ps |
| CPU time | 9.96 seconds |
| Started | Mar 05 01:42:20 PM PST 24 |
| Finished | Mar 05 01:42:30 PM PST 24 |
| Peak memory | 233436 kb |
| Host | smart-4851037f-24a2-47b8-8d20-e8b0f1f35ba9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317362814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.317362814 |
| Directory | /workspace/38.spi_device_upload/latest |
| Test location | /workspace/coverage/default/39.spi_device_alert_test.924226461 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 21677269 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 01:42:32 PM PST 24 |
| Finished | Mar 05 01:42:33 PM PST 24 |
| Peak memory | 204232 kb |
| Host | smart-a2bc6b66-0367-4b8a-a79a-9705384ffa40 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924226461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.924226461 |
| Directory | /workspace/39.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/39.spi_device_cfg_cmd.461916531 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 419523416 ps |
| CPU time | 4.04 seconds |
| Started | Mar 05 01:42:30 PM PST 24 |
| Finished | Mar 05 01:42:34 PM PST 24 |
| Peak memory | 232956 kb |
| Host | smart-589bcbbc-79d6-47fe-89a0-59a0a373c831 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461916531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.461916531 |
| Directory | /workspace/39.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/39.spi_device_csb_read.147754645 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 27120100 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:42:28 PM PST 24 |
| Finished | Mar 05 01:42:28 PM PST 24 |
| Peak memory | 205312 kb |
| Host | smart-8c29adaa-a5c6-46eb-8cb5-9e5e80e5a9b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147754645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.147754645 |
| Directory | /workspace/39.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/39.spi_device_flash_all.875310751 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 64423951340 ps |
| CPU time | 318.4 seconds |
| Started | Mar 05 01:42:34 PM PST 24 |
| Finished | Mar 05 01:47:53 PM PST 24 |
| Peak memory | 265380 kb |
| Host | smart-39036d7e-2c79-4cf5-90e8-680fa32ba50c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875310751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.875310751 |
| Directory | /workspace/39.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/39.spi_device_flash_mode.583062521 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2648678848 ps |
| CPU time | 9.5 seconds |
| Started | Mar 05 01:42:33 PM PST 24 |
| Finished | Mar 05 01:42:42 PM PST 24 |
| Peak memory | 224376 kb |
| Host | smart-f8527298-748e-4b90-ae4b-f9c83f9c1150 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583062521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.583062521 |
| Directory | /workspace/39.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/39.spi_device_intercept.70864407 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7599857779 ps |
| CPU time | 8.25 seconds |
| Started | Mar 05 01:42:22 PM PST 24 |
| Finished | Mar 05 01:42:30 PM PST 24 |
| Peak memory | 239148 kb |
| Host | smart-0cde68d2-4fc0-4c93-8f54-c31a36fdf2ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70864407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.70864407 |
| Directory | /workspace/39.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/39.spi_device_mailbox.4025437432 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 88134633 ps |
| CPU time | 3.03 seconds |
| Started | Mar 05 01:42:25 PM PST 24 |
| Finished | Mar 05 01:42:28 PM PST 24 |
| Peak memory | 233336 kb |
| Host | smart-21163ed1-43ec-419d-ab22-fd9ffae4aef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025437432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4025437432 |
| Directory | /workspace/39.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3600991228 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 13694837967 ps |
| CPU time | 9.63 seconds |
| Started | Mar 05 01:42:24 PM PST 24 |
| Finished | Mar 05 01:42:33 PM PST 24 |
| Peak memory | 224384 kb |
| Host | smart-03ca2b3d-8166-4884-bb5c-14b898d0f52a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600991228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa p.3600991228 |
| Directory | /workspace/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4113118575 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 18102192765 ps |
| CPU time | 44.96 seconds |
| Started | Mar 05 01:42:20 PM PST 24 |
| Finished | Mar 05 01:43:05 PM PST 24 |
| Peak memory | 232600 kb |
| Host | smart-e8f049d4-5bc3-49e9-9471-01ffdba89be5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113118575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4113118575 |
| Directory | /workspace/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/39.spi_device_read_buffer_direct.3465430191 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 302299737 ps |
| CPU time | 3.83 seconds |
| Started | Mar 05 01:42:28 PM PST 24 |
| Finished | Mar 05 01:42:32 PM PST 24 |
| Peak memory | 222368 kb |
| Host | smart-d9961529-6d38-45d8-900e-b45daedaa933 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3465430191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir ect.3465430191 |
| Directory | /workspace/39.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/39.spi_device_tpm_all.1407357799 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 6174877633 ps |
| CPU time | 22.37 seconds |
| Started | Mar 05 01:42:18 PM PST 24 |
| Finished | Mar 05 01:42:41 PM PST 24 |
| Peak memory | 216308 kb |
| Host | smart-70eb3cc6-c9d5-4df2-bcd6-0e752b7d46e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407357799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1407357799 |
| Directory | /workspace/39.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1678502992 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 19602099981 ps |
| CPU time | 17.88 seconds |
| Started | Mar 05 01:42:22 PM PST 24 |
| Finished | Mar 05 01:42:40 PM PST 24 |
| Peak memory | 216296 kb |
| Host | smart-344f5382-f7b6-4815-b822-c32e5ebb93fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678502992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1678502992 |
| Directory | /workspace/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/39.spi_device_tpm_rw.329836331 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 459358474 ps |
| CPU time | 3.65 seconds |
| Started | Mar 05 01:42:24 PM PST 24 |
| Finished | Mar 05 01:42:28 PM PST 24 |
| Peak memory | 216180 kb |
| Host | smart-5c974514-3650-4667-b7e2-1b8c8a5bcee4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329836331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.329836331 |
| Directory | /workspace/39.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/39.spi_device_tpm_sts_read.3336616349 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 176062509 ps |
| CPU time | 0.82 seconds |
| Started | Mar 05 01:42:19 PM PST 24 |
| Finished | Mar 05 01:42:20 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-c4987f92-1adf-4b7b-b086-d28ed0860511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3336616349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3336616349 |
| Directory | /workspace/39.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/39.spi_device_upload.2581743438 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 20086868083 ps |
| CPU time | 22.08 seconds |
| Started | Mar 05 01:42:31 PM PST 24 |
| Finished | Mar 05 01:42:54 PM PST 24 |
| Peak memory | 238612 kb |
| Host | smart-9e19dbd0-d424-4e33-a3c3-68f48fc7ec73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581743438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2581743438 |
| Directory | /workspace/39.spi_device_upload/latest |
| Test location | /workspace/coverage/default/4.spi_device_alert_test.3322782779 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 11470974 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:36:56 PM PST 24 |
| Finished | Mar 05 01:36:57 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-6afff166-09a9-45de-86f0-7d26a3d0017e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322782779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3 322782779 |
| Directory | /workspace/4.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/4.spi_device_cfg_cmd.4235019549 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 749880206 ps |
| CPU time | 4.65 seconds |
| Started | Mar 05 01:36:56 PM PST 24 |
| Finished | Mar 05 01:37:01 PM PST 24 |
| Peak memory | 233668 kb |
| Host | smart-9a33272a-fece-4b83-9e8b-f5236858c35d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235019549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4235019549 |
| Directory | /workspace/4.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/4.spi_device_csb_read.2856233838 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 36941139 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:36:50 PM PST 24 |
| Finished | Mar 05 01:36:52 PM PST 24 |
| Peak memory | 206216 kb |
| Host | smart-a576ab96-d7a3-4488-9050-b83a6378b82d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856233838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2856233838 |
| Directory | /workspace/4.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/4.spi_device_flash_all.144999335 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 27699256989 ps |
| CPU time | 46.78 seconds |
| Started | Mar 05 01:36:53 PM PST 24 |
| Finished | Mar 05 01:37:40 PM PST 24 |
| Peak memory | 235884 kb |
| Host | smart-f9e95986-2f4f-4415-ad48-13dea9616ceb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=144999335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.144999335 |
| Directory | /workspace/4.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/4.spi_device_flash_and_tpm.3194584064 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 2094162479 ps |
| CPU time | 38.68 seconds |
| Started | Mar 05 01:36:53 PM PST 24 |
| Finished | Mar 05 01:37:32 PM PST 24 |
| Peak memory | 251312 kb |
| Host | smart-599a1bc6-9a40-4599-9b5f-e0e5e1efea55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194584064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3194584064 |
| Directory | /workspace/4.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1786067578 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 41883671230 ps |
| CPU time | 376.35 seconds |
| Started | Mar 05 01:36:54 PM PST 24 |
| Finished | Mar 05 01:43:11 PM PST 24 |
| Peak memory | 265288 kb |
| Host | smart-6a7d9422-3cf7-4f40-8128-e1ae8833d1a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786067578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle .1786067578 |
| Directory | /workspace/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/4.spi_device_flash_mode.1202799208 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 9526204534 ps |
| CPU time | 25.21 seconds |
| Started | Mar 05 01:36:55 PM PST 24 |
| Finished | Mar 05 01:37:21 PM PST 24 |
| Peak memory | 243096 kb |
| Host | smart-4eb8ecaa-204d-4262-baf3-d3db0690d037 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202799208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1202799208 |
| Directory | /workspace/4.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/4.spi_device_intercept.3696698884 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 247471663 ps |
| CPU time | 5.04 seconds |
| Started | Mar 05 01:36:51 PM PST 24 |
| Finished | Mar 05 01:36:56 PM PST 24 |
| Peak memory | 233424 kb |
| Host | smart-72ef7f4b-daa9-4dc5-a450-f2a70ff1349e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696698884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3696698884 |
| Directory | /workspace/4.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/4.spi_device_mailbox.1543352674 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 9118314839 ps |
| CPU time | 30.98 seconds |
| Started | Mar 05 01:36:53 PM PST 24 |
| Finished | Mar 05 01:37:24 PM PST 24 |
| Peak memory | 244056 kb |
| Host | smart-c3785e68-e187-403e-bc90-566c72fa4faa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543352674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1543352674 |
| Directory | /workspace/4.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/4.spi_device_mem_parity.1957143946 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 15440751 ps |
| CPU time | 1.01 seconds |
| Started | Mar 05 01:36:43 PM PST 24 |
| Finished | Mar 05 01:36:45 PM PST 24 |
| Peak memory | 217772 kb |
| Host | smart-80d53cfd-44de-4dac-bcbf-895013a9b9da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957143946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.spi_device_mem_parity.1957143946 |
| Directory | /workspace/4.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2805651153 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3628107555 ps |
| CPU time | 12.96 seconds |
| Started | Mar 05 01:36:43 PM PST 24 |
| Finished | Mar 05 01:36:57 PM PST 24 |
| Peak memory | 225516 kb |
| Host | smart-702f0376-a3bb-41ac-9508-3dde2abfa4ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805651153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap .2805651153 |
| Directory | /workspace/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1084725367 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1405619508 ps |
| CPU time | 10.93 seconds |
| Started | Mar 05 01:36:45 PM PST 24 |
| Finished | Mar 05 01:36:56 PM PST 24 |
| Peak memory | 248376 kb |
| Host | smart-c5977245-9ab0-4ed1-abec-448bee16e954 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084725367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1084725367 |
| Directory | /workspace/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/4.spi_device_ram_cfg.1658557631 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 19252489 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:36:44 PM PST 24 |
| Finished | Mar 05 01:36:46 PM PST 24 |
| Peak memory | 216040 kb |
| Host | smart-373749dc-bf42-4b29-ad2f-d0a035be1737 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658557631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1658557631 |
| Directory | /workspace/4.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/4.spi_device_read_buffer_direct.2051598927 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 470515672 ps |
| CPU time | 4.15 seconds |
| Started | Mar 05 01:36:55 PM PST 24 |
| Finished | Mar 05 01:36:59 PM PST 24 |
| Peak memory | 218488 kb |
| Host | smart-03e143c1-11d3-4ac3-a19b-6b650d39c8b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2051598927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire ct.2051598927 |
| Directory | /workspace/4.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/4.spi_device_sec_cm.2741803545 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 109752321 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:36:54 PM PST 24 |
| Finished | Mar 05 01:36:56 PM PST 24 |
| Peak memory | 235108 kb |
| Host | smart-10e8771e-9a71-4b4d-8578-7e3f135283cc |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741803545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2741803545 |
| Directory | /workspace/4.spi_device_sec_cm/latest |
| Test location | /workspace/coverage/default/4.spi_device_stress_all.3607105959 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 51584688 ps |
| CPU time | 1.01 seconds |
| Started | Mar 05 01:36:56 PM PST 24 |
| Finished | Mar 05 01:36:57 PM PST 24 |
| Peak memory | 206140 kb |
| Host | smart-81e00d86-ff1c-4f09-aa5f-d326f459a84a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607105959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres s_all.3607105959 |
| Directory | /workspace/4.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/4.spi_device_tpm_all.2431713984 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1807556734 ps |
| CPU time | 24.97 seconds |
| Started | Mar 05 01:36:43 PM PST 24 |
| Finished | Mar 05 01:37:09 PM PST 24 |
| Peak memory | 216256 kb |
| Host | smart-007d6dc3-8272-48a7-a0f7-ac901435541a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431713984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2431713984 |
| Directory | /workspace/4.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3691928839 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 13316282064 ps |
| CPU time | 9.32 seconds |
| Started | Mar 05 01:36:51 PM PST 24 |
| Finished | Mar 05 01:37:00 PM PST 24 |
| Peak memory | 216212 kb |
| Host | smart-e85c3169-bb2f-40c7-a377-4981f1b72edb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691928839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3691928839 |
| Directory | /workspace/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/4.spi_device_tpm_rw.1555829499 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 68389652 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:36:45 PM PST 24 |
| Finished | Mar 05 01:36:47 PM PST 24 |
| Peak memory | 207644 kb |
| Host | smart-02905ee8-878b-488d-90b2-0097777c81d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1555829499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1555829499 |
| Directory | /workspace/4.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/4.spi_device_tpm_sts_read.167238031 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 82893904 ps |
| CPU time | 0.96 seconds |
| Started | Mar 05 01:36:43 PM PST 24 |
| Finished | Mar 05 01:36:45 PM PST 24 |
| Peak memory | 206380 kb |
| Host | smart-ce36c9f0-63cd-4888-b6d4-13e305cd20fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167238031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.167238031 |
| Directory | /workspace/4.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/4.spi_device_upload.947523236 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 29707764450 ps |
| CPU time | 13.09 seconds |
| Started | Mar 05 01:37:03 PM PST 24 |
| Finished | Mar 05 01:37:16 PM PST 24 |
| Peak memory | 232576 kb |
| Host | smart-0b475684-f14b-446f-b86d-65641219759d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947523236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.947523236 |
| Directory | /workspace/4.spi_device_upload/latest |
| Test location | /workspace/coverage/default/40.spi_device_alert_test.1116089408 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 38903885 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:42:38 PM PST 24 |
| Finished | Mar 05 01:42:40 PM PST 24 |
| Peak memory | 204844 kb |
| Host | smart-ddc1bc77-a616-40a9-a93e-580cb8a6a7d4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116089408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test. 1116089408 |
| Directory | /workspace/40.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/40.spi_device_cfg_cmd.3610963048 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 621017158 ps |
| CPU time | 2.75 seconds |
| Started | Mar 05 01:42:39 PM PST 24 |
| Finished | Mar 05 01:42:43 PM PST 24 |
| Peak memory | 233860 kb |
| Host | smart-40ed3177-885c-4a6c-ad7f-14b60f0c63ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610963048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3610963048 |
| Directory | /workspace/40.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/40.spi_device_csb_read.1664231642 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 55148649 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:42:33 PM PST 24 |
| Finished | Mar 05 01:42:35 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-ece76275-22f4-44c5-b275-07a218aeca32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664231642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1664231642 |
| Directory | /workspace/40.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/40.spi_device_flash_all.4000353719 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 148903478031 ps |
| CPU time | 169.35 seconds |
| Started | Mar 05 01:42:39 PM PST 24 |
| Finished | Mar 05 01:45:28 PM PST 24 |
| Peak memory | 240684 kb |
| Host | smart-d219f120-c054-48b0-916e-761db0530a67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000353719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4000353719 |
| Directory | /workspace/40.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/40.spi_device_flash_and_tpm.788416723 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 14451845691 ps |
| CPU time | 36.62 seconds |
| Started | Mar 05 01:42:41 PM PST 24 |
| Finished | Mar 05 01:43:18 PM PST 24 |
| Peak memory | 237252 kb |
| Host | smart-e647ec29-7ce7-427c-8c75-b55d852f25cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=788416723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.788416723 |
| Directory | /workspace/40.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3031589961 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 22888308680 ps |
| CPU time | 137.07 seconds |
| Started | Mar 05 01:42:39 PM PST 24 |
| Finished | Mar 05 01:44:57 PM PST 24 |
| Peak memory | 264672 kb |
| Host | smart-6077276a-9896-457e-baa2-6c592979f055 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031589961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl e.3031589961 |
| Directory | /workspace/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/40.spi_device_flash_mode.1444679421 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 12643026171 ps |
| CPU time | 35.41 seconds |
| Started | Mar 05 01:42:49 PM PST 24 |
| Finished | Mar 05 01:43:24 PM PST 24 |
| Peak memory | 247244 kb |
| Host | smart-1cdd61a0-6e9c-48e3-8f9d-82dcfe82e95c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444679421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1444679421 |
| Directory | /workspace/40.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/40.spi_device_intercept.2773367338 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 461902737 ps |
| CPU time | 2.77 seconds |
| Started | Mar 05 01:42:39 PM PST 24 |
| Finished | Mar 05 01:42:42 PM PST 24 |
| Peak memory | 233552 kb |
| Host | smart-c4745097-2f9c-4ac8-99ef-c00627387cb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773367338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2773367338 |
| Directory | /workspace/40.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/40.spi_device_mailbox.698291869 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2983521779 ps |
| CPU time | 12.03 seconds |
| Started | Mar 05 01:42:42 PM PST 24 |
| Finished | Mar 05 01:42:55 PM PST 24 |
| Peak memory | 216980 kb |
| Host | smart-33ecfd68-1fcb-49b0-a475-0f908e65ead6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698291869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.698291869 |
| Directory | /workspace/40.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2346828080 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1850352093 ps |
| CPU time | 7.92 seconds |
| Started | Mar 05 01:42:38 PM PST 24 |
| Finished | Mar 05 01:42:46 PM PST 24 |
| Peak memory | 233372 kb |
| Host | smart-f76ac3d4-658b-424f-92bb-e9c89690e11e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346828080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa p.2346828080 |
| Directory | /workspace/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1807912576 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2886152307 ps |
| CPU time | 10.12 seconds |
| Started | Mar 05 01:42:38 PM PST 24 |
| Finished | Mar 05 01:42:48 PM PST 24 |
| Peak memory | 233496 kb |
| Host | smart-348efb84-3ebf-4c78-8892-2bfc6a9c87a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807912576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1807912576 |
| Directory | /workspace/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/40.spi_device_read_buffer_direct.2391635573 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 821582841 ps |
| CPU time | 3.96 seconds |
| Started | Mar 05 01:42:43 PM PST 24 |
| Finished | Mar 05 01:42:47 PM PST 24 |
| Peak memory | 218384 kb |
| Host | smart-cdf76a91-1efc-4858-aef5-9fa4aa3ae6d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2391635573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir ect.2391635573 |
| Directory | /workspace/40.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/40.spi_device_stress_all.3589959690 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 54958735 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:42:47 PM PST 24 |
| Finished | Mar 05 01:42:49 PM PST 24 |
| Peak memory | 206552 kb |
| Host | smart-588487e5-39bb-41fe-82d4-3390e44c4e93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589959690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre ss_all.3589959690 |
| Directory | /workspace/40.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/40.spi_device_tpm_all.446881068 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 24152793117 ps |
| CPU time | 46.05 seconds |
| Started | Mar 05 01:42:31 PM PST 24 |
| Finished | Mar 05 01:43:18 PM PST 24 |
| Peak memory | 216340 kb |
| Host | smart-489f689b-ceba-40d1-b050-61313e3b84bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446881068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.446881068 |
| Directory | /workspace/40.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.757357443 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 28875171118 ps |
| CPU time | 22.88 seconds |
| Started | Mar 05 01:42:33 PM PST 24 |
| Finished | Mar 05 01:42:57 PM PST 24 |
| Peak memory | 216260 kb |
| Host | smart-fa397a01-ecdd-41e9-836e-336084e7f49e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=757357443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.757357443 |
| Directory | /workspace/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/40.spi_device_tpm_rw.243836768 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 24385345 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:42:42 PM PST 24 |
| Finished | Mar 05 01:42:44 PM PST 24 |
| Peak memory | 205360 kb |
| Host | smart-a9c90fff-bac4-4996-bdec-d1efe06ce1cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243836768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.243836768 |
| Directory | /workspace/40.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/40.spi_device_tpm_sts_read.215545156 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 60494062 ps |
| CPU time | 0.91 seconds |
| Started | Mar 05 01:42:42 PM PST 24 |
| Finished | Mar 05 01:42:43 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-1ccad6b7-2011-4265-a3b2-3ecf7f7600e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215545156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.215545156 |
| Directory | /workspace/40.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/40.spi_device_upload.587931186 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 49806515 ps |
| CPU time | 2.68 seconds |
| Started | Mar 05 01:42:42 PM PST 24 |
| Finished | Mar 05 01:42:46 PM PST 24 |
| Peak memory | 232580 kb |
| Host | smart-a9cfd48e-bb05-4300-8547-a6e7740a608a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587931186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.587931186 |
| Directory | /workspace/40.spi_device_upload/latest |
| Test location | /workspace/coverage/default/41.spi_device_alert_test.2044223544 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 17876618 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:42:50 PM PST 24 |
| Finished | Mar 05 01:42:51 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-fba8e3b4-d6e3-45cd-8173-4b65d5921497 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044223544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test. 2044223544 |
| Directory | /workspace/41.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/41.spi_device_cfg_cmd.4017933710 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2017351961 ps |
| CPU time | 3.78 seconds |
| Started | Mar 05 01:42:45 PM PST 24 |
| Finished | Mar 05 01:42:49 PM PST 24 |
| Peak memory | 224384 kb |
| Host | smart-38ec6f23-8372-48a2-8490-35f3a891ad62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017933710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4017933710 |
| Directory | /workspace/41.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/41.spi_device_csb_read.1578005650 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 114838733 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:42:40 PM PST 24 |
| Finished | Mar 05 01:42:42 PM PST 24 |
| Peak memory | 204940 kb |
| Host | smart-c9307689-f454-4e12-b631-b832626e4053 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578005650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1578005650 |
| Directory | /workspace/41.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/41.spi_device_flash_all.104191128 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 11645060928 ps |
| CPU time | 50.8 seconds |
| Started | Mar 05 01:42:45 PM PST 24 |
| Finished | Mar 05 01:43:36 PM PST 24 |
| Peak memory | 232584 kb |
| Host | smart-2da2cf08-bce4-4514-a73c-a969acce4b38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104191128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.104191128 |
| Directory | /workspace/41.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/41.spi_device_flash_and_tpm.2597868599 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 31170694380 ps |
| CPU time | 205.98 seconds |
| Started | Mar 05 01:42:47 PM PST 24 |
| Finished | Mar 05 01:46:13 PM PST 24 |
| Peak memory | 239592 kb |
| Host | smart-18ec4be6-5265-4fa2-992e-339f2bea191c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597868599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2597868599 |
| Directory | /workspace/41.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2739222699 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 95315530190 ps |
| CPU time | 329.4 seconds |
| Started | Mar 05 01:42:47 PM PST 24 |
| Finished | Mar 05 01:48:17 PM PST 24 |
| Peak memory | 240248 kb |
| Host | smart-db38c5fe-b970-4a6b-84a5-a5af45b7f414 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739222699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl e.2739222699 |
| Directory | /workspace/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/41.spi_device_flash_mode.3215333703 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 515513732 ps |
| CPU time | 6.16 seconds |
| Started | Mar 05 01:42:47 PM PST 24 |
| Finished | Mar 05 01:42:53 PM PST 24 |
| Peak memory | 224376 kb |
| Host | smart-cfc71ad8-64ee-48c3-8b73-5959c791e45b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215333703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3215333703 |
| Directory | /workspace/41.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/41.spi_device_intercept.2066294731 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1867052312 ps |
| CPU time | 4.13 seconds |
| Started | Mar 05 01:42:47 PM PST 24 |
| Finished | Mar 05 01:42:52 PM PST 24 |
| Peak memory | 216496 kb |
| Host | smart-f94d542c-3c9e-4fe9-add6-eed086fa460e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2066294731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2066294731 |
| Directory | /workspace/41.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/41.spi_device_mailbox.2303742349 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 27424736252 ps |
| CPU time | 33.25 seconds |
| Started | Mar 05 01:42:44 PM PST 24 |
| Finished | Mar 05 01:43:18 PM PST 24 |
| Peak memory | 232560 kb |
| Host | smart-245621ae-c4d3-4b90-839c-8cc7d7fa0e9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303742349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2303742349 |
| Directory | /workspace/41.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2498798522 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 51080518448 ps |
| CPU time | 27.74 seconds |
| Started | Mar 05 01:42:42 PM PST 24 |
| Finished | Mar 05 01:43:11 PM PST 24 |
| Peak memory | 228932 kb |
| Host | smart-b6a3a9c5-205e-439a-8e2a-e4733718ddc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498798522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa p.2498798522 |
| Directory | /workspace/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3648840465 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 874481690 ps |
| CPU time | 5.12 seconds |
| Started | Mar 05 01:42:52 PM PST 24 |
| Finished | Mar 05 01:42:57 PM PST 24 |
| Peak memory | 233456 kb |
| Host | smart-e5169d55-89c0-4e4b-8c36-2530769e7067 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648840465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3648840465 |
| Directory | /workspace/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/41.spi_device_read_buffer_direct.2974200297 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 551444257 ps |
| CPU time | 3.74 seconds |
| Started | Mar 05 01:42:49 PM PST 24 |
| Finished | Mar 05 01:42:53 PM PST 24 |
| Peak memory | 222560 kb |
| Host | smart-e2e9bb8d-662f-4d3e-bdee-c29dcff05f8f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2974200297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir ect.2974200297 |
| Directory | /workspace/41.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/41.spi_device_stress_all.2929834383 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 75741867624 ps |
| CPU time | 363.36 seconds |
| Started | Mar 05 01:42:45 PM PST 24 |
| Finished | Mar 05 01:48:49 PM PST 24 |
| Peak memory | 265096 kb |
| Host | smart-190e2f73-c51b-455b-b189-665967791ee1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929834383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre ss_all.2929834383 |
| Directory | /workspace/41.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/41.spi_device_tpm_all.3744057736 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 124954481626 ps |
| CPU time | 54.37 seconds |
| Started | Mar 05 01:42:41 PM PST 24 |
| Finished | Mar 05 01:43:36 PM PST 24 |
| Peak memory | 216272 kb |
| Host | smart-3ff064b9-e493-4d85-adc9-5ae8912a0641 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744057736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3744057736 |
| Directory | /workspace/41.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2454870496 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1377587279 ps |
| CPU time | 9.15 seconds |
| Started | Mar 05 01:42:41 PM PST 24 |
| Finished | Mar 05 01:42:51 PM PST 24 |
| Peak memory | 216284 kb |
| Host | smart-4b04f825-9377-4aca-96a8-6ce128ffdc5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454870496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2454870496 |
| Directory | /workspace/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/41.spi_device_tpm_rw.3494991086 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 370793740 ps |
| CPU time | 2.07 seconds |
| Started | Mar 05 01:42:46 PM PST 24 |
| Finished | Mar 05 01:42:48 PM PST 24 |
| Peak memory | 216232 kb |
| Host | smart-5cd7cf97-462c-489d-92fb-fa043de4da9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494991086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3494991086 |
| Directory | /workspace/41.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/41.spi_device_tpm_sts_read.1095315814 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 403937958 ps |
| CPU time | 1.05 seconds |
| Started | Mar 05 01:42:48 PM PST 24 |
| Finished | Mar 05 01:42:49 PM PST 24 |
| Peak memory | 206384 kb |
| Host | smart-b5731b17-3673-42f6-91b6-3e6b65c52774 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095315814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1095315814 |
| Directory | /workspace/41.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/41.spi_device_upload.932227761 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 418459789 ps |
| CPU time | 3.31 seconds |
| Started | Mar 05 01:42:46 PM PST 24 |
| Finished | Mar 05 01:42:50 PM PST 24 |
| Peak memory | 218628 kb |
| Host | smart-2d5d57c4-d62b-415e-97d5-93987fd29c24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932227761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.932227761 |
| Directory | /workspace/41.spi_device_upload/latest |
| Test location | /workspace/coverage/default/42.spi_device_alert_test.87165362 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 15395591 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:42:53 PM PST 24 |
| Finished | Mar 05 01:42:54 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-2beb09bf-0ecc-4c12-b634-58d0bcb86d4f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87165362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.87165362 |
| Directory | /workspace/42.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/42.spi_device_cfg_cmd.2416032836 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 4732455223 ps |
| CPU time | 6.75 seconds |
| Started | Mar 05 01:42:53 PM PST 24 |
| Finished | Mar 05 01:43:00 PM PST 24 |
| Peak memory | 233568 kb |
| Host | smart-42b59004-feee-4dd6-9e05-16cde8cf0d09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416032836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2416032836 |
| Directory | /workspace/42.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/42.spi_device_csb_read.105434059 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 16063414 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:42:46 PM PST 24 |
| Finished | Mar 05 01:42:47 PM PST 24 |
| Peak memory | 204952 kb |
| Host | smart-cc641140-3419-43d3-949d-75c18b2e21c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105434059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.105434059 |
| Directory | /workspace/42.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/42.spi_device_flash_all.1851041203 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 4294465989 ps |
| CPU time | 34.65 seconds |
| Started | Mar 05 01:42:54 PM PST 24 |
| Finished | Mar 05 01:43:29 PM PST 24 |
| Peak memory | 240824 kb |
| Host | smart-310b3556-814b-4b40-88b0-32b17486278d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851041203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1851041203 |
| Directory | /workspace/42.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/42.spi_device_flash_and_tpm.2314248197 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 14107853130 ps |
| CPU time | 81.15 seconds |
| Started | Mar 05 01:42:56 PM PST 24 |
| Finished | Mar 05 01:44:17 PM PST 24 |
| Peak memory | 262392 kb |
| Host | smart-595242b9-23bb-4fa2-9b26-35ab20114838 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314248197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2314248197 |
| Directory | /workspace/42.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1441206051 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 71993428159 ps |
| CPU time | 103.51 seconds |
| Started | Mar 05 01:42:53 PM PST 24 |
| Finished | Mar 05 01:44:37 PM PST 24 |
| Peak memory | 257304 kb |
| Host | smart-fad68745-96e5-49ce-b48b-00b5ddfed5bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441206051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl e.1441206051 |
| Directory | /workspace/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/42.spi_device_flash_mode.2457348883 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2362865373 ps |
| CPU time | 8.91 seconds |
| Started | Mar 05 01:42:52 PM PST 24 |
| Finished | Mar 05 01:43:02 PM PST 24 |
| Peak memory | 240304 kb |
| Host | smart-8bae77b7-724d-4ca3-8069-3b6593c64218 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2457348883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2457348883 |
| Directory | /workspace/42.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/42.spi_device_intercept.787742609 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1917545923 ps |
| CPU time | 7.79 seconds |
| Started | Mar 05 01:42:51 PM PST 24 |
| Finished | Mar 05 01:43:00 PM PST 24 |
| Peak memory | 234160 kb |
| Host | smart-fae175a0-cb80-4966-aaf6-9d04af0985c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787742609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.787742609 |
| Directory | /workspace/42.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/42.spi_device_mailbox.1675590177 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 22455420398 ps |
| CPU time | 54.01 seconds |
| Started | Mar 05 01:42:56 PM PST 24 |
| Finished | Mar 05 01:43:51 PM PST 24 |
| Peak memory | 236912 kb |
| Host | smart-be6661bc-9931-4bc8-b184-7774fc3f61ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675590177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1675590177 |
| Directory | /workspace/42.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1662946459 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 329466575 ps |
| CPU time | 2.62 seconds |
| Started | Mar 05 01:42:55 PM PST 24 |
| Finished | Mar 05 01:42:58 PM PST 24 |
| Peak memory | 232612 kb |
| Host | smart-c08d551a-1395-45d8-850e-1d1e9c919c09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1662946459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa p.1662946459 |
| Directory | /workspace/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2742032597 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 24735313554 ps |
| CPU time | 20.75 seconds |
| Started | Mar 05 01:42:49 PM PST 24 |
| Finished | Mar 05 01:43:10 PM PST 24 |
| Peak memory | 235268 kb |
| Host | smart-ce727921-2354-488c-9189-89f696bca2f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2742032597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2742032597 |
| Directory | /workspace/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/42.spi_device_read_buffer_direct.2745966652 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 540366728 ps |
| CPU time | 3.02 seconds |
| Started | Mar 05 01:42:54 PM PST 24 |
| Finished | Mar 05 01:42:58 PM PST 24 |
| Peak memory | 219868 kb |
| Host | smart-52b1957c-2e36-48bd-8055-0e86fd408793 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2745966652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir ect.2745966652 |
| Directory | /workspace/42.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/42.spi_device_stress_all.3729677126 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 134735948665 ps |
| CPU time | 163.85 seconds |
| Started | Mar 05 01:42:53 PM PST 24 |
| Finished | Mar 05 01:45:37 PM PST 24 |
| Peak memory | 249520 kb |
| Host | smart-125304e9-9a7d-4277-9c07-edaa51f19029 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729677126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre ss_all.3729677126 |
| Directory | /workspace/42.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/42.spi_device_tpm_all.1085417515 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 28064828164 ps |
| CPU time | 37.97 seconds |
| Started | Mar 05 01:42:49 PM PST 24 |
| Finished | Mar 05 01:43:27 PM PST 24 |
| Peak memory | 216584 kb |
| Host | smart-24f18110-1819-4166-9378-2a5581365d47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085417515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1085417515 |
| Directory | /workspace/42.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2558147424 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2176789974 ps |
| CPU time | 6.52 seconds |
| Started | Mar 05 01:42:46 PM PST 24 |
| Finished | Mar 05 01:42:53 PM PST 24 |
| Peak memory | 216128 kb |
| Host | smart-742e1083-50f3-403d-8ca7-9e9dc0cf0f71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558147424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2558147424 |
| Directory | /workspace/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/42.spi_device_tpm_rw.3854800315 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 154887545 ps |
| CPU time | 1.83 seconds |
| Started | Mar 05 01:42:48 PM PST 24 |
| Finished | Mar 05 01:42:50 PM PST 24 |
| Peak memory | 216168 kb |
| Host | smart-95ebce73-fe5e-490d-aff5-b811850cd3d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854800315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3854800315 |
| Directory | /workspace/42.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/42.spi_device_tpm_sts_read.2072251631 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 211956293 ps |
| CPU time | 0.96 seconds |
| Started | Mar 05 01:42:48 PM PST 24 |
| Finished | Mar 05 01:42:49 PM PST 24 |
| Peak memory | 206380 kb |
| Host | smart-a13a82e2-7130-4a87-8ee3-8250e084e77b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072251631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2072251631 |
| Directory | /workspace/42.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/42.spi_device_upload.2822183534 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 1662871569 ps |
| CPU time | 9.27 seconds |
| Started | Mar 05 01:42:54 PM PST 24 |
| Finished | Mar 05 01:43:03 PM PST 24 |
| Peak memory | 233404 kb |
| Host | smart-8f4988dd-327e-40ac-b1d6-1ffc56b0bdac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822183534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2822183534 |
| Directory | /workspace/42.spi_device_upload/latest |
| Test location | /workspace/coverage/default/43.spi_device_alert_test.2734361889 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 18431416 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:43:00 PM PST 24 |
| Finished | Mar 05 01:43:01 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-c5937f6d-0973-40d7-bbe6-a8f86e4582d5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734361889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test. 2734361889 |
| Directory | /workspace/43.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/43.spi_device_cfg_cmd.2810134154 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 484646727 ps |
| CPU time | 4.61 seconds |
| Started | Mar 05 01:43:00 PM PST 24 |
| Finished | Mar 05 01:43:05 PM PST 24 |
| Peak memory | 233472 kb |
| Host | smart-cd69d7c2-6889-4ffa-bae9-3ba059ec3cbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2810134154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2810134154 |
| Directory | /workspace/43.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/43.spi_device_csb_read.2673047203 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 30828601 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:42:54 PM PST 24 |
| Finished | Mar 05 01:42:55 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-abdbb2b9-b9b7-473b-914c-871a32d5a744 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673047203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2673047203 |
| Directory | /workspace/43.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/43.spi_device_flash_all.1978921528 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 84653448846 ps |
| CPU time | 131.27 seconds |
| Started | Mar 05 01:43:05 PM PST 24 |
| Finished | Mar 05 01:45:16 PM PST 24 |
| Peak memory | 257172 kb |
| Host | smart-eb58130c-cf0f-4bd0-a46b-1572c0e9f701 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978921528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1978921528 |
| Directory | /workspace/43.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1195553001 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 7202222544 ps |
| CPU time | 81.97 seconds |
| Started | Mar 05 01:43:00 PM PST 24 |
| Finished | Mar 05 01:44:23 PM PST 24 |
| Peak memory | 251480 kb |
| Host | smart-4c30ae8c-e8d3-4f84-880b-d210039efdfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195553001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl e.1195553001 |
| Directory | /workspace/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/43.spi_device_flash_mode.3965892375 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 8594008687 ps |
| CPU time | 25.77 seconds |
| Started | Mar 05 01:43:06 PM PST 24 |
| Finished | Mar 05 01:43:32 PM PST 24 |
| Peak memory | 244636 kb |
| Host | smart-1d5e699b-5185-4e15-b899-d91f120e990e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965892375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3965892375 |
| Directory | /workspace/43.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/43.spi_device_intercept.1654472438 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1859542530 ps |
| CPU time | 4.13 seconds |
| Started | Mar 05 01:43:00 PM PST 24 |
| Finished | Mar 05 01:43:05 PM PST 24 |
| Peak memory | 224344 kb |
| Host | smart-29798f9d-568f-4177-9779-c64d63e12df0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654472438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1654472438 |
| Directory | /workspace/43.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/43.spi_device_mailbox.3602994269 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 985585434 ps |
| CPU time | 8.8 seconds |
| Started | Mar 05 01:43:02 PM PST 24 |
| Finished | Mar 05 01:43:11 PM PST 24 |
| Peak memory | 235804 kb |
| Host | smart-38ef00ea-5e63-4887-a83b-05871ac95d4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602994269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3602994269 |
| Directory | /workspace/43.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2970694478 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 4140376089 ps |
| CPU time | 14.43 seconds |
| Started | Mar 05 01:43:00 PM PST 24 |
| Finished | Mar 05 01:43:15 PM PST 24 |
| Peak memory | 233564 kb |
| Host | smart-00d57c2a-3c7b-4bd4-8f83-f81d79a2a47c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970694478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa p.2970694478 |
| Directory | /workspace/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3335269258 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 7384985300 ps |
| CPU time | 11.89 seconds |
| Started | Mar 05 01:43:00 PM PST 24 |
| Finished | Mar 05 01:43:12 PM PST 24 |
| Peak memory | 237532 kb |
| Host | smart-3beb1cca-98f1-4e84-b44f-09c5963d6f7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335269258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3335269258 |
| Directory | /workspace/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/43.spi_device_read_buffer_direct.2413537781 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 7931065272 ps |
| CPU time | 6.95 seconds |
| Started | Mar 05 01:43:02 PM PST 24 |
| Finished | Mar 05 01:43:09 PM PST 24 |
| Peak memory | 221912 kb |
| Host | smart-c77adc28-a8bf-49f5-bae4-05dd7fdcbb32 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2413537781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir ect.2413537781 |
| Directory | /workspace/43.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/43.spi_device_stress_all.4030551629 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 69958450696 ps |
| CPU time | 271.18 seconds |
| Started | Mar 05 01:43:02 PM PST 24 |
| Finished | Mar 05 01:47:34 PM PST 24 |
| Peak memory | 289556 kb |
| Host | smart-0beaefb9-fa4a-4aeb-b90e-567bc0cad4ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030551629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre ss_all.4030551629 |
| Directory | /workspace/43.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/43.spi_device_tpm_all.2450392736 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2820484785 ps |
| CPU time | 37.12 seconds |
| Started | Mar 05 01:42:55 PM PST 24 |
| Finished | Mar 05 01:43:32 PM PST 24 |
| Peak memory | 216408 kb |
| Host | smart-b7b35d7f-90a3-4b37-b3de-584118ccf20c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450392736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2450392736 |
| Directory | /workspace/43.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1832044546 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 160619918 ps |
| CPU time | 1.5 seconds |
| Started | Mar 05 01:42:58 PM PST 24 |
| Finished | Mar 05 01:42:59 PM PST 24 |
| Peak memory | 206628 kb |
| Host | smart-aeb9717b-87c4-4a79-812a-8d5c0ce5f019 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832044546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1832044546 |
| Directory | /workspace/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/43.spi_device_tpm_rw.3997255242 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 72390422 ps |
| CPU time | 1.13 seconds |
| Started | Mar 05 01:42:52 PM PST 24 |
| Finished | Mar 05 01:42:54 PM PST 24 |
| Peak memory | 207040 kb |
| Host | smart-03fe1e62-4f9d-4d1c-a8db-b8eed06c9bb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997255242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3997255242 |
| Directory | /workspace/43.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/43.spi_device_tpm_sts_read.3763865443 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 130846752 ps |
| CPU time | 0.9 seconds |
| Started | Mar 05 01:42:54 PM PST 24 |
| Finished | Mar 05 01:42:55 PM PST 24 |
| Peak memory | 206328 kb |
| Host | smart-fef3bb4c-09dc-4cf4-8a1a-377b70546932 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763865443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3763865443 |
| Directory | /workspace/43.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/43.spi_device_upload.300195028 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2472354650 ps |
| CPU time | 4.54 seconds |
| Started | Mar 05 01:43:03 PM PST 24 |
| Finished | Mar 05 01:43:08 PM PST 24 |
| Peak memory | 219396 kb |
| Host | smart-205cc04f-9139-479c-adbf-8bd3dbc4a8e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300195028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.300195028 |
| Directory | /workspace/43.spi_device_upload/latest |
| Test location | /workspace/coverage/default/44.spi_device_alert_test.2823155896 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 40901242 ps |
| CPU time | 0.69 seconds |
| Started | Mar 05 01:43:12 PM PST 24 |
| Finished | Mar 05 01:43:13 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-c08d423a-3524-4eb5-8e06-0422de437bfd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823155896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test. 2823155896 |
| Directory | /workspace/44.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/44.spi_device_cfg_cmd.1334898991 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 103963204 ps |
| CPU time | 3 seconds |
| Started | Mar 05 01:43:12 PM PST 24 |
| Finished | Mar 05 01:43:16 PM PST 24 |
| Peak memory | 233468 kb |
| Host | smart-2ecb2f3d-0684-4558-a275-65aa139f8c94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334898991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1334898991 |
| Directory | /workspace/44.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/44.spi_device_csb_read.532174737 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 150496147 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:43:02 PM PST 24 |
| Finished | Mar 05 01:43:04 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-c0c76317-c467-4a2e-a019-8578856d5f67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532174737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.532174737 |
| Directory | /workspace/44.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/44.spi_device_flash_all.287389461 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 8552075682 ps |
| CPU time | 87.08 seconds |
| Started | Mar 05 01:43:10 PM PST 24 |
| Finished | Mar 05 01:44:37 PM PST 24 |
| Peak memory | 261728 kb |
| Host | smart-2bf59dac-8a1e-4f20-b883-5acb42b908bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287389461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.287389461 |
| Directory | /workspace/44.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/44.spi_device_flash_and_tpm.2775027427 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 320394008767 ps |
| CPU time | 390.41 seconds |
| Started | Mar 05 01:43:07 PM PST 24 |
| Finished | Mar 05 01:49:38 PM PST 24 |
| Peak memory | 253544 kb |
| Host | smart-264bd5a4-1757-41e5-be33-e979b5cfefb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2775027427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2775027427 |
| Directory | /workspace/44.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2480990605 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1711279791 ps |
| CPU time | 33.35 seconds |
| Started | Mar 05 01:43:08 PM PST 24 |
| Finished | Mar 05 01:43:42 PM PST 24 |
| Peak memory | 237020 kb |
| Host | smart-f1bf7a05-736e-43a8-8869-fc002160718e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480990605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl e.2480990605 |
| Directory | /workspace/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/44.spi_device_flash_mode.3863485063 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 263054340 ps |
| CPU time | 5.82 seconds |
| Started | Mar 05 01:43:09 PM PST 24 |
| Finished | Mar 05 01:43:16 PM PST 24 |
| Peak memory | 234908 kb |
| Host | smart-6ff54045-9134-4af1-b76e-50a32469ef47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863485063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3863485063 |
| Directory | /workspace/44.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/44.spi_device_intercept.1966148710 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 386581141 ps |
| CPU time | 3.37 seconds |
| Started | Mar 05 01:43:02 PM PST 24 |
| Finished | Mar 05 01:43:06 PM PST 24 |
| Peak memory | 219252 kb |
| Host | smart-8ad2c851-9871-4066-a524-6ac44904f9b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966148710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1966148710 |
| Directory | /workspace/44.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/44.spi_device_mailbox.3118203564 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 767125153 ps |
| CPU time | 6.93 seconds |
| Started | Mar 05 01:43:10 PM PST 24 |
| Finished | Mar 05 01:43:17 PM PST 24 |
| Peak memory | 233432 kb |
| Host | smart-bad5d893-a5e5-454b-81dc-245c91fb3b86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118203564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3118203564 |
| Directory | /workspace/44.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.876480793 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 302139011 ps |
| CPU time | 2.21 seconds |
| Started | Mar 05 01:43:03 PM PST 24 |
| Finished | Mar 05 01:43:06 PM PST 24 |
| Peak memory | 216480 kb |
| Host | smart-cae2c0d9-d47b-479d-ba45-cd0e1d958f8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876480793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap .876480793 |
| Directory | /workspace/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/44.spi_device_pass_cmd_filtering.706804350 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1728932843 ps |
| CPU time | 3.98 seconds |
| Started | Mar 05 01:43:03 PM PST 24 |
| Finished | Mar 05 01:43:07 PM PST 24 |
| Peak memory | 219236 kb |
| Host | smart-9603d676-49e8-4a3c-b224-146df73b23c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706804350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.706804350 |
| Directory | /workspace/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/44.spi_device_read_buffer_direct.290630373 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1823103543 ps |
| CPU time | 5.25 seconds |
| Started | Mar 05 01:43:12 PM PST 24 |
| Finished | Mar 05 01:43:18 PM PST 24 |
| Peak memory | 218340 kb |
| Host | smart-f0ae0db2-9090-4841-8c4b-a77b14c69034 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=290630373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire ct.290630373 |
| Directory | /workspace/44.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/44.spi_device_tpm_all.616540411 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4067932394 ps |
| CPU time | 14.46 seconds |
| Started | Mar 05 01:43:02 PM PST 24 |
| Finished | Mar 05 01:43:17 PM PST 24 |
| Peak memory | 216332 kb |
| Host | smart-fdce30c9-a3c4-412b-97cf-3f865de2a6e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616540411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.616540411 |
| Directory | /workspace/44.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.787052283 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 7639821570 ps |
| CPU time | 23.36 seconds |
| Started | Mar 05 01:43:02 PM PST 24 |
| Finished | Mar 05 01:43:26 PM PST 24 |
| Peak memory | 216312 kb |
| Host | smart-aeaa9140-f438-4e86-bb3d-dc9b5f18ebd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787052283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.787052283 |
| Directory | /workspace/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/44.spi_device_tpm_rw.3855564969 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 34351554 ps |
| CPU time | 1.33 seconds |
| Started | Mar 05 01:43:03 PM PST 24 |
| Finished | Mar 05 01:43:05 PM PST 24 |
| Peak memory | 216168 kb |
| Host | smart-26b13d02-935b-45b9-bae7-6b7902e63e0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855564969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3855564969 |
| Directory | /workspace/44.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/44.spi_device_tpm_sts_read.3882452547 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 54643676 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:43:01 PM PST 24 |
| Finished | Mar 05 01:43:02 PM PST 24 |
| Peak memory | 205332 kb |
| Host | smart-197e8900-3a71-45d1-9a2c-d78eb68da996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882452547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3882452547 |
| Directory | /workspace/44.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/44.spi_device_upload.1236161799 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 80516150050 ps |
| CPU time | 24.94 seconds |
| Started | Mar 05 01:43:08 PM PST 24 |
| Finished | Mar 05 01:43:33 PM PST 24 |
| Peak memory | 230056 kb |
| Host | smart-455a8816-f7d8-42b4-9cce-d4d6fe5faaed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236161799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1236161799 |
| Directory | /workspace/44.spi_device_upload/latest |
| Test location | /workspace/coverage/default/45.spi_device_alert_test.3532215042 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 124410250 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:43:23 PM PST 24 |
| Finished | Mar 05 01:43:24 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-de2b78eb-9934-42db-8092-138633366261 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532215042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test. 3532215042 |
| Directory | /workspace/45.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/45.spi_device_cfg_cmd.1613250065 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 601654869 ps |
| CPU time | 5.39 seconds |
| Started | Mar 05 01:43:18 PM PST 24 |
| Finished | Mar 05 01:43:23 PM PST 24 |
| Peak memory | 238232 kb |
| Host | smart-0757e2f3-ddbe-4017-b66e-52ed9e80b0b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613250065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1613250065 |
| Directory | /workspace/45.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/45.spi_device_csb_read.2137589720 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 16101449 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:43:08 PM PST 24 |
| Finished | Mar 05 01:43:09 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-d80f6a34-103e-4c8a-a4ee-a2e83f758453 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137589720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2137589720 |
| Directory | /workspace/45.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/45.spi_device_flash_all.1229144730 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 13420377296 ps |
| CPU time | 16.29 seconds |
| Started | Mar 05 01:43:20 PM PST 24 |
| Finished | Mar 05 01:43:37 PM PST 24 |
| Peak memory | 224396 kb |
| Host | smart-112a90e3-717e-4c68-ba8d-5ba594aee6f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229144730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1229144730 |
| Directory | /workspace/45.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/45.spi_device_flash_and_tpm.1544515766 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 7857180402 ps |
| CPU time | 46.27 seconds |
| Started | Mar 05 01:43:25 PM PST 24 |
| Finished | Mar 05 01:44:12 PM PST 24 |
| Peak memory | 250068 kb |
| Host | smart-e89c87af-6eb8-4ca4-8c28-90fb6c9613dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544515766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1544515766 |
| Directory | /workspace/45.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1786201195 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 19106810261 ps |
| CPU time | 54.39 seconds |
| Started | Mar 05 01:43:25 PM PST 24 |
| Finished | Mar 05 01:44:20 PM PST 24 |
| Peak memory | 224008 kb |
| Host | smart-a568b371-97ad-42d4-ab6c-c32f824abd9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786201195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl e.1786201195 |
| Directory | /workspace/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/45.spi_device_intercept.3554647259 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1370630317 ps |
| CPU time | 5.86 seconds |
| Started | Mar 05 01:43:17 PM PST 24 |
| Finished | Mar 05 01:43:23 PM PST 24 |
| Peak memory | 224184 kb |
| Host | smart-f8b4ea17-7d7e-4b46-8e0a-57de08b858b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554647259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3554647259 |
| Directory | /workspace/45.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/45.spi_device_mailbox.262039414 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 45665011844 ps |
| CPU time | 28.09 seconds |
| Started | Mar 05 01:43:17 PM PST 24 |
| Finished | Mar 05 01:43:45 PM PST 24 |
| Peak memory | 233536 kb |
| Host | smart-f4ce92f2-a85c-450c-b176-04b0435a0689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262039414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.262039414 |
| Directory | /workspace/45.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2477576915 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 10506910933 ps |
| CPU time | 16.87 seconds |
| Started | Mar 05 01:43:23 PM PST 24 |
| Finished | Mar 05 01:43:41 PM PST 24 |
| Peak memory | 233472 kb |
| Host | smart-ec5a9ec6-1b17-45bc-99d6-ebd6b96b2195 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2477576915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa p.2477576915 |
| Directory | /workspace/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1290985386 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1450658481 ps |
| CPU time | 5.48 seconds |
| Started | Mar 05 01:43:17 PM PST 24 |
| Finished | Mar 05 01:43:23 PM PST 24 |
| Peak memory | 233372 kb |
| Host | smart-720cba9b-956d-448f-8978-ce4911dbfb70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290985386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1290985386 |
| Directory | /workspace/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/45.spi_device_read_buffer_direct.54769956 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 208520594 ps |
| CPU time | 3.9 seconds |
| Started | Mar 05 01:43:22 PM PST 24 |
| Finished | Mar 05 01:43:27 PM PST 24 |
| Peak memory | 222472 kb |
| Host | smart-87ceec35-77c1-4515-bd28-f61dbdaf3e40 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=54769956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direc t.54769956 |
| Directory | /workspace/45.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/45.spi_device_tpm_all.177136716 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2332267788 ps |
| CPU time | 26.16 seconds |
| Started | Mar 05 01:43:12 PM PST 24 |
| Finished | Mar 05 01:43:39 PM PST 24 |
| Peak memory | 216360 kb |
| Host | smart-02caebe6-af39-4996-a1cf-4183c8700f11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177136716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.177136716 |
| Directory | /workspace/45.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3663524012 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 5144415697 ps |
| CPU time | 5.88 seconds |
| Started | Mar 05 01:43:07 PM PST 24 |
| Finished | Mar 05 01:43:13 PM PST 24 |
| Peak memory | 216172 kb |
| Host | smart-14b15f11-3dc3-4eba-acbe-f77967bda9cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3663524012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3663524012 |
| Directory | /workspace/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/45.spi_device_tpm_rw.1323347928 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 48286837 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:43:18 PM PST 24 |
| Finished | Mar 05 01:43:19 PM PST 24 |
| Peak memory | 206868 kb |
| Host | smart-e45a089b-f87e-458e-b360-0ddab5a186e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323347928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1323347928 |
| Directory | /workspace/45.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/45.spi_device_tpm_sts_read.2014407458 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 669040670 ps |
| CPU time | 1.13 seconds |
| Started | Mar 05 01:43:19 PM PST 24 |
| Finished | Mar 05 01:43:21 PM PST 24 |
| Peak memory | 206236 kb |
| Host | smart-a8bbc63c-b991-403f-81e6-2b9bd59fc6d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014407458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2014407458 |
| Directory | /workspace/45.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/45.spi_device_upload.3350009914 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3886688647 ps |
| CPU time | 11.12 seconds |
| Started | Mar 05 01:43:18 PM PST 24 |
| Finished | Mar 05 01:43:30 PM PST 24 |
| Peak memory | 234028 kb |
| Host | smart-04277bf9-6002-401b-84c4-61c1872269f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350009914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3350009914 |
| Directory | /workspace/45.spi_device_upload/latest |
| Test location | /workspace/coverage/default/46.spi_device_alert_test.3633972936 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 13071884 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:43:32 PM PST 24 |
| Finished | Mar 05 01:43:33 PM PST 24 |
| Peak memory | 204864 kb |
| Host | smart-6df543fc-17a5-4661-ac57-40348026125c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633972936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test. 3633972936 |
| Directory | /workspace/46.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/46.spi_device_cfg_cmd.2780618012 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 5841298229 ps |
| CPU time | 6.24 seconds |
| Started | Mar 05 01:43:26 PM PST 24 |
| Finished | Mar 05 01:43:33 PM PST 24 |
| Peak memory | 219940 kb |
| Host | smart-d46b8c69-42c7-41d5-af6c-5838e594db14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780618012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2780618012 |
| Directory | /workspace/46.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/46.spi_device_csb_read.3787281121 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 41114580 ps |
| CPU time | 0.78 seconds |
| Started | Mar 05 01:43:24 PM PST 24 |
| Finished | Mar 05 01:43:25 PM PST 24 |
| Peak memory | 205880 kb |
| Host | smart-3acefcfa-f401-42a2-8a9e-2901568735e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787281121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3787281121 |
| Directory | /workspace/46.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/46.spi_device_flash_all.1493052581 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 25970569758 ps |
| CPU time | 76.33 seconds |
| Started | Mar 05 01:43:25 PM PST 24 |
| Finished | Mar 05 01:44:42 PM PST 24 |
| Peak memory | 254692 kb |
| Host | smart-56557b60-50e0-4681-a3c6-121b77e808f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493052581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1493052581 |
| Directory | /workspace/46.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/46.spi_device_flash_and_tpm.1278759880 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 25771560630 ps |
| CPU time | 47.73 seconds |
| Started | Mar 05 01:43:25 PM PST 24 |
| Finished | Mar 05 01:44:13 PM PST 24 |
| Peak memory | 232748 kb |
| Host | smart-b2126d36-3896-49b0-bd43-33f224afa5c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278759880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1278759880 |
| Directory | /workspace/46.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1143271358 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 64376708254 ps |
| CPU time | 312.6 seconds |
| Started | Mar 05 01:43:24 PM PST 24 |
| Finished | Mar 05 01:48:37 PM PST 24 |
| Peak memory | 263256 kb |
| Host | smart-273d2e92-80d1-4604-a8e5-2ab894107b7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143271358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl e.1143271358 |
| Directory | /workspace/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/46.spi_device_flash_mode.397764012 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 34197512079 ps |
| CPU time | 47.06 seconds |
| Started | Mar 05 01:43:27 PM PST 24 |
| Finished | Mar 05 01:44:15 PM PST 24 |
| Peak memory | 240688 kb |
| Host | smart-0f7d2338-ae78-4565-afcc-4b9a53cccc30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397764012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.397764012 |
| Directory | /workspace/46.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/46.spi_device_intercept.2505563772 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2491650922 ps |
| CPU time | 4.99 seconds |
| Started | Mar 05 01:43:26 PM PST 24 |
| Finished | Mar 05 01:43:31 PM PST 24 |
| Peak memory | 219608 kb |
| Host | smart-b02b7bc6-30d7-4153-a606-09b2a8c03a49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505563772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2505563772 |
| Directory | /workspace/46.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/46.spi_device_mailbox.3363433179 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 20334170320 ps |
| CPU time | 33.76 seconds |
| Started | Mar 05 01:43:23 PM PST 24 |
| Finished | Mar 05 01:43:57 PM PST 24 |
| Peak memory | 235224 kb |
| Host | smart-8011d4d5-f769-4436-b04f-f65133d357a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363433179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3363433179 |
| Directory | /workspace/46.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.143009589 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 1699004463 ps |
| CPU time | 8.29 seconds |
| Started | Mar 05 01:43:26 PM PST 24 |
| Finished | Mar 05 01:43:34 PM PST 24 |
| Peak memory | 232540 kb |
| Host | smart-f64361b7-397b-4324-81a9-ddd2bacb4ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143009589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap .143009589 |
| Directory | /workspace/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3715049389 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 665745674 ps |
| CPU time | 7.74 seconds |
| Started | Mar 05 01:43:24 PM PST 24 |
| Finished | Mar 05 01:43:32 PM PST 24 |
| Peak memory | 235088 kb |
| Host | smart-d4f57b19-4f0a-413b-be45-f7ce4de4ae85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715049389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3715049389 |
| Directory | /workspace/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/46.spi_device_read_buffer_direct.1202700596 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2682611936 ps |
| CPU time | 4.23 seconds |
| Started | Mar 05 01:43:24 PM PST 24 |
| Finished | Mar 05 01:43:29 PM PST 24 |
| Peak memory | 222184 kb |
| Host | smart-2ce02fdf-1ec4-489a-a8ce-a11901e177b3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1202700596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir ect.1202700596 |
| Directory | /workspace/46.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/46.spi_device_tpm_all.882428245 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 28771060243 ps |
| CPU time | 37.01 seconds |
| Started | Mar 05 01:43:24 PM PST 24 |
| Finished | Mar 05 01:44:01 PM PST 24 |
| Peak memory | 216264 kb |
| Host | smart-ccbc376f-8464-4505-8ae5-36764db5c9c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882428245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.882428245 |
| Directory | /workspace/46.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3936204245 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 183234142 ps |
| CPU time | 1.38 seconds |
| Started | Mar 05 01:43:25 PM PST 24 |
| Finished | Mar 05 01:43:27 PM PST 24 |
| Peak memory | 206516 kb |
| Host | smart-cd038adb-3aaa-4fc1-918a-348fba8bd007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936204245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3936204245 |
| Directory | /workspace/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/46.spi_device_tpm_rw.2222766471 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 155930202 ps |
| CPU time | 1.04 seconds |
| Started | Mar 05 01:43:25 PM PST 24 |
| Finished | Mar 05 01:43:26 PM PST 24 |
| Peak memory | 206584 kb |
| Host | smart-7d93f648-53ef-46de-987c-5a7ad70d4228 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222766471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2222766471 |
| Directory | /workspace/46.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/46.spi_device_tpm_sts_read.5504791 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 95194825 ps |
| CPU time | 0.96 seconds |
| Started | Mar 05 01:43:24 PM PST 24 |
| Finished | Mar 05 01:43:25 PM PST 24 |
| Peak memory | 205372 kb |
| Host | smart-35b628d3-ec2d-4096-8d06-b5eceb2b3398 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5504791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.5504791 |
| Directory | /workspace/46.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/46.spi_device_upload.2328874295 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 24025109111 ps |
| CPU time | 9.6 seconds |
| Started | Mar 05 01:43:27 PM PST 24 |
| Finished | Mar 05 01:43:37 PM PST 24 |
| Peak memory | 219408 kb |
| Host | smart-eae3381f-f5e1-4f5e-ae76-d17237c36d80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328874295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2328874295 |
| Directory | /workspace/46.spi_device_upload/latest |
| Test location | /workspace/coverage/default/47.spi_device_alert_test.3181858712 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 37680121 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:43:34 PM PST 24 |
| Finished | Mar 05 01:43:35 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-e2882d79-dc21-477f-952f-0bdf45de17fa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181858712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test. 3181858712 |
| Directory | /workspace/47.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/47.spi_device_cfg_cmd.1638151829 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 36018576 ps |
| CPU time | 2.5 seconds |
| Started | Mar 05 01:43:31 PM PST 24 |
| Finished | Mar 05 01:43:33 PM PST 24 |
| Peak memory | 233460 kb |
| Host | smart-2f126eca-3cd5-4e91-bba5-014124dcc447 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638151829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1638151829 |
| Directory | /workspace/47.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/47.spi_device_csb_read.2886150862 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 32544668 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:43:33 PM PST 24 |
| Finished | Mar 05 01:43:34 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-38d49868-1577-4c3e-9e57-ea29f458efd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2886150862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2886150862 |
| Directory | /workspace/47.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/47.spi_device_flash_and_tpm.2618948582 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 54712094623 ps |
| CPU time | 81.05 seconds |
| Started | Mar 05 01:43:32 PM PST 24 |
| Finished | Mar 05 01:44:54 PM PST 24 |
| Peak memory | 235536 kb |
| Host | smart-8bb24d46-db00-4229-ae6a-918592d38d32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618948582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2618948582 |
| Directory | /workspace/47.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1370816081 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 57241003273 ps |
| CPU time | 358.45 seconds |
| Started | Mar 05 01:43:35 PM PST 24 |
| Finished | Mar 05 01:49:34 PM PST 24 |
| Peak memory | 273104 kb |
| Host | smart-087a0567-0daf-4fb2-bd01-0ff980631098 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370816081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl e.1370816081 |
| Directory | /workspace/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/47.spi_device_flash_mode.627271617 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 10306468240 ps |
| CPU time | 39.84 seconds |
| Started | Mar 05 01:43:34 PM PST 24 |
| Finished | Mar 05 01:44:14 PM PST 24 |
| Peak memory | 233356 kb |
| Host | smart-5e753b44-9d5a-479c-bd4a-503c41a8336a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627271617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.627271617 |
| Directory | /workspace/47.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/47.spi_device_intercept.115970348 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 838450059 ps |
| CPU time | 5.02 seconds |
| Started | Mar 05 01:43:33 PM PST 24 |
| Finished | Mar 05 01:43:38 PM PST 24 |
| Peak memory | 218972 kb |
| Host | smart-1aff3e63-d08b-4b24-8006-b3affebb53d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115970348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.115970348 |
| Directory | /workspace/47.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/47.spi_device_mailbox.204135688 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 2605036350 ps |
| CPU time | 5.03 seconds |
| Started | Mar 05 01:43:32 PM PST 24 |
| Finished | Mar 05 01:43:37 PM PST 24 |
| Peak memory | 224232 kb |
| Host | smart-c4d0e081-daf3-47a5-8269-7746a080371e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204135688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.204135688 |
| Directory | /workspace/47.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.546368878 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4740805218 ps |
| CPU time | 14.78 seconds |
| Started | Mar 05 01:43:33 PM PST 24 |
| Finished | Mar 05 01:43:48 PM PST 24 |
| Peak memory | 224304 kb |
| Host | smart-4ddcbbd8-dbf7-496c-a9fd-cf9787ca6fe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546368878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap .546368878 |
| Directory | /workspace/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1478347236 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 6477304188 ps |
| CPU time | 21.45 seconds |
| Started | Mar 05 01:43:31 PM PST 24 |
| Finished | Mar 05 01:43:53 PM PST 24 |
| Peak memory | 237776 kb |
| Host | smart-841c6084-2874-4783-8f4c-f3ba7dd716cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478347236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1478347236 |
| Directory | /workspace/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/47.spi_device_read_buffer_direct.1920951378 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2720136836 ps |
| CPU time | 4.54 seconds |
| Started | Mar 05 01:43:31 PM PST 24 |
| Finished | Mar 05 01:43:36 PM PST 24 |
| Peak memory | 216536 kb |
| Host | smart-baf4d474-4709-42be-962b-2fb86bcd8360 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1920951378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir ect.1920951378 |
| Directory | /workspace/47.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/47.spi_device_stress_all.2704649341 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 24932463331 ps |
| CPU time | 188.06 seconds |
| Started | Mar 05 01:43:33 PM PST 24 |
| Finished | Mar 05 01:46:41 PM PST 24 |
| Peak memory | 249128 kb |
| Host | smart-3066e75f-d25c-4981-a41f-0b6383bd6e54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704649341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre ss_all.2704649341 |
| Directory | /workspace/47.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/47.spi_device_tpm_all.3823985427 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 37952327288 ps |
| CPU time | 35.08 seconds |
| Started | Mar 05 01:43:33 PM PST 24 |
| Finished | Mar 05 01:44:08 PM PST 24 |
| Peak memory | 216308 kb |
| Host | smart-84ed171f-25f4-4c35-9c87-4a49f8aa85dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823985427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3823985427 |
| Directory | /workspace/47.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4090998269 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 10311216426 ps |
| CPU time | 17.68 seconds |
| Started | Mar 05 01:43:32 PM PST 24 |
| Finished | Mar 05 01:43:50 PM PST 24 |
| Peak memory | 216304 kb |
| Host | smart-2eb64de5-b9f5-4dbe-8b2e-b504cf5c7043 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090998269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4090998269 |
| Directory | /workspace/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/47.spi_device_tpm_rw.2074784035 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 39848832 ps |
| CPU time | 2.2 seconds |
| Started | Mar 05 01:43:32 PM PST 24 |
| Finished | Mar 05 01:43:35 PM PST 24 |
| Peak memory | 216272 kb |
| Host | smart-73c824fc-b70b-4888-8149-14641321bc28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074784035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2074784035 |
| Directory | /workspace/47.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/47.spi_device_tpm_sts_read.2745534310 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 443165477 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:43:32 PM PST 24 |
| Finished | Mar 05 01:43:33 PM PST 24 |
| Peak memory | 205336 kb |
| Host | smart-6704c0b2-0f69-4c85-a7c6-9f25e5dd9c0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745534310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2745534310 |
| Directory | /workspace/47.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/47.spi_device_upload.2487356845 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3780036118 ps |
| CPU time | 8.33 seconds |
| Started | Mar 05 01:43:36 PM PST 24 |
| Finished | Mar 05 01:43:45 PM PST 24 |
| Peak memory | 233308 kb |
| Host | smart-6be75815-c6b8-46ee-ae1f-f4a0a050df60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487356845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2487356845 |
| Directory | /workspace/47.spi_device_upload/latest |
| Test location | /workspace/coverage/default/48.spi_device_alert_test.556819430 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 12593781 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:43:46 PM PST 24 |
| Finished | Mar 05 01:43:47 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-8a8311fe-6112-48d9-a755-5c0a8f8bcb5b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556819430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.556819430 |
| Directory | /workspace/48.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/48.spi_device_cfg_cmd.2915046863 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 507731054 ps |
| CPU time | 3.15 seconds |
| Started | Mar 05 01:43:39 PM PST 24 |
| Finished | Mar 05 01:43:42 PM PST 24 |
| Peak memory | 224352 kb |
| Host | smart-a135e4bf-c2e0-405c-bec6-94fcf93dd003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915046863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2915046863 |
| Directory | /workspace/48.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/48.spi_device_csb_read.3977435324 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 16799519 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:43:34 PM PST 24 |
| Finished | Mar 05 01:43:35 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-260d9270-9276-4f06-b83b-e93e27d65c4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977435324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3977435324 |
| Directory | /workspace/48.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/48.spi_device_flash_all.3543305339 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 65775030033 ps |
| CPU time | 86.46 seconds |
| Started | Mar 05 01:43:46 PM PST 24 |
| Finished | Mar 05 01:45:13 PM PST 24 |
| Peak memory | 238416 kb |
| Host | smart-db38f2ce-3fa4-47ac-a256-69dc693a565d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543305339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3543305339 |
| Directory | /workspace/48.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/48.spi_device_flash_and_tpm.3997470497 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 225703108893 ps |
| CPU time | 357.7 seconds |
| Started | Mar 05 01:43:38 PM PST 24 |
| Finished | Mar 05 01:49:35 PM PST 24 |
| Peak memory | 264348 kb |
| Host | smart-2b61cf84-b985-48c4-bc08-8a25e8dbbdc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997470497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3997470497 |
| Directory | /workspace/48.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3183847973 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 30583778053 ps |
| CPU time | 185.29 seconds |
| Started | Mar 05 01:43:42 PM PST 24 |
| Finished | Mar 05 01:46:47 PM PST 24 |
| Peak memory | 252564 kb |
| Host | smart-2f3228d1-bcb2-4ab7-bc2a-91fffd103ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3183847973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl e.3183847973 |
| Directory | /workspace/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/48.spi_device_flash_mode.1380953608 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 3235291545 ps |
| CPU time | 8.99 seconds |
| Started | Mar 05 01:43:37 PM PST 24 |
| Finished | Mar 05 01:43:46 PM PST 24 |
| Peak memory | 232664 kb |
| Host | smart-0c354ec0-8e37-4c0c-8248-ffe591a83178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380953608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1380953608 |
| Directory | /workspace/48.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/48.spi_device_intercept.2555869150 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4483082465 ps |
| CPU time | 9.6 seconds |
| Started | Mar 05 01:43:38 PM PST 24 |
| Finished | Mar 05 01:43:48 PM PST 24 |
| Peak memory | 233536 kb |
| Host | smart-b4142e01-790c-4be3-8585-22dda4e0a7dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555869150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2555869150 |
| Directory | /workspace/48.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/48.spi_device_mailbox.4184878165 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 8349388386 ps |
| CPU time | 15.36 seconds |
| Started | Mar 05 01:43:39 PM PST 24 |
| Finished | Mar 05 01:43:54 PM PST 24 |
| Peak memory | 233652 kb |
| Host | smart-785b0d41-e39e-440f-9d41-fbc363e823fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184878165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4184878165 |
| Directory | /workspace/48.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2285989775 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 8361161474 ps |
| CPU time | 25.82 seconds |
| Started | Mar 05 01:43:37 PM PST 24 |
| Finished | Mar 05 01:44:03 PM PST 24 |
| Peak memory | 229172 kb |
| Host | smart-6b0ad9cb-fd77-426e-ac70-03f8e12419c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285989775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa p.2285989775 |
| Directory | /workspace/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1003695852 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8900058319 ps |
| CPU time | 15.05 seconds |
| Started | Mar 05 01:43:39 PM PST 24 |
| Finished | Mar 05 01:43:54 PM PST 24 |
| Peak memory | 233540 kb |
| Host | smart-07087be6-4fc1-4137-8716-28c5f3ceb4b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003695852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1003695852 |
| Directory | /workspace/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/48.spi_device_read_buffer_direct.1784295650 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 574737952 ps |
| CPU time | 3.18 seconds |
| Started | Mar 05 01:43:41 PM PST 24 |
| Finished | Mar 05 01:43:44 PM PST 24 |
| Peak memory | 220200 kb |
| Host | smart-002d92b5-a9e0-4f6c-a2cf-61ba11a39c81 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1784295650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir ect.1784295650 |
| Directory | /workspace/48.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/48.spi_device_tpm_all.3796645173 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1009585949 ps |
| CPU time | 3.4 seconds |
| Started | Mar 05 01:43:34 PM PST 24 |
| Finished | Mar 05 01:43:38 PM PST 24 |
| Peak memory | 216228 kb |
| Host | smart-b4b9a39f-aa9f-4fbc-b441-22efc4887d4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796645173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3796645173 |
| Directory | /workspace/48.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3311164779 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 16497055774 ps |
| CPU time | 24.96 seconds |
| Started | Mar 05 01:43:33 PM PST 24 |
| Finished | Mar 05 01:43:59 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-49fdfda1-4d18-4fa2-9b44-6c3cfc41923f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311164779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3311164779 |
| Directory | /workspace/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/48.spi_device_tpm_rw.3584008840 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 139869967 ps |
| CPU time | 1.76 seconds |
| Started | Mar 05 01:43:37 PM PST 24 |
| Finished | Mar 05 01:43:38 PM PST 24 |
| Peak memory | 216224 kb |
| Host | smart-78235532-a321-4680-8d6e-d586a995a1aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584008840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3584008840 |
| Directory | /workspace/48.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/48.spi_device_tpm_sts_read.3194834141 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 203916807 ps |
| CPU time | 0.93 seconds |
| Started | Mar 05 01:43:34 PM PST 24 |
| Finished | Mar 05 01:43:35 PM PST 24 |
| Peak memory | 206320 kb |
| Host | smart-5359f7f1-be44-4786-9559-542143d01b50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194834141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3194834141 |
| Directory | /workspace/48.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/48.spi_device_upload.3240382634 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 599171948 ps |
| CPU time | 3.13 seconds |
| Started | Mar 05 01:43:43 PM PST 24 |
| Finished | Mar 05 01:43:46 PM PST 24 |
| Peak memory | 232580 kb |
| Host | smart-d8a13fb3-650c-4ae7-a63e-8a406e6c197c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240382634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3240382634 |
| Directory | /workspace/48.spi_device_upload/latest |
| Test location | /workspace/coverage/default/49.spi_device_alert_test.941145384 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 14473212 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:43:47 PM PST 24 |
| Finished | Mar 05 01:43:47 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-e56fd2eb-b5e8-4b80-95bc-37b86a516eae |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941145384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.941145384 |
| Directory | /workspace/49.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/49.spi_device_cfg_cmd.1519242178 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 659804905 ps |
| CPU time | 4 seconds |
| Started | Mar 05 01:43:47 PM PST 24 |
| Finished | Mar 05 01:43:51 PM PST 24 |
| Peak memory | 217524 kb |
| Host | smart-c84fccfe-f9a7-49b1-97dd-5668ac43730b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519242178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1519242178 |
| Directory | /workspace/49.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/49.spi_device_csb_read.1782428620 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 22377270 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:43:38 PM PST 24 |
| Finished | Mar 05 01:43:39 PM PST 24 |
| Peak memory | 205316 kb |
| Host | smart-a99d7641-99a7-4a20-9b94-8acdedf03141 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782428620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1782428620 |
| Directory | /workspace/49.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/49.spi_device_flash_and_tpm.3787482609 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 46118103811 ps |
| CPU time | 137.12 seconds |
| Started | Mar 05 01:43:47 PM PST 24 |
| Finished | Mar 05 01:46:04 PM PST 24 |
| Peak memory | 238788 kb |
| Host | smart-f5c8b3c3-68c6-419b-bf0e-29ab01e1ce3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787482609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3787482609 |
| Directory | /workspace/49.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2448893919 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 4444098755 ps |
| CPU time | 73.82 seconds |
| Started | Mar 05 01:43:46 PM PST 24 |
| Finished | Mar 05 01:45:00 PM PST 24 |
| Peak memory | 265192 kb |
| Host | smart-6341f620-1e7e-4d00-b8d0-212a9d71399b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448893919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl e.2448893919 |
| Directory | /workspace/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/49.spi_device_flash_mode.1275941522 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 8373298505 ps |
| CPU time | 28.47 seconds |
| Started | Mar 05 01:43:45 PM PST 24 |
| Finished | Mar 05 01:44:14 PM PST 24 |
| Peak memory | 239640 kb |
| Host | smart-51777bc8-f7ae-4b8a-ab53-638fcd6f14c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275941522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1275941522 |
| Directory | /workspace/49.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/49.spi_device_intercept.3083462648 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 7716320897 ps |
| CPU time | 9.76 seconds |
| Started | Mar 05 01:43:45 PM PST 24 |
| Finished | Mar 05 01:43:55 PM PST 24 |
| Peak memory | 233680 kb |
| Host | smart-20ce90e2-8ecd-48c7-bdd7-20af5a5b1637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083462648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3083462648 |
| Directory | /workspace/49.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/49.spi_device_mailbox.3394493521 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 15750214272 ps |
| CPU time | 43.84 seconds |
| Started | Mar 05 01:43:46 PM PST 24 |
| Finished | Mar 05 01:44:30 PM PST 24 |
| Peak memory | 246260 kb |
| Host | smart-25099229-e7c1-4d4e-b0aa-540ac88d6b62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3394493521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3394493521 |
| Directory | /workspace/49.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1613197005 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 4955772988 ps |
| CPU time | 13.78 seconds |
| Started | Mar 05 01:43:43 PM PST 24 |
| Finished | Mar 05 01:43:57 PM PST 24 |
| Peak memory | 217748 kb |
| Host | smart-1932705e-c0d9-4401-bea5-09634fad8142 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613197005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa p.1613197005 |
| Directory | /workspace/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2673976337 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2289485819 ps |
| CPU time | 5.94 seconds |
| Started | Mar 05 01:43:43 PM PST 24 |
| Finished | Mar 05 01:43:49 PM PST 24 |
| Peak memory | 216792 kb |
| Host | smart-443db17d-c33d-44e3-ac87-9dcd889aee75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673976337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2673976337 |
| Directory | /workspace/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/49.spi_device_read_buffer_direct.3221704590 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 8242916275 ps |
| CPU time | 6.85 seconds |
| Started | Mar 05 01:43:45 PM PST 24 |
| Finished | Mar 05 01:43:52 PM PST 24 |
| Peak memory | 218660 kb |
| Host | smart-87d9f93a-e585-44f5-9b18-3787e13a3474 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3221704590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir ect.3221704590 |
| Directory | /workspace/49.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/49.spi_device_stress_all.1756370437 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 7409312146 ps |
| CPU time | 80.45 seconds |
| Started | Mar 05 01:43:49 PM PST 24 |
| Finished | Mar 05 01:45:09 PM PST 24 |
| Peak memory | 251712 kb |
| Host | smart-3db4b8de-0de6-41af-bb7f-42936e5270de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756370437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre ss_all.1756370437 |
| Directory | /workspace/49.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/49.spi_device_tpm_all.198695866 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2870349261 ps |
| CPU time | 27.31 seconds |
| Started | Mar 05 01:43:37 PM PST 24 |
| Finished | Mar 05 01:44:05 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-7f19cbc7-4e19-471e-ad3b-bdcf8f4bdc63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198695866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.198695866 |
| Directory | /workspace/49.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.597101602 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3267793388 ps |
| CPU time | 11.06 seconds |
| Started | Mar 05 01:43:40 PM PST 24 |
| Finished | Mar 05 01:43:51 PM PST 24 |
| Peak memory | 216252 kb |
| Host | smart-bb5f7326-50c1-4e5b-9732-9a37c6cee1b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597101602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.597101602 |
| Directory | /workspace/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/49.spi_device_tpm_rw.2321234626 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 671979504 ps |
| CPU time | 6.55 seconds |
| Started | Mar 05 01:43:48 PM PST 24 |
| Finished | Mar 05 01:43:54 PM PST 24 |
| Peak memory | 216148 kb |
| Host | smart-7dc58aa8-3ce4-4a87-8092-0fca5d3ebecf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321234626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2321234626 |
| Directory | /workspace/49.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/49.spi_device_tpm_sts_read.3649866445 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 105925388 ps |
| CPU time | 1.01 seconds |
| Started | Mar 05 01:43:38 PM PST 24 |
| Finished | Mar 05 01:43:39 PM PST 24 |
| Peak memory | 205804 kb |
| Host | smart-4f1e0012-c129-4065-97a9-4650b4e72f6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3649866445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3649866445 |
| Directory | /workspace/49.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/49.spi_device_upload.4215459757 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3122051689 ps |
| CPU time | 11.38 seconds |
| Started | Mar 05 01:43:47 PM PST 24 |
| Finished | Mar 05 01:43:58 PM PST 24 |
| Peak memory | 217684 kb |
| Host | smart-030ad8ae-ba19-41b3-895d-2d8ebb8d9f24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215459757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4215459757 |
| Directory | /workspace/49.spi_device_upload/latest |
| Test location | /workspace/coverage/default/5.spi_device_alert_test.2625254463 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 24041043 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:37:03 PM PST 24 |
| Finished | Mar 05 01:37:04 PM PST 24 |
| Peak memory | 204844 kb |
| Host | smart-b404ae71-a2d6-4740-91c5-0f0c2a2aed53 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625254463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2 625254463 |
| Directory | /workspace/5.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/5.spi_device_cfg_cmd.3062885065 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 575385562 ps |
| CPU time | 3.36 seconds |
| Started | Mar 05 01:37:02 PM PST 24 |
| Finished | Mar 05 01:37:06 PM PST 24 |
| Peak memory | 233428 kb |
| Host | smart-a96330a0-8a87-4e5b-a2e5-7b7be852c981 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062885065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3062885065 |
| Directory | /workspace/5.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/5.spi_device_csb_read.367224702 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 68014651 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:36:55 PM PST 24 |
| Finished | Mar 05 01:36:56 PM PST 24 |
| Peak memory | 205308 kb |
| Host | smart-ab9720b8-1f50-44e2-b13d-690c5021e403 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367224702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.367224702 |
| Directory | /workspace/5.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/5.spi_device_flash_all.2587932028 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 239038909586 ps |
| CPU time | 233.91 seconds |
| Started | Mar 05 01:37:04 PM PST 24 |
| Finished | Mar 05 01:40:58 PM PST 24 |
| Peak memory | 266132 kb |
| Host | smart-876c4a0e-2232-438c-aa37-1d0c2d51e0e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587932028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2587932028 |
| Directory | /workspace/5.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/5.spi_device_flash_and_tpm.2264328051 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 6967761603 ps |
| CPU time | 61.08 seconds |
| Started | Mar 05 01:37:03 PM PST 24 |
| Finished | Mar 05 01:38:04 PM PST 24 |
| Peak memory | 253968 kb |
| Host | smart-943de37d-425d-41d4-82ef-7839535bec11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264328051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2264328051 |
| Directory | /workspace/5.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3821439389 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 5870949542 ps |
| CPU time | 28.58 seconds |
| Started | Mar 05 01:37:06 PM PST 24 |
| Finished | Mar 05 01:37:35 PM PST 24 |
| Peak memory | 249772 kb |
| Host | smart-9848ef8b-04e9-4c46-a84d-73f6b158f911 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821439389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle .3821439389 |
| Directory | /workspace/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/5.spi_device_flash_mode.1508574816 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 9655511322 ps |
| CPU time | 37.71 seconds |
| Started | Mar 05 01:37:03 PM PST 24 |
| Finished | Mar 05 01:37:41 PM PST 24 |
| Peak memory | 233584 kb |
| Host | smart-5122f53f-b5d9-4f2a-a37e-332172d183ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1508574816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1508574816 |
| Directory | /workspace/5.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/5.spi_device_intercept.4291477864 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 271331653 ps |
| CPU time | 2.9 seconds |
| Started | Mar 05 01:37:04 PM PST 24 |
| Finished | Mar 05 01:37:07 PM PST 24 |
| Peak memory | 217816 kb |
| Host | smart-40f96853-15a6-45c5-a29e-205850ae2329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291477864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4291477864 |
| Directory | /workspace/5.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/5.spi_device_mailbox.2768754578 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 34012302965 ps |
| CPU time | 21.66 seconds |
| Started | Mar 05 01:37:00 PM PST 24 |
| Finished | Mar 05 01:37:22 PM PST 24 |
| Peak memory | 226100 kb |
| Host | smart-469568fa-78cf-47a2-979e-3d835ce846c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768754578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2768754578 |
| Directory | /workspace/5.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/5.spi_device_mem_parity.1767015546 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 380058950 ps |
| CPU time | 1.03 seconds |
| Started | Mar 05 01:36:54 PM PST 24 |
| Finished | Mar 05 01:36:56 PM PST 24 |
| Peak memory | 217620 kb |
| Host | smart-f5e8b37f-157f-4e19-8040-75eaf38b8a60 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767015546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.spi_device_mem_parity.1767015546 |
| Directory | /workspace/5.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1565438530 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3422668797 ps |
| CPU time | 6.32 seconds |
| Started | Mar 05 01:37:04 PM PST 24 |
| Finished | Mar 05 01:37:10 PM PST 24 |
| Peak memory | 216812 kb |
| Host | smart-6e9d0048-d9b2-4521-ab53-76b362602d16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1565438530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap .1565438530 |
| Directory | /workspace/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/5.spi_device_pass_cmd_filtering.759774224 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 157204215 ps |
| CPU time | 2.72 seconds |
| Started | Mar 05 01:37:03 PM PST 24 |
| Finished | Mar 05 01:37:05 PM PST 24 |
| Peak memory | 216672 kb |
| Host | smart-050e5975-0746-4ab8-8b29-8c6335aa7678 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759774224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.759774224 |
| Directory | /workspace/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/5.spi_device_ram_cfg.1786290145 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 33570521 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:36:55 PM PST 24 |
| Finished | Mar 05 01:36:56 PM PST 24 |
| Peak memory | 216056 kb |
| Host | smart-919f4379-d5fb-4f2b-8f93-9788b050e80f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786290145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1786290145 |
| Directory | /workspace/5.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/5.spi_device_read_buffer_direct.2413405397 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1119848585 ps |
| CPU time | 4.55 seconds |
| Started | Mar 05 01:37:02 PM PST 24 |
| Finished | Mar 05 01:37:07 PM PST 24 |
| Peak memory | 222624 kb |
| Host | smart-126d8e04-0107-4410-9594-1707ab00a38f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2413405397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire ct.2413405397 |
| Directory | /workspace/5.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/5.spi_device_stress_all.85766800 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 3877323069 ps |
| CPU time | 79.81 seconds |
| Started | Mar 05 01:37:03 PM PST 24 |
| Finished | Mar 05 01:38:23 PM PST 24 |
| Peak memory | 257264 kb |
| Host | smart-056d5bb9-d4d7-4c4a-aa2a-428972d3a7a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85766800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_ all.85766800 |
| Directory | /workspace/5.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/5.spi_device_tpm_all.269654056 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 21062566653 ps |
| CPU time | 34.39 seconds |
| Started | Mar 05 01:36:57 PM PST 24 |
| Finished | Mar 05 01:37:31 PM PST 24 |
| Peak memory | 216280 kb |
| Host | smart-6b11094e-368a-440e-81dd-7106092cdb5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269654056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.269654056 |
| Directory | /workspace/5.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1065947366 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 9847411548 ps |
| CPU time | 26.72 seconds |
| Started | Mar 05 01:36:54 PM PST 24 |
| Finished | Mar 05 01:37:22 PM PST 24 |
| Peak memory | 216352 kb |
| Host | smart-956e41f1-79a6-4794-ba3d-dd2b9c67b10f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065947366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1065947366 |
| Directory | /workspace/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/5.spi_device_tpm_rw.2394187464 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 214029790 ps |
| CPU time | 4.16 seconds |
| Started | Mar 05 01:37:01 PM PST 24 |
| Finished | Mar 05 01:37:05 PM PST 24 |
| Peak memory | 216296 kb |
| Host | smart-9842b6ee-9aa8-4169-bc70-30cf496563df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394187464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2394187464 |
| Directory | /workspace/5.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/5.spi_device_tpm_sts_read.1899410170 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 180520818 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:36:54 PM PST 24 |
| Finished | Mar 05 01:36:56 PM PST 24 |
| Peak memory | 205324 kb |
| Host | smart-b284b378-95ee-4bbb-9d0b-428ed77db00b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899410170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1899410170 |
| Directory | /workspace/5.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/5.spi_device_upload.2939029076 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 118642600570 ps |
| CPU time | 26.97 seconds |
| Started | Mar 05 01:37:03 PM PST 24 |
| Finished | Mar 05 01:37:30 PM PST 24 |
| Peak memory | 235572 kb |
| Host | smart-3ef2ae67-8675-42e7-b00c-06559081359e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939029076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2939029076 |
| Directory | /workspace/5.spi_device_upload/latest |
| Test location | /workspace/coverage/default/6.spi_device_alert_test.3984926591 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 12727874 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:37:15 PM PST 24 |
| Finished | Mar 05 01:37:17 PM PST 24 |
| Peak memory | 205188 kb |
| Host | smart-c2bf5c11-c2fe-489d-b083-5056b0f526a8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984926591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3 984926591 |
| Directory | /workspace/6.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/6.spi_device_cfg_cmd.1082930235 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1707434927 ps |
| CPU time | 6.86 seconds |
| Started | Mar 05 01:37:09 PM PST 24 |
| Finished | Mar 05 01:37:16 PM PST 24 |
| Peak memory | 218988 kb |
| Host | smart-d2d5fa68-f2f6-4e13-8c80-ea40b03518e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082930235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1082930235 |
| Directory | /workspace/6.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/6.spi_device_csb_read.2290108188 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 20237868 ps |
| CPU time | 0.86 seconds |
| Started | Mar 05 01:37:04 PM PST 24 |
| Finished | Mar 05 01:37:05 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-48da0bc0-e16f-4ccc-92e8-b3af9f26cb34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290108188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2290108188 |
| Directory | /workspace/6.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/6.spi_device_flash_all.1330089459 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 395037846271 ps |
| CPU time | 150.47 seconds |
| Started | Mar 05 01:37:16 PM PST 24 |
| Finished | Mar 05 01:39:47 PM PST 24 |
| Peak memory | 248952 kb |
| Host | smart-81422174-c716-44cb-aeb8-1e9461bfb8b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330089459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1330089459 |
| Directory | /workspace/6.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/6.spi_device_flash_and_tpm.217608014 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 13248524110 ps |
| CPU time | 54.27 seconds |
| Started | Mar 05 01:37:09 PM PST 24 |
| Finished | Mar 05 01:38:03 PM PST 24 |
| Peak memory | 257320 kb |
| Host | smart-8ea1c729-963c-4089-a245-03a617fa42be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217608014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.217608014 |
| Directory | /workspace/6.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2188807581 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 13462696946 ps |
| CPU time | 152.18 seconds |
| Started | Mar 05 01:37:13 PM PST 24 |
| Finished | Mar 05 01:39:45 PM PST 24 |
| Peak memory | 249120 kb |
| Host | smart-ff57ec01-4590-4a7a-970c-1dc6e99c2d17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188807581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle .2188807581 |
| Directory | /workspace/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/6.spi_device_flash_mode.3367480164 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3921975510 ps |
| CPU time | 10.79 seconds |
| Started | Mar 05 01:37:14 PM PST 24 |
| Finished | Mar 05 01:37:27 PM PST 24 |
| Peak memory | 228956 kb |
| Host | smart-1d1400f4-9fba-4c0e-8dee-2251f68d9ce5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367480164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3367480164 |
| Directory | /workspace/6.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/6.spi_device_intercept.3947475583 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 124710822 ps |
| CPU time | 2.75 seconds |
| Started | Mar 05 01:37:13 PM PST 24 |
| Finished | Mar 05 01:37:16 PM PST 24 |
| Peak memory | 233488 kb |
| Host | smart-80380837-9863-4102-abbc-f28eef666d71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947475583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3947475583 |
| Directory | /workspace/6.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/6.spi_device_mailbox.2427186446 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3321435806 ps |
| CPU time | 9.51 seconds |
| Started | Mar 05 01:37:09 PM PST 24 |
| Finished | Mar 05 01:37:18 PM PST 24 |
| Peak memory | 228760 kb |
| Host | smart-c84d7383-0873-4b4e-995e-1d66ee7a1673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2427186446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2427186446 |
| Directory | /workspace/6.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/6.spi_device_mem_parity.172020191 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 97319861 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:37:04 PM PST 24 |
| Finished | Mar 05 01:37:06 PM PST 24 |
| Peak memory | 217752 kb |
| Host | smart-08958836-80a6-41ce-b3b2-0fd210cb002c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172020191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.172020191 |
| Directory | /workspace/6.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2926117466 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 6324817377 ps |
| CPU time | 16.65 seconds |
| Started | Mar 05 01:37:07 PM PST 24 |
| Finished | Mar 05 01:37:24 PM PST 24 |
| Peak memory | 232568 kb |
| Host | smart-342a674b-af15-4967-8879-6bf6f2108ae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926117466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap .2926117466 |
| Directory | /workspace/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2639263960 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 22844108293 ps |
| CPU time | 6.02 seconds |
| Started | Mar 05 01:37:09 PM PST 24 |
| Finished | Mar 05 01:37:15 PM PST 24 |
| Peak memory | 234120 kb |
| Host | smart-38ddd594-3498-4651-9236-21f2b889a39f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639263960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2639263960 |
| Directory | /workspace/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/6.spi_device_ram_cfg.186022680 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 14838853 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:37:12 PM PST 24 |
| Finished | Mar 05 01:37:13 PM PST 24 |
| Peak memory | 216068 kb |
| Host | smart-58b3e978-9292-4b0d-8fff-ff1d1ea6952f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186022680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.186022680 |
| Directory | /workspace/6.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/6.spi_device_read_buffer_direct.643910938 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 621131256 ps |
| CPU time | 3.85 seconds |
| Started | Mar 05 01:37:13 PM PST 24 |
| Finished | Mar 05 01:37:17 PM PST 24 |
| Peak memory | 218584 kb |
| Host | smart-31c36946-dc2e-4e79-9b15-2ba6ae4ea9fe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=643910938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc t.643910938 |
| Directory | /workspace/6.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/6.spi_device_stress_all.4142418371 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 90739779 ps |
| CPU time | 1 seconds |
| Started | Mar 05 01:37:16 PM PST 24 |
| Finished | Mar 05 01:37:18 PM PST 24 |
| Peak memory | 206376 kb |
| Host | smart-61777eb5-e44a-49ab-abf7-26bd08b0efe7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142418371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres s_all.4142418371 |
| Directory | /workspace/6.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/6.spi_device_tpm_all.3899953395 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 4399792188 ps |
| CPU time | 27.22 seconds |
| Started | Mar 05 01:37:10 PM PST 24 |
| Finished | Mar 05 01:37:38 PM PST 24 |
| Peak memory | 216144 kb |
| Host | smart-700cbf4a-ef25-4b42-91a6-6508bec15f20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899953395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3899953395 |
| Directory | /workspace/6.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4206771432 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 21915707435 ps |
| CPU time | 12.89 seconds |
| Started | Mar 05 01:37:09 PM PST 24 |
| Finished | Mar 05 01:37:22 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-198169c6-a5be-49c5-b8b8-2703db28d965 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206771432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4206771432 |
| Directory | /workspace/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/6.spi_device_tpm_rw.3062457155 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 5231778710 ps |
| CPU time | 5.68 seconds |
| Started | Mar 05 01:37:10 PM PST 24 |
| Finished | Mar 05 01:37:16 PM PST 24 |
| Peak memory | 216280 kb |
| Host | smart-e8714a1c-e288-4f82-93dc-b0dfa11dd8f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062457155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3062457155 |
| Directory | /workspace/6.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/6.spi_device_tpm_sts_read.3777411649 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 167585218 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:37:11 PM PST 24 |
| Finished | Mar 05 01:37:12 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-872c4d2b-32ac-43b3-8ea4-30b271238903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777411649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3777411649 |
| Directory | /workspace/6.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/6.spi_device_upload.753751019 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 24805670195 ps |
| CPU time | 21.31 seconds |
| Started | Mar 05 01:37:11 PM PST 24 |
| Finished | Mar 05 01:37:32 PM PST 24 |
| Peak memory | 229196 kb |
| Host | smart-75410fab-7be0-4429-bece-4b46b85e898f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753751019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.753751019 |
| Directory | /workspace/6.spi_device_upload/latest |
| Test location | /workspace/coverage/default/7.spi_device_alert_test.1286232848 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 13533826 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:37:24 PM PST 24 |
| Finished | Mar 05 01:37:26 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-eddc255f-3b17-415e-a390-80f2b4dca92f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286232848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1 286232848 |
| Directory | /workspace/7.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/7.spi_device_cfg_cmd.1275386921 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 623916709 ps |
| CPU time | 3.45 seconds |
| Started | Mar 05 01:37:25 PM PST 24 |
| Finished | Mar 05 01:37:29 PM PST 24 |
| Peak memory | 218008 kb |
| Host | smart-fd58e808-29cc-467e-98e2-0f6806fc0144 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275386921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1275386921 |
| Directory | /workspace/7.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/7.spi_device_csb_read.2585927777 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 91503600 ps |
| CPU time | 0.8 seconds |
| Started | Mar 05 01:37:16 PM PST 24 |
| Finished | Mar 05 01:37:17 PM PST 24 |
| Peak memory | 206304 kb |
| Host | smart-85f789a9-2dfa-497b-8979-8a63464c3b28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585927777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2585927777 |
| Directory | /workspace/7.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/7.spi_device_flash_all.1997021580 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 187125708350 ps |
| CPU time | 285.61 seconds |
| Started | Mar 05 01:37:23 PM PST 24 |
| Finished | Mar 05 01:42:09 PM PST 24 |
| Peak memory | 272952 kb |
| Host | smart-a8d7d97b-5c8d-4d4e-9320-7cf1563d1fbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997021580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1997021580 |
| Directory | /workspace/7.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/7.spi_device_flash_and_tpm.706764062 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 76066298249 ps |
| CPU time | 96.09 seconds |
| Started | Mar 05 01:37:24 PM PST 24 |
| Finished | Mar 05 01:39:00 PM PST 24 |
| Peak memory | 249612 kb |
| Host | smart-0994d65b-ebaf-41e4-8440-8908904c91c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706764062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.706764062 |
| Directory | /workspace/7.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3914976302 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 61738049195 ps |
| CPU time | 216.37 seconds |
| Started | Mar 05 01:37:23 PM PST 24 |
| Finished | Mar 05 01:41:00 PM PST 24 |
| Peak memory | 254012 kb |
| Host | smart-425a2991-854d-4177-b05e-71c7bffcc7d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3914976302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle .3914976302 |
| Directory | /workspace/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/7.spi_device_flash_mode.1767199192 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 831698510 ps |
| CPU time | 12.63 seconds |
| Started | Mar 05 01:37:25 PM PST 24 |
| Finished | Mar 05 01:37:38 PM PST 24 |
| Peak memory | 246268 kb |
| Host | smart-d6a70eab-7e9e-49ba-8df2-6a447655ecd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767199192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1767199192 |
| Directory | /workspace/7.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/7.spi_device_intercept.1071529143 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 311639303 ps |
| CPU time | 3.53 seconds |
| Started | Mar 05 01:37:16 PM PST 24 |
| Finished | Mar 05 01:37:20 PM PST 24 |
| Peak memory | 216680 kb |
| Host | smart-de7c7e6f-edaa-4b7e-a100-869f358a3bc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071529143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1071529143 |
| Directory | /workspace/7.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/7.spi_device_mailbox.1575544426 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 542218909 ps |
| CPU time | 7.32 seconds |
| Started | Mar 05 01:37:16 PM PST 24 |
| Finished | Mar 05 01:37:24 PM PST 24 |
| Peak memory | 227704 kb |
| Host | smart-a50d4393-c68a-41fb-a612-84dcc1ac4c36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575544426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1575544426 |
| Directory | /workspace/7.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/7.spi_device_mem_parity.568526351 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 33020488 ps |
| CPU time | 1.12 seconds |
| Started | Mar 05 01:37:15 PM PST 24 |
| Finished | Mar 05 01:37:18 PM PST 24 |
| Peak memory | 216392 kb |
| Host | smart-95324271-729e-4d44-96f4-147554e57386 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568526351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.568526351 |
| Directory | /workspace/7.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.867911825 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1231599523 ps |
| CPU time | 7.03 seconds |
| Started | Mar 05 01:37:16 PM PST 24 |
| Finished | Mar 05 01:37:24 PM PST 24 |
| Peak memory | 240516 kb |
| Host | smart-aa13f1e2-95b9-47bb-8e7c-1262ba8e9da0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867911825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap. 867911825 |
| Directory | /workspace/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1828292419 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1135535414 ps |
| CPU time | 7.8 seconds |
| Started | Mar 05 01:37:18 PM PST 24 |
| Finished | Mar 05 01:37:26 PM PST 24 |
| Peak memory | 232504 kb |
| Host | smart-3feeac87-f868-4280-b1fd-2c36128ea588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828292419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1828292419 |
| Directory | /workspace/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/7.spi_device_ram_cfg.2074173680 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 16352488 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:37:19 PM PST 24 |
| Finished | Mar 05 01:37:20 PM PST 24 |
| Peak memory | 216132 kb |
| Host | smart-c2d36c95-b035-4430-807e-4e627797bb09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074173680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2074173680 |
| Directory | /workspace/7.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/7.spi_device_read_buffer_direct.4207708605 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 143247949 ps |
| CPU time | 3.41 seconds |
| Started | Mar 05 01:37:24 PM PST 24 |
| Finished | Mar 05 01:37:29 PM PST 24 |
| Peak memory | 217032 kb |
| Host | smart-232d248a-897c-4f78-ba76-5e1e8d86c7f7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4207708605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire ct.4207708605 |
| Directory | /workspace/7.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/7.spi_device_tpm_all.3761616871 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4763747244 ps |
| CPU time | 17.94 seconds |
| Started | Mar 05 01:37:18 PM PST 24 |
| Finished | Mar 05 01:37:36 PM PST 24 |
| Peak memory | 216264 kb |
| Host | smart-a5f0414a-fa3d-4ce6-abf0-e423a32abe99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761616871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3761616871 |
| Directory | /workspace/7.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.344116657 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1708839496 ps |
| CPU time | 8.52 seconds |
| Started | Mar 05 01:37:18 PM PST 24 |
| Finished | Mar 05 01:37:26 PM PST 24 |
| Peak memory | 216220 kb |
| Host | smart-e8518e12-248e-4344-b53c-902274d70689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=344116657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.344116657 |
| Directory | /workspace/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/7.spi_device_tpm_rw.3019457995 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 461100785 ps |
| CPU time | 1.69 seconds |
| Started | Mar 05 01:37:16 PM PST 24 |
| Finished | Mar 05 01:37:18 PM PST 24 |
| Peak memory | 207972 kb |
| Host | smart-e4c88236-8bf9-4f47-8549-19ab7c03886f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3019457995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3019457995 |
| Directory | /workspace/7.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/7.spi_device_tpm_sts_read.2296908372 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 118021449 ps |
| CPU time | 0.87 seconds |
| Started | Mar 05 01:37:15 PM PST 24 |
| Finished | Mar 05 01:37:17 PM PST 24 |
| Peak memory | 205328 kb |
| Host | smart-b166eede-7ce1-4c6e-9d62-3f47c8eaeb5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2296908372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2296908372 |
| Directory | /workspace/7.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/7.spi_device_upload.3863775089 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 198441998 ps |
| CPU time | 3.43 seconds |
| Started | Mar 05 01:37:16 PM PST 24 |
| Finished | Mar 05 01:37:20 PM PST 24 |
| Peak memory | 234036 kb |
| Host | smart-c5d85bd5-880d-40f6-bb25-59adf4693c38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863775089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3863775089 |
| Directory | /workspace/7.spi_device_upload/latest |
| Test location | /workspace/coverage/default/8.spi_device_alert_test.1510152090 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 13102680 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:37:36 PM PST 24 |
| Finished | Mar 05 01:37:37 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-7e49d6ff-44a2-49d3-a2bd-a571ea8e7417 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510152090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1 510152090 |
| Directory | /workspace/8.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/8.spi_device_cfg_cmd.1014518201 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 522206050 ps |
| CPU time | 4.04 seconds |
| Started | Mar 05 01:37:29 PM PST 24 |
| Finished | Mar 05 01:37:33 PM PST 24 |
| Peak memory | 224376 kb |
| Host | smart-7677f94d-01a7-4344-954f-6c0dbd6fda2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014518201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1014518201 |
| Directory | /workspace/8.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/8.spi_device_csb_read.3330574273 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 20428377 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:37:25 PM PST 24 |
| Finished | Mar 05 01:37:26 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-f8099af4-3cba-4a9d-aaff-398ae4d6ba3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330574273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3330574273 |
| Directory | /workspace/8.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/8.spi_device_flash_all.1130360687 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 581448948923 ps |
| CPU time | 189.97 seconds |
| Started | Mar 05 01:37:36 PM PST 24 |
| Finished | Mar 05 01:40:47 PM PST 24 |
| Peak memory | 257100 kb |
| Host | smart-16e56f3b-b7af-4e6b-ba52-d263dfc76d04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130360687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1130360687 |
| Directory | /workspace/8.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/8.spi_device_flash_and_tpm.1671209099 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 6800610210 ps |
| CPU time | 29.06 seconds |
| Started | Mar 05 01:37:39 PM PST 24 |
| Finished | Mar 05 01:38:08 PM PST 24 |
| Peak memory | 222716 kb |
| Host | smart-e53d544b-d817-4a2e-8aa9-81f60639873c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671209099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1671209099 |
| Directory | /workspace/8.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1415468739 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 23974388795 ps |
| CPU time | 62.32 seconds |
| Started | Mar 05 01:37:37 PM PST 24 |
| Finished | Mar 05 01:38:40 PM PST 24 |
| Peak memory | 241384 kb |
| Host | smart-2aa65e73-b823-4985-92f6-fba1f06ee9f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415468739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle .1415468739 |
| Directory | /workspace/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/8.spi_device_flash_mode.1878179914 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 4499577580 ps |
| CPU time | 27.09 seconds |
| Started | Mar 05 01:37:37 PM PST 24 |
| Finished | Mar 05 01:38:05 PM PST 24 |
| Peak memory | 248904 kb |
| Host | smart-4e3d4d50-112d-404c-905c-ec2ad3b0b6b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878179914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1878179914 |
| Directory | /workspace/8.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/8.spi_device_intercept.1033467910 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 432091798 ps |
| CPU time | 3.69 seconds |
| Started | Mar 05 01:37:32 PM PST 24 |
| Finished | Mar 05 01:37:38 PM PST 24 |
| Peak memory | 224368 kb |
| Host | smart-62353782-5aea-4cfe-9ecc-e7e172553636 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033467910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1033467910 |
| Directory | /workspace/8.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/8.spi_device_mailbox.1063414786 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 79114300194 ps |
| CPU time | 58.56 seconds |
| Started | Mar 05 01:37:30 PM PST 24 |
| Finished | Mar 05 01:38:30 PM PST 24 |
| Peak memory | 249028 kb |
| Host | smart-c2f6156f-c9b8-4dc8-bd63-352d05527015 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063414786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1063414786 |
| Directory | /workspace/8.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/8.spi_device_mem_parity.3022591847 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 89891303 ps |
| CPU time | 1.05 seconds |
| Started | Mar 05 01:37:24 PM PST 24 |
| Finished | Mar 05 01:37:25 PM PST 24 |
| Peak memory | 216532 kb |
| Host | smart-ca4f9e2c-5734-42b6-97b2-a3191441f13d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022591847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.spi_device_mem_parity.3022591847 |
| Directory | /workspace/8.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3584492233 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 5662224787 ps |
| CPU time | 10.03 seconds |
| Started | Mar 05 01:37:33 PM PST 24 |
| Finished | Mar 05 01:37:44 PM PST 24 |
| Peak memory | 217832 kb |
| Host | smart-3bc13d07-24f1-4a91-94c1-b4e2b47b5eb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584492233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap .3584492233 |
| Directory | /workspace/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1549927488 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1144431655 ps |
| CPU time | 4.39 seconds |
| Started | Mar 05 01:37:29 PM PST 24 |
| Finished | Mar 05 01:37:34 PM PST 24 |
| Peak memory | 224052 kb |
| Host | smart-7f5d140e-2962-46ec-801b-b29882eedb99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549927488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1549927488 |
| Directory | /workspace/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/8.spi_device_ram_cfg.446834730 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 27320772 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:37:25 PM PST 24 |
| Finished | Mar 05 01:37:26 PM PST 24 |
| Peak memory | 216056 kb |
| Host | smart-b98db758-1ed0-499b-ba02-218cdf855a0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446834730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.446834730 |
| Directory | /workspace/8.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/8.spi_device_read_buffer_direct.3414650411 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1219330916 ps |
| CPU time | 6.51 seconds |
| Started | Mar 05 01:37:38 PM PST 24 |
| Finished | Mar 05 01:37:44 PM PST 24 |
| Peak memory | 221988 kb |
| Host | smart-bf9e19ff-7347-43b4-9910-97c3da9a52e0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3414650411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire ct.3414650411 |
| Directory | /workspace/8.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/8.spi_device_stress_all.2665769303 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 26481635931 ps |
| CPU time | 215.28 seconds |
| Started | Mar 05 01:37:36 PM PST 24 |
| Finished | Mar 05 01:41:12 PM PST 24 |
| Peak memory | 254040 kb |
| Host | smart-e7f3eede-2a87-4811-a6e1-d692708a9a1e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665769303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres s_all.2665769303 |
| Directory | /workspace/8.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/8.spi_device_tpm_all.4035490026 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4212567471 ps |
| CPU time | 26.54 seconds |
| Started | Mar 05 01:37:25 PM PST 24 |
| Finished | Mar 05 01:37:52 PM PST 24 |
| Peak memory | 216328 kb |
| Host | smart-5896cbce-113f-4c58-8802-ee2c2c38a718 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035490026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4035490026 |
| Directory | /workspace/8.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2090344444 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4068941408 ps |
| CPU time | 3.71 seconds |
| Started | Mar 05 01:37:23 PM PST 24 |
| Finished | Mar 05 01:37:27 PM PST 24 |
| Peak memory | 216260 kb |
| Host | smart-c0d3128d-18a5-4880-9933-e298b3330f51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2090344444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2090344444 |
| Directory | /workspace/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/8.spi_device_tpm_rw.478559659 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 100772102 ps |
| CPU time | 2.03 seconds |
| Started | Mar 05 01:37:29 PM PST 24 |
| Finished | Mar 05 01:37:32 PM PST 24 |
| Peak memory | 216344 kb |
| Host | smart-9fbef4cc-68fb-4f06-81df-037a5f744b63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478559659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.478559659 |
| Directory | /workspace/8.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/8.spi_device_tpm_sts_read.3626221117 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 301631857 ps |
| CPU time | 0.85 seconds |
| Started | Mar 05 01:37:31 PM PST 24 |
| Finished | Mar 05 01:37:33 PM PST 24 |
| Peak memory | 205244 kb |
| Host | smart-34c87b20-eb1f-4eb8-bc9a-7375551c8432 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626221117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3626221117 |
| Directory | /workspace/8.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/8.spi_device_upload.1646250592 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 4240476307 ps |
| CPU time | 16.31 seconds |
| Started | Mar 05 01:37:33 PM PST 24 |
| Finished | Mar 05 01:37:51 PM PST 24 |
| Peak memory | 233280 kb |
| Host | smart-7cb8eb02-da5e-467f-8cac-4edd6df6d034 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646250592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1646250592 |
| Directory | /workspace/8.spi_device_upload/latest |
| Test location | /workspace/coverage/default/9.spi_device_alert_test.77970558 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 28100841 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:37:53 PM PST 24 |
| Finished | Mar 05 01:37:54 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-ba8b7816-48fb-43b5-b418-1fce9d3b8ecc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77970558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.77970558 |
| Directory | /workspace/9.spi_device_alert_test/latest |
| Test location | /workspace/coverage/default/9.spi_device_cfg_cmd.32159242 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 11169930120 ps |
| CPU time | 5.88 seconds |
| Started | Mar 05 01:37:42 PM PST 24 |
| Finished | Mar 05 01:37:49 PM PST 24 |
| Peak memory | 237904 kb |
| Host | smart-95ae0171-69f8-418e-9e9b-9b04db0614ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32159242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.32159242 |
| Directory | /workspace/9.spi_device_cfg_cmd/latest |
| Test location | /workspace/coverage/default/9.spi_device_csb_read.1530033294 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 67744538 ps |
| CPU time | 0.9 seconds |
| Started | Mar 05 01:37:36 PM PST 24 |
| Finished | Mar 05 01:37:37 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-764d8714-6d86-4ad0-b1a4-a26b6ba770f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530033294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1530033294 |
| Directory | /workspace/9.spi_device_csb_read/latest |
| Test location | /workspace/coverage/default/9.spi_device_flash_all.1753450192 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 16977332840 ps |
| CPU time | 86.93 seconds |
| Started | Mar 05 01:37:45 PM PST 24 |
| Finished | Mar 05 01:39:13 PM PST 24 |
| Peak memory | 240692 kb |
| Host | smart-d1271615-cc06-4dda-9b7a-24a0e7fc9057 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753450192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1753450192 |
| Directory | /workspace/9.spi_device_flash_all/latest |
| Test location | /workspace/coverage/default/9.spi_device_flash_and_tpm.3077811501 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 70568331134 ps |
| CPU time | 103.29 seconds |
| Started | Mar 05 01:37:45 PM PST 24 |
| Finished | Mar 05 01:39:30 PM PST 24 |
| Peak memory | 250368 kb |
| Host | smart-27649274-149d-48f1-9f7a-144e0aea0c7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077811501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3077811501 |
| Directory | /workspace/9.spi_device_flash_and_tpm/latest |
| Test location | /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.952759773 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5227529231 ps |
| CPU time | 59.16 seconds |
| Started | Mar 05 01:37:45 PM PST 24 |
| Finished | Mar 05 01:38:46 PM PST 24 |
| Peak memory | 255188 kb |
| Host | smart-98d2eb22-c447-48ec-b618-520f48ab8095 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952759773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle. 952759773 |
| Directory | /workspace/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspace/coverage/default/9.spi_device_flash_mode.1019298799 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 28521506354 ps |
| CPU time | 33.72 seconds |
| Started | Mar 05 01:37:44 PM PST 24 |
| Finished | Mar 05 01:38:20 PM PST 24 |
| Peak memory | 250332 kb |
| Host | smart-cdcbc3ae-20f0-457c-84ea-c20bff53f2ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019298799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1019298799 |
| Directory | /workspace/9.spi_device_flash_mode/latest |
| Test location | /workspace/coverage/default/9.spi_device_intercept.2702114947 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 63224296 ps |
| CPU time | 2.1 seconds |
| Started | Mar 05 01:37:44 PM PST 24 |
| Finished | Mar 05 01:37:49 PM PST 24 |
| Peak memory | 216220 kb |
| Host | smart-c240f05f-3fc0-4434-bc43-a4ac58ac367a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702114947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2702114947 |
| Directory | /workspace/9.spi_device_intercept/latest |
| Test location | /workspace/coverage/default/9.spi_device_mailbox.3946990418 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 17183400555 ps |
| CPU time | 15.69 seconds |
| Started | Mar 05 01:37:44 PM PST 24 |
| Finished | Mar 05 01:38:02 PM PST 24 |
| Peak memory | 247696 kb |
| Host | smart-f3559061-9447-4642-9f7a-d10f7105b094 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946990418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3946990418 |
| Directory | /workspace/9.spi_device_mailbox/latest |
| Test location | /workspace/coverage/default/9.spi_device_mem_parity.1121806902 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 35224182 ps |
| CPU time | 1.13 seconds |
| Started | Mar 05 01:37:36 PM PST 24 |
| Finished | Mar 05 01:37:38 PM PST 24 |
| Peak memory | 216544 kb |
| Host | smart-c3d294a1-d315-4755-b578-280eb46247ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121806902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.spi_device_mem_parity.1121806902 |
| Directory | /workspace/9.spi_device_mem_parity/latest |
| Test location | /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3302653431 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1522577681 ps |
| CPU time | 7.1 seconds |
| Started | Mar 05 01:37:44 PM PST 24 |
| Finished | Mar 05 01:37:54 PM PST 24 |
| Peak memory | 237856 kb |
| Host | smart-9b9939fd-70c9-4475-bac8-8bdd886d4c0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302653431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap .3302653431 |
| Directory | /workspace/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2625264277 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 166477025 ps |
| CPU time | 2.92 seconds |
| Started | Mar 05 01:37:44 PM PST 24 |
| Finished | Mar 05 01:37:49 PM PST 24 |
| Peak memory | 233576 kb |
| Host | smart-119a6b1d-1a24-4df7-9dad-86bc8abc296e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625264277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2625264277 |
| Directory | /workspace/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspace/coverage/default/9.spi_device_ram_cfg.1812379175 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 15419538 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:37:41 PM PST 24 |
| Finished | Mar 05 01:37:42 PM PST 24 |
| Peak memory | 216056 kb |
| Host | smart-f958438a-466c-4dfa-a3c5-8df3810a584b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812379175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1812379175 |
| Directory | /workspace/9.spi_device_ram_cfg/latest |
| Test location | /workspace/coverage/default/9.spi_device_read_buffer_direct.3462000754 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4032198066 ps |
| CPU time | 4.91 seconds |
| Started | Mar 05 01:37:42 PM PST 24 |
| Finished | Mar 05 01:37:48 PM PST 24 |
| Peak memory | 219708 kb |
| Host | smart-8ba5562e-504e-44af-bb48-3adf7f099035 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3462000754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire ct.3462000754 |
| Directory | /workspace/9.spi_device_read_buffer_direct/latest |
| Test location | /workspace/coverage/default/9.spi_device_stress_all.2134744311 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 239657171 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:37:50 PM PST 24 |
| Finished | Mar 05 01:37:52 PM PST 24 |
| Peak memory | 206660 kb |
| Host | smart-d004646f-d9a7-476c-85a1-7b48981f8f1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134744311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres s_all.2134744311 |
| Directory | /workspace/9.spi_device_stress_all/latest |
| Test location | /workspace/coverage/default/9.spi_device_tpm_all.1107385959 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 14381012664 ps |
| CPU time | 65.88 seconds |
| Started | Mar 05 01:37:38 PM PST 24 |
| Finished | Mar 05 01:38:44 PM PST 24 |
| Peak memory | 216340 kb |
| Host | smart-ff3360c9-5c86-455a-ac03-a470aacc6268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107385959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1107385959 |
| Directory | /workspace/9.spi_device_tpm_all/latest |
| Test location | /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2735552979 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 32561455585 ps |
| CPU time | 20.84 seconds |
| Started | Mar 05 01:37:37 PM PST 24 |
| Finished | Mar 05 01:37:58 PM PST 24 |
| Peak memory | 216260 kb |
| Host | smart-2c86a2ce-7431-4d25-ace3-4914befe0c53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735552979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2735552979 |
| Directory | /workspace/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspace/coverage/default/9.spi_device_tpm_rw.3579964352 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 56132725 ps |
| CPU time | 1.5 seconds |
| Started | Mar 05 01:37:38 PM PST 24 |
| Finished | Mar 05 01:37:40 PM PST 24 |
| Peak memory | 216152 kb |
| Host | smart-f6c750f4-23f8-4acf-9b2a-e6f41b3f2163 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579964352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3579964352 |
| Directory | /workspace/9.spi_device_tpm_rw/latest |
| Test location | /workspace/coverage/default/9.spi_device_tpm_sts_read.1255428617 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 90585071 ps |
| CPU time | 0.99 seconds |
| Started | Mar 05 01:37:38 PM PST 24 |
| Finished | Mar 05 01:37:39 PM PST 24 |
| Peak memory | 205344 kb |
| Host | smart-6b3ef174-7798-4675-95db-e3a5b0f9771b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255428617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1255428617 |
| Directory | /workspace/9.spi_device_tpm_sts_read/latest |
| Test location | /workspace/coverage/default/9.spi_device_upload.2013071433 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 8249414320 ps |
| CPU time | 26.81 seconds |
| Started | Mar 05 01:37:46 PM PST 24 |
| Finished | Mar 05 01:38:14 PM PST 24 |
| Peak memory | 219700 kb |
| Host | smart-8bf799e9-d514-4d48-bd43-59b76d7f24ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013071433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2013071433 |
| Directory | /workspace/9.spi_device_upload/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |