Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12223472	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13087477

1

T1

5623

T2

909

T3

78812

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16378469	1			T1	7068		T2	13		T3	107487
values[0x0]	4463698	1			T1	2701		T2	440		T3	24651
values[0x1]	4468782	1			T1	2673		T2	465		T3	24574

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8875698	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16435251

1

T1

7673

T2

913

T3

99884

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	104328	1			T3	583		T4	3		T10	5
valid_sources[0x01]	91749	1			T3	477		T4	1		T10	3
valid_sources[0x02]	95249	1			T3	529		T10	4		T11	4
valid_sources[0x03]	98900	1			T3	652		T6	4		T10	3
valid_sources[0x04]	94155	1			T3	566		T6	6		T10	3
valid_sources[0x05]	94446	1			T3	531		T6	15		T10	3
valid_sources[0x06]	98312	1			T3	636		T4	6		T10	1
valid_sources[0x07]	92092	1			T2	22		T3	660		T4	3
valid_sources[0x08]	99161	1			T3	616		T4	7		T10	5
valid_sources[0x09]	98818	1			T3	572		T4	1		T6	3
valid_sources[0x0a]	96952	1			T2	13		T3	564		T10	4
valid_sources[0x0b]	104539	1			T3	574		T4	4		T6	1
valid_sources[0x0c]	96332	1			T3	667		T4	7		T10	4
valid_sources[0x0d]	97371	1			T1	3		T2	5		T3	669
valid_sources[0x0e]	103766	1			T3	653		T4	3		T6	3
valid_sources[0x0f]	96553	1			T2	21		T3	625		T4	24
valid_sources[0x10]	100824	1			T3	617		T4	6		T10	3
valid_sources[0x11]	96083	1			T3	564		T4	1		T6	3
valid_sources[0x12]	100934	1			T3	643		T4	3		T6	9
valid_sources[0x13]	97952	1			T1	242		T3	530		T6	3
valid_sources[0x14]	95292	1			T3	479		T4	11		T10	4
valid_sources[0x15]	96956	1			T3	574		T4	8		T6	2
valid_sources[0x16]	95242	1			T3	672		T4	3		T10	2
valid_sources[0x17]	96867	1			T3	616		T6	8		T10	1
valid_sources[0x18]	94895	1			T3	622		T4	1		T6	10
valid_sources[0x19]	94340	1			T3	568		T4	5		T10	5
valid_sources[0x1a]	105226	1			T3	652		T4	7		T6	3
valid_sources[0x1b]	97102	1			T3	565		T4	20		T9	394
valid_sources[0x1c]	96671	1			T2	15		T3	635		T6	2
valid_sources[0x1d]	98264	1			T3	650		T4	6		T6	1
valid_sources[0x1e]	99818	1			T3	659		T4	1		T10	4
valid_sources[0x1f]	110284	1			T3	596		T4	11		T6	1
valid_sources[0x20]	95716	1			T2	4		T3	693		T7	2
valid_sources[0x21]	97509	1			T1	460		T3	660		T4	10
valid_sources[0x22]	98393	1			T1	48		T3	717		T4	2
valid_sources[0x23]	100844	1			T2	28		T3	681		T4	2
valid_sources[0x24]	94629	1			T3	646		T4	4		T6	3
valid_sources[0x25]	98953	1			T3	670		T6	9		T7	1
valid_sources[0x26]	93391	1			T1	2		T2	23		T3	573
valid_sources[0x27]	99770	1			T2	15		T3	578		T4	4
valid_sources[0x28]	95333	1			T1	415		T3	543		T4	7
valid_sources[0x29]	97188	1			T3	545		T10	2		T15	2
valid_sources[0x2a]	98596	1			T3	581		T4	4		T6	6
valid_sources[0x2b]	107160	1			T3	607		T4	2		T6	2
valid_sources[0x2c]	99306	1			T2	51		T3	671		T4	5
valid_sources[0x2d]	98452	1			T3	487		T4	1		T10	3
valid_sources[0x2e]	102003	1			T1	153		T3	588		T4	8
valid_sources[0x2f]	94543	1			T3	674		T6	13		T10	7
valid_sources[0x30]	95703	1			T2	26		T3	563		T4	3
valid_sources[0x31]	97347	1			T3	638		T4	4		T6	4
valid_sources[0x32]	104605	1			T3	656		T6	10		T7	2
valid_sources[0x33]	96553	1			T3	666		T4	2		T6	1
valid_sources[0x34]	98413	1			T3	676		T4	6		T6	9
valid_sources[0x35]	109051	1			T1	154		T3	507		T6	3
valid_sources[0x36]	92714	1			T3	672		T6	8		T10	7
valid_sources[0x37]	98602	1			T3	551		T4	18		T6	1
valid_sources[0x38]	98644	1			T3	604		T6	13		T10	4
valid_sources[0x39]	94465	1			T1	533		T2	55		T3	604
valid_sources[0x3a]	102635	1			T2	26		T3	575		T4	5
valid_sources[0x3b]	102167	1			T3	643		T4	2		T6	12
valid_sources[0x3c]	96500	1			T3	603		T4	5		T10	4
valid_sources[0x3d]	96546	1			T2	7		T3	673		T10	2
valid_sources[0x3e]	99343	1			T3	650		T4	15		T6	13
valid_sources[0x3f]	98831	1			T3	649		T4	2		T6	8
valid_sources[0x40]	96009	1			T3	590		T6	15		T10	4
valid_sources[0x41]	105658	1			T2	5		T3	691		T6	10
valid_sources[0x42]	98004	1			T1	1		T3	661		T4	3
valid_sources[0x43]	100171	1			T1	4		T3	663		T4	15
valid_sources[0x44]	96538	1			T3	563		T4	4		T10	2
valid_sources[0x45]	105365	1			T3	486		T4	2		T6	14
valid_sources[0x46]	95936	1			T3	604		T4	4		T6	5
valid_sources[0x47]	97138	1			T3	656		T4	3		T6	1
valid_sources[0x48]	99384	1			T3	591		T4	2		T6	4
valid_sources[0x49]	97391	1			T1	1		T3	641		T4	5
valid_sources[0x4a]	97899	1			T3	590		T4	10		T6	6
valid_sources[0x4b]	97279	1			T3	606		T4	3		T10	2
valid_sources[0x4c]	100417	1			T3	675		T4	1		T6	4
valid_sources[0x4d]	100721	1			T2	14		T3	624		T6	3
valid_sources[0x4e]	108079	1			T3	583		T4	2		T6	2
valid_sources[0x4f]	103509	1			T2	12		T3	508		T4	6
valid_sources[0x50]	100328	1			T3	576		T4	7		T6	6
valid_sources[0x51]	96212	1			T3	636		T4	10		T6	7
valid_sources[0x52]	95204	1			T3	727		T6	15		T10	3
valid_sources[0x53]	97212	1			T3	618		T4	11		T6	4
valid_sources[0x54]	97588	1			T3	574		T4	4		T10	2
valid_sources[0x55]	98227	1			T3	535		T4	5		T6	3
valid_sources[0x56]	94801	1			T2	6		T3	684		T6	9
valid_sources[0x57]	92665	1			T3	507		T4	5		T6	2
valid_sources[0x58]	95563	1			T3	602		T4	7		T7	1
valid_sources[0x59]	97612	1			T2	3		T3	576		T4	1
valid_sources[0x5a]	99164	1			T2	9		T3	600		T4	6
valid_sources[0x5b]	99168	1			T3	529		T6	1		T9	696
valid_sources[0x5c]	97048	1			T2	4		T3	720		T4	11
valid_sources[0x5d]	97486	1			T3	535		T4	4		T6	1
valid_sources[0x5e]	100227	1			T3	559		T4	12		T10	5
valid_sources[0x5f]	97428	1			T3	574		T4	1		T10	3
valid_sources[0x60]	94765	1			T3	626		T4	3		T6	8
valid_sources[0x61]	96710	1			T2	33		T3	690		T4	3
valid_sources[0x62]	98445	1			T2	17		T3	712		T10	1
valid_sources[0x63]	102803	1			T3	645		T7	3		T10	2
valid_sources[0x64]	100804	1			T1	166		T3	729		T4	4
valid_sources[0x65]	111861	1			T3	591		T4	7		T10	1
valid_sources[0x66]	100626	1			T1	1		T3	589		T4	10
valid_sources[0x67]	96852	1			T3	575		T4	1		T6	4
valid_sources[0x68]	103440	1			T3	557		T4	6		T6	5
valid_sources[0x69]	101045	1			T3	552		T4	19		T10	5
valid_sources[0x6a]	97627	1			T3	565		T4	11		T6	1
valid_sources[0x6b]	98420	1			T1	195		T3	612		T4	2
valid_sources[0x6c]	98891	1			T3	684		T6	6		T10	3
valid_sources[0x6d]	97012	1			T3	617		T6	7		T7	1
valid_sources[0x6e]	111181	1			T3	651		T4	1		T6	1
valid_sources[0x6f]	94764	1			T2	37		T3	620		T4	10
valid_sources[0x70]	98478	1			T3	738		T4	9		T6	2
valid_sources[0x71]	100078	1			T1	360		T3	724		T4	14
valid_sources[0x72]	98185	1			T3	555		T6	5		T10	4
valid_sources[0x73]	103895	1			T2	36		T3	710		T4	1
valid_sources[0x74]	102001	1			T1	3		T3	573		T4	3
valid_sources[0x75]	97465	1			T1	1		T3	693		T6	4
valid_sources[0x76]	98038	1			T1	4		T3	694		T4	6
valid_sources[0x77]	92038	1			T3	567		T6	17		T10	3
valid_sources[0x78]	96150	1			T2	13		T3	615		T4	6
valid_sources[0x79]	101971	1			T2	20		T3	588		T4	2
valid_sources[0x7a]	100250	1			T2	14		T3	592		T10	5
valid_sources[0x7b]	101677	1			T3	559		T4	6		T6	7
valid_sources[0x7c]	97710	1			T3	632		T6	2		T10	3
valid_sources[0x7d]	110378	1			T1	1		T3	580		T4	3
valid_sources[0x7e]	97726	1			T2	18		T3	693		T4	10
valid_sources[0x7f]	94758	1			T3	530		T4	1		T6	5
valid_sources[0x80]	97334	1			T3	541		T10	4		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5086798

1

T1

1963

T2

8

T3

34559

values[0x0]

all_enables

biggest_size

4031340

1

T1

1883

T2

439

T3

22263

values[0x1]

all_enables

biggest_size

3969339

1

T1

1777

T2

462

T3

21990