Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

12262825

1

T1

6819

T2

9

T3

77900

full_word

13085586

1

T1

5623

T2

909

T3

78812

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	25347691	1			T1	12442		T2	918		T3	156712
auto[TlIntgErrCmd]	254	1			T97	6		T98	11		T99	4
auto[TlIntgErrData]	222	1			T97	6		T98	5		T99	6
auto[TlIntgErrBoth]	244	1			T97	8		T98	4		T99	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16381530

1

T1

7068

T2

13

T3

107487

auto[1]

8966881

1

T1

5374

T2

905

T3

49225

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	11294212	1			T1	5105		T2	5		T3	72928
auto[TlIntgErrNone]	partial	auto[1]	967967	1			T1	1714		T2	4		T3	4972
auto[TlIntgErrNone]	full_word	auto[0]	5086992	1			T1	1963		T2	8		T3	34559
auto[TlIntgErrNone]	full_word	auto[1]	7998520	1			T1	3660		T2	901		T3	44253
auto[TlIntgErrCmd]	partial	auto[0]	103	1			T97	2		T98	5		T99	4
auto[TlIntgErrCmd]	partial	auto[1]	127	1			T97	2		T98	3		T174	7
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T98	1		T177	1		T176	1
auto[TlIntgErrCmd]	full_word	auto[1]	16	1			T97	2		T98	2		T177	1
auto[TlIntgErrData]	partial	auto[0]	96	1			T97	3		T98	3		T99	5
auto[TlIntgErrData]	partial	auto[1]	98	1			T97	3		T98	1		T174	6
auto[TlIntgErrData]	full_word	auto[0]	15	1			T98	1		T99	1		T174	1
auto[TlIntgErrData]	full_word	auto[1]	13	1			T177	1		T178	2		T180	1
auto[TlIntgErrBoth]	partial	auto[0]	93	1			T97	3		T98	1		T99	3
auto[TlIntgErrBoth]	partial	auto[1]	129	1			T97	5		T98	3		T99	6
auto[TlIntgErrBoth]	full_word	auto[0]	11	1			T181	1		T175	1		T179	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T99	1		T181	1		T178	1