Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T14
1	0	Covered	T3,T9,T14
1	1	Covered	T3,T9,T14

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T14
1	0	Covered	T3,T9,T14
1	1	Covered	T3,T9,T14

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	6900	0	0
SrcPulseCheck_M	1109558835	6900	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6900	0	0
T3	636211	39	0	0
T4	25004	0	0	0
T5	1645	0	0	0
T6	47666	0	0	0
T7	12070	0	0	0
T8	74589	0	0	0
T9	1000644	16	0	0
T10	12060	0	0	0
T11	491450	0	0	0
T12	132050	0	0	0
T13	43138	0	0	0
T14	918328	9	0	0
T15	8889	0	0	0
T16	3543	0	0	0
T18	0	10	0	0
T19	0	23	0	0
T21	0	17	0	0
T27	0	15	0	0
T34	15090	0	0	0
T35	15382	7	0	0
T39	0	6	0	0
T40	0	7	0	0
T41	0	7	0	0
T42	0	6	0	0
T44	0	1	0	0
T45	0	23	0	0
T128	0	20	0	0
T138	0	15	0	0
T139	0	7	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	0	4	0	0
T143	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109558835	6900	0	0
T3	157016	39	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	246438	16	0	0
T10	528	0	0	0
T11	91146	0	0	0
T12	25944	0	0	0
T13	51330	0	0	0
T14	1840500	9	0	0
T17	14874	0	0	0
T18	0	10	0	0
T19	0	23	0	0
T21	0	17	0	0
T27	0	15	0	0
T34	8400	0	0	0
T35	39814	7	0	0
T36	27678	0	0	0
T39	0	6	0	0
T40	0	7	0	0
T41	0	7	0	0
T42	0	6	0	0
T44	0	1	0	0
T45	0	23	0	0
T128	0	20	0	0
T138	0	15	0	0
T139	0	7	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	0	4	0	0
T143	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T35,T40
1	0	Covered	T9,T35,T40
1	1	Covered	T9,T35,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T35,T40
1	0	Covered	T9,T35,T40
1	1	Covered	T9,T35,T40

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1155154872	784	0	0
SrcPulseCheck_M	369852945	784	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	784	0	0
T9	333548	8	0	0
T10	4020	0	0	0
T11	245725	0	0	0
T12	66025	0	0	0
T13	21569	0	0	0
T14	459164	0	0	0
T15	2963	0	0	0
T16	1181	0	0	0
T34	7545	0	0	0
T35	7691	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T138	0	8	0	0
T139	0	2	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	4	0	0
T143	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	784	0	0
T9	82146	8	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	920250	0	0	0
T17	7437	0	0	0
T34	4200	0	0	0
T35	19907	2	0	0
T36	13839	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T138	0	8	0	0
T139	0	2	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	4	0	0
T143	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T35,T39
1	0	Covered	T9,T35,T39
1	1	Covered	T9,T35,T39

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T35,T39
1	0	Covered	T9,T35,T39
1	1	Covered	T9,T35,T39

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1155154872	1154	0	0
SrcPulseCheck_M	369852945	1154	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	1154	0	0
T9	333548	8	0	0
T10	4020	0	0	0
T11	245725	0	0	0
T12	66025	0	0	0
T13	21569	0	0	0
T14	459164	0	0	0
T15	2963	0	0	0
T16	1181	0	0	0
T34	7545	0	0	0
T35	7691	5	0	0
T39	0	6	0	0
T40	0	5	0	0
T41	0	5	0	0
T128	0	20	0	0
T138	0	7	0	0
T139	0	5	0	0
T140	0	5	0	0
T141	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1154	0	0
T9	82146	8	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	920250	0	0	0
T17	7437	0	0	0
T34	4200	0	0	0
T35	19907	5	0	0
T36	13839	0	0	0
T39	0	6	0	0
T40	0	5	0	0
T41	0	5	0	0
T128	0	20	0	0
T138	0	7	0	0
T139	0	5	0	0
T140	0	5	0	0
T141	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T18
1	0	Covered	T3,T14,T18
1	1	Covered	T3,T14,T18

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T18
1	0	Covered	T3,T14,T18
1	1	Covered	T3,T14,T18

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1155154872	4962	0	0
SrcPulseCheck_M	369852945	4962	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	4962	0	0
T3	636211	39	0	0
T4	25004	0	0	0
T5	1645	0	0	0
T6	47666	0	0	0
T7	12070	0	0	0
T8	74589	0	0	0
T9	333548	0	0	0
T10	4020	0	0	0
T14	0	9	0	0
T15	2963	0	0	0
T16	1181	0	0	0
T18	0	10	0	0
T19	0	23	0	0
T21	0	17	0	0
T27	0	15	0	0
T42	0	6	0	0
T44	0	1	0	0
T45	0	23	0	0
T54	0	10	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	4962	0	0
T3	157016	39	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	9	0	0
T18	0	10	0	0
T19	0	23	0	0
T21	0	17	0	0
T27	0	15	0	0
T42	0	6	0	0
T44	0	1	0	0
T45	0	23	0	0
T54	0	10	0	0