Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T14,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T18
1	0	Covered	T3,T14,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T3,T14,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1894860762	1521167570	0	0
CheckNGreaterZero_A	5643	5643	0	0
GntImpliesReady_A	1894860762	8633368	0	0
GntImpliesValid_A	1894860762	8633368	0	0
GrantKnown_A	1894860762	1521167570	0	0
IdxKnown_A	1894860762	1521167570	0	0
IndexIsCorrect_A	1894860762	8633368	0	0
LockArbDecision_A	1894860762	0	0	0
NoReadyValidNoGrant_A	1894860762	0	0	0
ReadyAndValidImplyGrant_A	1894860762	8633368	0	0
ReqAndReadyImplyGrant_A	1894860762	8633368	0	0
ReqImpliesValid_A	1894860762	8633368	0	0
ReqStaysHighUntilGranted0_M	1894860762	0	0	0
RoundRobin_A	1894860762	17	0	1881
ValidKnown_A	1894860762	1521167570	0	0
gen_data_port_assertion.DataFlow_A	1894860762	8633368	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	1521167570	0	0
T1	662657	657298	0	0
T2	366629	329891	0	0
T3	950243	897450	0	0
T4	32882	28781	0	0
T5	1645	1574	0	0
T6	91386	69442	0	0
T7	27258	19242	0	0
T8	203181	138496	0	0
T9	497840	415638	0	0
T10	4372	4097	0	0
T11	60764	30218	0	0
T12	8648	8352	0	0
T13	0	17110	0	0
T14	0	914829	0	0
T17	0	7256	0	0
T18	0	558344	0	0
T19	0	298896	0	0
T20	0	31928	0	0
T25	0	124240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5643	5643	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	8633368	0	0
T1	662657	12162	0	0
T2	330456	832	0	0
T3	950243	41520	0	0
T4	32882	298	0	0
T5	1645	0	0	0
T6	91386	832	0	0
T7	27258	0	0	0
T8	203181	832	0	0
T9	497840	2880	0	0
T10	4372	832	0	0
T11	60764	832	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	6852	0	0
T15	0	200	0	0
T17	0	358	0	0
T18	0	18385	0	0
T19	0	13884	0	0
T20	0	1065	0	0
T21	0	2845	0	0
T25	0	3153	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T43	0	1184	0	0
T44	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	8633368	0	0
T1	662657	12162	0	0
T2	330456	832	0	0
T3	950243	41520	0	0
T4	32882	298	0	0
T5	1645	0	0	0
T6	91386	832	0	0
T7	27258	0	0	0
T8	203181	832	0	0
T9	497840	2880	0	0
T10	4372	832	0	0
T11	60764	832	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	6852	0	0
T15	0	200	0	0
T17	0	358	0	0
T18	0	18385	0	0
T19	0	13884	0	0
T20	0	1065	0	0
T21	0	2845	0	0
T25	0	3153	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T43	0	1184	0	0
T44	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	1521167570	0	0
T1	662657	657298	0	0
T2	366629	329891	0	0
T3	950243	897450	0	0
T4	32882	28781	0	0
T5	1645	1574	0	0
T6	91386	69442	0	0
T7	27258	19242	0	0
T8	203181	138496	0	0
T9	497840	415638	0	0
T10	4372	4097	0	0
T11	60764	30218	0	0
T12	8648	8352	0	0
T13	0	17110	0	0
T14	0	914829	0	0
T17	0	7256	0	0
T18	0	558344	0	0
T19	0	298896	0	0
T20	0	31928	0	0
T25	0	124240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	1521167570	0	0
T1	662657	657298	0	0
T2	366629	329891	0	0
T3	950243	897450	0	0
T4	32882	28781	0	0
T5	1645	1574	0	0
T6	91386	69442	0	0
T7	27258	19242	0	0
T8	203181	138496	0	0
T9	497840	415638	0	0
T10	4372	4097	0	0
T11	60764	30218	0	0
T12	8648	8352	0	0
T13	0	17110	0	0
T14	0	914829	0	0
T17	0	7256	0	0
T18	0	558344	0	0
T19	0	298896	0	0
T20	0	31928	0	0
T25	0	124240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	8633368	0	0
T1	662657	12162	0	0
T2	330456	832	0	0
T3	950243	41520	0	0
T4	32882	298	0	0
T5	1645	0	0	0
T6	91386	832	0	0
T7	27258	0	0	0
T8	203181	832	0	0
T9	497840	2880	0	0
T10	4372	832	0	0
T11	60764	832	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	6852	0	0
T15	0	200	0	0
T17	0	358	0	0
T18	0	18385	0	0
T19	0	13884	0	0
T20	0	1065	0	0
T21	0	2845	0	0
T25	0	3153	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T43	0	1184	0	0
T44	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	8633368	0	0
T1	662657	12162	0	0
T2	330456	832	0	0
T3	950243	41520	0	0
T4	32882	298	0	0
T5	1645	0	0	0
T6	91386	832	0	0
T7	27258	0	0	0
T8	203181	832	0	0
T9	497840	2880	0	0
T10	4372	832	0	0
T11	60764	832	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	6852	0	0
T15	0	200	0	0
T17	0	358	0	0
T18	0	18385	0	0
T19	0	13884	0	0
T20	0	1065	0	0
T21	0	2845	0	0
T25	0	3153	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T43	0	1184	0	0
T44	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	8633368	0	0
T1	662657	12162	0	0
T2	330456	832	0	0
T3	950243	41520	0	0
T4	32882	298	0	0
T5	1645	0	0	0
T6	91386	832	0	0
T7	27258	0	0	0
T8	203181	832	0	0
T9	497840	2880	0	0
T10	4372	832	0	0
T11	60764	832	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	6852	0	0
T15	0	200	0	0
T17	0	358	0	0
T18	0	18385	0	0
T19	0	13884	0	0
T20	0	1065	0	0
T21	0	2845	0	0
T25	0	3153	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T43	0	1184	0	0
T44	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	8633368	0	0
T1	662657	12162	0	0
T2	330456	832	0	0
T3	950243	41520	0	0
T4	32882	298	0	0
T5	1645	0	0	0
T6	91386	832	0	0
T7	27258	0	0	0
T8	203181	832	0	0
T9	497840	2880	0	0
T10	4372	832	0	0
T11	60764	832	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	6852	0	0
T15	0	200	0	0
T17	0	358	0	0
T18	0	18385	0	0
T19	0	13884	0	0
T20	0	1065	0	0
T21	0	2845	0	0
T25	0	3153	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T43	0	1184	0	0
T44	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	17	0	1881
T3	636211	1	0	1
T4	25004	0	0	1
T5	1645	0	0	1
T6	47666	0	0	1
T7	12070	0	0	1
T8	74589	0	0	1
T9	333548	0	0	1
T10	4020	0	0	1
T15	2963	0	0	1
T16	1181	0	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	1521167570	0	0
T1	662657	657298	0	0
T2	366629	329891	0	0
T3	950243	897450	0	0
T4	32882	28781	0	0
T5	1645	1574	0	0
T6	91386	69442	0	0
T7	27258	19242	0	0
T8	203181	138496	0	0
T9	497840	415638	0	0
T10	4372	4097	0	0
T11	60764	30218	0	0
T12	8648	8352	0	0
T13	0	17110	0	0
T14	0	914829	0	0
T17	0	7256	0	0
T18	0	558344	0	0
T19	0	298896	0	0
T20	0	31928	0	0
T25	0	124240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1894860762	8633368	0	0
T1	662657	12162	0	0
T2	330456	832	0	0
T3	950243	41520	0	0
T4	32882	298	0	0
T5	1645	0	0	0
T6	91386	832	0	0
T7	27258	0	0	0
T8	203181	832	0	0
T9	497840	2880	0	0
T10	4372	832	0	0
T11	60764	832	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	6852	0	0
T15	0	200	0	0
T17	0	358	0	0
T18	0	18385	0	0
T19	0	13884	0	0
T20	0	1065	0	0
T21	0	2845	0	0
T25	0	3153	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T43	0	1184	0	0
T44	0	2	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369852945	82652904	0	0
CheckNGreaterZero_A	1881	1881	0	0
GntImpliesReady_A	369852945	1841259	0	0
GntImpliesValid_A	369852945	1841259	0	0
GrantKnown_A	369852945	82652904	0	0
IdxKnown_A	369852945	82652904	0	0
IndexIsCorrect_A	369852945	1841259	0	0
LockArbDecision_A	369852945	0	0	0
NoReadyValidNoGrant_A	369852945	0	0	0
ReadyAndValidImplyGrant_A	369852945	1841259	0	0
ReqAndReadyImplyGrant_A	369852945	1841259	0	0
ReqImpliesValid_A	369852945	1841259	0	0
ReqStaysHighUntilGranted0_M	369852945	0	0	0
RoundRobin_A	369852945	0	0	0
ValidKnown_A	369852945	82652904	0	0
gen_data_port_assertion.DataFlow_A	369852945	1841259	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	82652904	0	0
T1	301290	295984	0	0
T2	36173	0	0	0
T3	157016	117040	0	0
T4	3939	3856	0	0
T6	21860	0	0	0
T7	7594	7232	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	107712	0	0
T17	0	7256	0	0
T18	0	558344	0	0
T19	0	298896	0	0
T20	0	31928	0	0
T25	0	124240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1881	1881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1841259	0	0
T1	301290	8617	0	0
T2	36173	0	0	0
T3	157016	4790	0	0
T4	3939	200	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	4569	0	0
T17	0	358	0	0
T18	0	14666	0	0
T19	0	7524	0	0
T20	0	1065	0	0
T25	0	3153	0	0
T43	0	1184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1841259	0	0
T1	301290	8617	0	0
T2	36173	0	0	0
T3	157016	4790	0	0
T4	3939	200	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	4569	0	0
T17	0	358	0	0
T18	0	14666	0	0
T19	0	7524	0	0
T20	0	1065	0	0
T25	0	3153	0	0
T43	0	1184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	82652904	0	0
T1	301290	295984	0	0
T2	36173	0	0	0
T3	157016	117040	0	0
T4	3939	3856	0	0
T6	21860	0	0	0
T7	7594	7232	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	107712	0	0
T17	0	7256	0	0
T18	0	558344	0	0
T19	0	298896	0	0
T20	0	31928	0	0
T25	0	124240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	82652904	0	0
T1	301290	295984	0	0
T2	36173	0	0	0
T3	157016	117040	0	0
T4	3939	3856	0	0
T6	21860	0	0	0
T7	7594	7232	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	107712	0	0
T17	0	7256	0	0
T18	0	558344	0	0
T19	0	298896	0	0
T20	0	31928	0	0
T25	0	124240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1841259	0	0
T1	301290	8617	0	0
T2	36173	0	0	0
T3	157016	4790	0	0
T4	3939	200	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	4569	0	0
T17	0	358	0	0
T18	0	14666	0	0
T19	0	7524	0	0
T20	0	1065	0	0
T25	0	3153	0	0
T43	0	1184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1841259	0	0
T1	301290	8617	0	0
T2	36173	0	0	0
T3	157016	4790	0	0
T4	3939	200	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	4569	0	0
T17	0	358	0	0
T18	0	14666	0	0
T19	0	7524	0	0
T20	0	1065	0	0
T25	0	3153	0	0
T43	0	1184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1841259	0	0
T1	301290	8617	0	0
T2	36173	0	0	0
T3	157016	4790	0	0
T4	3939	200	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	4569	0	0
T17	0	358	0	0
T18	0	14666	0	0
T19	0	7524	0	0
T20	0	1065	0	0
T25	0	3153	0	0
T43	0	1184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1841259	0	0
T1	301290	8617	0	0
T2	36173	0	0	0
T3	157016	4790	0	0
T4	3939	200	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	4569	0	0
T17	0	358	0	0
T18	0	14666	0	0
T19	0	7524	0	0
T20	0	1065	0	0
T25	0	3153	0	0
T43	0	1184	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	82652904	0	0
T1	301290	295984	0	0
T2	36173	0	0	0
T3	157016	117040	0	0
T4	3939	3856	0	0
T6	21860	0	0	0
T7	7594	7232	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	107712	0	0
T17	0	7256	0	0
T18	0	558344	0	0
T19	0	298896	0	0
T20	0	31928	0	0
T25	0	124240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1841259	0	0
T1	301290	8617	0	0
T2	36173	0	0	0
T3	157016	4790	0	0
T4	3939	200	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T14	0	4569	0	0
T17	0	358	0	0
T18	0	14666	0	0
T19	0	7524	0	0
T20	0	1065	0	0
T25	0	3153	0	0
T43	0	1184	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T14,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T18
1	0	Covered	T3,T14,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T3,T14,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T14,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T14,T18
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T14,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T14,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	369852945	283533350	0	0
CheckNGreaterZero_A	1881	1881	0	0
GntImpliesReady_A	369852945	1368482	0	0
GntImpliesValid_A	369852945	1368482	0	0
GrantKnown_A	369852945	283533350	0	0
IdxKnown_A	369852945	283533350	0	0
IndexIsCorrect_A	369852945	1368482	0	0
LockArbDecision_A	369852945	0	0	0
NoReadyValidNoGrant_A	369852945	0	0	0
ReadyAndValidImplyGrant_A	369852945	1368482	0	0
ReqAndReadyImplyGrant_A	369852945	1368482	0	0
ReqImpliesValid_A	369852945	1368482	0	0
ReqStaysHighUntilGranted0_M	369852945	0	0	0
RoundRobin_A	369852945	0	0	0
ValidKnown_A	369852945	283533350	0	0
gen_data_port_assertion.DataFlow_A	369852945	1368482	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	283533350	0	0
T2	36173	35692	0	0
T3	157016	144234	0	0
T4	3939	0	0	0
T6	21860	21860	0	0
T7	7594	0	0	0
T8	64296	64002	0	0
T9	82146	82146	0	0
T10	176	176	0	0
T11	30382	30218	0	0
T12	8648	8352	0	0
T13	0	17110	0	0
T14	0	807117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1881	1881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1368482	0	0
T3	157016	10416	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	2283	0	0
T18	0	3719	0	0
T19	0	6360	0	0
T21	0	2845	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T44	0	2	0	0
T45	0	6571	0	0
T54	0	533	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1368482	0	0
T3	157016	10416	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	2283	0	0
T18	0	3719	0	0
T19	0	6360	0	0
T21	0	2845	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T44	0	2	0	0
T45	0	6571	0	0
T54	0	533	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	283533350	0	0
T2	36173	35692	0	0
T3	157016	144234	0	0
T4	3939	0	0	0
T6	21860	21860	0	0
T7	7594	0	0	0
T8	64296	64002	0	0
T9	82146	82146	0	0
T10	176	176	0	0
T11	30382	30218	0	0
T12	8648	8352	0	0
T13	0	17110	0	0
T14	0	807117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	283533350	0	0
T2	36173	35692	0	0
T3	157016	144234	0	0
T4	3939	0	0	0
T6	21860	21860	0	0
T7	7594	0	0	0
T8	64296	64002	0	0
T9	82146	82146	0	0
T10	176	176	0	0
T11	30382	30218	0	0
T12	8648	8352	0	0
T13	0	17110	0	0
T14	0	807117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1368482	0	0
T3	157016	10416	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	2283	0	0
T18	0	3719	0	0
T19	0	6360	0	0
T21	0	2845	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T44	0	2	0	0
T45	0	6571	0	0
T54	0	533	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1368482	0	0
T3	157016	10416	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	2283	0	0
T18	0	3719	0	0
T19	0	6360	0	0
T21	0	2845	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T44	0	2	0	0
T45	0	6571	0	0
T54	0	533	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1368482	0	0
T3	157016	10416	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	2283	0	0
T18	0	3719	0	0
T19	0	6360	0	0
T21	0	2845	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T44	0	2	0	0
T45	0	6571	0	0
T54	0	533	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1368482	0	0
T3	157016	10416	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	2283	0	0
T18	0	3719	0	0
T19	0	6360	0	0
T21	0	2845	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T44	0	2	0	0
T45	0	6571	0	0
T54	0	533	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	283533350	0	0
T2	36173	35692	0	0
T3	157016	144234	0	0
T4	3939	0	0	0
T6	21860	21860	0	0
T7	7594	0	0	0
T8	64296	64002	0	0
T9	82146	82146	0	0
T10	176	176	0	0
T11	30382	30218	0	0
T12	8648	8352	0	0
T13	0	17110	0	0
T14	0	807117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369852945	1368482	0	0
T3	157016	10416	0	0
T4	3939	0	0	0
T6	21860	0	0	0
T7	7594	0	0	0
T8	64296	0	0	0
T9	82146	0	0	0
T10	176	0	0	0
T11	30382	0	0	0
T12	8648	0	0	0
T13	17110	0	0	0
T14	0	2283	0	0
T18	0	3719	0	0
T19	0	6360	0	0
T21	0	2845	0	0
T27	0	2180	0	0
T42	0	4517	0	0
T44	0	2	0	0
T45	0	6571	0	0
T54	0	533	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1155154872	1154981316	0	0
CheckNGreaterZero_A	1881	1881	0	0
GntImpliesReady_A	1155154872	5423627	0	0
GntImpliesValid_A	1155154872	5423627	0	0
GrantKnown_A	1155154872	1154981316	0	0
IdxKnown_A	1155154872	1154981316	0	0
IndexIsCorrect_A	1155154872	5423627	0	0
LockArbDecision_A	1155154872	0	0	0
NoReadyValidNoGrant_A	1155154872	0	0	0
ReadyAndValidImplyGrant_A	1155154872	5423627	0	0
ReqAndReadyImplyGrant_A	1155154872	5423627	0	0
ReqImpliesValid_A	1155154872	5423627	0	0
ReqStaysHighUntilGranted0_M	1155154872	0	0	0
RoundRobin_A	1155154872	17	0	1881
ValidKnown_A	1155154872	1154981316	0	0
gen_data_port_assertion.DataFlow_A	1155154872	5423627	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	1154981316	0	0
T1	361367	361314	0	0
T2	294283	294199	0	0
T3	636211	636176	0	0
T4	25004	24925	0	0
T5	1645	1574	0	0
T6	47666	47582	0	0
T7	12070	12010	0	0
T8	74589	74494	0	0
T9	333548	333492	0	0
T10	4020	3921	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1881	1881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	5423627	0	0
T1	361367	3545	0	0
T2	294283	832	0	0
T3	636211	26314	0	0
T4	25004	98	0	0
T5	1645	0	0	0
T6	47666	832	0	0
T7	12070	0	0	0
T8	74589	832	0	0
T9	333548	2880	0	0
T10	4020	832	0	0
T11	0	832	0	0
T15	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	5423627	0	0
T1	361367	3545	0	0
T2	294283	832	0	0
T3	636211	26314	0	0
T4	25004	98	0	0
T5	1645	0	0	0
T6	47666	832	0	0
T7	12070	0	0	0
T8	74589	832	0	0
T9	333548	2880	0	0
T10	4020	832	0	0
T11	0	832	0	0
T15	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	1154981316	0	0
T1	361367	361314	0	0
T2	294283	294199	0	0
T3	636211	636176	0	0
T4	25004	24925	0	0
T5	1645	1574	0	0
T6	47666	47582	0	0
T7	12070	12010	0	0
T8	74589	74494	0	0
T9	333548	333492	0	0
T10	4020	3921	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	1154981316	0	0
T1	361367	361314	0	0
T2	294283	294199	0	0
T3	636211	636176	0	0
T4	25004	24925	0	0
T5	1645	1574	0	0
T6	47666	47582	0	0
T7	12070	12010	0	0
T8	74589	74494	0	0
T9	333548	333492	0	0
T10	4020	3921	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	5423627	0	0
T1	361367	3545	0	0
T2	294283	832	0	0
T3	636211	26314	0	0
T4	25004	98	0	0
T5	1645	0	0	0
T6	47666	832	0	0
T7	12070	0	0	0
T8	74589	832	0	0
T9	333548	2880	0	0
T10	4020	832	0	0
T11	0	832	0	0
T15	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	5423627	0	0
T1	361367	3545	0	0
T2	294283	832	0	0
T3	636211	26314	0	0
T4	25004	98	0	0
T5	1645	0	0	0
T6	47666	832	0	0
T7	12070	0	0	0
T8	74589	832	0	0
T9	333548	2880	0	0
T10	4020	832	0	0
T11	0	832	0	0
T15	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	5423627	0	0
T1	361367	3545	0	0
T2	294283	832	0	0
T3	636211	26314	0	0
T4	25004	98	0	0
T5	1645	0	0	0
T6	47666	832	0	0
T7	12070	0	0	0
T8	74589	832	0	0
T9	333548	2880	0	0
T10	4020	832	0	0
T11	0	832	0	0
T15	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	5423627	0	0
T1	361367	3545	0	0
T2	294283	832	0	0
T3	636211	26314	0	0
T4	25004	98	0	0
T5	1645	0	0	0
T6	47666	832	0	0
T7	12070	0	0	0
T8	74589	832	0	0
T9	333548	2880	0	0
T10	4020	832	0	0
T11	0	832	0	0
T15	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	17	0	1881
T3	636211	1	0	1
T4	25004	0	0	1
T5	1645	0	0	1
T6	47666	0	0	1
T7	12070	0	0	1
T8	74589	0	0	1
T9	333548	0	0	1
T10	4020	0	0	1
T15	2963	0	0	1
T16	1181	0	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	1154981316	0	0
T1	361367	361314	0	0
T2	294283	294199	0	0
T3	636211	636176	0	0
T4	25004	24925	0	0
T5	1645	1574	0	0
T6	47666	47582	0	0
T7	12070	12010	0	0
T8	74589	74494	0	0
T9	333548	333492	0	0
T10	4020	3921	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155154872	5423627	0	0
T1	361367	3545	0	0
T2	294283	832	0	0
T3	636211	26314	0	0
T4	25004	98	0	0
T5	1645	0	0	0
T6	47666	832	0	0
T7	12070	0	0	0
T8	74589	832	0	0
T9	333548	2880	0	0
T10	4020	832	0	0
T11	0	832	0	0
T15	0	200	0	0