Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.38 94.45 98.61 89.36 97.08 95.82 98.22


Total test records in report: 2231
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T1803 /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3172481868 Mar 10 01:52:40 PM PDT 24 Mar 10 01:53:13 PM PDT 24 39959801380 ps
T1804 /workspace/coverage/default/14.spi_device_cfg_cmd.20842407 Mar 10 01:50:00 PM PDT 24 Mar 10 01:50:03 PM PDT 24 487608957 ps
T1805 /workspace/coverage/default/37.spi_device_upload.4176131055 Mar 10 01:51:55 PM PDT 24 Mar 10 01:51:59 PM PDT 24 951369751 ps
T1806 /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3689031780 Mar 10 02:47:35 PM PDT 24 Mar 10 02:47:48 PM PDT 24 3703960450 ps
T1807 /workspace/coverage/default/1.spi_device_tpm_all.2720824099 Mar 10 01:48:50 PM PDT 24 Mar 10 01:48:53 PM PDT 24 923210221 ps
T1808 /workspace/coverage/default/11.spi_device_mem_parity.3712278796 Mar 10 01:49:43 PM PDT 24 Mar 10 01:49:45 PM PDT 24 16748942 ps
T1809 /workspace/coverage/default/7.spi_device_stress_all.1328034176 Mar 10 02:46:33 PM PDT 24 Mar 10 02:46:35 PM PDT 24 201154931 ps
T1810 /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1409373713 Mar 10 02:48:36 PM PDT 24 Mar 10 02:49:42 PM PDT 24 3453353273 ps
T1811 /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2347309116 Mar 10 01:52:14 PM PDT 24 Mar 10 01:52:28 PM PDT 24 14268807827 ps
T1812 /workspace/coverage/default/17.spi_device_intercept.2391151059 Mar 10 02:47:10 PM PDT 24 Mar 10 02:47:15 PM PDT 24 4969097627 ps
T1813 /workspace/coverage/default/14.spi_device_mailbox.2103152767 Mar 10 01:50:01 PM PDT 24 Mar 10 01:50:08 PM PDT 24 2891949418 ps
T1814 /workspace/coverage/default/26.spi_device_upload.1475741245 Mar 10 02:47:45 PM PDT 24 Mar 10 02:48:09 PM PDT 24 7733122272 ps
T1815 /workspace/coverage/default/18.spi_device_flash_and_tpm.2657475848 Mar 10 02:47:16 PM PDT 24 Mar 10 02:48:33 PM PDT 24 15068131536 ps
T1816 /workspace/coverage/default/13.spi_device_read_buffer_direct.868059522 Mar 10 02:47:02 PM PDT 24 Mar 10 02:47:06 PM PDT 24 968449985 ps
T1817 /workspace/coverage/default/34.spi_device_alert_test.3368161354 Mar 10 02:48:20 PM PDT 24 Mar 10 02:48:21 PM PDT 24 24281130 ps
T1818 /workspace/coverage/default/45.spi_device_stress_all.2034548453 Mar 10 02:49:00 PM PDT 24 Mar 10 02:52:02 PM PDT 24 75812981888 ps
T1819 /workspace/coverage/default/6.spi_device_mem_parity.2194968779 Mar 10 01:49:12 PM PDT 24 Mar 10 01:49:13 PM PDT 24 17563464 ps
T1820 /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1568960714 Mar 10 01:50:46 PM PDT 24 Mar 10 01:51:03 PM PDT 24 4875693698 ps
T1821 /workspace/coverage/default/9.spi_device_flash_all.2075636314 Mar 10 01:49:30 PM PDT 24 Mar 10 01:51:40 PM PDT 24 30557961321 ps
T1822 /workspace/coverage/default/19.spi_device_tpm_all.2256858156 Mar 10 01:50:24 PM PDT 24 Mar 10 01:50:55 PM PDT 24 4922079723 ps
T1823 /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1611180150 Mar 10 02:49:05 PM PDT 24 Mar 10 02:49:11 PM PDT 24 2122786941 ps
T1824 /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3364701167 Mar 10 02:46:12 PM PDT 24 Mar 10 02:46:34 PM PDT 24 11978117289 ps
T1825 /workspace/coverage/default/36.spi_device_flash_mode.452994700 Mar 10 02:48:24 PM PDT 24 Mar 10 02:48:32 PM PDT 24 2278764456 ps
T1826 /workspace/coverage/default/14.spi_device_csb_read.3140895899 Mar 10 02:47:00 PM PDT 24 Mar 10 02:47:01 PM PDT 24 20883922 ps
T1827 /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3089846548 Mar 10 02:47:00 PM PDT 24 Mar 10 02:47:04 PM PDT 24 456077674 ps
T1828 /workspace/coverage/default/38.spi_device_alert_test.4255689995 Mar 10 02:48:33 PM PDT 24 Mar 10 02:48:34 PM PDT 24 30816359 ps
T1829 /workspace/coverage/default/36.spi_device_csb_read.3485884714 Mar 10 01:51:44 PM PDT 24 Mar 10 01:51:45 PM PDT 24 24047072 ps
T1830 /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4174184753 Mar 10 02:46:57 PM PDT 24 Mar 10 02:47:51 PM PDT 24 14755329782 ps
T1831 /workspace/coverage/default/33.spi_device_stress_all.1199066308 Mar 10 02:48:16 PM PDT 24 Mar 10 02:53:42 PM PDT 24 195736052262 ps
T1832 /workspace/coverage/default/38.spi_device_mailbox.3642632960 Mar 10 02:48:31 PM PDT 24 Mar 10 02:48:40 PM PDT 24 2869810243 ps
T1833 /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1673386949 Mar 10 01:50:12 PM PDT 24 Mar 10 01:50:32 PM PDT 24 5498884395 ps
T1834 /workspace/coverage/default/31.spi_device_tpm_sts_read.3410196295 Mar 10 02:48:05 PM PDT 24 Mar 10 02:48:06 PM PDT 24 186693385 ps
T1835 /workspace/coverage/default/21.spi_device_flash_mode.1041679023 Mar 10 01:50:35 PM PDT 24 Mar 10 01:51:20 PM PDT 24 7233330252 ps
T1836 /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.552565020 Mar 10 01:49:27 PM PDT 24 Mar 10 01:49:56 PM PDT 24 10523380279 ps
T1837 /workspace/coverage/default/42.spi_device_read_buffer_direct.2611691334 Mar 10 01:52:13 PM PDT 24 Mar 10 01:52:19 PM PDT 24 604639651 ps
T1838 /workspace/coverage/default/33.spi_device_tpm_sts_read.3089288395 Mar 10 01:51:29 PM PDT 24 Mar 10 01:51:30 PM PDT 24 15675939 ps
T1839 /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3531213015 Mar 10 01:52:36 PM PDT 24 Mar 10 01:52:43 PM PDT 24 4229175612 ps
T1840 /workspace/coverage/default/0.spi_device_intercept.2244266374 Mar 10 01:48:47 PM PDT 24 Mar 10 01:48:51 PM PDT 24 126410922 ps
T1841 /workspace/coverage/default/26.spi_device_flash_all.29905695 Mar 10 02:47:45 PM PDT 24 Mar 10 02:50:57 PM PDT 24 38668041509 ps
T1842 /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.212723575 Mar 10 01:50:39 PM PDT 24 Mar 10 01:50:47 PM PDT 24 3058574861 ps
T1843 /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2265872283 Mar 10 01:51:15 PM PDT 24 Mar 10 01:51:37 PM PDT 24 29770927658 ps
T1844 /workspace/coverage/default/45.spi_device_tpm_sts_read.912128459 Mar 10 02:48:55 PM PDT 24 Mar 10 02:48:58 PM PDT 24 104566009 ps
T1845 /workspace/coverage/default/48.spi_device_intercept.700513221 Mar 10 01:52:48 PM PDT 24 Mar 10 01:52:51 PM PDT 24 298635777 ps
T1846 /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.896632440 Mar 10 01:52:31 PM PDT 24 Mar 10 01:52:48 PM PDT 24 11024006439 ps
T1847 /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4005735286 Mar 10 02:47:43 PM PDT 24 Mar 10 02:49:40 PM PDT 24 33966217634 ps
T1848 /workspace/coverage/default/11.spi_device_tpm_all.1141942375 Mar 10 02:46:50 PM PDT 24 Mar 10 02:47:13 PM PDT 24 4871991468 ps
T1849 /workspace/coverage/default/40.spi_device_tpm_sts_read.1233653448 Mar 10 01:52:03 PM PDT 24 Mar 10 01:52:04 PM PDT 24 219881412 ps
T1850 /workspace/coverage/default/9.spi_device_cfg_cmd.1550574516 Mar 10 01:49:31 PM PDT 24 Mar 10 01:49:35 PM PDT 24 95772707 ps
T1851 /workspace/coverage/default/35.spi_device_flash_and_tpm.3245399420 Mar 10 02:48:22 PM PDT 24 Mar 10 02:53:03 PM PDT 24 219114448186 ps
T1852 /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2020270986 Mar 10 02:49:05 PM PDT 24 Mar 10 02:49:10 PM PDT 24 668051020 ps
T1853 /workspace/coverage/default/32.spi_device_cfg_cmd.875732471 Mar 10 01:51:27 PM PDT 24 Mar 10 01:51:48 PM PDT 24 108924154207 ps
T1854 /workspace/coverage/default/25.spi_device_read_buffer_direct.475703154 Mar 10 01:50:54 PM PDT 24 Mar 10 01:50:58 PM PDT 24 128427542 ps
T1855 /workspace/coverage/default/48.spi_device_tpm_sts_read.2682581407 Mar 10 01:52:41 PM PDT 24 Mar 10 01:52:42 PM PDT 24 126288471 ps
T1856 /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1449351630 Mar 10 01:49:26 PM PDT 24 Mar 10 01:49:30 PM PDT 24 7131794361 ps
T1857 /workspace/coverage/default/19.spi_device_upload.4251015186 Mar 10 02:47:19 PM PDT 24 Mar 10 02:47:23 PM PDT 24 413011947 ps
T1858 /workspace/coverage/default/34.spi_device_flash_mode.1944635507 Mar 10 01:51:33 PM PDT 24 Mar 10 01:51:59 PM PDT 24 5042676485 ps
T1859 /workspace/coverage/default/13.spi_device_mem_parity.1298286456 Mar 10 02:46:59 PM PDT 24 Mar 10 02:47:00 PM PDT 24 16035285 ps
T1860 /workspace/coverage/default/4.spi_device_tpm_all.1901320391 Mar 10 02:46:19 PM PDT 24 Mar 10 02:46:32 PM PDT 24 1817919013 ps
T1861 /workspace/coverage/default/44.spi_device_alert_test.270186403 Mar 10 02:49:10 PM PDT 24 Mar 10 02:49:10 PM PDT 24 12844361 ps
T1862 /workspace/coverage/default/31.spi_device_mailbox.1924657614 Mar 10 01:51:21 PM PDT 24 Mar 10 01:51:46 PM PDT 24 28366885319 ps
T1863 /workspace/coverage/default/6.spi_device_flash_mode.2009981030 Mar 10 01:49:19 PM PDT 24 Mar 10 01:49:51 PM PDT 24 12040958899 ps
T1864 /workspace/coverage/default/26.spi_device_tpm_all.516749617 Mar 10 01:50:57 PM PDT 24 Mar 10 01:51:40 PM PDT 24 13138734801 ps
T1865 /workspace/coverage/default/12.spi_device_alert_test.2848628150 Mar 10 02:46:57 PM PDT 24 Mar 10 02:46:58 PM PDT 24 38965501 ps
T1866 /workspace/coverage/default/38.spi_device_upload.38862769 Mar 10 01:51:54 PM PDT 24 Mar 10 01:52:04 PM PDT 24 1484494439 ps
T1867 /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3619215074 Mar 10 02:48:50 PM PDT 24 Mar 10 02:52:51 PM PDT 24 34360409179 ps
T1868 /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3741831386 Mar 10 01:49:26 PM PDT 24 Mar 10 01:50:27 PM PDT 24 26930246765 ps
T1869 /workspace/coverage/default/40.spi_device_tpm_sts_read.2982524463 Mar 10 02:48:39 PM PDT 24 Mar 10 02:48:40 PM PDT 24 61706359 ps
T1870 /workspace/coverage/default/27.spi_device_cfg_cmd.273564496 Mar 10 01:51:01 PM PDT 24 Mar 10 01:51:07 PM PDT 24 404534619 ps
T1871 /workspace/coverage/default/8.spi_device_tpm_rw.2351759316 Mar 10 02:46:42 PM PDT 24 Mar 10 02:46:45 PM PDT 24 691193562 ps
T1872 /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3123923873 Mar 10 01:51:50 PM PDT 24 Mar 10 01:52:00 PM PDT 24 2246026231 ps
T1873 /workspace/coverage/default/35.spi_device_stress_all.2785337863 Mar 10 01:51:46 PM PDT 24 Mar 10 01:52:19 PM PDT 24 30432582263 ps
T1874 /workspace/coverage/default/33.spi_device_mailbox.2921596351 Mar 10 02:48:15 PM PDT 24 Mar 10 02:48:28 PM PDT 24 2595472556 ps
T1875 /workspace/coverage/default/30.spi_device_read_buffer_direct.2512873952 Mar 10 01:51:19 PM PDT 24 Mar 10 01:51:27 PM PDT 24 1674389328 ps
T1876 /workspace/coverage/default/7.spi_device_cfg_cmd.4138328032 Mar 10 02:46:33 PM PDT 24 Mar 10 02:46:36 PM PDT 24 458545320 ps
T1877 /workspace/coverage/default/21.spi_device_flash_all.3098739974 Mar 10 01:50:37 PM PDT 24 Mar 10 01:52:47 PM PDT 24 25885011663 ps
T1878 /workspace/coverage/default/30.spi_device_cfg_cmd.4269668585 Mar 10 02:48:05 PM PDT 24 Mar 10 02:48:08 PM PDT 24 94571880 ps
T1879 /workspace/coverage/default/49.spi_device_tpm_all.2872548027 Mar 10 01:52:47 PM PDT 24 Mar 10 01:52:52 PM PDT 24 661055538 ps
T1880 /workspace/coverage/default/8.spi_device_mem_parity.497513422 Mar 10 01:49:27 PM PDT 24 Mar 10 01:49:29 PM PDT 24 16841541 ps
T1881 /workspace/coverage/default/37.spi_device_cfg_cmd.1456093638 Mar 10 01:51:50 PM PDT 24 Mar 10 01:51:55 PM PDT 24 2713200374 ps
T1882 /workspace/coverage/default/42.spi_device_flash_mode.3416516902 Mar 10 02:48:51 PM PDT 24 Mar 10 02:49:12 PM PDT 24 751002597 ps
T1883 /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1178496179 Mar 10 02:47:52 PM PDT 24 Mar 10 02:48:11 PM PDT 24 12446384454 ps
T1884 /workspace/coverage/default/11.spi_device_read_buffer_direct.1462925338 Mar 10 02:46:51 PM PDT 24 Mar 10 02:46:57 PM PDT 24 1147637118 ps
T1885 /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2191285190 Mar 10 01:50:25 PM PDT 24 Mar 10 01:50:36 PM PDT 24 2807819419 ps
T1886 /workspace/coverage/default/25.spi_device_tpm_all.72830208 Mar 10 01:50:48 PM PDT 24 Mar 10 01:51:08 PM PDT 24 10626435249 ps
T1887 /workspace/coverage/default/48.spi_device_flash_and_tpm.4113490267 Mar 10 02:49:12 PM PDT 24 Mar 10 02:50:02 PM PDT 24 8006338095 ps
T1888 /workspace/coverage/default/21.spi_device_read_buffer_direct.2905523134 Mar 10 01:50:36 PM PDT 24 Mar 10 01:50:41 PM PDT 24 1772773873 ps
T1889 /workspace/coverage/default/13.spi_device_csb_read.256684655 Mar 10 02:46:57 PM PDT 24 Mar 10 02:46:58 PM PDT 24 26004604 ps
T1890 /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2136902808 Mar 10 01:51:21 PM PDT 24 Mar 10 01:51:24 PM PDT 24 418361677 ps
T1891 /workspace/coverage/default/2.spi_device_tpm_sts_read.1050597246 Mar 10 02:46:20 PM PDT 24 Mar 10 02:46:21 PM PDT 24 89874807 ps
T1892 /workspace/coverage/default/45.spi_device_flash_and_tpm.2968809382 Mar 10 02:49:01 PM PDT 24 Mar 10 02:50:42 PM PDT 24 9892165837 ps
T1893 /workspace/coverage/default/21.spi_device_stress_all.3216717451 Mar 10 01:50:37 PM PDT 24 Mar 10 01:52:45 PM PDT 24 18429934950 ps
T1894 /workspace/coverage/default/17.spi_device_alert_test.3577513781 Mar 10 01:50:20 PM PDT 24 Mar 10 01:50:21 PM PDT 24 38656424 ps
T1895 /workspace/coverage/default/28.spi_device_mailbox.2268586426 Mar 10 01:51:09 PM PDT 24 Mar 10 01:51:52 PM PDT 24 58775806177 ps
T1896 /workspace/coverage/default/34.spi_device_csb_read.1464136338 Mar 10 01:51:33 PM PDT 24 Mar 10 01:51:35 PM PDT 24 20789260 ps
T1897 /workspace/coverage/default/2.spi_device_flash_mode.951830132 Mar 10 01:49:00 PM PDT 24 Mar 10 01:49:19 PM PDT 24 8725104046 ps
T1898 /workspace/coverage/default/13.spi_device_cfg_cmd.635947542 Mar 10 01:49:52 PM PDT 24 Mar 10 01:50:00 PM PDT 24 1687918287 ps
T1899 /workspace/coverage/default/25.spi_device_csb_read.3748899650 Mar 10 02:47:39 PM PDT 24 Mar 10 02:47:39 PM PDT 24 37703383 ps
T1900 /workspace/coverage/default/11.spi_device_flash_mode.1956943721 Mar 10 02:46:50 PM PDT 24 Mar 10 02:47:02 PM PDT 24 2162928191 ps
T1901 /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.296827451 Mar 10 01:49:51 PM PDT 24 Mar 10 01:49:58 PM PDT 24 1675838777 ps
T1902 /workspace/coverage/default/7.spi_device_flash_mode.832530876 Mar 10 01:49:22 PM PDT 24 Mar 10 01:49:55 PM PDT 24 23825206716 ps
T1903 /workspace/coverage/default/29.spi_device_pass_cmd_filtering.776748974 Mar 10 01:51:10 PM PDT 24 Mar 10 01:51:38 PM PDT 24 9954682798 ps
T1904 /workspace/coverage/default/41.spi_device_tpm_rw.877757397 Mar 10 02:48:44 PM PDT 24 Mar 10 02:48:48 PM PDT 24 1113991770 ps
T1905 /workspace/coverage/default/28.spi_device_alert_test.225636234 Mar 10 01:51:10 PM PDT 24 Mar 10 01:51:11 PM PDT 24 76649207 ps
T1906 /workspace/coverage/default/6.spi_device_flash_and_tpm.769015852 Mar 10 02:46:29 PM PDT 24 Mar 10 02:47:53 PM PDT 24 8286021597 ps
T1907 /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3006432359 Mar 10 02:46:28 PM PDT 24 Mar 10 02:52:38 PM PDT 24 50765566808 ps
T1908 /workspace/coverage/default/27.spi_device_flash_mode.3992621847 Mar 10 01:51:05 PM PDT 24 Mar 10 01:51:18 PM PDT 24 12831204120 ps
T1909 /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.674385228 Mar 10 01:49:21 PM PDT 24 Mar 10 01:49:50 PM PDT 24 6162545014 ps
T1910 /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2958911779 Mar 10 02:48:58 PM PDT 24 Mar 10 02:49:02 PM PDT 24 1880505460 ps
T1911 /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2685952023 Mar 10 01:50:28 PM PDT 24 Mar 10 01:50:34 PM PDT 24 1551831114 ps
T1912 /workspace/coverage/default/34.spi_device_flash_all.1590369291 Mar 10 02:48:22 PM PDT 24 Mar 10 02:48:56 PM PDT 24 6692039377 ps
T1913 /workspace/coverage/default/17.spi_device_tpm_all.3988290839 Mar 10 02:47:11 PM PDT 24 Mar 10 02:47:42 PM PDT 24 4437798071 ps
T1914 /workspace/coverage/default/32.spi_device_csb_read.3202808181 Mar 10 02:48:08 PM PDT 24 Mar 10 02:48:08 PM PDT 24 14907692 ps
T1915 /workspace/coverage/default/26.spi_device_flash_and_tpm.3515045237 Mar 10 02:47:48 PM PDT 24 Mar 10 03:00:08 PM PDT 24 645933976421 ps
T1916 /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1548167466 Mar 10 02:48:07 PM PDT 24 Mar 10 02:49:18 PM PDT 24 13637859275 ps
T1917 /workspace/coverage/default/30.spi_device_alert_test.2348697549 Mar 10 02:48:09 PM PDT 24 Mar 10 02:48:10 PM PDT 24 26481430 ps
T1918 /workspace/coverage/default/45.spi_device_tpm_all.1870600036 Mar 10 02:48:55 PM PDT 24 Mar 10 02:49:12 PM PDT 24 3231202130 ps
T1919 /workspace/coverage/default/29.spi_device_upload.57313415 Mar 10 01:51:10 PM PDT 24 Mar 10 01:51:18 PM PDT 24 1884184495 ps
T1920 /workspace/coverage/default/16.spi_device_tpm_all.1414134903 Mar 10 02:47:07 PM PDT 24 Mar 10 02:47:22 PM PDT 24 4001281282 ps
T1921 /workspace/coverage/default/10.spi_device_upload.905471882 Mar 10 02:46:48 PM PDT 24 Mar 10 02:46:55 PM PDT 24 8648734574 ps
T1922 /workspace/coverage/default/40.spi_device_upload.1636838428 Mar 10 01:52:09 PM PDT 24 Mar 10 01:52:20 PM PDT 24 4071935350 ps
T1923 /workspace/coverage/default/43.spi_device_cfg_cmd.3840478052 Mar 10 02:48:49 PM PDT 24 Mar 10 02:48:54 PM PDT 24 342768667 ps
T1924 /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3605532145 Mar 10 02:48:55 PM PDT 24 Mar 10 02:49:06 PM PDT 24 3120315931 ps
T1925 /workspace/coverage/default/28.spi_device_intercept.2949192210 Mar 10 02:47:50 PM PDT 24 Mar 10 02:47:54 PM PDT 24 454682405 ps
T1926 /workspace/coverage/default/43.spi_device_flash_mode.1055091686 Mar 10 01:52:16 PM PDT 24 Mar 10 01:52:29 PM PDT 24 479144569 ps
T1927 /workspace/coverage/default/28.spi_device_tpm_sts_read.2745693059 Mar 10 01:51:05 PM PDT 24 Mar 10 01:51:07 PM PDT 24 226122810 ps
T1928 /workspace/coverage/default/41.spi_device_cfg_cmd.2909132373 Mar 10 01:52:09 PM PDT 24 Mar 10 01:52:13 PM PDT 24 689721923 ps
T1929 /workspace/coverage/default/17.spi_device_upload.59543009 Mar 10 02:47:10 PM PDT 24 Mar 10 02:47:23 PM PDT 24 10364765496 ps
T1930 /workspace/coverage/default/21.spi_device_upload.23508610 Mar 10 02:47:31 PM PDT 24 Mar 10 02:47:48 PM PDT 24 9024352346 ps
T1931 /workspace/coverage/default/38.spi_device_flash_mode.1105553402 Mar 10 02:48:33 PM PDT 24 Mar 10 02:48:46 PM PDT 24 454718436 ps
T1932 /workspace/coverage/default/44.spi_device_stress_all.522474502 Mar 10 01:52:21 PM PDT 24 Mar 10 02:00:13 PM PDT 24 67593990781 ps
T1933 /workspace/coverage/default/0.spi_device_flash_all.2812811837 Mar 10 01:48:44 PM PDT 24 Mar 10 01:54:46 PM PDT 24 310794960571 ps
T92 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.692355278 Mar 10 01:00:53 PM PDT 24 Mar 10 01:00:56 PM PDT 24 36880211 ps
T1934 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3596524831 Mar 10 01:00:31 PM PDT 24 Mar 10 01:00:32 PM PDT 24 21505458 ps
T1935 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3888266189 Mar 10 01:01:06 PM PDT 24 Mar 10 01:01:07 PM PDT 24 12859772 ps
T1936 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1115344965 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:30 PM PDT 24 16629030 ps
T1937 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1462463271 Mar 10 01:01:43 PM PDT 24 Mar 10 01:01:43 PM PDT 24 39071476 ps
T113 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2140951345 Mar 10 01:18:02 PM PDT 24 Mar 10 01:18:10 PM PDT 24 397687489 ps
T93 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1806605101 Mar 10 01:00:26 PM PDT 24 Mar 10 01:00:30 PM PDT 24 188323262 ps
T94 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1627520546 Mar 10 01:01:21 PM PDT 24 Mar 10 01:01:25 PM PDT 24 218349387 ps
T1938 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2274971276 Mar 10 01:18:33 PM PDT 24 Mar 10 01:18:34 PM PDT 24 59428130 ps
T1939 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1885684666 Mar 10 01:01:31 PM PDT 24 Mar 10 01:01:34 PM PDT 24 303472885 ps
T81 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2227053300 Mar 10 01:00:27 PM PDT 24 Mar 10 01:00:29 PM PDT 24 22436284 ps
T95 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2140729571 Mar 10 01:00:36 PM PDT 24 Mar 10 01:00:39 PM PDT 24 178984427 ps
T1940 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3804817345 Mar 10 01:18:32 PM PDT 24 Mar 10 01:18:33 PM PDT 24 14686272 ps
T96 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1667836731 Mar 10 01:17:55 PM PDT 24 Mar 10 01:18:00 PM PDT 24 221632786 ps
T111 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2830161983 Mar 10 01:18:05 PM PDT 24 Mar 10 01:18:09 PM PDT 24 581454790 ps
T97 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1151619260 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:27 PM PDT 24 764329432 ps
T114 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1678267025 Mar 10 01:18:21 PM PDT 24 Mar 10 01:18:23 PM PDT 24 130891263 ps
T1941 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4237926446 Mar 10 01:18:34 PM PDT 24 Mar 10 01:18:35 PM PDT 24 29222865 ps
T1942 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2008318857 Mar 10 01:01:34 PM PDT 24 Mar 10 01:01:35 PM PDT 24 22063127 ps
T144 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4083065277 Mar 10 01:00:49 PM PDT 24 Mar 10 01:01:03 PM PDT 24 920445275 ps
T109 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2188208611 Mar 10 01:18:09 PM PDT 24 Mar 10 01:18:12 PM PDT 24 39644143 ps
T1943 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.138208450 Mar 10 01:18:33 PM PDT 24 Mar 10 01:18:34 PM PDT 24 31197342 ps
T115 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.75644753 Mar 10 01:17:51 PM PDT 24 Mar 10 01:18:03 PM PDT 24 2968168756 ps
T98 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3385885782 Mar 10 01:01:02 PM PDT 24 Mar 10 01:01:19 PM PDT 24 2718618323 ps
T1944 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1585251767 Mar 10 01:17:59 PM PDT 24 Mar 10 01:18:01 PM PDT 24 43029430 ps
T1945 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.878158461 Mar 10 01:18:31 PM PDT 24 Mar 10 01:18:32 PM PDT 24 61059622 ps
T116 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3295724554 Mar 10 01:01:06 PM PDT 24 Mar 10 01:01:09 PM PDT 24 126820390 ps
T1946 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2095620478 Mar 10 01:18:19 PM PDT 24 Mar 10 01:18:20 PM PDT 24 17233628 ps
T117 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3368130084 Mar 10 01:01:32 PM PDT 24 Mar 10 01:01:33 PM PDT 24 20341296 ps
T82 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1757570955 Mar 10 01:17:52 PM PDT 24 Mar 10 01:17:53 PM PDT 24 22466419 ps
T145 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2377362080 Mar 10 01:18:24 PM PDT 24 Mar 10 01:18:29 PM PDT 24 823021881 ps
T112 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1643356596 Mar 10 01:18:12 PM PDT 24 Mar 10 01:18:14 PM PDT 24 220031512 ps
T1947 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3397058294 Mar 10 01:00:27 PM PDT 24 Mar 10 01:00:29 PM PDT 24 27681218 ps
T1948 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3357899861 Mar 10 01:00:54 PM PDT 24 Mar 10 01:00:55 PM PDT 24 14118764 ps
T1949 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3573508858 Mar 10 01:00:26 PM PDT 24 Mar 10 01:00:27 PM PDT 24 11435809 ps
T102 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3981109342 Mar 10 01:18:07 PM PDT 24 Mar 10 01:18:11 PM PDT 24 58169355 ps
T108 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.898371657 Mar 10 01:17:48 PM PDT 24 Mar 10 01:17:51 PM PDT 24 34077935 ps
T118 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3756733118 Mar 10 01:00:38 PM PDT 24 Mar 10 01:00:53 PM PDT 24 945712045 ps
T1950 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1783084372 Mar 10 01:00:33 PM PDT 24 Mar 10 01:00:35 PM PDT 24 29131026 ps
T103 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3143004925 Mar 10 01:17:57 PM PDT 24 Mar 10 01:18:00 PM PDT 24 344759948 ps
T104 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3837164718 Mar 10 01:18:24 PM PDT 24 Mar 10 01:18:27 PM PDT 24 324015655 ps
T105 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1728504769 Mar 10 01:18:17 PM PDT 24 Mar 10 01:18:20 PM PDT 24 179956718 ps
T1951 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3909782778 Mar 10 01:01:05 PM PDT 24 Mar 10 01:01:07 PM PDT 24 73693415 ps
T1952 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2719492957 Mar 10 01:17:49 PM PDT 24 Mar 10 01:17:50 PM PDT 24 20527908 ps
T1953 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1955478718 Mar 10 01:18:04 PM PDT 24 Mar 10 01:18:06 PM PDT 24 37848279 ps
T119 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3573996365 Mar 10 01:01:24 PM PDT 24 Mar 10 01:01:26 PM PDT 24 20836554 ps
T1954 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1219519245 Mar 10 01:01:45 PM PDT 24 Mar 10 01:01:46 PM PDT 24 17867238 ps
T99 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1105214380 Mar 10 01:01:25 PM PDT 24 Mar 10 01:01:39 PM PDT 24 4528796111 ps
T146 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3316707301 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:16 PM PDT 24 126881513 ps
T1955 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3331742296 Mar 10 01:00:37 PM PDT 24 Mar 10 01:00:40 PM PDT 24 42994829 ps
T1956 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1476370065 Mar 10 01:18:33 PM PDT 24 Mar 10 01:18:34 PM PDT 24 12294768 ps
T1957 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.613791697 Mar 10 01:17:55 PM PDT 24 Mar 10 01:18:08 PM PDT 24 385188167 ps
T120 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1361617349 Mar 10 01:18:08 PM PDT 24 Mar 10 01:18:10 PM PDT 24 20679989 ps
T1958 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.375297112 Mar 10 01:01:42 PM PDT 24 Mar 10 01:01:43 PM PDT 24 52329020 ps
T1959 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2020155891 Mar 10 01:01:36 PM PDT 24 Mar 10 01:01:38 PM PDT 24 79474879 ps
T1960 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3086876488 Mar 10 01:18:34 PM PDT 24 Mar 10 01:18:35 PM PDT 24 41000811 ps
T174 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1117527792 Mar 10 01:17:49 PM PDT 24 Mar 10 01:18:09 PM PDT 24 284810094 ps
T149 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.584164748 Mar 10 01:01:17 PM PDT 24 Mar 10 01:01:19 PM PDT 24 211748034 ps
T177 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3672816345 Mar 10 01:17:59 PM PDT 24 Mar 10 01:18:18 PM PDT 24 2525205214 ps
T1961 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2715843802 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:19 PM PDT 24 322225728 ps
T1962 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.971722977 Mar 10 01:01:09 PM PDT 24 Mar 10 01:01:15 PM PDT 24 85776648 ps
T1963 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3600636011 Mar 10 01:01:06 PM PDT 24 Mar 10 01:01:08 PM PDT 24 154497376 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3130733530 Mar 10 01:00:26 PM PDT 24 Mar 10 01:00:28 PM PDT 24 83253206 ps
T1964 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1483968804 Mar 10 01:00:37 PM PDT 24 Mar 10 01:00:38 PM PDT 24 11688935 ps
T147 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2483514914 Mar 10 01:18:00 PM PDT 24 Mar 10 01:18:04 PM PDT 24 201777244 ps
T122 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4293388883 Mar 10 01:01:05 PM PDT 24 Mar 10 01:01:08 PM PDT 24 38692818 ps
T148 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2803952235 Mar 10 01:18:11 PM PDT 24 Mar 10 01:18:13 PM PDT 24 302821546 ps
T1965 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3680758974 Mar 10 01:17:50 PM PDT 24 Mar 10 01:17:52 PM PDT 24 64471300 ps
T1966 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1470525175 Mar 10 01:00:30 PM PDT 24 Mar 10 01:00:32 PM PDT 24 164307399 ps
T1967 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1736222281 Mar 10 01:00:53 PM PDT 24 Mar 10 01:00:56 PM PDT 24 161959978 ps
T1968 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3531973794 Mar 10 01:01:12 PM PDT 24 Mar 10 01:01:14 PM PDT 24 11448718 ps
T83 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1685940054 Mar 10 01:18:07 PM PDT 24 Mar 10 01:18:08 PM PDT 24 16764489 ps
T110 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2899913974 Mar 10 01:01:31 PM PDT 24 Mar 10 01:01:33 PM PDT 24 28181316 ps
T1969 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3219912137 Mar 10 01:01:32 PM PDT 24 Mar 10 01:01:33 PM PDT 24 15704186 ps
T1970 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1486857979 Mar 10 01:00:54 PM PDT 24 Mar 10 01:00:59 PM PDT 24 637021723 ps
T1971 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2871055348 Mar 10 01:00:32 PM PDT 24 Mar 10 01:00:36 PM PDT 24 1105838686 ps
T181 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2235160075 Mar 10 01:00:54 PM PDT 24 Mar 10 01:01:10 PM PDT 24 1064014116 ps
T1972 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.562454410 Mar 10 01:01:09 PM PDT 24 Mar 10 01:01:12 PM PDT 24 175009312 ps
T1973 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4221444505 Mar 10 01:18:31 PM PDT 24 Mar 10 01:18:32 PM PDT 24 16548403 ps
T1974 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4235040494 Mar 10 01:01:12 PM PDT 24 Mar 10 01:01:14 PM PDT 24 132421983 ps
T175 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2271352649 Mar 10 01:18:11 PM PDT 24 Mar 10 01:18:25 PM PDT 24 1156348477 ps
T1975 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1712672171 Mar 10 01:18:09 PM PDT 24 Mar 10 01:18:14 PM PDT 24 1129236399 ps
T1976 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4041823371 Mar 10 01:01:20 PM PDT 24 Mar 10 01:01:23 PM PDT 24 440105853 ps
T1977 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.758430371 Mar 10 01:01:35 PM PDT 24 Mar 10 01:01:36 PM PDT 24 16073035 ps
T123 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1927047928 Mar 10 01:01:05 PM PDT 24 Mar 10 01:01:08 PM PDT 24 30401900 ps
T1978 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.511858990 Mar 10 01:01:47 PM PDT 24 Mar 10 01:01:47 PM PDT 24 33949255 ps
T1979 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3197121691 Mar 10 01:17:49 PM PDT 24 Mar 10 01:17:50 PM PDT 24 51643910 ps
T1980 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.527465279 Mar 10 01:00:54 PM PDT 24 Mar 10 01:00:58 PM PDT 24 542404377 ps
T1981 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1696276275 Mar 10 01:01:31 PM PDT 24 Mar 10 01:01:33 PM PDT 24 131111111 ps
T1982 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2942364071 Mar 10 01:01:02 PM PDT 24 Mar 10 01:01:04 PM PDT 24 67952716 ps
T1983 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3133693307 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:32 PM PDT 24 293628806 ps
T1984 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.40452287 Mar 10 01:18:28 PM PDT 24 Mar 10 01:18:29 PM PDT 24 51319410 ps
T1985 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.526921541 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:16 PM PDT 24 200913706 ps
T1986 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.606358172 Mar 10 01:18:34 PM PDT 24 Mar 10 01:18:35 PM PDT 24 135160442 ps
T1987 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1898310979 Mar 10 01:01:27 PM PDT 24 Mar 10 01:01:31 PM PDT 24 705695463 ps
T124 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4232850938 Mar 10 01:17:58 PM PDT 24 Mar 10 01:18:24 PM PDT 24 5031678031 ps
T1988 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.980494916 Mar 10 01:17:52 PM PDT 24 Mar 10 01:17:57 PM PDT 24 614537032 ps
T1989 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2328247293 Mar 10 01:00:50 PM PDT 24 Mar 10 01:00:51 PM PDT 24 16844941 ps
T1990 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2445547802 Mar 10 01:01:19 PM PDT 24 Mar 10 01:01:21 PM PDT 24 81396242 ps
T1991 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.383562056 Mar 10 01:00:31 PM PDT 24 Mar 10 01:00:31 PM PDT 24 11431206 ps
T125 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3697633020 Mar 10 01:00:53 PM PDT 24 Mar 10 01:01:09 PM PDT 24 785898675 ps
T1992 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4275181079 Mar 10 01:18:39 PM PDT 24 Mar 10 01:18:40 PM PDT 24 12077814 ps
T1993 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3311787327 Mar 10 01:18:15 PM PDT 24 Mar 10 01:18:19 PM PDT 24 57602162 ps
T178 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1022232253 Mar 10 01:18:20 PM PDT 24 Mar 10 01:18:35 PM PDT 24 1066054781 ps
T1994 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2888499222 Mar 10 01:01:38 PM PDT 24 Mar 10 01:01:39 PM PDT 24 58455553 ps
T1995 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3463467202 Mar 10 01:00:38 PM PDT 24 Mar 10 01:00:41 PM PDT 24 298649909 ps
T1996 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.348007809 Mar 10 01:18:02 PM PDT 24 Mar 10 01:18:24 PM PDT 24 731657515 ps
T1997 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3251482856 Mar 10 01:18:35 PM PDT 24 Mar 10 01:18:36 PM PDT 24 17054046 ps
T1998 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.163300797 Mar 10 01:01:09 PM PDT 24 Mar 10 01:01:11 PM PDT 24 40377976 ps
T1999 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4238900840 Mar 10 01:18:19 PM PDT 24 Mar 10 01:18:23 PM PDT 24 53331147 ps
T2000 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1734162196 Mar 10 01:18:28 PM PDT 24 Mar 10 01:18:30 PM PDT 24 12805365 ps
T2001 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1326825733 Mar 10 01:18:28 PM PDT 24 Mar 10 01:18:30 PM PDT 24 12354379 ps
T2002 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2066419760 Mar 10 01:01:43 PM PDT 24 Mar 10 01:01:45 PM PDT 24 25109918 ps
T2003 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4251371691 Mar 10 01:18:01 PM PDT 24 Mar 10 01:18:06 PM PDT 24 340263912 ps
T2004 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1218876371 Mar 10 01:18:28 PM PDT 24 Mar 10 01:18:30 PM PDT 24 22302703 ps
T2005 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3577511198 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:15 PM PDT 24 54247534 ps
T2006 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2298848030 Mar 10 01:18:22 PM PDT 24 Mar 10 01:18:26 PM PDT 24 54609485 ps
T2007 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1628761914 Mar 10 01:17:49 PM PDT 24 Mar 10 01:17:50 PM PDT 24 23812135 ps
T2008 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3297657832 Mar 10 01:18:28 PM PDT 24 Mar 10 01:18:29 PM PDT 24 19466185 ps
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