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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.38 94.45 98.61 89.36 97.08 95.82 98.22


Total test records in report: 2231
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T2009 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2025851818 Mar 10 01:01:24 PM PDT 24 Mar 10 01:01:25 PM PDT 24 15350656 ps
T2010 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.876113048 Mar 10 01:01:40 PM PDT 24 Mar 10 01:01:40 PM PDT 24 15596844 ps
T2011 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3566304346 Mar 10 01:01:17 PM PDT 24 Mar 10 01:01:25 PM PDT 24 112594899 ps
T2012 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1021990534 Mar 10 01:01:25 PM PDT 24 Mar 10 01:01:26 PM PDT 24 11809959 ps
T2013 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3849288104 Mar 10 01:18:06 PM PDT 24 Mar 10 01:18:09 PM PDT 24 207609717 ps
T2014 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.881869827 Mar 10 01:17:54 PM PDT 24 Mar 10 01:17:56 PM PDT 24 57192177 ps
T2015 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1624400254 Mar 10 01:18:15 PM PDT 24 Mar 10 01:18:18 PM PDT 24 93415481 ps
T2016 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3413816944 Mar 10 01:00:59 PM PDT 24 Mar 10 01:01:00 PM PDT 24 36296880 ps
T2017 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2761807623 Mar 10 01:17:57 PM PDT 24 Mar 10 01:17:59 PM PDT 24 67892659 ps
T2018 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3046072321 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:33 PM PDT 24 384325529 ps
T2019 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1963996485 Mar 10 01:17:52 PM PDT 24 Mar 10 01:17:54 PM PDT 24 245185578 ps
T2020 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.659052734 Mar 10 01:18:10 PM PDT 24 Mar 10 01:18:12 PM PDT 24 29700288 ps
T2021 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3729881246 Mar 10 01:18:10 PM PDT 24 Mar 10 01:18:10 PM PDT 24 16602656 ps
T172 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1627666831 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:19 PM PDT 24 3164359373 ps
T2022 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.637946989 Mar 10 01:01:35 PM PDT 24 Mar 10 01:01:36 PM PDT 24 51766849 ps
T2023 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3154126152 Mar 10 01:01:12 PM PDT 24 Mar 10 01:01:16 PM PDT 24 900438753 ps
T2024 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1554456051 Mar 10 01:00:48 PM PDT 24 Mar 10 01:00:49 PM PDT 24 18703720 ps
T2025 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1892407229 Mar 10 01:01:09 PM PDT 24 Mar 10 01:01:14 PM PDT 24 511209992 ps
T84 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1537036844 Mar 10 01:17:53 PM PDT 24 Mar 10 01:17:54 PM PDT 24 233482997 ps
T2026 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3995210258 Mar 10 01:01:18 PM PDT 24 Mar 10 01:01:21 PM PDT 24 463984577 ps
T2027 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.847319149 Mar 10 01:01:03 PM PDT 24 Mar 10 01:01:06 PM PDT 24 213684195 ps
T179 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2603118274 Mar 10 01:00:36 PM PDT 24 Mar 10 01:00:53 PM PDT 24 582202209 ps
T2028 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.216656022 Mar 10 01:01:19 PM PDT 24 Mar 10 01:01:22 PM PDT 24 42579328 ps
T2029 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1279341479 Mar 10 01:01:19 PM PDT 24 Mar 10 01:01:27 PM PDT 24 1203974501 ps
T2030 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1489429602 Mar 10 01:18:20 PM PDT 24 Mar 10 01:18:22 PM PDT 24 277975105 ps
T176 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1601584164 Mar 10 01:18:22 PM PDT 24 Mar 10 01:18:30 PM PDT 24 1083796950 ps
T2031 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.128607854 Mar 10 01:18:19 PM PDT 24 Mar 10 01:18:21 PM PDT 24 314131164 ps
T2032 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2956197008 Mar 10 01:18:00 PM PDT 24 Mar 10 01:18:03 PM PDT 24 166963787 ps
T173 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2898924538 Mar 10 01:01:19 PM PDT 24 Mar 10 01:01:24 PM PDT 24 482903198 ps
T2033 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.719965033 Mar 10 01:18:23 PM PDT 24 Mar 10 01:18:25 PM PDT 24 313113355 ps
T2034 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3010507925 Mar 10 01:01:06 PM PDT 24 Mar 10 01:01:07 PM PDT 24 23728836 ps
T2035 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1867699473 Mar 10 01:18:20 PM PDT 24 Mar 10 01:18:28 PM PDT 24 640541518 ps
T2036 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1720935648 Mar 10 01:00:38 PM PDT 24 Mar 10 01:00:39 PM PDT 24 35950536 ps
T2037 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1251539544 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:16 PM PDT 24 72202766 ps
T2038 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4123286846 Mar 10 01:00:38 PM PDT 24 Mar 10 01:00:39 PM PDT 24 15734398 ps
T2039 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2510938912 Mar 10 01:01:12 PM PDT 24 Mar 10 01:01:14 PM PDT 24 53563191 ps
T2040 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2813879360 Mar 10 01:18:20 PM PDT 24 Mar 10 01:18:21 PM PDT 24 27383008 ps
T2041 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3674714770 Mar 10 01:01:18 PM PDT 24 Mar 10 01:01:20 PM PDT 24 152338598 ps
T2042 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2482302299 Mar 10 01:17:59 PM PDT 24 Mar 10 01:18:01 PM PDT 24 38312382 ps
T2043 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2849735824 Mar 10 01:01:25 PM PDT 24 Mar 10 01:01:45 PM PDT 24 4266439507 ps
T2044 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3111128645 Mar 10 01:01:13 PM PDT 24 Mar 10 01:01:16 PM PDT 24 189212112 ps
T2045 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2283746593 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:18 PM PDT 24 170086365 ps
T2046 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3560001075 Mar 10 01:01:25 PM PDT 24 Mar 10 01:01:26 PM PDT 24 42276292 ps
T2047 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1432785363 Mar 10 01:01:47 PM PDT 24 Mar 10 01:01:48 PM PDT 24 66361121 ps
T2048 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1678569816 Mar 10 01:17:54 PM PDT 24 Mar 10 01:17:55 PM PDT 24 18012261 ps
T2049 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2062147001 Mar 10 01:01:25 PM PDT 24 Mar 10 01:01:28 PM PDT 24 183993042 ps
T2050 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2450570564 Mar 10 01:17:58 PM PDT 24 Mar 10 01:17:59 PM PDT 24 89406635 ps
T2051 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1927533488 Mar 10 01:17:57 PM PDT 24 Mar 10 01:18:04 PM PDT 24 555562289 ps
T2052 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1104413174 Mar 10 01:01:29 PM PDT 24 Mar 10 01:01:30 PM PDT 24 17577461 ps
T2053 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1588560148 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:22 PM PDT 24 300885569 ps
T2054 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3072780263 Mar 10 01:01:43 PM PDT 24 Mar 10 01:01:44 PM PDT 24 41703981 ps
T2055 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1133295803 Mar 10 01:17:59 PM PDT 24 Mar 10 01:18:23 PM PDT 24 4412362216 ps
T2056 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2585003732 Mar 10 01:00:56 PM PDT 24 Mar 10 01:00:57 PM PDT 24 33814175 ps
T2057 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3954744325 Mar 10 01:17:51 PM PDT 24 Mar 10 01:17:53 PM PDT 24 49471253 ps
T2058 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.296615140 Mar 10 01:00:27 PM PDT 24 Mar 10 01:00:28 PM PDT 24 33476359 ps
T2059 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.450129931 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:15 PM PDT 24 32230415 ps
T2060 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.378272210 Mar 10 01:00:33 PM PDT 24 Mar 10 01:00:58 PM PDT 24 3429266030 ps
T2061 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2645638829 Mar 10 01:01:44 PM PDT 24 Mar 10 01:01:45 PM PDT 24 46756670 ps
T2062 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1144817764 Mar 10 01:18:04 PM PDT 24 Mar 10 01:18:05 PM PDT 24 15335245 ps
T2063 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1735383447 Mar 10 01:18:05 PM PDT 24 Mar 10 01:18:07 PM PDT 24 74526151 ps
T2064 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3022960091 Mar 10 01:18:28 PM PDT 24 Mar 10 01:18:32 PM PDT 24 143883588 ps
T2065 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.265773791 Mar 10 01:01:25 PM PDT 24 Mar 10 01:01:30 PM PDT 24 137873881 ps
T2066 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3780949855 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:34 PM PDT 24 891350054 ps
T2067 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3712414324 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:34 PM PDT 24 111150433 ps
T2068 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2215608210 Mar 10 01:00:28 PM PDT 24 Mar 10 01:00:31 PM PDT 24 167809840 ps
T180 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.934552020 Mar 10 01:01:26 PM PDT 24 Mar 10 01:01:33 PM PDT 24 205143816 ps
T2069 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2694783390 Mar 10 01:18:19 PM PDT 24 Mar 10 01:18:41 PM PDT 24 3293158365 ps
T2070 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3983371016 Mar 10 01:00:32 PM PDT 24 Mar 10 01:01:08 PM PDT 24 2492986815 ps
T2071 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1908387499 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:17 PM PDT 24 48561009 ps
T2072 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3250181961 Mar 10 01:01:18 PM PDT 24 Mar 10 01:01:19 PM PDT 24 16292008 ps
T2073 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4074311416 Mar 10 01:18:00 PM PDT 24 Mar 10 01:18:02 PM PDT 24 22910118 ps
T2074 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1792016104 Mar 10 01:18:22 PM PDT 24 Mar 10 01:18:45 PM PDT 24 9643886452 ps
T2075 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2064572998 Mar 10 01:00:31 PM PDT 24 Mar 10 01:00:33 PM PDT 24 38161783 ps
T2076 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3690825282 Mar 10 01:18:19 PM PDT 24 Mar 10 01:18:24 PM PDT 24 158657620 ps
T2077 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3664076912 Mar 10 01:17:41 PM PDT 24 Mar 10 01:17:45 PM PDT 24 216577089 ps
T2078 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1489520408 Mar 10 01:18:04 PM PDT 24 Mar 10 01:18:20 PM PDT 24 1422013484 ps
T2079 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1134811815 Mar 10 01:00:29 PM PDT 24 Mar 10 01:00:38 PM PDT 24 1556707404 ps
T2080 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1358788907 Mar 10 01:01:44 PM PDT 24 Mar 10 01:01:45 PM PDT 24 48903361 ps
T2081 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4010055312 Mar 10 01:00:27 PM PDT 24 Mar 10 01:00:28 PM PDT 24 13458653 ps
T2082 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.51715768 Mar 10 01:00:28 PM PDT 24 Mar 10 01:01:07 PM PDT 24 2345875159 ps
T2083 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2837350772 Mar 10 01:18:13 PM PDT 24 Mar 10 01:18:17 PM PDT 24 158919816 ps
T2084 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1899199198 Mar 10 01:01:18 PM PDT 24 Mar 10 01:01:22 PM PDT 24 196272416 ps
T2085 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.497841362 Mar 10 01:18:32 PM PDT 24 Mar 10 01:18:33 PM PDT 24 13920257 ps
T2086 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2225628942 Mar 10 01:01:46 PM PDT 24 Mar 10 01:01:47 PM PDT 24 15813516 ps
T2087 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.40277483 Mar 10 01:18:34 PM PDT 24 Mar 10 01:18:35 PM PDT 24 36167610 ps
T2088 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1884107701 Mar 10 01:00:27 PM PDT 24 Mar 10 01:00:40 PM PDT 24 204626887 ps
T2089 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3490389035 Mar 10 01:01:38 PM PDT 24 Mar 10 01:01:39 PM PDT 24 14194787 ps
T2090 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2042999769 Mar 10 01:00:37 PM PDT 24 Mar 10 01:00:38 PM PDT 24 36561554 ps
T2091 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4064221860 Mar 10 01:01:00 PM PDT 24 Mar 10 01:01:02 PM PDT 24 227178347 ps
T2092 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2512187538 Mar 10 01:01:32 PM PDT 24 Mar 10 01:01:35 PM PDT 24 488252876 ps
T2093 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.907725433 Mar 10 01:01:18 PM PDT 24 Mar 10 01:01:19 PM PDT 24 22053392 ps
T2094 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.796026604 Mar 10 01:18:30 PM PDT 24 Mar 10 01:18:34 PM PDT 24 123465451 ps
T2095 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3135020043 Mar 10 01:00:37 PM PDT 24 Mar 10 01:00:58 PM PDT 24 629014379 ps
T2096 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2650537172 Mar 10 01:01:34 PM PDT 24 Mar 10 01:01:35 PM PDT 24 44521910 ps
T2097 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.94721657 Mar 10 01:18:38 PM PDT 24 Mar 10 01:18:39 PM PDT 24 43261857 ps
T2098 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3186718374 Mar 10 01:18:09 PM PDT 24 Mar 10 01:18:25 PM PDT 24 1095925291 ps
T2099 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.519883271 Mar 10 01:17:56 PM PDT 24 Mar 10 01:17:57 PM PDT 24 31529824 ps
T2100 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1840120540 Mar 10 01:18:30 PM PDT 24 Mar 10 01:18:31 PM PDT 24 58965591 ps
T2101 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1167379945 Mar 10 01:18:04 PM PDT 24 Mar 10 01:18:06 PM PDT 24 37730674 ps
T2102 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.997561302 Mar 10 01:17:51 PM PDT 24 Mar 10 01:18:06 PM PDT 24 625675875 ps
T2103 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2119651141 Mar 10 01:17:51 PM PDT 24 Mar 10 01:18:13 PM PDT 24 1529930129 ps
T2104 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1547777743 Mar 10 01:01:09 PM PDT 24 Mar 10 01:01:24 PM PDT 24 214840875 ps
T2105 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1068161837 Mar 10 01:01:47 PM PDT 24 Mar 10 01:01:48 PM PDT 24 87937402 ps
T2106 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3659195092 Mar 10 01:01:13 PM PDT 24 Mar 10 01:01:15 PM PDT 24 35539704 ps
T2107 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3522139135 Mar 10 01:01:12 PM PDT 24 Mar 10 01:01:14 PM PDT 24 73349441 ps
T2108 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.378518821 Mar 10 01:17:59 PM PDT 24 Mar 10 01:18:02 PM PDT 24 99523480 ps
T2109 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3002101672 Mar 10 01:01:17 PM PDT 24 Mar 10 01:01:22 PM PDT 24 109781052 ps
T2110 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.521102959 Mar 10 01:00:27 PM PDT 24 Mar 10 01:00:29 PM PDT 24 267219819 ps
T2111 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1411090348 Mar 10 01:00:33 PM PDT 24 Mar 10 01:00:35 PM PDT 24 47095612 ps
T2112 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2456909910 Mar 10 01:18:00 PM PDT 24 Mar 10 01:18:03 PM PDT 24 248937954 ps
T2113 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.21418295 Mar 10 01:01:02 PM PDT 24 Mar 10 01:01:04 PM PDT 24 44526115 ps
T2114 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1031539276 Mar 10 01:01:38 PM PDT 24 Mar 10 01:01:39 PM PDT 24 12365188 ps
T2115 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.418745792 Mar 10 01:18:18 PM PDT 24 Mar 10 01:18:22 PM PDT 24 549660019 ps
T2116 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3760214009 Mar 10 01:01:31 PM PDT 24 Mar 10 01:01:33 PM PDT 24 64083276 ps
T2117 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2565675039 Mar 10 01:01:18 PM PDT 24 Mar 10 01:01:19 PM PDT 24 17261442 ps
T2118 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2962562552 Mar 10 01:18:27 PM PDT 24 Mar 10 01:18:41 PM PDT 24 809360463 ps
T2119 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1471530520 Mar 10 01:00:44 PM PDT 24 Mar 10 01:00:50 PM PDT 24 405588418 ps
T2120 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2002866290 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:36 PM PDT 24 436685907 ps
T2121 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.354566713 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:18 PM PDT 24 85730261 ps
T2122 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2365784391 Mar 10 01:17:49 PM PDT 24 Mar 10 01:17:51 PM PDT 24 30212000 ps
T2123 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.7057294 Mar 10 01:01:31 PM PDT 24 Mar 10 01:01:32 PM PDT 24 46751249 ps
T2124 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2022574128 Mar 10 01:01:42 PM PDT 24 Mar 10 01:01:43 PM PDT 24 43160588 ps
T2125 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1385869509 Mar 10 01:17:57 PM PDT 24 Mar 10 01:17:59 PM PDT 24 239816997 ps
T2126 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1436906621 Mar 10 01:18:05 PM PDT 24 Mar 10 01:18:06 PM PDT 24 43247272 ps
T2127 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.217765967 Mar 10 01:00:33 PM PDT 24 Mar 10 01:00:42 PM PDT 24 1261644031 ps
T2128 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1673267001 Mar 10 01:17:50 PM PDT 24 Mar 10 01:18:26 PM PDT 24 2423636551 ps
T2129 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1886454337 Mar 10 01:18:13 PM PDT 24 Mar 10 01:18:21 PM PDT 24 290096807 ps
T2130 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3937246284 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:31 PM PDT 24 58974425 ps
T2131 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2396753155 Mar 10 01:01:11 PM PDT 24 Mar 10 01:01:16 PM PDT 24 235220640 ps
T2132 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1470584795 Mar 10 01:00:42 PM PDT 24 Mar 10 01:00:44 PM PDT 24 139489882 ps
T2133 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2052207464 Mar 10 01:18:33 PM PDT 24 Mar 10 01:18:34 PM PDT 24 38630474 ps
T2134 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2085537149 Mar 10 01:01:07 PM PDT 24 Mar 10 01:01:15 PM PDT 24 1213085888 ps
T2135 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.602193954 Mar 10 01:18:35 PM PDT 24 Mar 10 01:18:35 PM PDT 24 13523828 ps
T2136 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1963760275 Mar 10 01:01:12 PM PDT 24 Mar 10 01:01:27 PM PDT 24 2674499708 ps
T2137 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2823323188 Mar 10 01:00:26 PM PDT 24 Mar 10 01:00:28 PM PDT 24 138048917 ps
T2138 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1676422820 Mar 10 01:18:28 PM PDT 24 Mar 10 01:18:30 PM PDT 24 59105086 ps
T2139 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3747925084 Mar 10 01:18:35 PM PDT 24 Mar 10 01:18:36 PM PDT 24 15407470 ps
T2140 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.708979039 Mar 10 01:00:50 PM PDT 24 Mar 10 01:00:51 PM PDT 24 50940786 ps
T2141 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1071667137 Mar 10 01:18:25 PM PDT 24 Mar 10 01:18:26 PM PDT 24 17479237 ps
T2142 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3763497400 Mar 10 01:18:06 PM PDT 24 Mar 10 01:18:07 PM PDT 24 11797372 ps
T2143 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1362434996 Mar 10 01:01:14 PM PDT 24 Mar 10 01:01:18 PM PDT 24 428009967 ps
T2144 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.809118268 Mar 10 01:01:18 PM PDT 24 Mar 10 01:01:20 PM PDT 24 61248644 ps
T2145 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2559036641 Mar 10 01:00:54 PM PDT 24 Mar 10 01:00:56 PM PDT 24 204179873 ps
T2146 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1781415440 Mar 10 01:17:49 PM PDT 24 Mar 10 01:17:52 PM PDT 24 275121943 ps
T2147 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2576565841 Mar 10 01:00:38 PM PDT 24 Mar 10 01:00:46 PM PDT 24 1301099736 ps
T2148 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2095041965 Mar 10 01:00:43 PM PDT 24 Mar 10 01:00:46 PM PDT 24 131669249 ps
T2149 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3320182771 Mar 10 01:18:24 PM PDT 24 Mar 10 01:18:26 PM PDT 24 219423344 ps
T2150 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2489590456 Mar 10 01:00:37 PM PDT 24 Mar 10 01:00:39 PM PDT 24 116888556 ps
T2151 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2743367166 Mar 10 01:18:26 PM PDT 24 Mar 10 01:18:30 PM PDT 24 262852211 ps
T2152 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3724903193 Mar 10 01:18:21 PM PDT 24 Mar 10 01:18:23 PM PDT 24 140874598 ps
T2153 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1765138118 Mar 10 01:18:28 PM PDT 24 Mar 10 01:18:29 PM PDT 24 49952958 ps
T2154 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.402680768 Mar 10 01:01:00 PM PDT 24 Mar 10 01:01:04 PM PDT 24 237731275 ps
T2155 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3831915054 Mar 10 01:01:45 PM PDT 24 Mar 10 01:01:47 PM PDT 24 83682877 ps
T2156 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3552661067 Mar 10 01:18:09 PM PDT 24 Mar 10 01:18:13 PM PDT 24 224282505 ps
T107 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3474264690 Mar 10 01:01:06 PM PDT 24 Mar 10 01:01:20 PM PDT 24 844464262 ps
T2157 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3529121726 Mar 10 01:17:49 PM PDT 24 Mar 10 01:17:54 PM PDT 24 240474823 ps
T2158 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.469120358 Mar 10 01:17:56 PM PDT 24 Mar 10 01:17:59 PM PDT 24 253899691 ps
T2159 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.753717112 Mar 10 01:18:07 PM PDT 24 Mar 10 01:18:09 PM PDT 24 157537271 ps
T2160 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1374975773 Mar 10 01:18:30 PM PDT 24 Mar 10 01:18:34 PM PDT 24 511842440 ps
T2161 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.467268814 Mar 10 01:17:49 PM PDT 24 Mar 10 01:17:52 PM PDT 24 414734094 ps
T2162 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.510094740 Mar 10 01:17:54 PM PDT 24 Mar 10 01:18:07 PM PDT 24 790135307 ps
T2163 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1895138640 Mar 10 01:01:26 PM PDT 24 Mar 10 01:01:27 PM PDT 24 40924626 ps
T2164 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1310353039 Mar 10 01:18:34 PM PDT 24 Mar 10 01:18:35 PM PDT 24 10726896 ps
T2165 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2068568021 Mar 10 01:18:33 PM PDT 24 Mar 10 01:18:34 PM PDT 24 18451270 ps
T2166 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3077654590 Mar 10 01:00:41 PM PDT 24 Mar 10 01:00:43 PM PDT 24 74313315 ps
T2167 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2132589805 Mar 10 01:01:26 PM PDT 24 Mar 10 01:01:29 PM PDT 24 28910176 ps
T2168 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.732357330 Mar 10 01:17:51 PM PDT 24 Mar 10 01:17:52 PM PDT 24 31834766 ps
T2169 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3322778713 Mar 10 01:18:25 PM PDT 24 Mar 10 01:18:27 PM PDT 24 29334440 ps
T2170 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2561446953 Mar 10 01:01:06 PM PDT 24 Mar 10 01:01:10 PM PDT 24 229502528 ps
T2171 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1801527812 Mar 10 01:01:26 PM PDT 24 Mar 10 01:01:28 PM PDT 24 154548641 ps
T2172 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4118928311 Mar 10 01:00:26 PM PDT 24 Mar 10 01:00:28 PM PDT 24 87834409 ps
T2173 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3706704134 Mar 10 01:18:09 PM PDT 24 Mar 10 01:18:11 PM PDT 24 41556920 ps
T2174 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1963511502 Mar 10 01:01:05 PM PDT 24 Mar 10 01:01:10 PM PDT 24 342485194 ps
T2175 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2133683450 Mar 10 01:18:19 PM PDT 24 Mar 10 01:18:23 PM PDT 24 166448968 ps
T2176 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1473546002 Mar 10 01:17:50 PM PDT 24 Mar 10 01:17:52 PM PDT 24 60537373 ps
T2177 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.627776867 Mar 10 01:17:50 PM PDT 24 Mar 10 01:17:59 PM PDT 24 580265014 ps
T2178 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3426960607 Mar 10 01:18:20 PM PDT 24 Mar 10 01:18:22 PM PDT 24 81569781 ps
T2179 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3008480116 Mar 10 01:17:58 PM PDT 24 Mar 10 01:17:59 PM PDT 24 71634634 ps
T2180 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2743999179 Mar 10 01:01:12 PM PDT 24 Mar 10 01:01:15 PM PDT 24 236240100 ps
T2181 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2426801089 Mar 10 01:18:08 PM PDT 24 Mar 10 01:18:09 PM PDT 24 14582640 ps
T2182 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2148055358 Mar 10 01:01:30 PM PDT 24 Mar 10 01:01:31 PM PDT 24 34874355 ps
T2183 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.274852622 Mar 10 01:18:10 PM PDT 24 Mar 10 01:18:11 PM PDT 24 114927832 ps
T2184 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2254473397 Mar 10 01:18:06 PM PDT 24 Mar 10 01:18:07 PM PDT 24 24039421 ps
T2185 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.824489255 Mar 10 01:00:34 PM PDT 24 Mar 10 01:00:45 PM PDT 24 774959483 ps
T2186 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1293067985 Mar 10 01:00:27 PM PDT 24 Mar 10 01:00:35 PM PDT 24 2087210954 ps
T2187 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2890931238 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:31 PM PDT 24 16317726 ps
T2188 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.142215338 Mar 10 01:18:32 PM PDT 24 Mar 10 01:18:33 PM PDT 24 26086741 ps
T2189 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2647654022 Mar 10 01:00:48 PM PDT 24 Mar 10 01:00:51 PM PDT 24 27137906 ps
T2190 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1715763204 Mar 10 01:01:20 PM PDT 24 Mar 10 01:01:22 PM PDT 24 32815446 ps
T2191 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.640484822 Mar 10 01:01:41 PM PDT 24 Mar 10 01:01:42 PM PDT 24 32898257 ps
T2192 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1541985971 Mar 10 01:18:05 PM PDT 24 Mar 10 01:18:07 PM PDT 24 75775728 ps
T2193 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3346986883 Mar 10 01:01:13 PM PDT 24 Mar 10 01:01:17 PM PDT 24 55524586 ps
T2194 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.862953287 Mar 10 01:01:06 PM PDT 24 Mar 10 01:01:07 PM PDT 24 26923827 ps
T2195 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1476974583 Mar 10 01:18:04 PM PDT 24 Mar 10 01:18:06 PM PDT 24 239657108 ps
T2196 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1275006962 Mar 10 01:17:52 PM PDT 24 Mar 10 01:18:06 PM PDT 24 2430080157 ps
T2197 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3059714112 Mar 10 01:17:51 PM PDT 24 Mar 10 01:17:53 PM PDT 24 26817488 ps
T2198 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3098552482 Mar 10 01:18:35 PM PDT 24 Mar 10 01:18:35 PM PDT 24 29043669 ps
T2199 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2303149443 Mar 10 01:01:09 PM PDT 24 Mar 10 01:01:14 PM PDT 24 482828753 ps
T2200 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1555251816 Mar 10 01:00:28 PM PDT 24 Mar 10 01:00:29 PM PDT 24 31882484 ps
T2201 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2238921047 Mar 10 01:01:44 PM PDT 24 Mar 10 01:01:45 PM PDT 24 49375726 ps
T106 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3832893485 Mar 10 01:01:35 PM PDT 24 Mar 10 01:01:48 PM PDT 24 242171493 ps
T2202 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.42194423 Mar 10 01:01:31 PM PDT 24 Mar 10 01:01:32 PM PDT 24 35062487 ps
T2203 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.991564927 Mar 10 01:18:33 PM PDT 24 Mar 10 01:18:34 PM PDT 24 15335348 ps
T2204 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2585758825 Mar 10 01:17:59 PM PDT 24 Mar 10 01:18:01 PM PDT 24 23544782 ps
T2205 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1853163353 Mar 10 01:18:19 PM PDT 24 Mar 10 01:18:22 PM PDT 24 67506656 ps
T2206 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3511082421 Mar 10 01:18:29 PM PDT 24 Mar 10 01:18:30 PM PDT 24 30127282 ps
T2207 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3596076480 Mar 10 01:18:34 PM PDT 24 Mar 10 01:18:35 PM PDT 24 50835534 ps
T2208 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1660751682 Mar 10 01:01:05 PM PDT 24 Mar 10 01:01:08 PM PDT 24 523214949 ps
T2209 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4165078579 Mar 10 01:00:31 PM PDT 24 Mar 10 01:00:33 PM PDT 24 82509401 ps
T2210 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2093031849 Mar 10 01:18:18 PM PDT 24 Mar 10 01:18:20 PM PDT 24 81466205 ps
T2211 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3748622041 Mar 10 01:01:26 PM PDT 24 Mar 10 01:01:28 PM PDT 24 59098583 ps
T2212 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2289511307 Mar 10 01:01:06 PM PDT 24 Mar 10 01:01:10 PM PDT 24 272101901 ps
T2213 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.884033420 Mar 10 01:17:57 PM PDT 24 Mar 10 01:18:01 PM PDT 24 58335727 ps
T2214 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1903794843 Mar 10 01:01:19 PM PDT 24 Mar 10 01:01:20 PM PDT 24 32525639 ps
T2215 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.112518267 Mar 10 01:00:32 PM PDT 24 Mar 10 01:00:34 PM PDT 24 62327804 ps
T2216 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1707894881 Mar 10 01:18:07 PM PDT 24 Mar 10 01:18:08 PM PDT 24 33171279 ps
T2217 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2533742255 Mar 10 01:18:14 PM PDT 24 Mar 10 01:18:34 PM PDT 24 294212942 ps
T2218 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3198106587 Mar 10 01:01:13 PM PDT 24 Mar 10 01:01:20 PM PDT 24 1314609347 ps
T2219 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2433582869 Mar 10 01:01:08 PM PDT 24 Mar 10 01:01:16 PM PDT 24 1014421241 ps
T2220 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.675271694 Mar 10 01:17:51 PM PDT 24 Mar 10 01:17:56 PM PDT 24 59339305 ps
T2221 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.532055515 Mar 10 01:01:47 PM PDT 24 Mar 10 01:01:48 PM PDT 24 43683969 ps
T2222 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4136210920 Mar 10 01:17:52 PM PDT 24 Mar 10 01:17:52 PM PDT 24 28314837 ps
T2223 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1952401955 Mar 10 01:01:17 PM PDT 24 Mar 10 01:01:32 PM PDT 24 1058651346 ps
T2224 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4055336186 Mar 10 01:01:32 PM PDT 24 Mar 10 01:01:33 PM PDT 24 11893185 ps
T2225 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.953125800 Mar 10 01:18:20 PM PDT 24 Mar 10 01:18:20 PM PDT 24 41011901 ps
T2226 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2912188648 Mar 10 01:00:32 PM PDT 24 Mar 10 01:00:35 PM PDT 24 78480173 ps
T2227 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.415835969 Mar 10 01:18:10 PM PDT 24 Mar 10 01:18:14 PM PDT 24 540243580 ps
T2228 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.266754268 Mar 10 01:01:19 PM PDT 24 Mar 10 01:01:22 PM PDT 24 271256481 ps
T2229 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2329052304 Mar 10 01:18:00 PM PDT 24 Mar 10 01:18:13 PM PDT 24 201769826 ps
T2230 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4113927687 Mar 10 01:01:32 PM PDT 24 Mar 10 01:01:36 PM PDT 24 164217207 ps
T2231 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1649407479 Mar 10 01:00:48 PM PDT 24 Mar 10 01:00:50 PM PDT 24 197634725 ps

Test location /workspace/coverage/default/35.spi_device_stress_all.3182013619
Short name T3
Test name
Test status
Simulation time 129838105196 ps
CPU time 483.28 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:56:29 PM PDT 24
Peak memory 281652 kb
Host smart-bf426c6b-4aaf-45e6-af8a-38dc463cbaea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182013619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3182013619
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1006234260
Short name T33
Test name
Test status
Simulation time 91300685713 ps
CPU time 627.83 seconds
Started Mar 10 01:50:42 PM PDT 24
Finished Mar 10 02:01:10 PM PDT 24
Peak memory 265036 kb
Host smart-596fbede-a83c-4eb3-bd29-cad55366871a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006234260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1006234260
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2830161983
Short name T111
Test name
Test status
Simulation time 581454790 ps
CPU time 3.62 seconds
Started Mar 10 01:18:05 PM PDT 24
Finished Mar 10 01:18:09 PM PDT 24
Peak memory 217048 kb
Host smart-d4b39d30-bd9b-4265-8dd2-f19f78bda7fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830161983 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2830161983
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.331541845
Short name T21
Test name
Test status
Simulation time 236368839506 ps
CPU time 476.75 seconds
Started Mar 10 01:50:10 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 269392 kb
Host smart-896a7326-3b9f-4657-8d14-a64d5923d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331541845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.331541845
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.378123425
Short name T5
Test name
Test status
Simulation time 17518486 ps
CPU time 0.72 seconds
Started Mar 10 01:48:56 PM PDT 24
Finished Mar 10 01:48:56 PM PDT 24
Peak memory 215664 kb
Host smart-b389b860-1372-43dd-b6b1-416607c5a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378123425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.378123425
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1459399027
Short name T166
Test name
Test status
Simulation time 6098453828 ps
CPU time 114.46 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:48:43 PM PDT 24
Peak memory 273056 kb
Host smart-d24a23ea-e85f-4cfc-bf81-1f2661020472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459399027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1459399027
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1793665159
Short name T46
Test name
Test status
Simulation time 96001891487 ps
CPU time 233.13 seconds
Started Mar 10 01:51:59 PM PDT 24
Finished Mar 10 01:55:52 PM PDT 24
Peak memory 271256 kb
Host smart-6dcf3f2e-b84d-4860-a373-28019aba38f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793665159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1793665159
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.517836180
Short name T18
Test name
Test status
Simulation time 14976527491 ps
CPU time 178.26 seconds
Started Mar 10 01:52:16 PM PDT 24
Finished Mar 10 01:55:15 PM PDT 24
Peak memory 265060 kb
Host smart-4c6fcce4-36fb-45ce-9e89-78eace5f1c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517836180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.517836180
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2309721748
Short name T31
Test name
Test status
Simulation time 8930626408 ps
CPU time 125.33 seconds
Started Mar 10 02:48:41 PM PDT 24
Finished Mar 10 02:50:46 PM PDT 24
Peak memory 262848 kb
Host smart-737be6b5-7558-4001-9f93-913ade60c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309721748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2309721748
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2580162426
Short name T9
Test name
Test status
Simulation time 3369185024 ps
CPU time 24.07 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:47:19 PM PDT 24
Peak memory 233944 kb
Host smart-43868e5a-5128-4969-9b9c-35f49569336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580162426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2580162426
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.381146889
Short name T56
Test name
Test status
Simulation time 21054137 ps
CPU time 0.71 seconds
Started Mar 10 01:50:56 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 203888 kb
Host smart-5c2b561f-31c7-4c3d-9800-fe2537e40dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381146889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.381146889
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4244026562
Short name T51
Test name
Test status
Simulation time 19675864639 ps
CPU time 142.27 seconds
Started Mar 10 01:50:45 PM PDT 24
Finished Mar 10 01:53:08 PM PDT 24
Peak memory 268248 kb
Host smart-0de4ab44-73f7-4c52-b13d-3633927e3711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244026562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4244026562
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.643529146
Short name T71
Test name
Test status
Simulation time 62909961 ps
CPU time 1.13 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:08 PM PDT 24
Peak memory 234888 kb
Host smart-66257adb-5777-43ff-9783-4b5717c805fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643529146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.643529146
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1667836731
Short name T96
Test name
Test status
Simulation time 221632786 ps
CPU time 4.35 seconds
Started Mar 10 01:17:55 PM PDT 24
Finished Mar 10 01:18:00 PM PDT 24
Peak memory 215000 kb
Host smart-482d6833-4389-41bb-b409-b537fd471046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667836731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
667836731
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2235160075
Short name T181
Test name
Test status
Simulation time 1064014116 ps
CPU time 15.37 seconds
Started Mar 10 01:00:54 PM PDT 24
Finished Mar 10 01:01:10 PM PDT 24
Peak memory 214712 kb
Host smart-2b8f8fd7-e8de-4e13-834c-e1bf6e1f576b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235160075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2235160075
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3802284948
Short name T169
Test name
Test status
Simulation time 304315507596 ps
CPU time 455.14 seconds
Started Mar 10 01:50:19 PM PDT 24
Finished Mar 10 01:57:54 PM PDT 24
Peak memory 268928 kb
Host smart-73e98191-d6bd-429a-a82e-952436197dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802284948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3802284948
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3502932347
Short name T76
Test name
Test status
Simulation time 122200113154 ps
CPU time 588.45 seconds
Started Mar 10 02:48:04 PM PDT 24
Finished Mar 10 02:57:52 PM PDT 24
Peak memory 266776 kb
Host smart-5e7cc167-3646-42b3-a64c-80b1777aac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502932347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3502932347
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1757570955
Short name T82
Test name
Test status
Simulation time 22466419 ps
CPU time 1.38 seconds
Started Mar 10 01:17:52 PM PDT 24
Finished Mar 10 01:17:53 PM PDT 24
Peak memory 206516 kb
Host smart-91758654-c932-4bb0-98dc-b65fdc92db19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757570955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1757570955
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2334791373
Short name T15
Test name
Test status
Simulation time 29658885 ps
CPU time 1.12 seconds
Started Mar 10 02:47:24 PM PDT 24
Finished Mar 10 02:47:26 PM PDT 24
Peak memory 217304 kb
Host smart-139f4cb0-f959-48ba-983a-5b85dd36e0a3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334791373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2334791373
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3653385676
Short name T217
Test name
Test status
Simulation time 160506785660 ps
CPU time 529.54 seconds
Started Mar 10 01:51:04 PM PDT 24
Finished Mar 10 01:59:54 PM PDT 24
Peak memory 270668 kb
Host smart-3c61154a-c34b-469d-be81-bbcd1b7e42fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653385676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3653385676
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3955143523
Short name T136
Test name
Test status
Simulation time 193014691408 ps
CPU time 369.65 seconds
Started Mar 10 01:52:39 PM PDT 24
Finished Mar 10 01:58:50 PM PDT 24
Peak memory 275172 kb
Host smart-d8688ede-c14a-4c94-b149-e453d9d5887d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955143523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3955143523
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1504018788
Short name T49
Test name
Test status
Simulation time 162811816495 ps
CPU time 1262.53 seconds
Started Mar 10 02:46:59 PM PDT 24
Finished Mar 10 03:08:02 PM PDT 24
Peak memory 314260 kb
Host smart-1dbe67f2-d876-4eaf-a605-efbdf5d803d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504018788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1504018788
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3549966461
Short name T1
Test name
Test status
Simulation time 3687412499 ps
CPU time 39.23 seconds
Started Mar 10 01:49:05 PM PDT 24
Finished Mar 10 01:49:45 PM PDT 24
Peak memory 215784 kb
Host smart-b1c4d7cd-dbf4-408e-9e36-b616051a0bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549966461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3549966461
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1002439339
Short name T253
Test name
Test status
Simulation time 118698671326 ps
CPU time 884.16 seconds
Started Mar 10 02:48:00 PM PDT 24
Finished Mar 10 03:02:45 PM PDT 24
Peak memory 272884 kb
Host smart-22f02a83-5010-4939-bd73-69adbcc143a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002439339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1002439339
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3754127781
Short name T52
Test name
Test status
Simulation time 124180816459 ps
CPU time 751.52 seconds
Started Mar 10 02:48:57 PM PDT 24
Finished Mar 10 03:01:28 PM PDT 24
Peak memory 294760 kb
Host smart-39ec09cc-14db-42a6-9ccb-bfbdca16c9f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754127781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3754127781
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2154428003
Short name T73
Test name
Test status
Simulation time 147647655588 ps
CPU time 345.58 seconds
Started Mar 10 01:48:56 PM PDT 24
Finished Mar 10 01:54:42 PM PDT 24
Peak memory 272128 kb
Host smart-7bb7fb14-6a51-4794-a06e-41bf350a25aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154428003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2154428003
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4211638996
Short name T27
Test name
Test status
Simulation time 4828354341 ps
CPU time 89.1 seconds
Started Mar 10 01:51:09 PM PDT 24
Finished Mar 10 01:52:39 PM PDT 24
Peak memory 264924 kb
Host smart-1d6b80c3-a167-4be5-b0d4-7ca9de77fb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211638996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4211638996
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1792016104
Short name T2074
Test name
Test status
Simulation time 9643886452 ps
CPU time 22.07 seconds
Started Mar 10 01:18:22 PM PDT 24
Finished Mar 10 01:18:45 PM PDT 24
Peak memory 214788 kb
Host smart-15e89d5f-11ad-4f55-bb53-9932df43e436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792016104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1792016104
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1099368890
Short name T264
Test name
Test status
Simulation time 200180008278 ps
CPU time 362.73 seconds
Started Mar 10 01:50:53 PM PDT 24
Finished Mar 10 01:56:56 PM PDT 24
Peak memory 253952 kb
Host smart-8cd7aba3-e9d8-4102-a0b4-e543bd559a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099368890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1099368890
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2682022786
Short name T257
Test name
Test status
Simulation time 6572147125 ps
CPU time 89.87 seconds
Started Mar 10 01:51:35 PM PDT 24
Finished Mar 10 01:53:05 PM PDT 24
Peak memory 256852 kb
Host smart-bffbe770-9b4b-45fd-982e-f9462063a8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682022786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2682022786
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2318551123
Short name T682
Test name
Test status
Simulation time 5682355632 ps
CPU time 37.16 seconds
Started Mar 10 02:49:03 PM PDT 24
Finished Mar 10 02:49:40 PM PDT 24
Peak memory 238060 kb
Host smart-f4a3c7a5-c4cc-4f4d-b423-6a0a08a6471a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318551123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2318551123
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.236870888
Short name T138
Test name
Test status
Simulation time 498204734 ps
CPU time 15.17 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:26 PM PDT 24
Peak memory 249672 kb
Host smart-6882b65c-952c-4d08-9366-818ec47016c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236870888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.236870888
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1898310979
Short name T1987
Test name
Test status
Simulation time 705695463 ps
CPU time 4.14 seconds
Started Mar 10 01:01:27 PM PDT 24
Finished Mar 10 01:01:31 PM PDT 24
Peak memory 214968 kb
Host smart-62d99ec7-21c0-49aa-9d85-a548d2d58b1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898310979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1898310979
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3999250470
Short name T773
Test name
Test status
Simulation time 28888654435 ps
CPU time 127.81 seconds
Started Mar 10 02:49:11 PM PDT 24
Finished Mar 10 02:51:19 PM PDT 24
Peak memory 263172 kb
Host smart-e847ba2c-3a74-48ea-8422-0e58ba2957e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999250470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3999250470
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4123325060
Short name T86
Test name
Test status
Simulation time 47486928590 ps
CPU time 63.08 seconds
Started Mar 10 02:46:08 PM PDT 24
Finished Mar 10 02:47:11 PM PDT 24
Peak memory 215788 kb
Host smart-f8ce3f90-fded-41cc-9240-eab07df26b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123325060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4123325060
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.223777531
Short name T11
Test name
Test status
Simulation time 5014784104 ps
CPU time 8.17 seconds
Started Mar 10 02:47:41 PM PDT 24
Finished Mar 10 02:47:50 PM PDT 24
Peak memory 233020 kb
Host smart-6b2df08f-d4ec-4e97-babd-62218a6ef286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223777531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.223777531
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.627776867
Short name T2177
Test name
Test status
Simulation time 580265014 ps
CPU time 8.55 seconds
Started Mar 10 01:17:50 PM PDT 24
Finished Mar 10 01:17:59 PM PDT 24
Peak memory 214688 kb
Host smart-fcb707aa-cedb-4667-a08f-b63749d730dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627776867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.627776867
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1627666831
Short name T172
Test name
Test status
Simulation time 3164359373 ps
CPU time 3.99 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:19 PM PDT 24
Peak memory 214892 kb
Host smart-01f7b8ca-bc4c-4fff-a4d1-b742ced197e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627666831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1627666831
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2977169599
Short name T30
Test name
Test status
Simulation time 43328165465 ps
CPU time 113.88 seconds
Started Mar 10 02:46:48 PM PDT 24
Finished Mar 10 02:48:42 PM PDT 24
Peak memory 262580 kb
Host smart-92bd6bbd-74ad-432a-aa91-63d144b13311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977169599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2977169599
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.152984951
Short name T91
Test name
Test status
Simulation time 39510424482 ps
CPU time 268.06 seconds
Started Mar 10 02:47:11 PM PDT 24
Finished Mar 10 02:51:39 PM PDT 24
Peak memory 249960 kb
Host smart-4aaf9373-5c3d-4b69-9129-460eb1565c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152984951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.152984951
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2227053300
Short name T81
Test name
Test status
Simulation time 22436284 ps
CPU time 0.94 seconds
Started Mar 10 01:00:27 PM PDT 24
Finished Mar 10 01:00:29 PM PDT 24
Peak memory 205916 kb
Host smart-e28a510b-d6e9-478b-bc62-be28b39a20a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227053300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2227053300
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3832893485
Short name T106
Test name
Test status
Simulation time 242171493 ps
CPU time 12.61 seconds
Started Mar 10 01:01:35 PM PDT 24
Finished Mar 10 01:01:48 PM PDT 24
Peak memory 214684 kb
Host smart-ec6fe327-63d9-448e-b03d-a2efae62f648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832893485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3832893485
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3474264690
Short name T107
Test name
Test status
Simulation time 844464262 ps
CPU time 13.3 seconds
Started Mar 10 01:01:06 PM PDT 24
Finished Mar 10 01:01:20 PM PDT 24
Peak memory 214676 kb
Host smart-6307d94d-b6d8-4efc-b9c1-4a2f28878779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474264690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3474264690
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1134811815
Short name T2079
Test name
Test status
Simulation time 1556707404 ps
CPU time 8.75 seconds
Started Mar 10 01:00:29 PM PDT 24
Finished Mar 10 01:00:38 PM PDT 24
Peak memory 206376 kb
Host smart-43f6292a-de22-4f72-9be4-fa9d8e755711
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134811815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1134811815
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.997561302
Short name T2102
Test name
Test status
Simulation time 625675875 ps
CPU time 15.53 seconds
Started Mar 10 01:17:51 PM PDT 24
Finished Mar 10 01:18:06 PM PDT 24
Peak memory 206520 kb
Host smart-9b396ef7-28d2-4dac-9a51-f5e9a1ed1612
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997561302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.997561302
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1275006962
Short name T2196
Test name
Test status
Simulation time 2430080157 ps
CPU time 13.09 seconds
Started Mar 10 01:17:52 PM PDT 24
Finished Mar 10 01:18:06 PM PDT 24
Peak memory 206244 kb
Host smart-862690ce-a795-49d2-908f-f9652c9958c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275006962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1275006962
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.51715768
Short name T2082
Test name
Test status
Simulation time 2345875159 ps
CPU time 38.91 seconds
Started Mar 10 01:00:28 PM PDT 24
Finished Mar 10 01:01:07 PM PDT 24
Peak memory 206464 kb
Host smart-803d7841-e492-43e8-b3c9-80e3e08f5954
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51715768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
bit_bash.51715768
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2365784391
Short name T2122
Test name
Test status
Simulation time 30212000 ps
CPU time 1.21 seconds
Started Mar 10 01:17:49 PM PDT 24
Finished Mar 10 01:17:51 PM PDT 24
Peak memory 206420 kb
Host smart-17d8c4c9-c496-4a3c-a8d9-3481e1a6f23f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365784391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2365784391
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1781415440
Short name T2146
Test name
Test status
Simulation time 275121943 ps
CPU time 3.47 seconds
Started Mar 10 01:17:49 PM PDT 24
Finished Mar 10 01:17:52 PM PDT 24
Peak memory 216292 kb
Host smart-f089ca3b-e4dc-44c4-9bb0-2e6faac125df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781415440 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1781415440
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1806605101
Short name T93
Test name
Test status
Simulation time 188323262 ps
CPU time 3.87 seconds
Started Mar 10 01:00:26 PM PDT 24
Finished Mar 10 01:00:30 PM PDT 24
Peak memory 216176 kb
Host smart-a65358a6-9439-4904-b9a7-7d5002dafb5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806605101 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1806605101
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1473546002
Short name T2176
Test name
Test status
Simulation time 60537373 ps
CPU time 2.25 seconds
Started Mar 10 01:17:50 PM PDT 24
Finished Mar 10 01:17:52 PM PDT 24
Peak memory 214704 kb
Host smart-c5e7bdd9-2f76-4fc7-9ce2-ab30536ba2fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473546002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
473546002
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3397058294
Short name T1947
Test name
Test status
Simulation time 27681218 ps
CPU time 1.84 seconds
Started Mar 10 01:00:27 PM PDT 24
Finished Mar 10 01:00:29 PM PDT 24
Peak memory 214700 kb
Host smart-e34615b2-a41a-4334-b922-8e9ff3016e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397058294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
397058294
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3573508858
Short name T1949
Test name
Test status
Simulation time 11435809 ps
CPU time 0.73 seconds
Started Mar 10 01:00:26 PM PDT 24
Finished Mar 10 01:00:27 PM PDT 24
Peak memory 202864 kb
Host smart-52a0db48-8408-4828-8eb5-5e97fac0925d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573508858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
573508858
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4136210920
Short name T2222
Test name
Test status
Simulation time 28314837 ps
CPU time 0.69 seconds
Started Mar 10 01:17:52 PM PDT 24
Finished Mar 10 01:17:52 PM PDT 24
Peak memory 202532 kb
Host smart-5fbfb652-0e95-497a-8ea9-e566e4f89d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136210920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
136210920
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3059714112
Short name T2197
Test name
Test status
Simulation time 26817488 ps
CPU time 2.34 seconds
Started Mar 10 01:17:51 PM PDT 24
Finished Mar 10 01:17:53 PM PDT 24
Peak memory 214660 kb
Host smart-118c1148-2d12-473a-985c-59a9cf2ec2dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059714112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3059714112
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3130733530
Short name T121
Test name
Test status
Simulation time 83253206 ps
CPU time 1.61 seconds
Started Mar 10 01:00:26 PM PDT 24
Finished Mar 10 01:00:28 PM PDT 24
Peak memory 214640 kb
Host smart-288627a1-aef7-4cb9-ac44-08b2505cdbb0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130733530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3130733530
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4010055312
Short name T2081
Test name
Test status
Simulation time 13458653 ps
CPU time 0.69 seconds
Started Mar 10 01:00:27 PM PDT 24
Finished Mar 10 01:00:28 PM PDT 24
Peak memory 202384 kb
Host smart-2517e57f-2650-4d00-b027-0691f4e9f719
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010055312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4010055312
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.732357330
Short name T2168
Test name
Test status
Simulation time 31834766 ps
CPU time 0.67 seconds
Started Mar 10 01:17:51 PM PDT 24
Finished Mar 10 01:17:52 PM PDT 24
Peak memory 202416 kb
Host smart-4a68944a-d1a2-42ee-8fd9-7462d93f07eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732357330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.732357330
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2823323188
Short name T2137
Test name
Test status
Simulation time 138048917 ps
CPU time 1.76 seconds
Started Mar 10 01:00:26 PM PDT 24
Finished Mar 10 01:00:28 PM PDT 24
Peak memory 214468 kb
Host smart-47a45104-ca9e-4ea6-b434-9990521631ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823323188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2823323188
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.467268814
Short name T2161
Test name
Test status
Simulation time 414734094 ps
CPU time 2.84 seconds
Started Mar 10 01:17:49 PM PDT 24
Finished Mar 10 01:17:52 PM PDT 24
Peak memory 206408 kb
Host smart-56e9e9c9-1354-429e-b64a-da96be80dbce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467268814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.467268814
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2215608210
Short name T2068
Test name
Test status
Simulation time 167809840 ps
CPU time 2.9 seconds
Started Mar 10 01:00:28 PM PDT 24
Finished Mar 10 01:00:31 PM PDT 24
Peak memory 214904 kb
Host smart-74051f3f-e897-4dd8-a3d5-6c04115d9dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215608210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
215608210
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3664076912
Short name T2077
Test name
Test status
Simulation time 216577089 ps
CPU time 4.18 seconds
Started Mar 10 01:17:41 PM PDT 24
Finished Mar 10 01:17:45 PM PDT 24
Peak memory 214780 kb
Host smart-5df3c413-99a5-43ac-886d-751418051ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664076912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
664076912
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1293067985
Short name T2186
Test name
Test status
Simulation time 2087210954 ps
CPU time 7.46 seconds
Started Mar 10 01:00:27 PM PDT 24
Finished Mar 10 01:00:35 PM PDT 24
Peak memory 214716 kb
Host smart-ae9fea7b-b5d2-4545-a45d-1f69aafbc4fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293067985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1293067985
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2119651141
Short name T2103
Test name
Test status
Simulation time 1529930129 ps
CPU time 21.69 seconds
Started Mar 10 01:17:51 PM PDT 24
Finished Mar 10 01:18:13 PM PDT 24
Peak memory 214580 kb
Host smart-84edaae1-098c-4674-b0c0-44b143cfabfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119651141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2119651141
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.217765967
Short name T2127
Test name
Test status
Simulation time 1261644031 ps
CPU time 8.58 seconds
Started Mar 10 01:00:33 PM PDT 24
Finished Mar 10 01:00:42 PM PDT 24
Peak memory 206404 kb
Host smart-494f3db7-d257-48ac-b9a7-6a5f7ca4471b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217765967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.217765967
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3983371016
Short name T2070
Test name
Test status
Simulation time 2492986815 ps
CPU time 34.35 seconds
Started Mar 10 01:00:32 PM PDT 24
Finished Mar 10 01:01:08 PM PDT 24
Peak memory 206500 kb
Host smart-16238709-d075-4023-b04d-a81e4fed99b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983371016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3983371016
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.75644753
Short name T115
Test name
Test status
Simulation time 2968168756 ps
CPU time 12.02 seconds
Started Mar 10 01:17:51 PM PDT 24
Finished Mar 10 01:18:03 PM PDT 24
Peak memory 206236 kb
Host smart-a1aed337-f710-4970-ac0c-f1c915196877
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75644753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
bit_bash.75644753
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.112518267
Short name T2215
Test name
Test status
Simulation time 62327804 ps
CPU time 0.97 seconds
Started Mar 10 01:00:32 PM PDT 24
Finished Mar 10 01:00:34 PM PDT 24
Peak memory 206260 kb
Host smart-a252ffdc-97c4-44a9-8309-b6905199ea3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112518267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.112518267
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2871055348
Short name T1971
Test name
Test status
Simulation time 1105838686 ps
CPU time 2.39 seconds
Started Mar 10 01:00:32 PM PDT 24
Finished Mar 10 01:00:36 PM PDT 24
Peak memory 215716 kb
Host smart-a9688351-2f35-4226-8ff4-9e2095c80f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871055348 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2871055348
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.675271694
Short name T2220
Test name
Test status
Simulation time 59339305 ps
CPU time 4.5 seconds
Started Mar 10 01:17:51 PM PDT 24
Finished Mar 10 01:17:56 PM PDT 24
Peak memory 216468 kb
Host smart-9b16cecb-9edb-4e1c-bcdb-7288c1853dfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675271694 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.675271694
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1783084372
Short name T1950
Test name
Test status
Simulation time 29131026 ps
CPU time 1.74 seconds
Started Mar 10 01:00:33 PM PDT 24
Finished Mar 10 01:00:35 PM PDT 24
Peak memory 206420 kb
Host smart-fcd05d8e-6415-444d-b215-b163ab70b743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783084372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
783084372
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3680758974
Short name T1965
Test name
Test status
Simulation time 64471300 ps
CPU time 1.37 seconds
Started Mar 10 01:17:50 PM PDT 24
Finished Mar 10 01:17:52 PM PDT 24
Peak memory 206416 kb
Host smart-cf808bd7-f028-4cc5-aab2-747e226ba891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680758974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
680758974
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1555251816
Short name T2200
Test name
Test status
Simulation time 31882484 ps
CPU time 0.71 seconds
Started Mar 10 01:00:28 PM PDT 24
Finished Mar 10 01:00:29 PM PDT 24
Peak memory 202488 kb
Host smart-47443af7-cfee-40b5-9534-c74992a22d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555251816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
555251816
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3197121691
Short name T1979
Test name
Test status
Simulation time 51643910 ps
CPU time 0.74 seconds
Started Mar 10 01:17:49 PM PDT 24
Finished Mar 10 01:17:50 PM PDT 24
Peak memory 202852 kb
Host smart-6ed8018a-c5dc-40b2-91c8-d52a4dd74edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197121691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
197121691
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4118928311
Short name T2172
Test name
Test status
Simulation time 87834409 ps
CPU time 1.7 seconds
Started Mar 10 01:00:26 PM PDT 24
Finished Mar 10 01:00:28 PM PDT 24
Peak memory 214556 kb
Host smart-658fe7f5-5d20-424a-a3f2-3e4dc4c9322c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118928311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4118928311
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.881869827
Short name T2014
Test name
Test status
Simulation time 57192177 ps
CPU time 1.41 seconds
Started Mar 10 01:17:54 PM PDT 24
Finished Mar 10 01:17:56 PM PDT 24
Peak memory 214680 kb
Host smart-fda70b37-8a42-4b8e-8dc1-a1c3d230c907
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881869827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.881869827
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2719492957
Short name T1952
Test name
Test status
Simulation time 20527908 ps
CPU time 0.66 seconds
Started Mar 10 01:17:49 PM PDT 24
Finished Mar 10 01:17:50 PM PDT 24
Peak memory 202436 kb
Host smart-0b19d9ab-74fe-487d-af53-1c4f34982add
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719492957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2719492957
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.296615140
Short name T2058
Test name
Test status
Simulation time 33476359 ps
CPU time 0.63 seconds
Started Mar 10 01:00:27 PM PDT 24
Finished Mar 10 01:00:28 PM PDT 24
Peak memory 202364 kb
Host smart-68da0535-d6bf-4923-be94-93265e9a9ef2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296615140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.296615140
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1411090348
Short name T2111
Test name
Test status
Simulation time 47095612 ps
CPU time 1.76 seconds
Started Mar 10 01:00:33 PM PDT 24
Finished Mar 10 01:00:35 PM PDT 24
Peak memory 214464 kb
Host smart-c7841ce1-6950-41e0-ae68-75242b5b7999
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411090348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1411090348
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.980494916
Short name T1988
Test name
Test status
Simulation time 614537032 ps
CPU time 4.58 seconds
Started Mar 10 01:17:52 PM PDT 24
Finished Mar 10 01:17:57 PM PDT 24
Peak memory 206572 kb
Host smart-ece4a7b2-a541-4d11-85ad-223740f6e9bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980494916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.980494916
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.521102959
Short name T2110
Test name
Test status
Simulation time 267219819 ps
CPU time 2.19 seconds
Started Mar 10 01:00:27 PM PDT 24
Finished Mar 10 01:00:29 PM PDT 24
Peak memory 214872 kb
Host smart-6808e6fe-11dc-4ec8-8a93-6970bf0cf792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521102959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.521102959
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.898371657
Short name T108
Test name
Test status
Simulation time 34077935 ps
CPU time 2.38 seconds
Started Mar 10 01:17:48 PM PDT 24
Finished Mar 10 01:17:51 PM PDT 24
Peak memory 214796 kb
Host smart-75c680a8-0909-4f2d-a206-205f093d5cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898371657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.898371657
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1117527792
Short name T174
Test name
Test status
Simulation time 284810094 ps
CPU time 19.37 seconds
Started Mar 10 01:17:49 PM PDT 24
Finished Mar 10 01:18:09 PM PDT 24
Peak memory 214764 kb
Host smart-2f79899a-ec99-4cf7-a8b9-bb14872c56d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117527792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1117527792
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1884107701
Short name T2088
Test name
Test status
Simulation time 204626887 ps
CPU time 13.24 seconds
Started Mar 10 01:00:27 PM PDT 24
Finished Mar 10 01:00:40 PM PDT 24
Peak memory 221384 kb
Host smart-f8ac1c97-9b6f-45a0-b5a5-b75bcfe1175e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884107701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1884107701
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2396753155
Short name T2131
Test name
Test status
Simulation time 235220640 ps
CPU time 3.96 seconds
Started Mar 10 01:01:11 PM PDT 24
Finished Mar 10 01:01:16 PM PDT 24
Peak memory 215964 kb
Host smart-a3de7310-777c-404e-bb8b-623f76642f1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396753155 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2396753155
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3552661067
Short name T2156
Test name
Test status
Simulation time 224282505 ps
CPU time 3.63 seconds
Started Mar 10 01:18:09 PM PDT 24
Finished Mar 10 01:18:13 PM PDT 24
Peak memory 215928 kb
Host smart-44f81a07-4b10-4a42-a9f8-b0e1f34fa5e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552661067 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3552661067
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1927047928
Short name T123
Test name
Test status
Simulation time 30401900 ps
CPU time 1.95 seconds
Started Mar 10 01:01:05 PM PDT 24
Finished Mar 10 01:01:08 PM PDT 24
Peak memory 214672 kb
Host smart-08570c17-6be8-4454-8472-76de98216a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927047928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1927047928
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.659052734
Short name T2020
Test name
Test status
Simulation time 29700288 ps
CPU time 1.89 seconds
Started Mar 10 01:18:10 PM PDT 24
Finished Mar 10 01:18:12 PM PDT 24
Peak memory 206444 kb
Host smart-195ee6d7-e116-4799-b14a-fea06418f971
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659052734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.659052734
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2426801089
Short name T2181
Test name
Test status
Simulation time 14582640 ps
CPU time 0.71 seconds
Started Mar 10 01:18:08 PM PDT 24
Finished Mar 10 01:18:09 PM PDT 24
Peak memory 202480 kb
Host smart-6ad583a7-015c-433d-bee0-691e2efdee7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426801089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2426801089
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3888266189
Short name T1935
Test name
Test status
Simulation time 12859772 ps
CPU time 0.71 seconds
Started Mar 10 01:01:06 PM PDT 24
Finished Mar 10 01:01:07 PM PDT 24
Peak memory 202476 kb
Host smart-9b19d4ff-ffe1-4f77-997c-fafde64ecc4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888266189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3888266189
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3154126152
Short name T2023
Test name
Test status
Simulation time 900438753 ps
CPU time 3.09 seconds
Started Mar 10 01:01:12 PM PDT 24
Finished Mar 10 01:01:16 PM PDT 24
Peak memory 214668 kb
Host smart-5f0b7fef-68bb-448a-a6b0-9a1bd6d824e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154126152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3154126152
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.415835969
Short name T2227
Test name
Test status
Simulation time 540243580 ps
CPU time 4.27 seconds
Started Mar 10 01:18:10 PM PDT 24
Finished Mar 10 01:18:14 PM PDT 24
Peak memory 214708 kb
Host smart-cb63dd11-e686-4758-81cd-e70a76447dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415835969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.415835969
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3981109342
Short name T102
Test name
Test status
Simulation time 58169355 ps
CPU time 4.15 seconds
Started Mar 10 01:18:07 PM PDT 24
Finished Mar 10 01:18:11 PM PDT 24
Peak memory 215812 kb
Host smart-c53b4da9-8a0f-4151-a75e-b382664edb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981109342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3981109342
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.971722977
Short name T1962
Test name
Test status
Simulation time 85776648 ps
CPU time 3.62 seconds
Started Mar 10 01:01:09 PM PDT 24
Finished Mar 10 01:01:15 PM PDT 24
Peak memory 215824 kb
Host smart-ba8c7d11-23b8-4f5a-96cf-24e3c094342a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971722977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.971722977
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1151619260
Short name T97
Test name
Test status
Simulation time 764329432 ps
CPU time 12.36 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:27 PM PDT 24
Peak memory 215000 kb
Host smart-8c2b53fd-9810-4863-927f-aae0416a9a41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151619260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1151619260
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1547777743
Short name T2104
Test name
Test status
Simulation time 214840875 ps
CPU time 13.72 seconds
Started Mar 10 01:01:09 PM PDT 24
Finished Mar 10 01:01:24 PM PDT 24
Peak memory 214736 kb
Host smart-8cb6af52-fb96-450b-a612-d6ec7122b5af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547777743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1547777743
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3311787327
Short name T1993
Test name
Test status
Simulation time 57602162 ps
CPU time 3.7 seconds
Started Mar 10 01:18:15 PM PDT 24
Finished Mar 10 01:18:19 PM PDT 24
Peak memory 216408 kb
Host smart-d41c5f5c-860a-4aba-b5ca-5fdf91325209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311787327 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3311787327
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3346986883
Short name T2193
Test name
Test status
Simulation time 55524586 ps
CPU time 4.38 seconds
Started Mar 10 01:01:13 PM PDT 24
Finished Mar 10 01:01:17 PM PDT 24
Peak memory 216020 kb
Host smart-03b46c04-5302-481c-b00d-9ebbde94e6fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346986883 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3346986883
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3316707301
Short name T146
Test name
Test status
Simulation time 126881513 ps
CPU time 1.64 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:16 PM PDT 24
Peak memory 206452 kb
Host smart-11509fc9-daf8-4562-a4b7-368eeae19dc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316707301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3316707301
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4235040494
Short name T1974
Test name
Test status
Simulation time 132421983 ps
CPU time 1.36 seconds
Started Mar 10 01:01:12 PM PDT 24
Finished Mar 10 01:01:14 PM PDT 24
Peak memory 206404 kb
Host smart-07de652d-3c74-41be-add0-3c6c87387549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235040494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4235040494
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3531973794
Short name T1968
Test name
Test status
Simulation time 11448718 ps
CPU time 0.74 seconds
Started Mar 10 01:01:12 PM PDT 24
Finished Mar 10 01:01:14 PM PDT 24
Peak memory 202800 kb
Host smart-6bd1bc28-2db2-4eca-bf83-0029a06411b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531973794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3531973794
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3577511198
Short name T2005
Test name
Test status
Simulation time 54247534 ps
CPU time 0.76 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:15 PM PDT 24
Peak memory 202548 kb
Host smart-a485f71f-2521-4165-a30c-321066f9b07c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577511198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3577511198
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1362434996
Short name T2143
Test name
Test status
Simulation time 428009967 ps
CPU time 3.74 seconds
Started Mar 10 01:01:14 PM PDT 24
Finished Mar 10 01:01:18 PM PDT 24
Peak memory 214652 kb
Host smart-47cba687-e5d8-4fbf-b485-c8636d009715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362434996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1362434996
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2837350772
Short name T2083
Test name
Test status
Simulation time 158919816 ps
CPU time 3.15 seconds
Started Mar 10 01:18:13 PM PDT 24
Finished Mar 10 01:18:17 PM PDT 24
Peak memory 214708 kb
Host smart-7682a08c-53b0-4b11-bf64-3f471905ec44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837350772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2837350772
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1908387499
Short name T2071
Test name
Test status
Simulation time 48561009 ps
CPU time 1.91 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:17 PM PDT 24
Peak memory 214740 kb
Host smart-30b74289-c8c0-4ed2-aea1-29ef53deb995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908387499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1908387499
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3111128645
Short name T2044
Test name
Test status
Simulation time 189212112 ps
CPU time 2.54 seconds
Started Mar 10 01:01:13 PM PDT 24
Finished Mar 10 01:01:16 PM PDT 24
Peak memory 214964 kb
Host smart-5dbd381f-1bb6-4a37-9b7d-6cbeea524474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111128645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3111128645
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1963760275
Short name T2136
Test name
Test status
Simulation time 2674499708 ps
CPU time 14.54 seconds
Started Mar 10 01:01:12 PM PDT 24
Finished Mar 10 01:01:27 PM PDT 24
Peak memory 214768 kb
Host smart-4eae71f8-34f3-4bb2-b2ae-38107d99a078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963760275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1963760275
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2533742255
Short name T2217
Test name
Test status
Simulation time 294212942 ps
CPU time 19.32 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 214640 kb
Host smart-9a3c7dc6-de21-42f5-9f67-feeda6cde20e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533742255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2533742255
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1624400254
Short name T2015
Test name
Test status
Simulation time 93415481 ps
CPU time 3.4 seconds
Started Mar 10 01:18:15 PM PDT 24
Finished Mar 10 01:18:18 PM PDT 24
Peak memory 216052 kb
Host smart-b4eddf65-ebef-4ffb-a2b7-a85f9651b9b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624400254 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1624400254
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3002101672
Short name T2109
Test name
Test status
Simulation time 109781052 ps
CPU time 4.22 seconds
Started Mar 10 01:01:17 PM PDT 24
Finished Mar 10 01:01:22 PM PDT 24
Peak memory 216212 kb
Host smart-f3620417-27da-4045-8839-6b71c786f88f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002101672 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3002101672
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3659195092
Short name T2106
Test name
Test status
Simulation time 35539704 ps
CPU time 1.47 seconds
Started Mar 10 01:01:13 PM PDT 24
Finished Mar 10 01:01:15 PM PDT 24
Peak memory 214672 kb
Host smart-af8d8316-0ab7-4b83-b451-5bd6d719e5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659195092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3659195092
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.526921541
Short name T1985
Test name
Test status
Simulation time 200913706 ps
CPU time 2.14 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:16 PM PDT 24
Peak memory 206488 kb
Host smart-30c53385-d1c5-4e63-8295-65d9fac9afbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526921541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.526921541
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1251539544
Short name T2037
Test name
Test status
Simulation time 72202766 ps
CPU time 0.78 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:16 PM PDT 24
Peak memory 202512 kb
Host smart-09648753-a65f-4a76-8c20-9754bdc3d209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251539544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1251539544
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2510938912
Short name T2039
Test name
Test status
Simulation time 53563191 ps
CPU time 0.71 seconds
Started Mar 10 01:01:12 PM PDT 24
Finished Mar 10 01:01:14 PM PDT 24
Peak memory 202488 kb
Host smart-401c2f18-7e4d-44ce-854e-8405b9d5a730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510938912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2510938912
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2283746593
Short name T2045
Test name
Test status
Simulation time 170086365 ps
CPU time 3.65 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:18 PM PDT 24
Peak memory 214436 kb
Host smart-c9c38506-4404-44cc-9f33-f52681d21474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283746593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2283746593
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2743999179
Short name T2180
Test name
Test status
Simulation time 236240100 ps
CPU time 1.88 seconds
Started Mar 10 01:01:12 PM PDT 24
Finished Mar 10 01:01:15 PM PDT 24
Peak memory 206516 kb
Host smart-d880563a-2923-442b-b35b-57e737bdfe52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743999179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2743999179
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3522139135
Short name T2107
Test name
Test status
Simulation time 73349441 ps
CPU time 1.41 seconds
Started Mar 10 01:01:12 PM PDT 24
Finished Mar 10 01:01:14 PM PDT 24
Peak memory 206000 kb
Host smart-0b9ee9a7-9f62-4262-8c9f-ef631f577176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522139135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3522139135
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1886454337
Short name T2129
Test name
Test status
Simulation time 290096807 ps
CPU time 7.8 seconds
Started Mar 10 01:18:13 PM PDT 24
Finished Mar 10 01:18:21 PM PDT 24
Peak memory 214840 kb
Host smart-b2411f40-e18d-4799-9b08-8ac543360ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886454337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1886454337
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3198106587
Short name T2218
Test name
Test status
Simulation time 1314609347 ps
CPU time 7.06 seconds
Started Mar 10 01:01:13 PM PDT 24
Finished Mar 10 01:01:20 PM PDT 24
Peak memory 214692 kb
Host smart-a9cf2351-948a-4938-b01e-42e69e0f6507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198106587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3198106587
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2133683450
Short name T2175
Test name
Test status
Simulation time 166448968 ps
CPU time 3.6 seconds
Started Mar 10 01:18:19 PM PDT 24
Finished Mar 10 01:18:23 PM PDT 24
Peak memory 216516 kb
Host smart-de67733c-c93d-4ae2-917e-922eb4b4c744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133683450 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2133683450
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2445547802
Short name T1990
Test name
Test status
Simulation time 81396242 ps
CPU time 1.75 seconds
Started Mar 10 01:01:19 PM PDT 24
Finished Mar 10 01:01:21 PM PDT 24
Peak memory 214664 kb
Host smart-c4950ef4-da00-43c8-a5d3-307714871843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445547802 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2445547802
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1715763204
Short name T2190
Test name
Test status
Simulation time 32815446 ps
CPU time 1.42 seconds
Started Mar 10 01:01:20 PM PDT 24
Finished Mar 10 01:01:22 PM PDT 24
Peak memory 214660 kb
Host smart-b840c073-1f29-44c7-a20a-b142c2fdb971
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715763204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1715763204
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3426960607
Short name T2178
Test name
Test status
Simulation time 81569781 ps
CPU time 2.13 seconds
Started Mar 10 01:18:20 PM PDT 24
Finished Mar 10 01:18:22 PM PDT 24
Peak memory 214740 kb
Host smart-ff35fff9-dff1-4896-80da-9691767b60b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426960607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3426960607
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2095620478
Short name T1946
Test name
Test status
Simulation time 17233628 ps
CPU time 0.72 seconds
Started Mar 10 01:18:19 PM PDT 24
Finished Mar 10 01:18:20 PM PDT 24
Peak memory 202564 kb
Host smart-244995a1-cfa0-4200-9e6a-5154ff2dfa83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095620478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2095620478
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3250181961
Short name T2072
Test name
Test status
Simulation time 16292008 ps
CPU time 0.78 seconds
Started Mar 10 01:01:18 PM PDT 24
Finished Mar 10 01:01:19 PM PDT 24
Peak memory 202536 kb
Host smart-8b1fd180-1b3f-438c-9d71-d1b0bfcbe5e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250181961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3250181961
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2093031849
Short name T2210
Test name
Test status
Simulation time 81466205 ps
CPU time 2.07 seconds
Started Mar 10 01:18:18 PM PDT 24
Finished Mar 10 01:18:20 PM PDT 24
Peak memory 214736 kb
Host smart-ed4e9329-6974-4b17-8d85-749416be9fbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093031849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2093031849
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.216656022
Short name T2028
Test name
Test status
Simulation time 42579328 ps
CPU time 2.7 seconds
Started Mar 10 01:01:19 PM PDT 24
Finished Mar 10 01:01:22 PM PDT 24
Peak memory 206536 kb
Host smart-b5af2ef4-62e0-44e0-86d0-ba648bbb5184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216656022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.216656022
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4041823371
Short name T1976
Test name
Test status
Simulation time 440105853 ps
CPU time 3.65 seconds
Started Mar 10 01:01:20 PM PDT 24
Finished Mar 10 01:01:23 PM PDT 24
Peak memory 214748 kb
Host smart-7a470776-5057-4659-a8ad-a2b6a4b30dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041823371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4041823371
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.418745792
Short name T2115
Test name
Test status
Simulation time 549660019 ps
CPU time 4.09 seconds
Started Mar 10 01:18:18 PM PDT 24
Finished Mar 10 01:18:22 PM PDT 24
Peak memory 214868 kb
Host smart-832d9b8f-ef78-45eb-9b4a-6f1009669d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418745792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.418745792
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1279341479
Short name T2029
Test name
Test status
Simulation time 1203974501 ps
CPU time 8.12 seconds
Started Mar 10 01:01:19 PM PDT 24
Finished Mar 10 01:01:27 PM PDT 24
Peak memory 214716 kb
Host smart-32f84437-b836-4e93-ba6c-a26fa8a1bfdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279341479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1279341479
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2694783390
Short name T2069
Test name
Test status
Simulation time 3293158365 ps
CPU time 21.17 seconds
Started Mar 10 01:18:19 PM PDT 24
Finished Mar 10 01:18:41 PM PDT 24
Peak memory 214764 kb
Host smart-018d84ae-d3bf-4435-8c3f-a8a182d16265
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694783390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2694783390
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1489429602
Short name T2030
Test name
Test status
Simulation time 277975105 ps
CPU time 2.6 seconds
Started Mar 10 01:18:20 PM PDT 24
Finished Mar 10 01:18:22 PM PDT 24
Peak memory 215952 kb
Host smart-384a027a-9e3c-4017-a7b9-b6fbe5375d34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489429602 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1489429602
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1627520546
Short name T94
Test name
Test status
Simulation time 218349387 ps
CPU time 4.1 seconds
Started Mar 10 01:01:21 PM PDT 24
Finished Mar 10 01:01:25 PM PDT 24
Peak memory 215952 kb
Host smart-8abc038c-2154-436c-b79a-9eb62c53d66f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627520546 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1627520546
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1903794843
Short name T2214
Test name
Test status
Simulation time 32525639 ps
CPU time 1.12 seconds
Started Mar 10 01:01:19 PM PDT 24
Finished Mar 10 01:01:20 PM PDT 24
Peak memory 206404 kb
Host smart-1fe47757-0831-4d99-93cb-b068966f547f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903794843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1903794843
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3724903193
Short name T2152
Test name
Test status
Simulation time 140874598 ps
CPU time 2.59 seconds
Started Mar 10 01:18:21 PM PDT 24
Finished Mar 10 01:18:23 PM PDT 24
Peak memory 206404 kb
Host smart-00fc1df8-3603-4835-afd7-6fb4f96b63e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724903193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3724903193
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2565675039
Short name T2117
Test name
Test status
Simulation time 17261442 ps
CPU time 0.71 seconds
Started Mar 10 01:01:18 PM PDT 24
Finished Mar 10 01:01:19 PM PDT 24
Peak memory 202768 kb
Host smart-23b01002-2b5a-4a86-8987-de894b955018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565675039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2565675039
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2813879360
Short name T2040
Test name
Test status
Simulation time 27383008 ps
CPU time 0.68 seconds
Started Mar 10 01:18:20 PM PDT 24
Finished Mar 10 01:18:21 PM PDT 24
Peak memory 202840 kb
Host smart-fe2f3478-27ce-44ab-8a85-cffe29ca1c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813879360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2813879360
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1853163353
Short name T2205
Test name
Test status
Simulation time 67506656 ps
CPU time 2.42 seconds
Started Mar 10 01:18:19 PM PDT 24
Finished Mar 10 01:18:22 PM PDT 24
Peak memory 214628 kb
Host smart-a2d30825-fd16-4b4c-a63d-4372acbe2443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853163353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1853163353
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.266754268
Short name T2228
Test name
Test status
Simulation time 271256481 ps
CPU time 3.1 seconds
Started Mar 10 01:01:19 PM PDT 24
Finished Mar 10 01:01:22 PM PDT 24
Peak memory 214448 kb
Host smart-40cff513-3350-4f43-aaf3-70daace0a487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266754268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.266754268
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1899199198
Short name T2084
Test name
Test status
Simulation time 196272416 ps
CPU time 3.68 seconds
Started Mar 10 01:01:18 PM PDT 24
Finished Mar 10 01:01:22 PM PDT 24
Peak memory 214788 kb
Host smart-fee7399c-1c87-4f3d-bca4-28f2523fcb63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899199198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1899199198
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3690825282
Short name T2076
Test name
Test status
Simulation time 158657620 ps
CPU time 4.81 seconds
Started Mar 10 01:18:19 PM PDT 24
Finished Mar 10 01:18:24 PM PDT 24
Peak memory 214860 kb
Host smart-8f6fc277-194a-43c0-9f7f-0bb2ed5bdf76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690825282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3690825282
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1022232253
Short name T178
Test name
Test status
Simulation time 1066054781 ps
CPU time 14.36 seconds
Started Mar 10 01:18:20 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 214688 kb
Host smart-ee66e470-51d0-46ff-b664-19ea7d6c465f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022232253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1022232253
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3566304346
Short name T2011
Test name
Test status
Simulation time 112594899 ps
CPU time 6.95 seconds
Started Mar 10 01:01:17 PM PDT 24
Finished Mar 10 01:01:25 PM PDT 24
Peak memory 214644 kb
Host smart-bf6af565-4554-408c-b0ef-e6e9e2a88868
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566304346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3566304346
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4238900840
Short name T1999
Test name
Test status
Simulation time 53331147 ps
CPU time 3.53 seconds
Started Mar 10 01:18:19 PM PDT 24
Finished Mar 10 01:18:23 PM PDT 24
Peak memory 217024 kb
Host smart-a4c6acd5-f641-4fc2-8828-7e3f62bdfa29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238900840 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4238900840
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.584164748
Short name T149
Test name
Test status
Simulation time 211748034 ps
CPU time 1.69 seconds
Started Mar 10 01:01:17 PM PDT 24
Finished Mar 10 01:01:19 PM PDT 24
Peak memory 214756 kb
Host smart-a9098b53-6384-4a87-a568-b97157738a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584164748 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.584164748
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1678267025
Short name T114
Test name
Test status
Simulation time 130891263 ps
CPU time 2.69 seconds
Started Mar 10 01:18:21 PM PDT 24
Finished Mar 10 01:18:23 PM PDT 24
Peak memory 214668 kb
Host smart-8e012e43-3c31-40c8-9b4b-c55281135db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678267025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1678267025
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3674714770
Short name T2041
Test name
Test status
Simulation time 152338598 ps
CPU time 1.27 seconds
Started Mar 10 01:01:18 PM PDT 24
Finished Mar 10 01:01:20 PM PDT 24
Peak memory 206492 kb
Host smart-0045099d-46f7-4867-8d09-3ba108837e83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674714770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3674714770
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.907725433
Short name T2093
Test name
Test status
Simulation time 22053392 ps
CPU time 0.75 seconds
Started Mar 10 01:01:18 PM PDT 24
Finished Mar 10 01:01:19 PM PDT 24
Peak memory 202540 kb
Host smart-3ad64e41-e703-4bc5-b235-f5e9b64d32fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907725433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.907725433
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.953125800
Short name T2225
Test name
Test status
Simulation time 41011901 ps
CPU time 0.69 seconds
Started Mar 10 01:18:20 PM PDT 24
Finished Mar 10 01:18:20 PM PDT 24
Peak memory 202804 kb
Host smart-b2e71672-0145-4ca2-a113-dc22c60a142f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953125800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.953125800
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.128607854
Short name T2031
Test name
Test status
Simulation time 314131164 ps
CPU time 1.95 seconds
Started Mar 10 01:18:19 PM PDT 24
Finished Mar 10 01:18:21 PM PDT 24
Peak memory 214516 kb
Host smart-89027554-b1d2-4336-8b66-2bedce7209ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128607854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.128607854
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3995210258
Short name T2026
Test name
Test status
Simulation time 463984577 ps
CPU time 3.01 seconds
Started Mar 10 01:01:18 PM PDT 24
Finished Mar 10 01:01:21 PM PDT 24
Peak memory 214352 kb
Host smart-de6a793b-70c8-494c-acb3-63b4ed244cb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995210258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3995210258
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1728504769
Short name T105
Test name
Test status
Simulation time 179956718 ps
CPU time 2.21 seconds
Started Mar 10 01:18:17 PM PDT 24
Finished Mar 10 01:18:20 PM PDT 24
Peak memory 214712 kb
Host smart-0c4c0ff7-0d1e-48ea-9172-fdac14d79846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728504769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1728504769
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.809118268
Short name T2144
Test name
Test status
Simulation time 61248644 ps
CPU time 2.35 seconds
Started Mar 10 01:01:18 PM PDT 24
Finished Mar 10 01:01:20 PM PDT 24
Peak memory 215628 kb
Host smart-48023c0d-8945-47ba-97f3-61a3f534dcf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809118268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.809118268
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1867699473
Short name T2035
Test name
Test status
Simulation time 640541518 ps
CPU time 7.84 seconds
Started Mar 10 01:18:20 PM PDT 24
Finished Mar 10 01:18:28 PM PDT 24
Peak memory 214672 kb
Host smart-19a5560c-f82d-4a32-9be3-f47ff13203c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867699473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1867699473
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1952401955
Short name T2223
Test name
Test status
Simulation time 1058651346 ps
CPU time 14.71 seconds
Started Mar 10 01:01:17 PM PDT 24
Finished Mar 10 01:01:32 PM PDT 24
Peak memory 214660 kb
Host smart-54769c52-0b84-4a46-857d-e605dd4be72e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952401955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1952401955
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2132589805
Short name T2167
Test name
Test status
Simulation time 28910176 ps
CPU time 2.11 seconds
Started Mar 10 01:01:26 PM PDT 24
Finished Mar 10 01:01:29 PM PDT 24
Peak memory 214716 kb
Host smart-a674cd63-f801-4e46-818c-320a97d79050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132589805 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2132589805
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3046072321
Short name T2018
Test name
Test status
Simulation time 384325529 ps
CPU time 2.85 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:33 PM PDT 24
Peak memory 214988 kb
Host smart-06ae8007-6ec3-4d44-a535-48114e0c9335
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046072321 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3046072321
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1895138640
Short name T2163
Test name
Test status
Simulation time 40924626 ps
CPU time 1.27 seconds
Started Mar 10 01:01:26 PM PDT 24
Finished Mar 10 01:01:27 PM PDT 24
Peak memory 214684 kb
Host smart-e4cf8f03-c2ea-46b5-ad5a-8765dcc9321f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895138640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1895138640
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3320182771
Short name T2149
Test name
Test status
Simulation time 219423344 ps
CPU time 1.8 seconds
Started Mar 10 01:18:24 PM PDT 24
Finished Mar 10 01:18:26 PM PDT 24
Peak memory 214648 kb
Host smart-d7aa5f48-1319-4ae0-92f5-9cce269093d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320182771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3320182771
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1071667137
Short name T2141
Test name
Test status
Simulation time 17479237 ps
CPU time 0.78 seconds
Started Mar 10 01:18:25 PM PDT 24
Finished Mar 10 01:18:26 PM PDT 24
Peak memory 202564 kb
Host smart-50e882c1-0ab1-47f6-84c4-5ab454b0e768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071667137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1071667137
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3560001075
Short name T2046
Test name
Test status
Simulation time 42276292 ps
CPU time 0.77 seconds
Started Mar 10 01:01:25 PM PDT 24
Finished Mar 10 01:01:26 PM PDT 24
Peak memory 202584 kb
Host smart-b114daad-a678-427c-a49e-b2c4224e7fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560001075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3560001075
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3748622041
Short name T2211
Test name
Test status
Simulation time 59098583 ps
CPU time 1.82 seconds
Started Mar 10 01:01:26 PM PDT 24
Finished Mar 10 01:01:28 PM PDT 24
Peak memory 206508 kb
Host smart-09e2ae6e-e2a1-41ba-816d-3f1f6d908dcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748622041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3748622041
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3780949855
Short name T2066
Test name
Test status
Simulation time 891350054 ps
CPU time 4.5 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 214664 kb
Host smart-23f2f02b-ac50-4844-b464-076683705fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780949855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3780949855
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2898924538
Short name T173
Test name
Test status
Simulation time 482903198 ps
CPU time 4.85 seconds
Started Mar 10 01:01:19 PM PDT 24
Finished Mar 10 01:01:24 PM PDT 24
Peak memory 214720 kb
Host smart-ba9fe620-c878-4677-9647-e15034539d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898924538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2898924538
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.719965033
Short name T2033
Test name
Test status
Simulation time 313113355 ps
CPU time 1.87 seconds
Started Mar 10 01:18:23 PM PDT 24
Finished Mar 10 01:18:25 PM PDT 24
Peak memory 214780 kb
Host smart-1ab00048-73b7-42ca-836a-0eb15d18a777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719965033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.719965033
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1601584164
Short name T176
Test name
Test status
Simulation time 1083796950 ps
CPU time 6.99 seconds
Started Mar 10 01:18:22 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 214716 kb
Host smart-ba9fe20a-bb03-43f7-bb0a-83b449d4394b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601584164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1601584164
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2849735824
Short name T2043
Test name
Test status
Simulation time 4266439507 ps
CPU time 20.06 seconds
Started Mar 10 01:01:25 PM PDT 24
Finished Mar 10 01:01:45 PM PDT 24
Peak memory 214860 kb
Host smart-a54a4e29-f390-45f9-8e7b-1b2a243c9611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849735824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2849735824
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2298848030
Short name T2006
Test name
Test status
Simulation time 54609485 ps
CPU time 3.61 seconds
Started Mar 10 01:18:22 PM PDT 24
Finished Mar 10 01:18:26 PM PDT 24
Peak memory 215796 kb
Host smart-485ab308-b00d-4e1d-8f2f-efc43f755da1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298848030 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2298848030
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.265773791
Short name T2065
Test name
Test status
Simulation time 137873881 ps
CPU time 4.29 seconds
Started Mar 10 01:01:25 PM PDT 24
Finished Mar 10 01:01:30 PM PDT 24
Peak memory 215748 kb
Host smart-d779de5d-60b0-4ab4-8c4a-c98d6ec8efa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265773791 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.265773791
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3322778713
Short name T2169
Test name
Test status
Simulation time 29334440 ps
CPU time 1.84 seconds
Started Mar 10 01:18:25 PM PDT 24
Finished Mar 10 01:18:27 PM PDT 24
Peak memory 214688 kb
Host smart-fc20771d-58ac-4b76-8941-8a45a42f018a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322778713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3322778713
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3573996365
Short name T119
Test name
Test status
Simulation time 20836554 ps
CPU time 1.26 seconds
Started Mar 10 01:01:24 PM PDT 24
Finished Mar 10 01:01:26 PM PDT 24
Peak memory 206452 kb
Host smart-8910b684-7934-4419-808d-c89b971947b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573996365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3573996365
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1115344965
Short name T1936
Test name
Test status
Simulation time 16629030 ps
CPU time 0.74 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 202820 kb
Host smart-f93cd8b1-fcb9-47c4-918f-e39bf5990088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115344965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1115344965
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2025851818
Short name T2009
Test name
Test status
Simulation time 15350656 ps
CPU time 0.71 seconds
Started Mar 10 01:01:24 PM PDT 24
Finished Mar 10 01:01:25 PM PDT 24
Peak memory 202436 kb
Host smart-674c2ab1-85c7-4fe3-a296-99fa6961d2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025851818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2025851818
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1801527812
Short name T2171
Test name
Test status
Simulation time 154548641 ps
CPU time 1.9 seconds
Started Mar 10 01:01:26 PM PDT 24
Finished Mar 10 01:01:28 PM PDT 24
Peak memory 214608 kb
Host smart-25483812-8f7c-4ff6-8548-6147ae463ab3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801527812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1801527812
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2377362080
Short name T145
Test name
Test status
Simulation time 823021881 ps
CPU time 4.33 seconds
Started Mar 10 01:18:24 PM PDT 24
Finished Mar 10 01:18:29 PM PDT 24
Peak memory 214684 kb
Host smart-2b1966e3-e204-4bb1-b7d3-f9ee5562e159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377362080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2377362080
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3837164718
Short name T104
Test name
Test status
Simulation time 324015655 ps
CPU time 2.52 seconds
Started Mar 10 01:18:24 PM PDT 24
Finished Mar 10 01:18:27 PM PDT 24
Peak memory 214756 kb
Host smart-cba9477f-2c71-4638-b2b5-07707ec18b29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837164718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3837164718
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.934552020
Short name T180
Test name
Test status
Simulation time 205143816 ps
CPU time 6.72 seconds
Started Mar 10 01:01:26 PM PDT 24
Finished Mar 10 01:01:33 PM PDT 24
Peak memory 215000 kb
Host smart-48e183e7-7702-460d-9bdc-08adca82f9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934552020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.934552020
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4113927687
Short name T2230
Test name
Test status
Simulation time 164217207 ps
CPU time 3.01 seconds
Started Mar 10 01:01:32 PM PDT 24
Finished Mar 10 01:01:36 PM PDT 24
Peak memory 216056 kb
Host smart-ec7e9915-3b41-4e95-9c7f-b6e8f903f550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113927687 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4113927687
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.796026604
Short name T2094
Test name
Test status
Simulation time 123465451 ps
CPU time 3.41 seconds
Started Mar 10 01:18:30 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 215844 kb
Host smart-fc60b8d7-1ab9-4e46-9de3-2cbf5b34d681
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796026604 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.796026604
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3133693307
Short name T1983
Test name
Test status
Simulation time 293628806 ps
CPU time 2.44 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:32 PM PDT 24
Peak memory 214684 kb
Host smart-85c920b3-ce0e-4a09-9565-61d46bfb8219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133693307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3133693307
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3368130084
Short name T117
Test name
Test status
Simulation time 20341296 ps
CPU time 1.28 seconds
Started Mar 10 01:01:32 PM PDT 24
Finished Mar 10 01:01:33 PM PDT 24
Peak memory 206480 kb
Host smart-9643bae1-b415-4cbd-b72e-44b38a8b23a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368130084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3368130084
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1021990534
Short name T2012
Test name
Test status
Simulation time 11809959 ps
CPU time 0.71 seconds
Started Mar 10 01:01:25 PM PDT 24
Finished Mar 10 01:01:26 PM PDT 24
Peak memory 202856 kb
Host smart-4d56f310-9e16-4f38-a527-1ed5b78df693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021990534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1021990534
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3937246284
Short name T2130
Test name
Test status
Simulation time 58974425 ps
CPU time 0.74 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:31 PM PDT 24
Peak memory 202508 kb
Host smart-eabeb7ee-3d88-48be-a0b0-09663db321c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937246284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3937246284
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1696276275
Short name T1981
Test name
Test status
Simulation time 131111111 ps
CPU time 1.9 seconds
Started Mar 10 01:01:31 PM PDT 24
Finished Mar 10 01:01:33 PM PDT 24
Peak memory 214584 kb
Host smart-80e00408-e2cc-4eff-8ef1-5b0397d4f5d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696276275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1696276275
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2743367166
Short name T2151
Test name
Test status
Simulation time 262852211 ps
CPU time 4.16 seconds
Started Mar 10 01:18:26 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 214516 kb
Host smart-7b6f38c6-39be-4ebd-beec-048e6d04d8b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743367166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2743367166
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2062147001
Short name T2049
Test name
Test status
Simulation time 183993042 ps
CPU time 3.21 seconds
Started Mar 10 01:01:25 PM PDT 24
Finished Mar 10 01:01:28 PM PDT 24
Peak memory 214720 kb
Host smart-989a00fe-8471-4476-b115-48634eea06da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062147001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2062147001
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3712414324
Short name T2067
Test name
Test status
Simulation time 111150433 ps
CPU time 3.86 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 214836 kb
Host smart-14847873-ddee-4242-8040-c8489e8f8e52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712414324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3712414324
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1105214380
Short name T99
Test name
Test status
Simulation time 4528796111 ps
CPU time 13.88 seconds
Started Mar 10 01:01:25 PM PDT 24
Finished Mar 10 01:01:39 PM PDT 24
Peak memory 214552 kb
Host smart-7df3b9aa-afb3-4f06-b357-dec2ea8fcc0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105214380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1105214380
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2962562552
Short name T2118
Test name
Test status
Simulation time 809360463 ps
CPU time 13.19 seconds
Started Mar 10 01:18:27 PM PDT 24
Finished Mar 10 01:18:41 PM PDT 24
Peak memory 214856 kb
Host smart-5dbb9b69-c34a-4c4e-94cf-b420c95baa03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962562552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2962562552
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1676422820
Short name T2138
Test name
Test status
Simulation time 59105086 ps
CPU time 2.02 seconds
Started Mar 10 01:18:28 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 214776 kb
Host smart-e4602f98-c7d4-4bf7-9292-d23227e4f313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676422820 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1676422820
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3760214009
Short name T2116
Test name
Test status
Simulation time 64083276 ps
CPU time 1.93 seconds
Started Mar 10 01:01:31 PM PDT 24
Finished Mar 10 01:01:33 PM PDT 24
Peak memory 214772 kb
Host smart-a6c85bc8-d140-4005-8fbe-5beea69da444
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760214009 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3760214009
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1218876371
Short name T2004
Test name
Test status
Simulation time 22302703 ps
CPU time 1.31 seconds
Started Mar 10 01:18:28 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 206424 kb
Host smart-609125db-c3ae-47ba-86cc-d86e95704420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218876371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1218876371
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1885684666
Short name T1939
Test name
Test status
Simulation time 303472885 ps
CPU time 2.57 seconds
Started Mar 10 01:01:31 PM PDT 24
Finished Mar 10 01:01:34 PM PDT 24
Peak memory 206416 kb
Host smart-f89da82b-55ac-423a-aaf2-3951ea278383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885684666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1885684666
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2008318857
Short name T1942
Test name
Test status
Simulation time 22063127 ps
CPU time 0.71 seconds
Started Mar 10 01:01:34 PM PDT 24
Finished Mar 10 01:01:35 PM PDT 24
Peak memory 202440 kb
Host smart-db962b88-3dd3-4ed3-97c3-356d4d01cae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008318857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2008318857
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.40452287
Short name T1984
Test name
Test status
Simulation time 51319410 ps
CPU time 0.77 seconds
Started Mar 10 01:18:28 PM PDT 24
Finished Mar 10 01:18:29 PM PDT 24
Peak memory 202524 kb
Host smart-e6cb1d22-9d63-4faa-aa57-72f7ff85b026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40452287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.40452287
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2512187538
Short name T2092
Test name
Test status
Simulation time 488252876 ps
CPU time 3.04 seconds
Started Mar 10 01:01:32 PM PDT 24
Finished Mar 10 01:01:35 PM PDT 24
Peak memory 214448 kb
Host smart-7e44d271-03fd-4bee-b28e-9152a86a6069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512187538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2512187538
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3022960091
Short name T2064
Test name
Test status
Simulation time 143883588 ps
CPU time 3.24 seconds
Started Mar 10 01:18:28 PM PDT 24
Finished Mar 10 01:18:32 PM PDT 24
Peak memory 214440 kb
Host smart-2eef61e7-6bf4-4b7c-a9ba-b99e3e586538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022960091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3022960091
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1374975773
Short name T2160
Test name
Test status
Simulation time 511842440 ps
CPU time 3.38 seconds
Started Mar 10 01:18:30 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 214824 kb
Host smart-3f111af6-ca28-4ef4-ad57-fde37bd79617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374975773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1374975773
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2899913974
Short name T110
Test name
Test status
Simulation time 28181316 ps
CPU time 1.98 seconds
Started Mar 10 01:01:31 PM PDT 24
Finished Mar 10 01:01:33 PM PDT 24
Peak memory 214736 kb
Host smart-0bb7aded-2f17-484f-9a2a-1355b39451a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899913974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2899913974
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2002866290
Short name T2120
Test name
Test status
Simulation time 436685907 ps
CPU time 6.47 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:36 PM PDT 24
Peak memory 214752 kb
Host smart-cd26d5a1-e7a2-4789-80c1-2e381d2b5fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002866290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2002866290
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1133295803
Short name T2055
Test name
Test status
Simulation time 4412362216 ps
CPU time 23.42 seconds
Started Mar 10 01:17:59 PM PDT 24
Finished Mar 10 01:18:23 PM PDT 24
Peak memory 206452 kb
Host smart-a13148ce-496a-4304-807e-3709455d357d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133295803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1133295803
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3135020043
Short name T2095
Test name
Test status
Simulation time 629014379 ps
CPU time 21.52 seconds
Started Mar 10 01:00:37 PM PDT 24
Finished Mar 10 01:00:58 PM PDT 24
Peak memory 214692 kb
Host smart-43cf0d60-6c1f-4958-b81d-b2d4966a7b11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135020043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3135020043
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1673267001
Short name T2128
Test name
Test status
Simulation time 2423636551 ps
CPU time 35.63 seconds
Started Mar 10 01:17:50 PM PDT 24
Finished Mar 10 01:18:26 PM PDT 24
Peak memory 206552 kb
Host smart-41936aed-106a-49df-98ba-eacfccc9c4dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673267001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1673267001
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.824489255
Short name T2185
Test name
Test status
Simulation time 774959483 ps
CPU time 11.29 seconds
Started Mar 10 01:00:34 PM PDT 24
Finished Mar 10 01:00:45 PM PDT 24
Peak memory 206172 kb
Host smart-e69907b8-396a-41c0-a080-b1f46b5e9ef2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824489255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.824489255
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1537036844
Short name T84
Test name
Test status
Simulation time 233482997 ps
CPU time 0.95 seconds
Started Mar 10 01:17:53 PM PDT 24
Finished Mar 10 01:17:54 PM PDT 24
Peak memory 206328 kb
Host smart-85e6628c-abe4-4965-bbab-46ac4d3c94ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537036844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1537036844
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2064572998
Short name T2075
Test name
Test status
Simulation time 38161783 ps
CPU time 1.27 seconds
Started Mar 10 01:00:31 PM PDT 24
Finished Mar 10 01:00:33 PM PDT 24
Peak memory 214636 kb
Host smart-877feee5-1625-4f92-9f15-26d93ce1f3c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064572998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2064572998
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3331742296
Short name T1955
Test name
Test status
Simulation time 42994829 ps
CPU time 2.84 seconds
Started Mar 10 01:00:37 PM PDT 24
Finished Mar 10 01:00:40 PM PDT 24
Peak memory 215764 kb
Host smart-5e6f4fa9-f219-45b9-84a4-b9feee0ad522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331742296 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3331742296
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.884033420
Short name T2213
Test name
Test status
Simulation time 58335727 ps
CPU time 4.11 seconds
Started Mar 10 01:17:57 PM PDT 24
Finished Mar 10 01:18:01 PM PDT 24
Peak memory 217128 kb
Host smart-fcdbb82a-716b-4ebd-9595-4680a10fcf34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884033420 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.884033420
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1963996485
Short name T2019
Test name
Test status
Simulation time 245185578 ps
CPU time 2.04 seconds
Started Mar 10 01:17:52 PM PDT 24
Finished Mar 10 01:17:54 PM PDT 24
Peak memory 214736 kb
Host smart-0778b444-c9db-44a3-a612-cc0f876094ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963996485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
963996485
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4165078579
Short name T2209
Test name
Test status
Simulation time 82509401 ps
CPU time 2.09 seconds
Started Mar 10 01:00:31 PM PDT 24
Finished Mar 10 01:00:33 PM PDT 24
Peak memory 214684 kb
Host smart-c9982dfb-916a-475c-b0f2-9c3ea5fa32ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165078579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
165078579
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1628761914
Short name T2007
Test name
Test status
Simulation time 23812135 ps
CPU time 0.71 seconds
Started Mar 10 01:17:49 PM PDT 24
Finished Mar 10 01:17:50 PM PDT 24
Peak memory 202856 kb
Host smart-075efb6c-6819-4ae4-9ccf-768fb10a5e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628761914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
628761914
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3596524831
Short name T1934
Test name
Test status
Simulation time 21505458 ps
CPU time 0.7 seconds
Started Mar 10 01:00:31 PM PDT 24
Finished Mar 10 01:00:32 PM PDT 24
Peak memory 202488 kb
Host smart-bc1df2e5-22b5-4668-b2fa-71de7a72ec17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596524831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
596524831
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1470525175
Short name T1966
Test name
Test status
Simulation time 164307399 ps
CPU time 1.22 seconds
Started Mar 10 01:00:30 PM PDT 24
Finished Mar 10 01:00:32 PM PDT 24
Peak memory 214568 kb
Host smart-a5d41c0c-d42a-4c3c-8e80-b82a68a7ab17
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470525175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1470525175
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3954744325
Short name T2057
Test name
Test status
Simulation time 49471253 ps
CPU time 1.77 seconds
Started Mar 10 01:17:51 PM PDT 24
Finished Mar 10 01:17:53 PM PDT 24
Peak memory 214660 kb
Host smart-2ca098c1-9493-423c-807a-c1edb3c269ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954744325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3954744325
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1678569816
Short name T2048
Test name
Test status
Simulation time 18012261 ps
CPU time 0.66 seconds
Started Mar 10 01:17:54 PM PDT 24
Finished Mar 10 01:17:55 PM PDT 24
Peak memory 202424 kb
Host smart-334fe1ec-62b9-4082-884d-75a482233e99
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678569816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1678569816
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.383562056
Short name T1991
Test name
Test status
Simulation time 11431206 ps
CPU time 0.64 seconds
Started Mar 10 01:00:31 PM PDT 24
Finished Mar 10 01:00:31 PM PDT 24
Peak memory 202340 kb
Host smart-b443805f-883b-4627-a7d5-bcf955834ab0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383562056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.383562056
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3463467202
Short name T1995
Test name
Test status
Simulation time 298649909 ps
CPU time 2.05 seconds
Started Mar 10 01:00:38 PM PDT 24
Finished Mar 10 01:00:41 PM PDT 24
Peak memory 206392 kb
Host smart-11769a5b-b889-4ee6-adb8-da6541572217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463467202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3463467202
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.469120358
Short name T2158
Test name
Test status
Simulation time 253899691 ps
CPU time 3.19 seconds
Started Mar 10 01:17:56 PM PDT 24
Finished Mar 10 01:17:59 PM PDT 24
Peak memory 206476 kb
Host smart-69437b04-ebd2-4add-9e11-196f5340ac60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469120358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.469120358
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2912188648
Short name T2226
Test name
Test status
Simulation time 78480173 ps
CPU time 1.52 seconds
Started Mar 10 01:00:32 PM PDT 24
Finished Mar 10 01:00:35 PM PDT 24
Peak memory 214752 kb
Host smart-3fe635e3-0b5d-4692-9618-847eaecb2b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912188648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
912188648
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3529121726
Short name T2157
Test name
Test status
Simulation time 240474823 ps
CPU time 4.77 seconds
Started Mar 10 01:17:49 PM PDT 24
Finished Mar 10 01:17:54 PM PDT 24
Peak memory 214812 kb
Host smart-c476c668-1583-4462-8906-4811f771b655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529121726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
529121726
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.378272210
Short name T2060
Test name
Test status
Simulation time 3429266030 ps
CPU time 24.14 seconds
Started Mar 10 01:00:33 PM PDT 24
Finished Mar 10 01:00:58 PM PDT 24
Peak memory 214740 kb
Host smart-eb258525-aea0-4450-891e-68b0325d2685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378272210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.378272210
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.510094740
Short name T2162
Test name
Test status
Simulation time 790135307 ps
CPU time 12.71 seconds
Started Mar 10 01:17:54 PM PDT 24
Finished Mar 10 01:18:07 PM PDT 24
Peak memory 214744 kb
Host smart-def71d17-5c34-4a6d-ad7a-c404dfc49042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510094740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.510094740
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1840120540
Short name T2100
Test name
Test status
Simulation time 58965591 ps
CPU time 0.8 seconds
Started Mar 10 01:18:30 PM PDT 24
Finished Mar 10 01:18:31 PM PDT 24
Peak memory 202548 kb
Host smart-4fa890b7-1bcb-4f44-b7c7-d273fee6b97d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840120540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1840120540
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.637946989
Short name T2022
Test name
Test status
Simulation time 51766849 ps
CPU time 0.73 seconds
Started Mar 10 01:01:35 PM PDT 24
Finished Mar 10 01:01:36 PM PDT 24
Peak memory 202808 kb
Host smart-0922fd4b-514b-4720-b92c-046f8f2ac892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637946989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.637946989
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3098552482
Short name T2198
Test name
Test status
Simulation time 29043669 ps
CPU time 0.7 seconds
Started Mar 10 01:18:35 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 202496 kb
Host smart-e0c9a42a-1485-456d-ae9c-a7397e4d159d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098552482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3098552482
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.7057294
Short name T2123
Test name
Test status
Simulation time 46751249 ps
CPU time 0.72 seconds
Started Mar 10 01:01:31 PM PDT 24
Finished Mar 10 01:01:32 PM PDT 24
Peak memory 202464 kb
Host smart-c87531d4-fe4e-449a-9b31-6f0b32d76853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7057294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.7057294
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2650537172
Short name T2096
Test name
Test status
Simulation time 44521910 ps
CPU time 0.79 seconds
Started Mar 10 01:01:34 PM PDT 24
Finished Mar 10 01:01:35 PM PDT 24
Peak memory 202480 kb
Host smart-31f061f1-9248-49c4-85ad-c6b9b8517665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650537172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2650537172
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3297657832
Short name T2008
Test name
Test status
Simulation time 19466185 ps
CPU time 0.77 seconds
Started Mar 10 01:18:28 PM PDT 24
Finished Mar 10 01:18:29 PM PDT 24
Peak memory 202536 kb
Host smart-2bb11daa-44ad-4325-9ff8-f349371a5036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297657832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3297657832
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1104413174
Short name T2052
Test name
Test status
Simulation time 17577461 ps
CPU time 0.79 seconds
Started Mar 10 01:01:29 PM PDT 24
Finished Mar 10 01:01:30 PM PDT 24
Peak memory 202440 kb
Host smart-79e0f657-3c9e-4386-a06b-995470418de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104413174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1104413174
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1734162196
Short name T2000
Test name
Test status
Simulation time 12805365 ps
CPU time 0.78 seconds
Started Mar 10 01:18:28 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 202816 kb
Host smart-c1a134e8-e32b-4bbd-b6f1-175a85437de8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734162196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1734162196
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1765138118
Short name T2153
Test name
Test status
Simulation time 49952958 ps
CPU time 0.72 seconds
Started Mar 10 01:18:28 PM PDT 24
Finished Mar 10 01:18:29 PM PDT 24
Peak memory 202536 kb
Host smart-3e12f1b9-4728-4fc5-bee1-53f6419a2b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765138118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1765138118
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3219912137
Short name T1969
Test name
Test status
Simulation time 15704186 ps
CPU time 0.76 seconds
Started Mar 10 01:01:32 PM PDT 24
Finished Mar 10 01:01:33 PM PDT 24
Peak memory 202544 kb
Host smart-9a5aad86-4a87-4100-ba00-b180ce4cdfc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219912137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3219912137
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3511082421
Short name T2206
Test name
Test status
Simulation time 30127282 ps
CPU time 0.75 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 202904 kb
Host smart-041a17e2-e919-41eb-84c6-7eff7ba98c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511082421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3511082421
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.758430371
Short name T1977
Test name
Test status
Simulation time 16073035 ps
CPU time 0.73 seconds
Started Mar 10 01:01:35 PM PDT 24
Finished Mar 10 01:01:36 PM PDT 24
Peak memory 202808 kb
Host smart-b32cb08f-8c80-4b9c-9bb6-acd0924d6a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758430371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.758430371
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3747925084
Short name T2139
Test name
Test status
Simulation time 15407470 ps
CPU time 0.71 seconds
Started Mar 10 01:18:35 PM PDT 24
Finished Mar 10 01:18:36 PM PDT 24
Peak memory 202820 kb
Host smart-40e2db66-294c-45d8-ae9c-d23d6b0329e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747925084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3747925084
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.42194423
Short name T2202
Test name
Test status
Simulation time 35062487 ps
CPU time 0.77 seconds
Started Mar 10 01:01:31 PM PDT 24
Finished Mar 10 01:01:32 PM PDT 24
Peak memory 202536 kb
Host smart-43548ec4-05b1-4fe4-8848-8215b3102fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42194423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.42194423
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4055336186
Short name T2224
Test name
Test status
Simulation time 11893185 ps
CPU time 0.73 seconds
Started Mar 10 01:01:32 PM PDT 24
Finished Mar 10 01:01:33 PM PDT 24
Peak memory 202480 kb
Host smart-376594db-013d-4c22-ac14-6a101fe7ca26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055336186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4055336186
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.878158461
Short name T1945
Test name
Test status
Simulation time 61059622 ps
CPU time 0.78 seconds
Started Mar 10 01:18:31 PM PDT 24
Finished Mar 10 01:18:32 PM PDT 24
Peak memory 202576 kb
Host smart-2dba5250-78f6-49bf-9c65-9e9f346526a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878158461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.878158461
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1326825733
Short name T2001
Test name
Test status
Simulation time 12354379 ps
CPU time 0.77 seconds
Started Mar 10 01:18:28 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 202524 kb
Host smart-d3ffbb93-7aa5-4347-9d7e-da4d38cf7cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326825733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1326825733
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2020155891
Short name T1959
Test name
Test status
Simulation time 79474879 ps
CPU time 0.74 seconds
Started Mar 10 01:01:36 PM PDT 24
Finished Mar 10 01:01:38 PM PDT 24
Peak memory 202524 kb
Host smart-ca59ec80-63ed-4619-bbc3-57b7a276c6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020155891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2020155891
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2148055358
Short name T2182
Test name
Test status
Simulation time 34874355 ps
CPU time 0.7 seconds
Started Mar 10 01:01:30 PM PDT 24
Finished Mar 10 01:01:31 PM PDT 24
Peak memory 202860 kb
Host smart-4f825bcb-62f0-4770-bc09-80c9da1379f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148055358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2148055358
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2890931238
Short name T2187
Test name
Test status
Simulation time 16317726 ps
CPU time 0.74 seconds
Started Mar 10 01:18:29 PM PDT 24
Finished Mar 10 01:18:31 PM PDT 24
Peak memory 202524 kb
Host smart-fcc6dbc1-1e27-4ac4-bcdc-b8eb37371a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890931238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2890931238
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2576565841
Short name T2147
Test name
Test status
Simulation time 1301099736 ps
CPU time 7.58 seconds
Started Mar 10 01:00:38 PM PDT 24
Finished Mar 10 01:00:46 PM PDT 24
Peak memory 206488 kb
Host smart-e9c4fecf-a1f5-4bf7-aa32-08cf2e36f8cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576565841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2576565841
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4232850938
Short name T124
Test name
Test status
Simulation time 5031678031 ps
CPU time 25.92 seconds
Started Mar 10 01:17:58 PM PDT 24
Finished Mar 10 01:18:24 PM PDT 24
Peak memory 214684 kb
Host smart-93619094-4fce-43bb-bff2-ba44c2aa79a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232850938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4232850938
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3756733118
Short name T118
Test name
Test status
Simulation time 945712045 ps
CPU time 14.8 seconds
Started Mar 10 01:00:38 PM PDT 24
Finished Mar 10 01:00:53 PM PDT 24
Peak memory 206444 kb
Host smart-2ca8ef6a-d2fb-4a8b-8bbc-7538b9568fe9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756733118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3756733118
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.613791697
Short name T1957
Test name
Test status
Simulation time 385188167 ps
CPU time 12.9 seconds
Started Mar 10 01:17:55 PM PDT 24
Finished Mar 10 01:18:08 PM PDT 24
Peak memory 206500 kb
Host smart-6bec7db0-a44b-4e1a-982e-174ae495b85b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613791697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.613791697
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2042999769
Short name T2090
Test name
Test status
Simulation time 36561554 ps
CPU time 1.2 seconds
Started Mar 10 01:00:37 PM PDT 24
Finished Mar 10 01:00:38 PM PDT 24
Peak memory 206408 kb
Host smart-06fb211e-3f59-49a7-bd99-54c7b75807d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042999769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2042999769
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2482302299
Short name T2042
Test name
Test status
Simulation time 38312382 ps
CPU time 1.24 seconds
Started Mar 10 01:17:59 PM PDT 24
Finished Mar 10 01:18:01 PM PDT 24
Peak memory 215744 kb
Host smart-c0839c24-be76-4d00-9dc3-a344af62c5ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482302299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2482302299
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2095041965
Short name T2148
Test name
Test status
Simulation time 131669249 ps
CPU time 3.35 seconds
Started Mar 10 01:00:43 PM PDT 24
Finished Mar 10 01:00:46 PM PDT 24
Peak memory 216324 kb
Host smart-d6bb319a-57f9-45bb-9d2d-342c63ad52a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095041965 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2095041965
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.378518821
Short name T2108
Test name
Test status
Simulation time 99523480 ps
CPU time 2.69 seconds
Started Mar 10 01:17:59 PM PDT 24
Finished Mar 10 01:18:02 PM PDT 24
Peak memory 215784 kb
Host smart-402a7806-6e67-4aa3-a185-9ab669a6db27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378518821 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.378518821
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1385869509
Short name T2125
Test name
Test status
Simulation time 239816997 ps
CPU time 2.02 seconds
Started Mar 10 01:17:57 PM PDT 24
Finished Mar 10 01:17:59 PM PDT 24
Peak memory 214700 kb
Host smart-c66a354b-689e-4362-8717-f1ee67d9458b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385869509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
385869509
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2489590456
Short name T2150
Test name
Test status
Simulation time 116888556 ps
CPU time 1.89 seconds
Started Mar 10 01:00:37 PM PDT 24
Finished Mar 10 01:00:39 PM PDT 24
Peak memory 214656 kb
Host smart-047489e7-7af4-4062-9477-2b920fb25948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489590456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
489590456
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3008480116
Short name T2179
Test name
Test status
Simulation time 71634634 ps
CPU time 0.73 seconds
Started Mar 10 01:17:58 PM PDT 24
Finished Mar 10 01:17:59 PM PDT 24
Peak memory 202504 kb
Host smart-e4f311d2-82d2-4201-a043-54e8e0d2b9a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008480116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
008480116
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4123286846
Short name T2038
Test name
Test status
Simulation time 15734398 ps
CPU time 0.73 seconds
Started Mar 10 01:00:38 PM PDT 24
Finished Mar 10 01:00:39 PM PDT 24
Peak memory 202844 kb
Host smart-00d7efb3-7a8a-4a1c-bd9f-54dcb093ae14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123286846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
123286846
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1720935648
Short name T2036
Test name
Test status
Simulation time 35950536 ps
CPU time 1.34 seconds
Started Mar 10 01:00:38 PM PDT 24
Finished Mar 10 01:00:39 PM PDT 24
Peak memory 214644 kb
Host smart-6251f725-e90f-4f8c-94d3-61fe8f888d78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720935648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1720935648
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2585758825
Short name T2204
Test name
Test status
Simulation time 23544782 ps
CPU time 1.56 seconds
Started Mar 10 01:17:59 PM PDT 24
Finished Mar 10 01:18:01 PM PDT 24
Peak memory 214744 kb
Host smart-7bcf4677-0ba2-4d65-9d39-1fb6a8547df6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585758825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2585758825
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1483968804
Short name T1964
Test name
Test status
Simulation time 11688935 ps
CPU time 0.65 seconds
Started Mar 10 01:00:37 PM PDT 24
Finished Mar 10 01:00:38 PM PDT 24
Peak memory 202740 kb
Host smart-3d4d8c9e-02d3-40ef-9c5f-cfa0f435ecd6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483968804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1483968804
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.519883271
Short name T2099
Test name
Test status
Simulation time 31529824 ps
CPU time 0.65 seconds
Started Mar 10 01:17:56 PM PDT 24
Finished Mar 10 01:17:57 PM PDT 24
Peak memory 202752 kb
Host smart-cd44196b-a684-4ea1-8807-80d1430bf000
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519883271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.519883271
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2761807623
Short name T2017
Test name
Test status
Simulation time 67892659 ps
CPU time 1.91 seconds
Started Mar 10 01:17:57 PM PDT 24
Finished Mar 10 01:17:59 PM PDT 24
Peak memory 206596 kb
Host smart-743994ec-c6e3-432e-a873-ff6251eab121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761807623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2761807623
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3077654590
Short name T2166
Test name
Test status
Simulation time 74313315 ps
CPU time 1.9 seconds
Started Mar 10 01:00:41 PM PDT 24
Finished Mar 10 01:00:43 PM PDT 24
Peak memory 206492 kb
Host smart-294df820-9cf0-450f-92bd-5c1dccfd0d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077654590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3077654590
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2140729571
Short name T95
Test name
Test status
Simulation time 178984427 ps
CPU time 3.09 seconds
Started Mar 10 01:00:36 PM PDT 24
Finished Mar 10 01:00:39 PM PDT 24
Peak memory 214720 kb
Host smart-8a5cec4f-d2dd-4aad-966f-c47761def33b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140729571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
140729571
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3143004925
Short name T103
Test name
Test status
Simulation time 344759948 ps
CPU time 2.74 seconds
Started Mar 10 01:17:57 PM PDT 24
Finished Mar 10 01:18:00 PM PDT 24
Peak memory 214712 kb
Host smart-d93b73d9-04df-4010-ae31-d2cf7199e360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143004925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
143004925
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1927533488
Short name T2051
Test name
Test status
Simulation time 555562289 ps
CPU time 7.6 seconds
Started Mar 10 01:17:57 PM PDT 24
Finished Mar 10 01:18:04 PM PDT 24
Peak memory 214736 kb
Host smart-362738a6-ecba-47cd-bb89-bcfdcad48415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927533488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1927533488
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2603118274
Short name T179
Test name
Test status
Simulation time 582202209 ps
CPU time 17.33 seconds
Started Mar 10 01:00:36 PM PDT 24
Finished Mar 10 01:00:53 PM PDT 24
Peak memory 214596 kb
Host smart-474f5c72-3106-41bd-8ecd-379273b769f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603118274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2603118274
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1310353039
Short name T2164
Test name
Test status
Simulation time 10726896 ps
CPU time 0.68 seconds
Started Mar 10 01:18:34 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 202476 kb
Host smart-67dbbe7f-ff7b-48b9-902d-a43433949ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310353039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1310353039
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2225628942
Short name T2086
Test name
Test status
Simulation time 15813516 ps
CPU time 0.72 seconds
Started Mar 10 01:01:46 PM PDT 24
Finished Mar 10 01:01:47 PM PDT 24
Peak memory 202500 kb
Host smart-0c358713-da0a-49eb-ad98-a4a92bf4c9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225628942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2225628942
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.142215338
Short name T2188
Test name
Test status
Simulation time 26086741 ps
CPU time 0.75 seconds
Started Mar 10 01:18:32 PM PDT 24
Finished Mar 10 01:18:33 PM PDT 24
Peak memory 202576 kb
Host smart-63c12f4c-0f7d-4b4e-88b7-c834d9b7d473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142215338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.142215338
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.876113048
Short name T2010
Test name
Test status
Simulation time 15596844 ps
CPU time 0.69 seconds
Started Mar 10 01:01:40 PM PDT 24
Finished Mar 10 01:01:40 PM PDT 24
Peak memory 202804 kb
Host smart-3d4ca20b-45d7-4149-952a-a29ebf7b75d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876113048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.876113048
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1031539276
Short name T2114
Test name
Test status
Simulation time 12365188 ps
CPU time 0.7 seconds
Started Mar 10 01:01:38 PM PDT 24
Finished Mar 10 01:01:39 PM PDT 24
Peak memory 202512 kb
Host smart-ea48db1f-5333-47ba-9630-c39209ade8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031539276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1031539276
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2068568021
Short name T2165
Test name
Test status
Simulation time 18451270 ps
CPU time 0.66 seconds
Started Mar 10 01:18:33 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 202528 kb
Host smart-2a718ac9-3667-42ee-ac07-ade64d10f909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068568021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2068568021
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2274971276
Short name T1938
Test name
Test status
Simulation time 59428130 ps
CPU time 0.71 seconds
Started Mar 10 01:18:33 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 202520 kb
Host smart-98a69a51-f853-403a-8c33-65bbe67bbc7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274971276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2274971276
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.511858990
Short name T1978
Test name
Test status
Simulation time 33949255 ps
CPU time 0.72 seconds
Started Mar 10 01:01:47 PM PDT 24
Finished Mar 10 01:01:47 PM PDT 24
Peak memory 202780 kb
Host smart-01d496c9-29ee-4f56-ad06-b03b421f530a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511858990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.511858990
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1219519245
Short name T1954
Test name
Test status
Simulation time 17867238 ps
CPU time 0.75 seconds
Started Mar 10 01:01:45 PM PDT 24
Finished Mar 10 01:01:46 PM PDT 24
Peak memory 202476 kb
Host smart-881a0b84-97a0-4fb1-9c5e-5faec7240f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219519245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1219519245
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.991564927
Short name T2203
Test name
Test status
Simulation time 15335348 ps
CPU time 0.83 seconds
Started Mar 10 01:18:33 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 202580 kb
Host smart-1593963b-1ff9-4eaa-9fbb-738249c9dd75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991564927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.991564927
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2066419760
Short name T2002
Test name
Test status
Simulation time 25109918 ps
CPU time 0.68 seconds
Started Mar 10 01:01:43 PM PDT 24
Finished Mar 10 01:01:45 PM PDT 24
Peak memory 202824 kb
Host smart-dd69955f-cf5a-4ebe-a320-4b3b4d3036a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066419760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2066419760
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3804817345
Short name T1940
Test name
Test status
Simulation time 14686272 ps
CPU time 0.75 seconds
Started Mar 10 01:18:32 PM PDT 24
Finished Mar 10 01:18:33 PM PDT 24
Peak memory 202464 kb
Host smart-a42af0cb-ceb7-46cf-b964-0ac8d2fb6569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804817345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3804817345
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3831915054
Short name T2155
Test name
Test status
Simulation time 83682877 ps
CPU time 0.67 seconds
Started Mar 10 01:01:45 PM PDT 24
Finished Mar 10 01:01:47 PM PDT 24
Peak memory 202496 kb
Host smart-301abc44-c59c-4858-ba39-bb81a93dd6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831915054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3831915054
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.497841362
Short name T2085
Test name
Test status
Simulation time 13920257 ps
CPU time 0.7 seconds
Started Mar 10 01:18:32 PM PDT 24
Finished Mar 10 01:18:33 PM PDT 24
Peak memory 202548 kb
Host smart-5aa0650c-f8a0-4bbe-9f56-59fc133fc651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497841362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.497841362
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3490389035
Short name T2089
Test name
Test status
Simulation time 14194787 ps
CPU time 0.73 seconds
Started Mar 10 01:01:38 PM PDT 24
Finished Mar 10 01:01:39 PM PDT 24
Peak memory 202796 kb
Host smart-ddb12dbd-b350-49f2-88d4-c675ee9e38fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490389035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3490389035
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3596076480
Short name T2207
Test name
Test status
Simulation time 50835534 ps
CPU time 0.78 seconds
Started Mar 10 01:18:34 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 202548 kb
Host smart-fc56ce41-354d-4ac0-9bc3-089ef489179a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596076480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3596076480
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2888499222
Short name T1994
Test name
Test status
Simulation time 58455553 ps
CPU time 0.78 seconds
Started Mar 10 01:01:38 PM PDT 24
Finished Mar 10 01:01:39 PM PDT 24
Peak memory 202864 kb
Host smart-6b59af3b-e8f3-41d3-ac20-42440c3be01a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888499222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2888499222
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3251482856
Short name T1997
Test name
Test status
Simulation time 17054046 ps
CPU time 0.78 seconds
Started Mar 10 01:18:35 PM PDT 24
Finished Mar 10 01:18:36 PM PDT 24
Peak memory 202584 kb
Host smart-18101c14-850e-4db8-9c78-4b6724fba647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251482856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3251482856
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3072780263
Short name T2054
Test name
Test status
Simulation time 41703981 ps
CPU time 0.74 seconds
Started Mar 10 01:01:43 PM PDT 24
Finished Mar 10 01:01:44 PM PDT 24
Peak memory 202808 kb
Host smart-8167800f-023a-4c04-bca4-2ee2038af7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072780263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3072780263
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4237926446
Short name T1941
Test name
Test status
Simulation time 29222865 ps
CPU time 0.73 seconds
Started Mar 10 01:18:34 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 202548 kb
Host smart-604731ab-3caf-4709-83f2-8e4b8f019ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237926446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4237926446
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2140951345
Short name T113
Test name
Test status
Simulation time 397687489 ps
CPU time 8.84 seconds
Started Mar 10 01:18:02 PM PDT 24
Finished Mar 10 01:18:10 PM PDT 24
Peak memory 206400 kb
Host smart-ce4a5827-4561-4654-a08a-bd708dd21776
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140951345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2140951345
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3697633020
Short name T125
Test name
Test status
Simulation time 785898675 ps
CPU time 15.86 seconds
Started Mar 10 01:00:53 PM PDT 24
Finished Mar 10 01:01:09 PM PDT 24
Peak memory 214704 kb
Host smart-05425497-88bd-4b9c-b215-7c9895babaf9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697633020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3697633020
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.348007809
Short name T1996
Test name
Test status
Simulation time 731657515 ps
CPU time 21.43 seconds
Started Mar 10 01:18:02 PM PDT 24
Finished Mar 10 01:18:24 PM PDT 24
Peak memory 206224 kb
Host smart-1c9aa697-c039-4897-a3a8-21c056e165b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348007809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.348007809
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4083065277
Short name T144
Test name
Test status
Simulation time 920445275 ps
CPU time 14.36 seconds
Started Mar 10 01:00:49 PM PDT 24
Finished Mar 10 01:01:03 PM PDT 24
Peak memory 206060 kb
Host smart-cfb05b5c-a93c-494d-a2c5-6a6ef07ea0a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083065277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.4083065277
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1685940054
Short name T83
Test name
Test status
Simulation time 16764489 ps
CPU time 0.98 seconds
Started Mar 10 01:18:07 PM PDT 24
Finished Mar 10 01:18:08 PM PDT 24
Peak memory 205976 kb
Host smart-f335f39a-73f8-4733-9813-21c6d5d2b6e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685940054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1685940054
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.708979039
Short name T2140
Test name
Test status
Simulation time 50940786 ps
CPU time 1.48 seconds
Started Mar 10 01:00:50 PM PDT 24
Finished Mar 10 01:00:51 PM PDT 24
Peak memory 215640 kb
Host smart-660b3bbb-6a8b-47b3-9ed8-b3bcb5d7c94a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708979039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.708979039
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1486857979
Short name T1970
Test name
Test status
Simulation time 637021723 ps
CPU time 4.04 seconds
Started Mar 10 01:00:54 PM PDT 24
Finished Mar 10 01:00:59 PM PDT 24
Peak memory 216192 kb
Host smart-98caea80-8bd6-4dae-ac11-c605d57ac216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486857979 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1486857979
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2956197008
Short name T2032
Test name
Test status
Simulation time 166963787 ps
CPU time 2.92 seconds
Started Mar 10 01:18:00 PM PDT 24
Finished Mar 10 01:18:03 PM PDT 24
Peak memory 215808 kb
Host smart-57f6cf96-e856-4e63-8650-00a39cf92241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956197008 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2956197008
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1476974583
Short name T2195
Test name
Test status
Simulation time 239657108 ps
CPU time 1.95 seconds
Started Mar 10 01:18:04 PM PDT 24
Finished Mar 10 01:18:06 PM PDT 24
Peak memory 206404 kb
Host smart-110c2e88-35dd-4836-a723-aa2b39141533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476974583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
476974583
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1649407479
Short name T2231
Test name
Test status
Simulation time 197634725 ps
CPU time 1.49 seconds
Started Mar 10 01:00:48 PM PDT 24
Finished Mar 10 01:00:50 PM PDT 24
Peak memory 206516 kb
Host smart-99f2ab32-1c40-403d-98a1-792910371b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649407479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
649407479
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2254473397
Short name T2184
Test name
Test status
Simulation time 24039421 ps
CPU time 0.74 seconds
Started Mar 10 01:18:06 PM PDT 24
Finished Mar 10 01:18:07 PM PDT 24
Peak memory 202564 kb
Host smart-9ddc3ef7-49e0-4f69-8df1-4c4dd57f0c49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254473397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
254473397
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2328247293
Short name T1989
Test name
Test status
Simulation time 16844941 ps
CPU time 0.71 seconds
Started Mar 10 01:00:50 PM PDT 24
Finished Mar 10 01:00:51 PM PDT 24
Peak memory 202484 kb
Host smart-2efe03be-6778-47e2-869b-457a96b9cdd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328247293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
328247293
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1167379945
Short name T2101
Test name
Test status
Simulation time 37730674 ps
CPU time 1.4 seconds
Started Mar 10 01:18:04 PM PDT 24
Finished Mar 10 01:18:06 PM PDT 24
Peak memory 214652 kb
Host smart-f98191b4-e39e-4dbc-a4f6-90730daca8f8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167379945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1167379945
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2647654022
Short name T2189
Test name
Test status
Simulation time 27137906 ps
CPU time 2.2 seconds
Started Mar 10 01:00:48 PM PDT 24
Finished Mar 10 01:00:51 PM PDT 24
Peak memory 214620 kb
Host smart-f8f0b6c4-851d-46bd-950c-f99d101011c1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647654022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2647654022
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1554456051
Short name T2024
Test name
Test status
Simulation time 18703720 ps
CPU time 0.65 seconds
Started Mar 10 01:00:48 PM PDT 24
Finished Mar 10 01:00:49 PM PDT 24
Peak memory 202384 kb
Host smart-473ce2ac-e75e-4322-b285-f05ef5df8846
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554456051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1554456051
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1707894881
Short name T2216
Test name
Test status
Simulation time 33171279 ps
CPU time 0.66 seconds
Started Mar 10 01:18:07 PM PDT 24
Finished Mar 10 01:18:08 PM PDT 24
Peak memory 202424 kb
Host smart-634b1be4-e41e-4a30-8b4b-11a748f90d1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707894881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1707894881
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1585251767
Short name T1944
Test name
Test status
Simulation time 43029430 ps
CPU time 2.53 seconds
Started Mar 10 01:17:59 PM PDT 24
Finished Mar 10 01:18:01 PM PDT 24
Peak memory 206572 kb
Host smart-b3097d90-adb4-4b3a-8bc4-4e8382e1e24b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585251767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1585251767
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2559036641
Short name T2145
Test name
Test status
Simulation time 204179873 ps
CPU time 1.85 seconds
Started Mar 10 01:00:54 PM PDT 24
Finished Mar 10 01:00:56 PM PDT 24
Peak memory 206524 kb
Host smart-1c612195-a34d-43fa-ae8f-ac0c3dae6839
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559036641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2559036641
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1470584795
Short name T2132
Test name
Test status
Simulation time 139489882 ps
CPU time 2.2 seconds
Started Mar 10 01:00:42 PM PDT 24
Finished Mar 10 01:00:44 PM PDT 24
Peak memory 214812 kb
Host smart-9fd76e3e-0495-4855-abc1-5d931467a659
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470584795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
470584795
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1471530520
Short name T2119
Test name
Test status
Simulation time 405588418 ps
CPU time 6.29 seconds
Started Mar 10 01:00:44 PM PDT 24
Finished Mar 10 01:00:50 PM PDT 24
Peak memory 214592 kb
Host smart-4fa14de5-cdcb-4c90-b3b1-1ff8784d215a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471530520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1471530520
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3672816345
Short name T177
Test name
Test status
Simulation time 2525205214 ps
CPU time 19.36 seconds
Started Mar 10 01:17:59 PM PDT 24
Finished Mar 10 01:18:18 PM PDT 24
Peak memory 214740 kb
Host smart-387a43b6-c5b6-4d2d-b516-9947a8c0e03c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672816345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3672816345
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1068161837
Short name T2105
Test name
Test status
Simulation time 87937402 ps
CPU time 0.81 seconds
Started Mar 10 01:01:47 PM PDT 24
Finished Mar 10 01:01:48 PM PDT 24
Peak memory 202824 kb
Host smart-5db61e26-7faf-4f75-a155-ad48770d0882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068161837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1068161837
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.138208450
Short name T1943
Test name
Test status
Simulation time 31197342 ps
CPU time 0.75 seconds
Started Mar 10 01:18:33 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 202584 kb
Host smart-b1b78bfb-4536-43e8-ae04-74e8f628e765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138208450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.138208450
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.602193954
Short name T2135
Test name
Test status
Simulation time 13523828 ps
CPU time 0.68 seconds
Started Mar 10 01:18:35 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 202852 kb
Host smart-462380cc-e057-4d58-a983-1b09864d7923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602193954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.602193954
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.640484822
Short name T2191
Test name
Test status
Simulation time 32898257 ps
CPU time 0.8 seconds
Started Mar 10 01:01:41 PM PDT 24
Finished Mar 10 01:01:42 PM PDT 24
Peak memory 202568 kb
Host smart-a8c46587-7671-44ce-a4d7-2f53fc05e37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640484822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.640484822
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.375297112
Short name T1958
Test name
Test status
Simulation time 52329020 ps
CPU time 0.77 seconds
Started Mar 10 01:01:42 PM PDT 24
Finished Mar 10 01:01:43 PM PDT 24
Peak memory 202580 kb
Host smart-d0ec07ae-ce85-4058-9c54-adc527133370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375297112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.375297112
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4221444505
Short name T1973
Test name
Test status
Simulation time 16548403 ps
CPU time 0.67 seconds
Started Mar 10 01:18:31 PM PDT 24
Finished Mar 10 01:18:32 PM PDT 24
Peak memory 202476 kb
Host smart-cb7575f0-0969-4ceb-b218-34caf045b2e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221444505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4221444505
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3086876488
Short name T1960
Test name
Test status
Simulation time 41000811 ps
CPU time 0.69 seconds
Started Mar 10 01:18:34 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 202544 kb
Host smart-ee9c8d16-78bf-4595-a67b-4e6ee26e4549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086876488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3086876488
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.532055515
Short name T2221
Test name
Test status
Simulation time 43683969 ps
CPU time 0.75 seconds
Started Mar 10 01:01:47 PM PDT 24
Finished Mar 10 01:01:48 PM PDT 24
Peak memory 202544 kb
Host smart-49573349-a3ed-4f15-9069-36e969eda72d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532055515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.532055515
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1462463271
Short name T1937
Test name
Test status
Simulation time 39071476 ps
CPU time 0.74 seconds
Started Mar 10 01:01:43 PM PDT 24
Finished Mar 10 01:01:43 PM PDT 24
Peak memory 202544 kb
Host smart-c3da29e8-76cc-4aa6-9e92-079b09723f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462463271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1462463271
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.606358172
Short name T1986
Test name
Test status
Simulation time 135160442 ps
CPU time 0.76 seconds
Started Mar 10 01:18:34 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 202864 kb
Host smart-2114df5e-d6e6-4d62-9226-7de9103feb49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606358172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.606358172
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1432785363
Short name T2047
Test name
Test status
Simulation time 66361121 ps
CPU time 0.75 seconds
Started Mar 10 01:01:47 PM PDT 24
Finished Mar 10 01:01:48 PM PDT 24
Peak memory 202540 kb
Host smart-c26d2845-5352-437e-b2f9-a3625064fe95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432785363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1432785363
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1476370065
Short name T1956
Test name
Test status
Simulation time 12294768 ps
CPU time 0.74 seconds
Started Mar 10 01:18:33 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 202596 kb
Host smart-372dd1a1-ed23-42dd-b1bc-0026cdf3015d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476370065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1476370065
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1358788907
Short name T2080
Test name
Test status
Simulation time 48903361 ps
CPU time 0.73 seconds
Started Mar 10 01:01:44 PM PDT 24
Finished Mar 10 01:01:45 PM PDT 24
Peak memory 202832 kb
Host smart-2e197528-d117-41b2-8d69-64dbaa73e611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358788907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1358788907
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2052207464
Short name T2133
Test name
Test status
Simulation time 38630474 ps
CPU time 0.79 seconds
Started Mar 10 01:18:33 PM PDT 24
Finished Mar 10 01:18:34 PM PDT 24
Peak memory 202548 kb
Host smart-c4d08d14-c8e7-45d6-8985-93c96e80749a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052207464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2052207464
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2238921047
Short name T2201
Test name
Test status
Simulation time 49375726 ps
CPU time 0.74 seconds
Started Mar 10 01:01:44 PM PDT 24
Finished Mar 10 01:01:45 PM PDT 24
Peak memory 202828 kb
Host smart-d8c47c7f-e269-4f61-b833-c5ea2a5af7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238921047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2238921047
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.40277483
Short name T2087
Test name
Test status
Simulation time 36167610 ps
CPU time 0.71 seconds
Started Mar 10 01:18:34 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 202868 kb
Host smart-8142626b-eb65-4ced-9ba2-f181dcac612b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40277483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.40277483
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2022574128
Short name T2124
Test name
Test status
Simulation time 43160588 ps
CPU time 0.69 seconds
Started Mar 10 01:01:42 PM PDT 24
Finished Mar 10 01:01:43 PM PDT 24
Peak memory 202328 kb
Host smart-f0035ab9-0a50-439e-b4a1-84e386f840d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022574128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2022574128
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.94721657
Short name T2097
Test name
Test status
Simulation time 43261857 ps
CPU time 0.73 seconds
Started Mar 10 01:18:38 PM PDT 24
Finished Mar 10 01:18:39 PM PDT 24
Peak memory 202456 kb
Host smart-8229b933-a22f-4cce-991b-c14c475c3795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94721657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.94721657
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2645638829
Short name T2061
Test name
Test status
Simulation time 46756670 ps
CPU time 0.7 seconds
Started Mar 10 01:01:44 PM PDT 24
Finished Mar 10 01:01:45 PM PDT 24
Peak memory 202816 kb
Host smart-4bb91a03-4e6d-4b2b-8431-7394b09df2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645638829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2645638829
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4275181079
Short name T1992
Test name
Test status
Simulation time 12077814 ps
CPU time 0.69 seconds
Started Mar 10 01:18:39 PM PDT 24
Finished Mar 10 01:18:40 PM PDT 24
Peak memory 202528 kb
Host smart-ad1e05c3-9dd1-41ea-9c7a-124fb1d4579e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275181079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4275181079
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4074311416
Short name T2073
Test name
Test status
Simulation time 22910118 ps
CPU time 1.75 seconds
Started Mar 10 01:18:00 PM PDT 24
Finished Mar 10 01:18:02 PM PDT 24
Peak memory 214780 kb
Host smart-85fc4f3f-2b61-452c-a292-3004c2217e82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074311416 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4074311416
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.527465279
Short name T1980
Test name
Test status
Simulation time 542404377 ps
CPU time 3.49 seconds
Started Mar 10 01:00:54 PM PDT 24
Finished Mar 10 01:00:58 PM PDT 24
Peak memory 217216 kb
Host smart-02a8d320-7dde-4970-947d-b0111f1c9290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527465279 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.527465279
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2585003732
Short name T2056
Test name
Test status
Simulation time 33814175 ps
CPU time 1.21 seconds
Started Mar 10 01:00:56 PM PDT 24
Finished Mar 10 01:00:57 PM PDT 24
Peak memory 214620 kb
Host smart-f064015a-f38c-472f-979e-ca8e4f2e2751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585003732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
585003732
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.753717112
Short name T2159
Test name
Test status
Simulation time 157537271 ps
CPU time 2.08 seconds
Started Mar 10 01:18:07 PM PDT 24
Finished Mar 10 01:18:09 PM PDT 24
Peak memory 214760 kb
Host smart-92844ec6-9b9f-4e7b-9276-f06e5e04e347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753717112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.753717112
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2450570564
Short name T2050
Test name
Test status
Simulation time 89406635 ps
CPU time 0.7 seconds
Started Mar 10 01:17:58 PM PDT 24
Finished Mar 10 01:17:59 PM PDT 24
Peak memory 202488 kb
Host smart-cf234c31-6fff-4f1c-b464-b474aa9b0bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450570564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
450570564
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3357899861
Short name T1948
Test name
Test status
Simulation time 14118764 ps
CPU time 0.75 seconds
Started Mar 10 01:00:54 PM PDT 24
Finished Mar 10 01:00:55 PM PDT 24
Peak memory 202556 kb
Host smart-aa087769-45dd-4491-a5b8-8e05258cfcb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357899861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
357899861
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1736222281
Short name T1967
Test name
Test status
Simulation time 161959978 ps
CPU time 3.02 seconds
Started Mar 10 01:00:53 PM PDT 24
Finished Mar 10 01:00:56 PM PDT 24
Peak memory 206424 kb
Host smart-2307ddf6-9ee9-4b84-8131-df3e29fcfa82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736222281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1736222281
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2483514914
Short name T147
Test name
Test status
Simulation time 201777244 ps
CPU time 4.39 seconds
Started Mar 10 01:18:00 PM PDT 24
Finished Mar 10 01:18:04 PM PDT 24
Peak memory 214704 kb
Host smart-529a9171-0f8c-4d84-a11a-1c3e8977067a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483514914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2483514914
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4251371691
Short name T2003
Test name
Test status
Simulation time 340263912 ps
CPU time 5.07 seconds
Started Mar 10 01:18:01 PM PDT 24
Finished Mar 10 01:18:06 PM PDT 24
Peak memory 215744 kb
Host smart-d554170f-25d8-449b-bc45-51fb89f226e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251371691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
251371691
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.692355278
Short name T92
Test name
Test status
Simulation time 36880211 ps
CPU time 2.6 seconds
Started Mar 10 01:00:53 PM PDT 24
Finished Mar 10 01:00:56 PM PDT 24
Peak memory 206572 kb
Host smart-83391913-c623-41b6-899b-090f06823294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692355278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.692355278
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2329052304
Short name T2229
Test name
Test status
Simulation time 201769826 ps
CPU time 12.51 seconds
Started Mar 10 01:18:00 PM PDT 24
Finished Mar 10 01:18:13 PM PDT 24
Peak memory 214700 kb
Host smart-c6209c6a-72be-43f7-a9ca-5684cb6d9d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329052304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2329052304
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3706704134
Short name T2173
Test name
Test status
Simulation time 41556920 ps
CPU time 2.67 seconds
Started Mar 10 01:18:09 PM PDT 24
Finished Mar 10 01:18:11 PM PDT 24
Peak memory 215800 kb
Host smart-75f61263-dc18-4f10-bff5-97d758af70c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706704134 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3706704134
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.402680768
Short name T2154
Test name
Test status
Simulation time 237731275 ps
CPU time 3.49 seconds
Started Mar 10 01:01:00 PM PDT 24
Finished Mar 10 01:01:04 PM PDT 24
Peak memory 215828 kb
Host smart-bf8cc030-d12a-4f5a-ba7d-52c950a8406f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402680768 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.402680768
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1436906621
Short name T2126
Test name
Test status
Simulation time 43247272 ps
CPU time 1.52 seconds
Started Mar 10 01:18:05 PM PDT 24
Finished Mar 10 01:18:06 PM PDT 24
Peak memory 214704 kb
Host smart-408f481f-695a-423e-bdaf-b379b18a5174
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436906621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
436906621
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4064221860
Short name T2091
Test name
Test status
Simulation time 227178347 ps
CPU time 1.69 seconds
Started Mar 10 01:01:00 PM PDT 24
Finished Mar 10 01:01:02 PM PDT 24
Peak memory 214652 kb
Host smart-8bacc89a-7ba3-4141-9b64-cbb5ba01c4f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064221860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
064221860
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1144817764
Short name T2062
Test name
Test status
Simulation time 15335245 ps
CPU time 0.74 seconds
Started Mar 10 01:18:04 PM PDT 24
Finished Mar 10 01:18:05 PM PDT 24
Peak memory 202556 kb
Host smart-dccced88-5d70-4540-85e8-e598216d1ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144817764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
144817764
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3413816944
Short name T2016
Test name
Test status
Simulation time 36296880 ps
CPU time 0.68 seconds
Started Mar 10 01:00:59 PM PDT 24
Finished Mar 10 01:01:00 PM PDT 24
Peak memory 202480 kb
Host smart-814564c0-93d8-4382-929e-4d2f3ab9315f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413816944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
413816944
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1541985971
Short name T2192
Test name
Test status
Simulation time 75775728 ps
CPU time 1.73 seconds
Started Mar 10 01:18:05 PM PDT 24
Finished Mar 10 01:18:07 PM PDT 24
Peak memory 206448 kb
Host smart-7f0771f8-7b98-4904-978d-d067ffd97f23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541985971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1541985971
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2942364071
Short name T1982
Test name
Test status
Simulation time 67952716 ps
CPU time 1.84 seconds
Started Mar 10 01:01:02 PM PDT 24
Finished Mar 10 01:01:04 PM PDT 24
Peak memory 214736 kb
Host smart-e78b17a9-dc00-4ffe-8203-c5e4feaf6ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942364071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2942364071
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2456909910
Short name T2112
Test name
Test status
Simulation time 248937954 ps
CPU time 2.08 seconds
Started Mar 10 01:18:00 PM PDT 24
Finished Mar 10 01:18:03 PM PDT 24
Peak memory 214828 kb
Host smart-fd9f8da3-8837-4096-9756-612e6699ea02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456909910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
456909910
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.847319149
Short name T2027
Test name
Test status
Simulation time 213684195 ps
CPU time 1.87 seconds
Started Mar 10 01:01:03 PM PDT 24
Finished Mar 10 01:01:06 PM PDT 24
Peak memory 206520 kb
Host smart-5131982b-f052-4132-8a2a-f3ad260f5d65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847319149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.847319149
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3186718374
Short name T2098
Test name
Test status
Simulation time 1095925291 ps
CPU time 15.8 seconds
Started Mar 10 01:18:09 PM PDT 24
Finished Mar 10 01:18:25 PM PDT 24
Peak memory 214700 kb
Host smart-d7ca51d6-d0b8-4a22-ac35-ba4ef9f8ed14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186718374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3186718374
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3385885782
Short name T98
Test name
Test status
Simulation time 2718618323 ps
CPU time 15.86 seconds
Started Mar 10 01:01:02 PM PDT 24
Finished Mar 10 01:01:19 PM PDT 24
Peak memory 214696 kb
Host smart-716e90a6-4a0d-4e88-bb7f-2119e9331971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385885782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3385885782
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1892407229
Short name T2025
Test name
Test status
Simulation time 511209992 ps
CPU time 3.54 seconds
Started Mar 10 01:01:09 PM PDT 24
Finished Mar 10 01:01:14 PM PDT 24
Peak memory 215968 kb
Host smart-14cfefe1-ed27-4aad-bec0-da930e6de896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892407229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1892407229
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1735383447
Short name T2063
Test name
Test status
Simulation time 74526151 ps
CPU time 1.82 seconds
Started Mar 10 01:18:05 PM PDT 24
Finished Mar 10 01:18:07 PM PDT 24
Peak memory 206344 kb
Host smart-e1fd22c6-aab0-4760-ad5f-2f2e9328bed3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735383447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
735383447
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3295724554
Short name T116
Test name
Test status
Simulation time 126820390 ps
CPU time 2.39 seconds
Started Mar 10 01:01:06 PM PDT 24
Finished Mar 10 01:01:09 PM PDT 24
Peak memory 214680 kb
Host smart-51d54133-cfd1-432a-8096-8f7a2df2218f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295724554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
295724554
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3763497400
Short name T2142
Test name
Test status
Simulation time 11797372 ps
CPU time 0.75 seconds
Started Mar 10 01:18:06 PM PDT 24
Finished Mar 10 01:18:07 PM PDT 24
Peak memory 202876 kb
Host smart-2e662f00-9421-45bc-8e69-3c2cf8cdcb54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763497400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
763497400
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.862953287
Short name T2194
Test name
Test status
Simulation time 26923827 ps
CPU time 0.74 seconds
Started Mar 10 01:01:06 PM PDT 24
Finished Mar 10 01:01:07 PM PDT 24
Peak memory 202500 kb
Host smart-5eb82efd-e7d4-44ce-b2f8-b27734c4f79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862953287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.862953287
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1955478718
Short name T1953
Test name
Test status
Simulation time 37848279 ps
CPU time 1.65 seconds
Started Mar 10 01:18:04 PM PDT 24
Finished Mar 10 01:18:06 PM PDT 24
Peak memory 206396 kb
Host smart-32d41103-22b2-4133-870c-c7a11803a838
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955478718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1955478718
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3600636011
Short name T1963
Test name
Test status
Simulation time 154497376 ps
CPU time 1.74 seconds
Started Mar 10 01:01:06 PM PDT 24
Finished Mar 10 01:01:08 PM PDT 24
Peak memory 214572 kb
Host smart-5026a243-3fd3-4da8-8f1e-79ed161f322f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600636011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3600636011
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.21418295
Short name T2113
Test name
Test status
Simulation time 44526115 ps
CPU time 1.57 seconds
Started Mar 10 01:01:02 PM PDT 24
Finished Mar 10 01:01:04 PM PDT 24
Peak memory 214720 kb
Host smart-4439a5ed-e4e4-4c4a-be5e-432702314fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21418295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.21418295
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3849288104
Short name T2013
Test name
Test status
Simulation time 207609717 ps
CPU time 2.32 seconds
Started Mar 10 01:18:06 PM PDT 24
Finished Mar 10 01:18:09 PM PDT 24
Peak memory 214724 kb
Host smart-6fe64a70-4fa9-436d-a194-a1b31b9dc842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849288104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
849288104
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1489520408
Short name T2078
Test name
Test status
Simulation time 1422013484 ps
CPU time 15.59 seconds
Started Mar 10 01:18:04 PM PDT 24
Finished Mar 10 01:18:20 PM PDT 24
Peak memory 214696 kb
Host smart-d4515cfe-866b-4696-8005-8a2ecb5b31f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489520408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1489520408
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2085537149
Short name T2134
Test name
Test status
Simulation time 1213085888 ps
CPU time 7.25 seconds
Started Mar 10 01:01:07 PM PDT 24
Finished Mar 10 01:01:15 PM PDT 24
Peak memory 214700 kb
Host smart-035407cb-16b9-41ab-8101-7c84ed33badc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085537149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2085537149
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1643356596
Short name T112
Test name
Test status
Simulation time 220031512 ps
CPU time 1.83 seconds
Started Mar 10 01:18:12 PM PDT 24
Finished Mar 10 01:18:14 PM PDT 24
Peak memory 214792 kb
Host smart-cb6f01e6-0f4e-4a8b-8464-6a1c5eeebc78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643356596 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1643356596
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2303149443
Short name T2199
Test name
Test status
Simulation time 482828753 ps
CPU time 3.65 seconds
Started Mar 10 01:01:09 PM PDT 24
Finished Mar 10 01:01:14 PM PDT 24
Peak memory 216160 kb
Host smart-7973cbd3-4d44-423e-bfac-11f925022c0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303149443 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2303149443
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1361617349
Short name T120
Test name
Test status
Simulation time 20679989 ps
CPU time 1.31 seconds
Started Mar 10 01:18:08 PM PDT 24
Finished Mar 10 01:18:10 PM PDT 24
Peak memory 206448 kb
Host smart-5accc3bb-dee9-4b26-ada0-75859e37ce9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361617349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
361617349
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4293388883
Short name T122
Test name
Test status
Simulation time 38692818 ps
CPU time 2.43 seconds
Started Mar 10 01:01:05 PM PDT 24
Finished Mar 10 01:01:08 PM PDT 24
Peak memory 206660 kb
Host smart-fc8ce7f3-de14-47aa-84b0-ae6af40b2ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293388883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
293388883
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.163300797
Short name T1998
Test name
Test status
Simulation time 40377976 ps
CPU time 0.73 seconds
Started Mar 10 01:01:09 PM PDT 24
Finished Mar 10 01:01:11 PM PDT 24
Peak memory 202800 kb
Host smart-7414c20d-e993-41e7-b772-a04b405b9834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163300797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.163300797
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.450129931
Short name T2059
Test name
Test status
Simulation time 32230415 ps
CPU time 0.74 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:15 PM PDT 24
Peak memory 202828 kb
Host smart-930b8ed2-8817-4b18-88ce-6748f312ae98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450129931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.450129931
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1660751682
Short name T2208
Test name
Test status
Simulation time 523214949 ps
CPU time 1.77 seconds
Started Mar 10 01:01:05 PM PDT 24
Finished Mar 10 01:01:08 PM PDT 24
Peak memory 206268 kb
Host smart-aac6056f-0e6a-440f-8a7a-1e2fef590848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660751682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1660751682
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2803952235
Short name T148
Test name
Test status
Simulation time 302821546 ps
CPU time 2.02 seconds
Started Mar 10 01:18:11 PM PDT 24
Finished Mar 10 01:18:13 PM PDT 24
Peak memory 206552 kb
Host smart-12fd8cb4-57e7-41c5-9b3d-c64e36160f3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803952235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2803952235
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1712672171
Short name T1975
Test name
Test status
Simulation time 1129236399 ps
CPU time 5.11 seconds
Started Mar 10 01:18:09 PM PDT 24
Finished Mar 10 01:18:14 PM PDT 24
Peak memory 215844 kb
Host smart-36170e57-d783-42f1-8eeb-b693d7547ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712672171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
712672171
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1963511502
Short name T2174
Test name
Test status
Simulation time 342485194 ps
CPU time 4.11 seconds
Started Mar 10 01:01:05 PM PDT 24
Finished Mar 10 01:01:10 PM PDT 24
Peak memory 214920 kb
Host smart-bb118e75-ddcd-438c-b8d3-86480ee689fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963511502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
963511502
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1588560148
Short name T2053
Test name
Test status
Simulation time 300885569 ps
CPU time 7.67 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:22 PM PDT 24
Peak memory 214684 kb
Host smart-c32037bc-d5a4-43b0-abc7-244a34785cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588560148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1588560148
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2433582869
Short name T2219
Test name
Test status
Simulation time 1014421241 ps
CPU time 7.04 seconds
Started Mar 10 01:01:08 PM PDT 24
Finished Mar 10 01:01:16 PM PDT 24
Peak memory 214688 kb
Host smart-b3cfc1b2-7802-4d61-9e7b-690a2c5484b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433582869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2433582869
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2188208611
Short name T109
Test name
Test status
Simulation time 39644143 ps
CPU time 2.63 seconds
Started Mar 10 01:18:09 PM PDT 24
Finished Mar 10 01:18:12 PM PDT 24
Peak memory 214768 kb
Host smart-db02531e-5ca5-4061-8c3c-49234d4386b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188208611 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2188208611
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.562454410
Short name T1972
Test name
Test status
Simulation time 175009312 ps
CPU time 1.75 seconds
Started Mar 10 01:01:09 PM PDT 24
Finished Mar 10 01:01:12 PM PDT 24
Peak memory 214776 kb
Host smart-6480ef5d-e418-494a-b141-edf76d2830df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562454410 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.562454410
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.274852622
Short name T2183
Test name
Test status
Simulation time 114927832 ps
CPU time 1.65 seconds
Started Mar 10 01:18:10 PM PDT 24
Finished Mar 10 01:18:11 PM PDT 24
Peak memory 214744 kb
Host smart-4e2dedbc-c070-4e03-bdc3-b4a84c8cd8a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274852622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.274852622
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3909782778
Short name T1951
Test name
Test status
Simulation time 73693415 ps
CPU time 1.4 seconds
Started Mar 10 01:01:05 PM PDT 24
Finished Mar 10 01:01:07 PM PDT 24
Peak memory 206492 kb
Host smart-fe2275c4-4654-4d05-a133-9cbe3fdb26bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909782778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
909782778
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3010507925
Short name T2034
Test name
Test status
Simulation time 23728836 ps
CPU time 0.75 seconds
Started Mar 10 01:01:06 PM PDT 24
Finished Mar 10 01:01:07 PM PDT 24
Peak memory 202540 kb
Host smart-258871bf-65a3-4f72-b7ac-2da47bcacb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010507925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
010507925
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3729881246
Short name T2021
Test name
Test status
Simulation time 16602656 ps
CPU time 0.71 seconds
Started Mar 10 01:18:10 PM PDT 24
Finished Mar 10 01:18:10 PM PDT 24
Peak memory 202376 kb
Host smart-7213c69b-8bb4-4df1-9cf5-508b47f3a9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729881246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
729881246
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2561446953
Short name T2170
Test name
Test status
Simulation time 229502528 ps
CPU time 3.81 seconds
Started Mar 10 01:01:06 PM PDT 24
Finished Mar 10 01:01:10 PM PDT 24
Peak memory 214384 kb
Host smart-4424702f-eb49-4b73-8372-fc42f801d7fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561446953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2561446953
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2715843802
Short name T1961
Test name
Test status
Simulation time 322225728 ps
CPU time 4.22 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:19 PM PDT 24
Peak memory 214684 kb
Host smart-b40e4849-737e-4d30-a34f-a35eedcd3c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715843802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2715843802
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2289511307
Short name T2212
Test name
Test status
Simulation time 272101901 ps
CPU time 3.39 seconds
Started Mar 10 01:01:06 PM PDT 24
Finished Mar 10 01:01:10 PM PDT 24
Peak memory 214928 kb
Host smart-a559d2d9-0fa4-4075-8987-ae7e0fe6e7db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289511307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
289511307
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.354566713
Short name T2121
Test name
Test status
Simulation time 85730261 ps
CPU time 4.08 seconds
Started Mar 10 01:18:14 PM PDT 24
Finished Mar 10 01:18:18 PM PDT 24
Peak memory 214832 kb
Host smart-f21fa851-5c49-4513-9abb-8702451b1f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354566713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.354566713
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2271352649
Short name T175
Test name
Test status
Simulation time 1156348477 ps
CPU time 13.99 seconds
Started Mar 10 01:18:11 PM PDT 24
Finished Mar 10 01:18:25 PM PDT 24
Peak memory 214712 kb
Host smart-13fef0a2-f59d-4228-be64-c603e20b088d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271352649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2271352649
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1818692392
Short name T1097
Test name
Test status
Simulation time 23911825 ps
CPU time 0.73 seconds
Started Mar 10 02:46:09 PM PDT 24
Finished Mar 10 02:46:10 PM PDT 24
Peak memory 204756 kb
Host smart-52e5be9d-fad8-46fd-bc76-ad82a7f13c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818692392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
818692392
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3330310167
Short name T778
Test name
Test status
Simulation time 52805044 ps
CPU time 0.77 seconds
Started Mar 10 01:48:49 PM PDT 24
Finished Mar 10 01:48:50 PM PDT 24
Peak memory 203808 kb
Host smart-1cccca30-1cd5-4928-9c3f-d98805a4f68f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330310167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
330310167
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2060782487
Short name T321
Test name
Test status
Simulation time 208421338 ps
CPU time 2.93 seconds
Started Mar 10 01:48:47 PM PDT 24
Finished Mar 10 01:48:51 PM PDT 24
Peak memory 218208 kb
Host smart-7896c747-aeb9-49d5-953d-3566eb9cfbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060782487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2060782487
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3117605460
Short name T521
Test name
Test status
Simulation time 350909956 ps
CPU time 3.77 seconds
Started Mar 10 02:46:02 PM PDT 24
Finished Mar 10 02:46:06 PM PDT 24
Peak memory 232920 kb
Host smart-be54c07f-2c5f-4132-91b8-6fbbbdb73c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117605460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3117605460
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2138708111
Short name T578
Test name
Test status
Simulation time 12234565 ps
CPU time 0.72 seconds
Started Mar 10 01:48:43 PM PDT 24
Finished Mar 10 01:48:44 PM PDT 24
Peak memory 204800 kb
Host smart-094d1ee0-f82b-47b2-b1b5-9b51a20b9bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138708111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2138708111
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.566326007
Short name T954
Test name
Test status
Simulation time 51479914 ps
CPU time 0.78 seconds
Started Mar 10 02:46:05 PM PDT 24
Finished Mar 10 02:46:05 PM PDT 24
Peak memory 204512 kb
Host smart-ce469897-ded5-4aec-963a-f0c49b11cf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566326007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.566326007
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1522354687
Short name T1035
Test name
Test status
Simulation time 17307376752 ps
CPU time 22.41 seconds
Started Mar 10 02:46:06 PM PDT 24
Finished Mar 10 02:46:29 PM PDT 24
Peak memory 233128 kb
Host smart-a5a1e159-c0d0-4765-9fbb-1bb97cfaeea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522354687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1522354687
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2812811837
Short name T1933
Test name
Test status
Simulation time 310794960571 ps
CPU time 362.53 seconds
Started Mar 10 01:48:44 PM PDT 24
Finished Mar 10 01:54:46 PM PDT 24
Peak memory 255968 kb
Host smart-474fa53c-508d-4df2-ab5c-2f07cf98dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812811837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2812811837
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1038567741
Short name T1045
Test name
Test status
Simulation time 47838266866 ps
CPU time 44.28 seconds
Started Mar 10 01:48:47 PM PDT 24
Finished Mar 10 01:49:31 PM PDT 24
Peak memory 233652 kb
Host smart-55083bf2-5f5b-4234-8435-11641c897a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038567741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1038567741
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3363060967
Short name T1210
Test name
Test status
Simulation time 132688780311 ps
CPU time 377.96 seconds
Started Mar 10 02:46:01 PM PDT 24
Finished Mar 10 02:52:20 PM PDT 24
Peak memory 255528 kb
Host smart-0d9e12d3-d64c-4360-89d5-cac1d9f7e063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363060967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3363060967
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1866191905
Short name T1558
Test name
Test status
Simulation time 21308928816 ps
CPU time 153.84 seconds
Started Mar 10 01:48:54 PM PDT 24
Finished Mar 10 01:51:28 PM PDT 24
Peak memory 255820 kb
Host smart-7f1972e4-f7bb-42bb-acc6-fd1f5e0531a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866191905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1866191905
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2646827418
Short name T1580
Test name
Test status
Simulation time 1900158859 ps
CPU time 34.28 seconds
Started Mar 10 02:46:05 PM PDT 24
Finished Mar 10 02:46:40 PM PDT 24
Peak memory 237160 kb
Host smart-130901e0-4e30-493c-ba0f-0ed76384f3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646827418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2646827418
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2729719130
Short name T804
Test name
Test status
Simulation time 5585352899 ps
CPU time 16.82 seconds
Started Mar 10 02:46:06 PM PDT 24
Finished Mar 10 02:46:23 PM PDT 24
Peak memory 232188 kb
Host smart-c6818eaf-7f53-4c5a-8f12-5688b184fff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729719130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2729719130
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2244266374
Short name T1840
Test name
Test status
Simulation time 126410922 ps
CPU time 3.46 seconds
Started Mar 10 01:48:47 PM PDT 24
Finished Mar 10 01:48:51 PM PDT 24
Peak memory 232868 kb
Host smart-a16429d8-daf3-4a93-98ce-d4431165fa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244266374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2244266374
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2812436787
Short name T232
Test name
Test status
Simulation time 328755755 ps
CPU time 2.77 seconds
Started Mar 10 02:46:03 PM PDT 24
Finished Mar 10 02:46:06 PM PDT 24
Peak memory 216268 kb
Host smart-aaceda5b-758e-49c8-88d7-d2d4c770112b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812436787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2812436787
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.234031181
Short name T513
Test name
Test status
Simulation time 872725976 ps
CPU time 6.01 seconds
Started Mar 10 02:46:01 PM PDT 24
Finished Mar 10 02:46:07 PM PDT 24
Peak memory 219752 kb
Host smart-d2db7d6b-fff6-49e4-81f1-7e0ec8856028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234031181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.234031181
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4110203501
Short name T197
Test name
Test status
Simulation time 25103475758 ps
CPU time 25.92 seconds
Started Mar 10 01:48:48 PM PDT 24
Finished Mar 10 01:49:14 PM PDT 24
Peak memory 237372 kb
Host smart-ae37528a-b5db-48cf-b36d-cb35ae14aae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110203501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4110203501
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2874916312
Short name T932
Test name
Test status
Simulation time 16677780 ps
CPU time 1.12 seconds
Started Mar 10 01:48:47 PM PDT 24
Finished Mar 10 01:48:48 PM PDT 24
Peak memory 216076 kb
Host smart-188dd446-6c36-4cce-98da-fe019280af61
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874916312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2874916312
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3517261968
Short name T1281
Test name
Test status
Simulation time 141331534 ps
CPU time 1.06 seconds
Started Mar 10 02:46:04 PM PDT 24
Finished Mar 10 02:46:05 PM PDT 24
Peak memory 216088 kb
Host smart-d38b454f-688a-4212-84bb-d9d5f582528e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517261968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3517261968
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4216129210
Short name T241
Test name
Test status
Simulation time 3805694155 ps
CPU time 11.02 seconds
Started Mar 10 01:48:47 PM PDT 24
Finished Mar 10 01:48:58 PM PDT 24
Peak memory 216248 kb
Host smart-051dc30e-4557-4793-ac5c-d6be511e3f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216129210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4216129210
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.650308661
Short name T1797
Test name
Test status
Simulation time 13420520351 ps
CPU time 11.66 seconds
Started Mar 10 02:46:08 PM PDT 24
Finished Mar 10 02:46:19 PM PDT 24
Peak memory 226056 kb
Host smart-b6d68364-fd55-4998-9a66-a883efe4b4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650308661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
650308661
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.292475915
Short name T1429
Test name
Test status
Simulation time 10335469864 ps
CPU time 10.69 seconds
Started Mar 10 01:48:48 PM PDT 24
Finished Mar 10 01:48:59 PM PDT 24
Peak memory 232872 kb
Host smart-eb8f55a0-888e-45dd-9637-5c4fc336f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292475915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.292475915
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3692853471
Short name T725
Test name
Test status
Simulation time 4020248550 ps
CPU time 13.72 seconds
Started Mar 10 02:46:03 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 232860 kb
Host smart-a65b97ee-493a-42de-b2dd-e0af6e7b40e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692853471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3692853471
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3456107679
Short name T1700
Test name
Test status
Simulation time 26689768 ps
CPU time 0.8 seconds
Started Mar 10 01:48:46 PM PDT 24
Finished Mar 10 01:48:46 PM PDT 24
Peak memory 215620 kb
Host smart-32aa2400-e749-459a-9592-a2011db4654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456107679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3456107679
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.705124453
Short name T775
Test name
Test status
Simulation time 35598076 ps
CPU time 0.76 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:08 PM PDT 24
Peak memory 215484 kb
Host smart-ca436561-1dcb-48d0-aecf-c93cbab8668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705124453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.705124453
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2304351081
Short name T1714
Test name
Test status
Simulation time 6090870786 ps
CPU time 5.97 seconds
Started Mar 10 02:46:02 PM PDT 24
Finished Mar 10 02:46:08 PM PDT 24
Peak memory 216728 kb
Host smart-8281fe4b-36e9-4d6d-9da6-2aadc2c763dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2304351081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2304351081
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2410856679
Short name T680
Test name
Test status
Simulation time 238152993 ps
CPU time 3.51 seconds
Started Mar 10 01:48:47 PM PDT 24
Finished Mar 10 01:48:51 PM PDT 24
Peak memory 219248 kb
Host smart-15161e57-3d58-4e08-8bcd-b545844cbfe7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2410856679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2410856679
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.823438697
Short name T68
Test name
Test status
Simulation time 318803961 ps
CPU time 1.13 seconds
Started Mar 10 01:48:53 PM PDT 24
Finished Mar 10 01:48:54 PM PDT 24
Peak memory 235076 kb
Host smart-d168ad02-7e51-48c1-be74-ebbd9d2c8a1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823438697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.823438697
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1503785516
Short name T1475
Test name
Test status
Simulation time 76095772866 ps
CPU time 288.08 seconds
Started Mar 10 01:48:52 PM PDT 24
Finished Mar 10 01:53:40 PM PDT 24
Peak memory 265616 kb
Host smart-8ed75905-6a56-41f3-811b-b90870c78c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503785516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1503785516
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2511100982
Short name T1527
Test name
Test status
Simulation time 167251391501 ps
CPU time 232.75 seconds
Started Mar 10 02:46:06 PM PDT 24
Finished Mar 10 02:49:59 PM PDT 24
Peak memory 252888 kb
Host smart-53717aaa-a39b-472b-8951-83e740e156ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511100982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2511100982
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1680852517
Short name T315
Test name
Test status
Simulation time 6468658373 ps
CPU time 16.41 seconds
Started Mar 10 02:46:04 PM PDT 24
Finished Mar 10 02:46:21 PM PDT 24
Peak memory 215848 kb
Host smart-c191bc54-a713-4dc8-b59d-d1b0c7fd5507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680852517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1680852517
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3697139753
Short name T1582
Test name
Test status
Simulation time 2329769033 ps
CPU time 7.26 seconds
Started Mar 10 01:48:45 PM PDT 24
Finished Mar 10 01:48:53 PM PDT 24
Peak memory 217508 kb
Host smart-9b7b8a02-f529-48a4-bca8-908cba854b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697139753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3697139753
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.54499516
Short name T323
Test name
Test status
Simulation time 5448912732 ps
CPU time 15.22 seconds
Started Mar 10 02:46:01 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 215768 kb
Host smart-528b6205-6294-4fb4-8021-0ec06314ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54499516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.54499516
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.878192553
Short name T1244
Test name
Test status
Simulation time 2405512422 ps
CPU time 10.78 seconds
Started Mar 10 01:48:45 PM PDT 24
Finished Mar 10 01:48:56 PM PDT 24
Peak memory 215828 kb
Host smart-8a668dee-32cb-40e8-8199-a3447f119871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878192553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.878192553
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2246766974
Short name T1181
Test name
Test status
Simulation time 1474367432 ps
CPU time 4.12 seconds
Started Mar 10 01:48:45 PM PDT 24
Finished Mar 10 01:48:49 PM PDT 24
Peak memory 216996 kb
Host smart-e9e41eec-e52c-471b-ae54-11d41d2afbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246766974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2246766974
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3624692250
Short name T295
Test name
Test status
Simulation time 146530579 ps
CPU time 6.83 seconds
Started Mar 10 02:46:02 PM PDT 24
Finished Mar 10 02:46:09 PM PDT 24
Peak memory 215816 kb
Host smart-1c16cf0f-12ff-43b1-bdac-27cb0fae8f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624692250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3624692250
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2707455860
Short name T689
Test name
Test status
Simulation time 54909437 ps
CPU time 0.7 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:08 PM PDT 24
Peak memory 204900 kb
Host smart-5abd7f9a-1c46-494d-937a-8ec9e0487f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707455860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2707455860
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.4034722442
Short name T994
Test name
Test status
Simulation time 29603151 ps
CPU time 0.77 seconds
Started Mar 10 01:48:48 PM PDT 24
Finished Mar 10 01:48:49 PM PDT 24
Peak memory 204880 kb
Host smart-60ea7085-6a26-45dc-a643-baa02b5fe39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034722442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4034722442
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1508455828
Short name T1616
Test name
Test status
Simulation time 20605044793 ps
CPU time 18 seconds
Started Mar 10 02:46:04 PM PDT 24
Finished Mar 10 02:46:23 PM PDT 24
Peak memory 233628 kb
Host smart-e6b396e1-41f4-4a40-9f5f-86135e8faf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508455828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1508455828
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_upload.1976143846
Short name T750
Test name
Test status
Simulation time 233186667 ps
CPU time 2.73 seconds
Started Mar 10 01:48:48 PM PDT 24
Finished Mar 10 01:48:50 PM PDT 24
Peak memory 232032 kb
Host smart-a9a66a15-310f-4cbe-823f-2e5eadeeafcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976143846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1976143846
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3685813464
Short name T509
Test name
Test status
Simulation time 21458293 ps
CPU time 0.78 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:16 PM PDT 24
Peak memory 204684 kb
Host smart-825f1859-517a-4ddb-9ad5-f5c27b9894c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685813464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
685813464
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3884992516
Short name T1480
Test name
Test status
Simulation time 57242906 ps
CPU time 0.69 seconds
Started Mar 10 01:48:53 PM PDT 24
Finished Mar 10 01:48:54 PM PDT 24
Peak memory 204760 kb
Host smart-46732656-906c-42cc-a810-5e6e84fad8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884992516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
884992516
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3080047934
Short name T1228
Test name
Test status
Simulation time 457876118 ps
CPU time 4.31 seconds
Started Mar 10 02:46:06 PM PDT 24
Finished Mar 10 02:46:10 PM PDT 24
Peak memory 233744 kb
Host smart-9a3344b4-5749-4cf8-beee-a7641c008193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080047934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3080047934
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3786620057
Short name T229
Test name
Test status
Simulation time 17095865152 ps
CPU time 6.24 seconds
Started Mar 10 01:48:53 PM PDT 24
Finished Mar 10 01:48:59 PM PDT 24
Peak memory 233744 kb
Host smart-6992d1ce-f2b4-47ae-902c-7fc6a6e2a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786620057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3786620057
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2765901078
Short name T875
Test name
Test status
Simulation time 35300564 ps
CPU time 0.76 seconds
Started Mar 10 01:48:50 PM PDT 24
Finished Mar 10 01:48:51 PM PDT 24
Peak memory 204820 kb
Host smart-5b7d7803-0067-4ea7-8769-1d93af8149f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765901078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2765901078
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3333502344
Short name T362
Test name
Test status
Simulation time 16352224 ps
CPU time 0.75 seconds
Started Mar 10 02:46:06 PM PDT 24
Finished Mar 10 02:46:07 PM PDT 24
Peak memory 204436 kb
Host smart-97a968f2-72f4-469b-9793-5f673585a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333502344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3333502344
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1027550624
Short name T665
Test name
Test status
Simulation time 15597390775 ps
CPU time 79.52 seconds
Started Mar 10 01:48:52 PM PDT 24
Finished Mar 10 01:50:12 PM PDT 24
Peak memory 240104 kb
Host smart-d287b0cf-5019-4244-8f49-b616d6c329b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027550624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1027550624
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1597279333
Short name T832
Test name
Test status
Simulation time 27472852366 ps
CPU time 158.58 seconds
Started Mar 10 02:46:09 PM PDT 24
Finished Mar 10 02:48:48 PM PDT 24
Peak memory 255792 kb
Host smart-b0a3e204-61f3-456f-93bc-553b82e78b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597279333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1597279333
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2706260861
Short name T240
Test name
Test status
Simulation time 140739535442 ps
CPU time 828.29 seconds
Started Mar 10 01:48:53 PM PDT 24
Finished Mar 10 02:02:42 PM PDT 24
Peak memory 273220 kb
Host smart-d6900718-1f03-4838-bbd5-7d634c18236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706260861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2706260861
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3916738767
Short name T418
Test name
Test status
Simulation time 44379503784 ps
CPU time 75.93 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:47:23 PM PDT 24
Peak memory 224064 kb
Host smart-82482e5d-fa4e-479f-9cc4-52c375903601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916738767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3916738767
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3590144622
Short name T263
Test name
Test status
Simulation time 40100704962 ps
CPU time 214.33 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:49:50 PM PDT 24
Peak memory 253348 kb
Host smart-5b0c1b5e-36c9-4500-9568-095e1c0cdf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590144622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3590144622
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1458039083
Short name T1143
Test name
Test status
Simulation time 1863365064 ps
CPU time 18.77 seconds
Started Mar 10 01:48:47 PM PDT 24
Finished Mar 10 01:49:06 PM PDT 24
Peak memory 239968 kb
Host smart-95c2ad3a-3e36-49ec-9a21-c320353449d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458039083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1458039083
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1558489920
Short name T653
Test name
Test status
Simulation time 24125609341 ps
CPU time 35.99 seconds
Started Mar 10 02:46:14 PM PDT 24
Finished Mar 10 02:46:51 PM PDT 24
Peak memory 240284 kb
Host smart-d03498ba-779f-4f68-bce3-baef6153f3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558489920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1558489920
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1560425438
Short name T1082
Test name
Test status
Simulation time 810598620 ps
CPU time 6.7 seconds
Started Mar 10 02:46:05 PM PDT 24
Finished Mar 10 02:46:13 PM PDT 24
Peak memory 232848 kb
Host smart-3f63fcf8-d9f0-49a8-abe0-52046ce2f302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560425438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1560425438
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3399126918
Short name T220
Test name
Test status
Simulation time 4207653593 ps
CPU time 12.79 seconds
Started Mar 10 01:48:48 PM PDT 24
Finished Mar 10 01:49:01 PM PDT 24
Peak memory 219108 kb
Host smart-264b7a44-6342-4225-8da0-79fb7564d230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399126918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3399126918
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2546643351
Short name T1258
Test name
Test status
Simulation time 3742789541 ps
CPU time 7.03 seconds
Started Mar 10 01:48:50 PM PDT 24
Finished Mar 10 01:48:57 PM PDT 24
Peak memory 235288 kb
Host smart-5fe3a382-8212-4258-bffa-9c1c7d7cddb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546643351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2546643351
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.4073979003
Short name T333
Test name
Test status
Simulation time 22134537499 ps
CPU time 9.87 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:25 PM PDT 24
Peak memory 248440 kb
Host smart-0d03c3ec-950e-4b21-9537-381b7ffc1d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073979003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4073979003
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.284457259
Short name T1771
Test name
Test status
Simulation time 38244440 ps
CPU time 1.09 seconds
Started Mar 10 02:46:12 PM PDT 24
Finished Mar 10 02:46:14 PM PDT 24
Peak memory 216048 kb
Host smart-faf133d5-0850-4b68-afc2-299f5202dc47
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284457259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.284457259
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3042700100
Short name T1615
Test name
Test status
Simulation time 98382306 ps
CPU time 1.07 seconds
Started Mar 10 01:48:49 PM PDT 24
Finished Mar 10 01:48:50 PM PDT 24
Peak memory 216068 kb
Host smart-ee9ce2cb-3d45-4a50-8fd3-af16557bd4a9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042700100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3042700100
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2228933922
Short name T504
Test name
Test status
Simulation time 247036628 ps
CPU time 2.57 seconds
Started Mar 10 01:48:52 PM PDT 24
Finished Mar 10 01:48:55 PM PDT 24
Peak memory 216220 kb
Host smart-d32aaee9-e4b7-46f4-a805-4c22b26a5dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228933922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2228933922
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2504232106
Short name T238
Test name
Test status
Simulation time 219890819 ps
CPU time 3.08 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:10 PM PDT 24
Peak memory 223896 kb
Host smart-1a4dcf79-f14f-4211-9f00-04f30d2ac93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504232106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2504232106
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1906217330
Short name T1341
Test name
Test status
Simulation time 3526167528 ps
CPU time 10.97 seconds
Started Mar 10 01:48:48 PM PDT 24
Finished Mar 10 01:48:59 PM PDT 24
Peak memory 217096 kb
Host smart-26298ba5-8aa4-4a3a-8f5a-d922ca60c619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906217330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1906217330
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4018353146
Short name T802
Test name
Test status
Simulation time 45678503085 ps
CPU time 27.77 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:35 PM PDT 24
Peak memory 226556 kb
Host smart-3501f143-5413-4def-91d8-fef393b590c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018353146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4018353146
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3527393398
Short name T626
Test name
Test status
Simulation time 15952113 ps
CPU time 0.72 seconds
Started Mar 10 01:48:54 PM PDT 24
Finished Mar 10 01:48:55 PM PDT 24
Peak memory 215620 kb
Host smart-b5f7fa27-c21b-417c-ae55-ae2463b2f0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527393398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3527393398
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.527297809
Short name T1354
Test name
Test status
Simulation time 19158268 ps
CPU time 0.79 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:08 PM PDT 24
Peak memory 215600 kb
Host smart-83f5a464-2002-4dc4-9933-2a9b91ee52d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527297809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.527297809
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2503847583
Short name T693
Test name
Test status
Simulation time 2833755109 ps
CPU time 4.65 seconds
Started Mar 10 01:48:55 PM PDT 24
Finished Mar 10 01:48:59 PM PDT 24
Peak memory 217980 kb
Host smart-5e0d7992-3fce-48e9-96d8-e6bc5dd8be9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503847583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2503847583
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3884912533
Short name T621
Test name
Test status
Simulation time 132508230 ps
CPU time 3.82 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:19 PM PDT 24
Peak memory 222032 kb
Host smart-75ae98fa-086a-4c7d-ab3e-428d8dfd40fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3884912533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3884912533
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2404972820
Short name T62
Test name
Test status
Simulation time 312210818 ps
CPU time 1.19 seconds
Started Mar 10 02:46:06 PM PDT 24
Finished Mar 10 02:46:07 PM PDT 24
Peak memory 234560 kb
Host smart-a2c9d8a0-2a89-48b2-a937-ce297a40e1d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404972820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2404972820
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3916250834
Short name T66
Test name
Test status
Simulation time 39669384 ps
CPU time 0.94 seconds
Started Mar 10 01:48:55 PM PDT 24
Finished Mar 10 01:48:56 PM PDT 24
Peak memory 234972 kb
Host smart-4febdf7b-07df-4963-a286-03cf15c0d964
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916250834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3916250834
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2207583729
Short name T450
Test name
Test status
Simulation time 203829809 ps
CPU time 0.95 seconds
Started Mar 10 01:48:56 PM PDT 24
Finished Mar 10 01:48:57 PM PDT 24
Peak memory 205848 kb
Host smart-b46bd331-15c7-45c6-b652-f36fcfca9ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207583729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2207583729
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.456427892
Short name T662
Test name
Test status
Simulation time 232142863786 ps
CPU time 479 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:54:06 PM PDT 24
Peak memory 272544 kb
Host smart-092352b1-795a-474f-a003-de7db73c2784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456427892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.456427892
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2720824099
Short name T1807
Test name
Test status
Simulation time 923210221 ps
CPU time 3.07 seconds
Started Mar 10 01:48:50 PM PDT 24
Finished Mar 10 01:48:53 PM PDT 24
Peak memory 215736 kb
Host smart-09c7b07e-33b5-4c35-a4e5-62b3bf82e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720824099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2720824099
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2637690089
Short name T409
Test name
Test status
Simulation time 1097783554 ps
CPU time 3.69 seconds
Started Mar 10 01:48:50 PM PDT 24
Finished Mar 10 01:48:54 PM PDT 24
Peak memory 215568 kb
Host smart-7bdcf6ee-9a29-4ec2-9c17-6971f3aaf63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637690089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2637690089
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3364701167
Short name T1824
Test name
Test status
Simulation time 11978117289 ps
CPU time 21.4 seconds
Started Mar 10 02:46:12 PM PDT 24
Finished Mar 10 02:46:34 PM PDT 24
Peak memory 215796 kb
Host smart-b3f8d045-4e75-471f-9a82-82cbabda9585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364701167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3364701167
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1871661367
Short name T1202
Test name
Test status
Simulation time 57085623 ps
CPU time 1.36 seconds
Started Mar 10 02:46:08 PM PDT 24
Finished Mar 10 02:46:10 PM PDT 24
Peak memory 215792 kb
Host smart-b52cc53b-97b0-48b9-b619-f1829d4b5a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871661367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1871661367
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.478322575
Short name T131
Test name
Test status
Simulation time 43596712 ps
CPU time 1.44 seconds
Started Mar 10 01:48:49 PM PDT 24
Finished Mar 10 01:48:51 PM PDT 24
Peak memory 215740 kb
Host smart-faa579ba-57ea-41c7-9b24-bfd6853acb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478322575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.478322575
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.395189397
Short name T1048
Test name
Test status
Simulation time 136604434 ps
CPU time 0.77 seconds
Started Mar 10 02:46:14 PM PDT 24
Finished Mar 10 02:46:16 PM PDT 24
Peak memory 204828 kb
Host smart-c1647847-8e76-428d-8b30-74d75976d63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395189397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.395189397
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.756153919
Short name T607
Test name
Test status
Simulation time 111917351 ps
CPU time 0.8 seconds
Started Mar 10 01:48:47 PM PDT 24
Finished Mar 10 01:48:48 PM PDT 24
Peak memory 204860 kb
Host smart-e1f97acf-9d7f-49a1-8b69-70d703356b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756153919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.756153919
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1440518297
Short name T1229
Test name
Test status
Simulation time 133592853 ps
CPU time 2.97 seconds
Started Mar 10 02:46:08 PM PDT 24
Finished Mar 10 02:46:11 PM PDT 24
Peak memory 223824 kb
Host smart-1178ee26-8a75-429c-a164-6127eda018ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440518297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1440518297
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_upload.1647262686
Short name T1651
Test name
Test status
Simulation time 11220408645 ps
CPU time 31.7 seconds
Started Mar 10 01:48:52 PM PDT 24
Finished Mar 10 01:49:24 PM PDT 24
Peak memory 218228 kb
Host smart-a28d1629-dd7b-4c4a-a711-bb539baba029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647262686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1647262686
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1629466074
Short name T1118
Test name
Test status
Simulation time 16403375 ps
CPU time 0.72 seconds
Started Mar 10 01:49:41 PM PDT 24
Finished Mar 10 01:49:42 PM PDT 24
Peak memory 203860 kb
Host smart-cd27552d-3865-4e6d-a90e-c99d85cacf6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629466074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1629466074
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.609613863
Short name T556
Test name
Test status
Simulation time 22601310 ps
CPU time 0.74 seconds
Started Mar 10 02:46:42 PM PDT 24
Finished Mar 10 02:46:43 PM PDT 24
Peak memory 204792 kb
Host smart-ddf4b967-d576-405e-a757-52d187fcdcc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609613863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.609613863
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1497169368
Short name T1069
Test name
Test status
Simulation time 1055061796 ps
CPU time 4.23 seconds
Started Mar 10 01:49:36 PM PDT 24
Finished Mar 10 01:49:41 PM PDT 24
Peak memory 217208 kb
Host smart-7b7ec1a7-05e3-4f2b-b6e6-3856543fcdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497169368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1497169368
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.150589654
Short name T947
Test name
Test status
Simulation time 2303551620 ps
CPU time 7.14 seconds
Started Mar 10 02:46:46 PM PDT 24
Finished Mar 10 02:46:53 PM PDT 24
Peak memory 217536 kb
Host smart-b72685ca-ecad-419d-83ca-31078f3de624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150589654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.150589654
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1818309391
Short name T774
Test name
Test status
Simulation time 46103251 ps
CPU time 0.77 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:46:44 PM PDT 24
Peak memory 205836 kb
Host smart-b0f82500-74cf-41ad-8026-e8117a23833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818309391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1818309391
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3452149072
Short name T877
Test name
Test status
Simulation time 25681756 ps
CPU time 0.78 seconds
Started Mar 10 01:49:32 PM PDT 24
Finished Mar 10 01:49:34 PM PDT 24
Peak memory 205816 kb
Host smart-41fd69a2-f0fa-49fb-b9e9-04025b73eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452149072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3452149072
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3047012687
Short name T563
Test name
Test status
Simulation time 6381695301 ps
CPU time 36.11 seconds
Started Mar 10 02:46:42 PM PDT 24
Finished Mar 10 02:47:18 PM PDT 24
Peak memory 248444 kb
Host smart-756317ff-1155-4128-b698-31f8c7c1cb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047012687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3047012687
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4258458475
Short name T1133
Test name
Test status
Simulation time 4639266264 ps
CPU time 35.43 seconds
Started Mar 10 01:49:36 PM PDT 24
Finished Mar 10 01:50:12 PM PDT 24
Peak memory 240312 kb
Host smart-18abf71e-4ba4-4c65-96ef-d6f4d3c8134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258458475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4258458475
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1717775352
Short name T1147
Test name
Test status
Simulation time 76665457989 ps
CPU time 86.08 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 239892 kb
Host smart-2d0d11b4-2d25-4c8b-a321-1ded23460dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717775352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1717775352
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.648838727
Short name T1078
Test name
Test status
Simulation time 8482455073 ps
CPU time 114.33 seconds
Started Mar 10 01:49:35 PM PDT 24
Finished Mar 10 01:51:30 PM PDT 24
Peak memory 253060 kb
Host smart-7a38b1e7-4379-4ccf-893c-31eb63572790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648838727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.648838727
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.850052118
Short name T272
Test name
Test status
Simulation time 180555017609 ps
CPU time 337.58 seconds
Started Mar 10 01:49:37 PM PDT 24
Finished Mar 10 01:55:15 PM PDT 24
Peak memory 255368 kb
Host smart-2012f4e9-d8bc-4de1-afb0-ae9c81b765a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850052118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.850052118
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2513790798
Short name T1630
Test name
Test status
Simulation time 3971347213 ps
CPU time 22.99 seconds
Started Mar 10 02:46:42 PM PDT 24
Finished Mar 10 02:47:05 PM PDT 24
Peak memory 235964 kb
Host smart-89171c64-96f8-4ba1-beb8-035fa2336d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513790798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2513790798
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.744218993
Short name T432
Test name
Test status
Simulation time 351720878 ps
CPU time 6.49 seconds
Started Mar 10 01:49:36 PM PDT 24
Finished Mar 10 01:49:42 PM PDT 24
Peak memory 232124 kb
Host smart-c2038889-0be0-4635-83cc-877242a22777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744218993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.744218993
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1099381090
Short name T879
Test name
Test status
Simulation time 7001009624 ps
CPU time 7.11 seconds
Started Mar 10 01:49:36 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 223968 kb
Host smart-c158d6cc-d974-4d18-921f-efad6324eaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099381090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1099381090
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4030890187
Short name T1364
Test name
Test status
Simulation time 8496096180 ps
CPU time 5.23 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:46:49 PM PDT 24
Peak memory 217156 kb
Host smart-c531db25-d606-4989-957a-b204802a0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030890187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4030890187
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2120179180
Short name T1798
Test name
Test status
Simulation time 10418416052 ps
CPU time 41.67 seconds
Started Mar 10 02:46:48 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 255216 kb
Host smart-b1d7ac39-4407-4494-b219-962fda1cf32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120179180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2120179180
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.309550487
Short name T478
Test name
Test status
Simulation time 106345844 ps
CPU time 3.23 seconds
Started Mar 10 01:49:39 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 223872 kb
Host smart-da02be23-2359-4d39-b802-e34cce768544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309550487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.309550487
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1199695670
Short name T345
Test name
Test status
Simulation time 121844170 ps
CPU time 1.18 seconds
Started Mar 10 01:49:32 PM PDT 24
Finished Mar 10 01:49:33 PM PDT 24
Peak memory 216052 kb
Host smart-34dfcbb0-3051-416a-a0ef-5e186ac55189
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199695670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1199695670
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3388868216
Short name T997
Test name
Test status
Simulation time 52047912 ps
CPU time 1.06 seconds
Started Mar 10 02:46:46 PM PDT 24
Finished Mar 10 02:46:47 PM PDT 24
Peak memory 216076 kb
Host smart-929a1b9b-d285-4239-a30a-bf04e2b14977
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388868216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3388868216
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3792355294
Short name T538
Test name
Test status
Simulation time 3300641720 ps
CPU time 7.16 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:46:54 PM PDT 24
Peak memory 232732 kb
Host smart-76241793-56fc-42ad-9cd1-2cba5c73be7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792355294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3792355294
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.998474331
Short name T732
Test name
Test status
Simulation time 21331293794 ps
CPU time 21.37 seconds
Started Mar 10 01:49:36 PM PDT 24
Finished Mar 10 01:49:58 PM PDT 24
Peak memory 236576 kb
Host smart-1c24cec0-75b9-4080-8b7e-ecd89b974e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998474331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.998474331
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1200835793
Short name T1585
Test name
Test status
Simulation time 2349320196 ps
CPU time 4.14 seconds
Started Mar 10 02:46:46 PM PDT 24
Finished Mar 10 02:46:51 PM PDT 24
Peak memory 232836 kb
Host smart-800947d4-c052-46b7-a719-6cc310483902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200835793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1200835793
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3594234775
Short name T843
Test name
Test status
Simulation time 30318579036 ps
CPU time 53.72 seconds
Started Mar 10 01:49:37 PM PDT 24
Finished Mar 10 01:50:31 PM PDT 24
Peak memory 232136 kb
Host smart-3318ef80-5d91-4b29-af8c-0492aa2194ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594234775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3594234775
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2244542788
Short name T973
Test name
Test status
Simulation time 19413027 ps
CPU time 0.77 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:46:48 PM PDT 24
Peak memory 215616 kb
Host smart-3b152dc7-00da-4526-a5a0-2b7cd0bb3edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244542788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2244542788
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.247765647
Short name T61
Test name
Test status
Simulation time 31439373 ps
CPU time 0.72 seconds
Started Mar 10 01:49:32 PM PDT 24
Finished Mar 10 01:49:33 PM PDT 24
Peak memory 215624 kb
Host smart-0d0e7ed2-2407-433d-9cad-b91df13b77fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247765647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.247765647
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2072407310
Short name T476
Test name
Test status
Simulation time 707696256 ps
CPU time 4.37 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:46:47 PM PDT 24
Peak memory 221612 kb
Host smart-3cc9325e-f138-4dbc-acc7-fbed48169c29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2072407310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2072407310
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2582689134
Short name T855
Test name
Test status
Simulation time 503010569 ps
CPU time 5.13 seconds
Started Mar 10 01:49:37 PM PDT 24
Finished Mar 10 01:49:42 PM PDT 24
Peak memory 222004 kb
Host smart-309e1f32-48eb-4d3d-a12b-2f01f3a46a8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2582689134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2582689134
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1831503281
Short name T155
Test name
Test status
Simulation time 22036546948 ps
CPU time 70.12 seconds
Started Mar 10 02:46:45 PM PDT 24
Finished Mar 10 02:47:56 PM PDT 24
Peak memory 240524 kb
Host smart-925ec1f8-b23c-4541-8ebe-e84584d80fb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831503281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1831503281
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1295037593
Short name T1157
Test name
Test status
Simulation time 48411885105 ps
CPU time 47.24 seconds
Started Mar 10 02:46:42 PM PDT 24
Finished Mar 10 02:47:29 PM PDT 24
Peak memory 215752 kb
Host smart-ddf65ec2-dd64-4e48-90aa-e6b1f20bb7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295037593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1295037593
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1345702130
Short name T20
Test name
Test status
Simulation time 1536922722 ps
CPU time 9.73 seconds
Started Mar 10 01:49:36 PM PDT 24
Finished Mar 10 01:49:46 PM PDT 24
Peak memory 215740 kb
Host smart-4f5a34cb-9a25-4033-ad54-63792879b249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345702130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1345702130
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3477543656
Short name T1428
Test name
Test status
Simulation time 15271773455 ps
CPU time 11.54 seconds
Started Mar 10 01:49:35 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 215704 kb
Host smart-ce663c54-a57c-49af-bb4f-005e196074a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477543656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3477543656
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.615417328
Short name T499
Test name
Test status
Simulation time 13316756228 ps
CPU time 34.54 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:47:18 PM PDT 24
Peak memory 216776 kb
Host smart-604925a3-a6db-46bc-a3f7-70517ece3c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615417328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.615417328
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2317866428
Short name T664
Test name
Test status
Simulation time 626723743 ps
CPU time 2.34 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:46:46 PM PDT 24
Peak memory 215948 kb
Host smart-d3f6824f-84d5-402f-8f6d-3a0f8f4d0068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317866428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2317866428
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2795101051
Short name T763
Test name
Test status
Simulation time 478803355 ps
CPU time 1.99 seconds
Started Mar 10 01:49:36 PM PDT 24
Finished Mar 10 01:49:39 PM PDT 24
Peak memory 215768 kb
Host smart-3c0e9a4c-a3cc-49c2-bd1e-c136153ed770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795101051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2795101051
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2988030322
Short name T394
Test name
Test status
Simulation time 85903137 ps
CPU time 0.81 seconds
Started Mar 10 02:46:45 PM PDT 24
Finished Mar 10 02:46:46 PM PDT 24
Peak memory 204896 kb
Host smart-349099aa-c26f-43eb-b6c8-e8a555ed83f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988030322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2988030322
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3532689276
Short name T906
Test name
Test status
Simulation time 152548451 ps
CPU time 0.99 seconds
Started Mar 10 01:49:37 PM PDT 24
Finished Mar 10 01:49:38 PM PDT 24
Peak memory 205748 kb
Host smart-2e1e6e88-99e3-473e-9c9e-0fe0f106c102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532689276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3532689276
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.114622370
Short name T1144
Test name
Test status
Simulation time 651610443 ps
CPU time 9.74 seconds
Started Mar 10 01:49:37 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 233252 kb
Host smart-4330ef0e-4d39-45ad-be11-f5a7107fab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114622370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.114622370
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_upload.905471882
Short name T1921
Test name
Test status
Simulation time 8648734574 ps
CPU time 6.61 seconds
Started Mar 10 02:46:48 PM PDT 24
Finished Mar 10 02:46:55 PM PDT 24
Peak memory 234836 kb
Host smart-2512b2d8-cb46-4dfe-9ee2-ba00b91a5813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905471882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.905471882
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2645382622
Short name T984
Test name
Test status
Simulation time 14141817 ps
CPU time 0.7 seconds
Started Mar 10 02:46:52 PM PDT 24
Finished Mar 10 02:46:53 PM PDT 24
Peak memory 203860 kb
Host smart-135f922e-36a1-4365-a42e-c8a64bee660e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645382622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2645382622
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.982945321
Short name T1543
Test name
Test status
Simulation time 41370939 ps
CPU time 0.68 seconds
Started Mar 10 01:49:42 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 204376 kb
Host smart-e673d0b3-d1bb-456c-b370-25b46a622701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982945321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.982945321
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2729603092
Short name T1629
Test name
Test status
Simulation time 315449135 ps
CPU time 2.65 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:47:01 PM PDT 24
Peak memory 217360 kb
Host smart-fad90c0a-8e1e-4889-b0c7-718195275035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729603092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2729603092
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.885328998
Short name T1028
Test name
Test status
Simulation time 2040090287 ps
CPU time 5.16 seconds
Started Mar 10 01:49:41 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 223900 kb
Host smart-8beb1064-967e-4eb5-8351-7f11eb436256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885328998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.885328998
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1299130182
Short name T1494
Test name
Test status
Simulation time 44615916 ps
CPU time 0.75 seconds
Started Mar 10 02:46:53 PM PDT 24
Finished Mar 10 02:46:53 PM PDT 24
Peak memory 204416 kb
Host smart-28c979c9-4bca-47ee-a37d-14a259c96398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299130182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1299130182
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3215230689
Short name T293
Test name
Test status
Simulation time 58589934 ps
CPU time 0.77 seconds
Started Mar 10 01:49:41 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 205448 kb
Host smart-bed0e088-e8df-47b1-84c4-12073677b31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215230689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3215230689
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1199452894
Short name T192
Test name
Test status
Simulation time 34415318189 ps
CPU time 217.81 seconds
Started Mar 10 01:49:42 PM PDT 24
Finished Mar 10 01:53:20 PM PDT 24
Peak memory 271772 kb
Host smart-3dd970cd-661f-4390-8ebe-cd9ddd16328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199452894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1199452894
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2483301409
Short name T1734
Test name
Test status
Simulation time 66467966593 ps
CPU time 115.9 seconds
Started Mar 10 02:46:51 PM PDT 24
Finished Mar 10 02:48:47 PM PDT 24
Peak memory 253520 kb
Host smart-96f3c4ea-1c82-4618-8729-d4f6d2b97d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483301409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2483301409
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2003313592
Short name T377
Test name
Test status
Simulation time 88820143988 ps
CPU time 141.1 seconds
Started Mar 10 02:46:56 PM PDT 24
Finished Mar 10 02:49:17 PM PDT 24
Peak memory 250024 kb
Host smart-98bd4387-b6be-4ec5-b2d8-844a291ec84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003313592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2003313592
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3437927934
Short name T1476
Test name
Test status
Simulation time 45551539832 ps
CPU time 75.47 seconds
Started Mar 10 01:49:42 PM PDT 24
Finished Mar 10 01:50:58 PM PDT 24
Peak memory 232392 kb
Host smart-493fbea2-05dc-41ad-af95-3bd9b023c176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437927934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3437927934
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3806080707
Short name T19
Test name
Test status
Simulation time 19089626289 ps
CPU time 129.1 seconds
Started Mar 10 01:49:42 PM PDT 24
Finished Mar 10 01:51:52 PM PDT 24
Peak memory 265012 kb
Host smart-b43d1653-df43-422e-976f-fa3c1f6f82c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806080707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3806080707
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1956943721
Short name T1900
Test name
Test status
Simulation time 2162928191 ps
CPU time 11.15 seconds
Started Mar 10 02:46:50 PM PDT 24
Finished Mar 10 02:47:02 PM PDT 24
Peak memory 233148 kb
Host smart-e8cf0f11-a131-48fb-9af2-0004874528cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956943721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1956943721
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3614173174
Short name T1039
Test name
Test status
Simulation time 13220320679 ps
CPU time 24.33 seconds
Started Mar 10 01:49:42 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 234368 kb
Host smart-cccad3f4-07de-416e-87bd-3467a5ebd6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614173174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3614173174
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2363857380
Short name T630
Test name
Test status
Simulation time 5224506984 ps
CPU time 6.01 seconds
Started Mar 10 02:46:51 PM PDT 24
Finished Mar 10 02:46:57 PM PDT 24
Peak memory 235708 kb
Host smart-d5549a59-fb4e-44e4-be80-3dadb4744203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363857380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2363857380
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intercept.877599669
Short name T352
Test name
Test status
Simulation time 573360944 ps
CPU time 4.35 seconds
Started Mar 10 01:49:40 PM PDT 24
Finished Mar 10 01:49:45 PM PDT 24
Peak memory 233112 kb
Host smart-e8d975f8-c8b2-4afc-ad31-e4a81cce3a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877599669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.877599669
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1948975535
Short name T697
Test name
Test status
Simulation time 369015040 ps
CPU time 3.32 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:46:50 PM PDT 24
Peak memory 232088 kb
Host smart-de2ed3af-7d1d-4bbe-8f2d-1a0cd6ba54d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948975535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1948975535
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.350869014
Short name T836
Test name
Test status
Simulation time 15082145982 ps
CPU time 35.27 seconds
Started Mar 10 01:49:43 PM PDT 24
Finished Mar 10 01:50:19 PM PDT 24
Peak memory 232044 kb
Host smart-938362a7-3325-439b-8d83-57586400d02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350869014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.350869014
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3011719065
Short name T420
Test name
Test status
Simulation time 27791110 ps
CPU time 1.15 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:46:50 PM PDT 24
Peak memory 216068 kb
Host smart-dae303f4-b548-4932-a658-30fd7f71f8d2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011719065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3011719065
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3712278796
Short name T1808
Test name
Test status
Simulation time 16748942 ps
CPU time 0.97 seconds
Started Mar 10 01:49:43 PM PDT 24
Finished Mar 10 01:49:45 PM PDT 24
Peak memory 217244 kb
Host smart-3ae67a8e-5952-49e8-a83c-939dd714026e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712278796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3712278796
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1940490336
Short name T772
Test name
Test status
Simulation time 73063804872 ps
CPU time 32.97 seconds
Started Mar 10 01:49:42 PM PDT 24
Finished Mar 10 01:50:15 PM PDT 24
Peak memory 234508 kb
Host smart-bccea614-924a-4feb-b2c1-25ac0489015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940490336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1940490336
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2919095535
Short name T1153
Test name
Test status
Simulation time 3655119729 ps
CPU time 6.85 seconds
Started Mar 10 02:46:49 PM PDT 24
Finished Mar 10 02:46:56 PM PDT 24
Peak memory 215920 kb
Host smart-c5b97818-90c7-427e-bd51-7bab2531bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919095535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2919095535
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2158407932
Short name T1504
Test name
Test status
Simulation time 2554839660 ps
CPU time 7.25 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:46:55 PM PDT 24
Peak memory 228256 kb
Host smart-5e74cc17-8342-43c7-8e0a-53b288001332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158407932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2158407932
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2333812848
Short name T980
Test name
Test status
Simulation time 12641690349 ps
CPU time 20.71 seconds
Started Mar 10 01:49:43 PM PDT 24
Finished Mar 10 01:50:05 PM PDT 24
Peak memory 227916 kb
Host smart-babdffc3-c883-4dfd-bb54-767a222b9ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333812848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2333812848
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3283393844
Short name T1332
Test name
Test status
Simulation time 44160880 ps
CPU time 0.74 seconds
Started Mar 10 02:46:49 PM PDT 24
Finished Mar 10 02:46:50 PM PDT 24
Peak memory 215612 kb
Host smart-69c83233-f71d-4c46-a6bf-be402fef7f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283393844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3283393844
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3510237329
Short name T1054
Test name
Test status
Simulation time 45390464 ps
CPU time 0.72 seconds
Started Mar 10 01:49:39 PM PDT 24
Finished Mar 10 01:49:40 PM PDT 24
Peak memory 215628 kb
Host smart-ef682deb-ca62-47c7-8796-9f17cb1ee129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510237329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3510237329
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1462925338
Short name T1884
Test name
Test status
Simulation time 1147637118 ps
CPU time 5.89 seconds
Started Mar 10 02:46:51 PM PDT 24
Finished Mar 10 02:46:57 PM PDT 24
Peak memory 215884 kb
Host smart-8a299cf3-3673-4f39-a123-fb3a07d3b042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1462925338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1462925338
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2162077185
Short name T1038
Test name
Test status
Simulation time 239779134 ps
CPU time 3.76 seconds
Started Mar 10 01:49:42 PM PDT 24
Finished Mar 10 01:49:46 PM PDT 24
Peak memory 215936 kb
Host smart-6a589af7-30e4-4fed-a80b-112867956ec2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2162077185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2162077185
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1705969488
Short name T85
Test name
Test status
Simulation time 131547385944 ps
CPU time 450.14 seconds
Started Mar 10 01:49:40 PM PDT 24
Finished Mar 10 01:57:10 PM PDT 24
Peak memory 252016 kb
Host smart-9f1ae253-d75f-4451-8c8f-23802ab2c97b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705969488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1705969488
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3730929128
Short name T413
Test name
Test status
Simulation time 180419351 ps
CPU time 0.95 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:46:56 PM PDT 24
Peak memory 205708 kb
Host smart-6d647fb8-7763-440c-bf7f-131609b2652c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730929128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3730929128
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1141942375
Short name T1848
Test name
Test status
Simulation time 4871991468 ps
CPU time 23.28 seconds
Started Mar 10 02:46:50 PM PDT 24
Finished Mar 10 02:47:13 PM PDT 24
Peak memory 215832 kb
Host smart-42c71193-36f4-47b2-99b4-8f36d4948860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141942375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1141942375
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3266122757
Short name T1666
Test name
Test status
Simulation time 1605323899 ps
CPU time 9.86 seconds
Started Mar 10 01:49:42 PM PDT 24
Finished Mar 10 01:49:52 PM PDT 24
Peak memory 215780 kb
Host smart-cc9ed9cc-c243-4f81-a38f-a385c64c5109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266122757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3266122757
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1195712132
Short name T1466
Test name
Test status
Simulation time 604432767 ps
CPU time 4.3 seconds
Started Mar 10 01:49:39 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 216036 kb
Host smart-76455166-5480-4722-9c2d-e50d6419efea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195712132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1195712132
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2466657779
Short name T894
Test name
Test status
Simulation time 535835033 ps
CPU time 3.63 seconds
Started Mar 10 02:46:56 PM PDT 24
Finished Mar 10 02:47:00 PM PDT 24
Peak memory 215792 kb
Host smart-d8ba611c-6e73-4f37-b267-a81722a7ea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466657779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2466657779
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1549969893
Short name T456
Test name
Test status
Simulation time 181696288 ps
CPU time 5.71 seconds
Started Mar 10 01:49:43 PM PDT 24
Finished Mar 10 01:49:49 PM PDT 24
Peak memory 215772 kb
Host smart-ca4392e9-1728-4597-9cea-3dc26392e786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549969893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1549969893
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3807198607
Short name T977
Test name
Test status
Simulation time 44302788 ps
CPU time 1.14 seconds
Started Mar 10 02:46:51 PM PDT 24
Finished Mar 10 02:46:52 PM PDT 24
Peak memory 207088 kb
Host smart-a39c9736-f86b-441a-99e3-385d448fcccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807198607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3807198607
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2261352839
Short name T391
Test name
Test status
Simulation time 152165174 ps
CPU time 0.85 seconds
Started Mar 10 02:46:48 PM PDT 24
Finished Mar 10 02:46:49 PM PDT 24
Peak memory 204892 kb
Host smart-b029dbcb-edbb-462f-8651-728bcd6b7c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261352839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2261352839
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.895655400
Short name T462
Test name
Test status
Simulation time 12567512 ps
CPU time 0.75 seconds
Started Mar 10 01:49:43 PM PDT 24
Finished Mar 10 01:49:45 PM PDT 24
Peak memory 204888 kb
Host smart-b5e4b3ec-06ac-46c2-8944-970495f504ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895655400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.895655400
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2091249143
Short name T1577
Test name
Test status
Simulation time 51481754997 ps
CPU time 35.57 seconds
Started Mar 10 02:46:50 PM PDT 24
Finished Mar 10 02:47:26 PM PDT 24
Peak memory 233188 kb
Host smart-b80b2cdf-60a0-4d9b-900f-5938a66c3897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091249143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2091249143
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_upload.989584878
Short name T505
Test name
Test status
Simulation time 2312013429 ps
CPU time 3.72 seconds
Started Mar 10 01:49:43 PM PDT 24
Finished Mar 10 01:49:48 PM PDT 24
Peak memory 216828 kb
Host smart-cd0817d3-82d7-489a-8d33-60fe7b7a3e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989584878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.989584878
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2366798573
Short name T1477
Test name
Test status
Simulation time 20481041 ps
CPU time 0.73 seconds
Started Mar 10 01:49:49 PM PDT 24
Finished Mar 10 01:49:50 PM PDT 24
Peak memory 203884 kb
Host smart-040f32b6-28b3-4173-93ca-0568f7b2a34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366798573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2366798573
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2848628150
Short name T1865
Test name
Test status
Simulation time 38965501 ps
CPU time 0.74 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:46:58 PM PDT 24
Peak memory 204768 kb
Host smart-113fc0e8-6e29-48fa-b288-ec7c89237e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848628150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2848628150
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1280482480
Short name T1030
Test name
Test status
Simulation time 595661915 ps
CPU time 4.56 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:49:50 PM PDT 24
Peak memory 219008 kb
Host smart-6df00e65-1aee-47a0-b800-93825476017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280482480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1280482480
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1476011526
Short name T1776
Test name
Test status
Simulation time 2051047635 ps
CPU time 4.54 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:47:02 PM PDT 24
Peak memory 223920 kb
Host smart-5330dd49-27dd-4721-a1d8-5e434a08a8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476011526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1476011526
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2994233485
Short name T887
Test name
Test status
Simulation time 19423604 ps
CPU time 0.85 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 205528 kb
Host smart-adbc7f53-b0f1-4bc9-ad27-972cf19833a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994233485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2994233485
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.713155279
Short name T899
Test name
Test status
Simulation time 46093701 ps
CPU time 0.76 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:46:58 PM PDT 24
Peak memory 204404 kb
Host smart-fc961302-e5f9-481f-bd97-86648b8bc6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713155279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.713155279
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3128956987
Short name T1018
Test name
Test status
Simulation time 2371724056 ps
CPU time 38.81 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:47:33 PM PDT 24
Peak memory 254312 kb
Host smart-33c3cce7-d2ea-4287-86fd-969fab9109d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128956987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3128956987
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.769981608
Short name T878
Test name
Test status
Simulation time 2097051002 ps
CPU time 10.92 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:49:57 PM PDT 24
Peak memory 240240 kb
Host smart-a531d472-09d1-4bbe-bdb3-6a263d34d62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769981608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.769981608
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2876230428
Short name T1462
Test name
Test status
Simulation time 232037004074 ps
CPU time 468.86 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:54:46 PM PDT 24
Peak memory 261868 kb
Host smart-870aa625-9c8f-4116-8164-c4141e96abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876230428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2876230428
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.648453108
Short name T260
Test name
Test status
Simulation time 75047295056 ps
CPU time 319.65 seconds
Started Mar 10 01:49:48 PM PDT 24
Finished Mar 10 01:55:08 PM PDT 24
Peak memory 269288 kb
Host smart-13c55af7-a044-4358-a481-8ab94354daa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648453108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.648453108
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4174184753
Short name T1830
Test name
Test status
Simulation time 14755329782 ps
CPU time 54.01 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:47:51 PM PDT 24
Peak memory 253924 kb
Host smart-d1093f05-445f-4e42-850f-0362b9ea23d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174184753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4174184753
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4255696020
Short name T397
Test name
Test status
Simulation time 3982101951 ps
CPU time 70.74 seconds
Started Mar 10 01:49:49 PM PDT 24
Finished Mar 10 01:51:00 PM PDT 24
Peak memory 248648 kb
Host smart-dbd25995-34d9-4c97-96fa-110c372e801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255696020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4255696020
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1425756529
Short name T417
Test name
Test status
Simulation time 13231164524 ps
CPU time 34.7 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:50:21 PM PDT 24
Peak memory 243000 kb
Host smart-43c7999a-17ef-49af-abda-7f8e15e2d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425756529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1425756529
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2157870894
Short name T1392
Test name
Test status
Simulation time 2065128354 ps
CPU time 14.54 seconds
Started Mar 10 02:46:54 PM PDT 24
Finished Mar 10 02:47:09 PM PDT 24
Peak memory 233076 kb
Host smart-c65acd23-585c-4c4c-8c8a-79775efa0f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157870894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2157870894
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3676351735
Short name T883
Test name
Test status
Simulation time 50937376811 ps
CPU time 9.18 seconds
Started Mar 10 01:49:47 PM PDT 24
Finished Mar 10 01:49:56 PM PDT 24
Peak memory 223952 kb
Host smart-f0184a66-398c-456f-9fd8-91b66be18b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676351735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3676351735
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3910045402
Short name T340
Test name
Test status
Simulation time 33982763 ps
CPU time 2.39 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:46:59 PM PDT 24
Peak memory 232132 kb
Host smart-e3e6ffa8-2169-4468-bbf1-75a940e013c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910045402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3910045402
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1543117239
Short name T233
Test name
Test status
Simulation time 5636172370 ps
CPU time 9.45 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:47:08 PM PDT 24
Peak memory 217892 kb
Host smart-d2fcd893-6ab1-4fbc-80f6-e5c00615a611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543117239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1543117239
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1888586357
Short name T1795
Test name
Test status
Simulation time 28969743579 ps
CPU time 42.33 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:50:29 PM PDT 24
Peak memory 226520 kb
Host smart-176166f1-09de-4ef1-bdf8-3f767a5ea13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888586357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1888586357
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3773470214
Short name T953
Test name
Test status
Simulation time 24516503 ps
CPU time 1.08 seconds
Started Mar 10 02:46:48 PM PDT 24
Finished Mar 10 02:46:49 PM PDT 24
Peak memory 215996 kb
Host smart-ead626b6-53e4-42b0-847b-e2f758c4588a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773470214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3773470214
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3823316253
Short name T1596
Test name
Test status
Simulation time 15655499 ps
CPU time 1.05 seconds
Started Mar 10 01:49:43 PM PDT 24
Finished Mar 10 01:49:45 PM PDT 24
Peak memory 216004 kb
Host smart-663bc5e6-e3ff-4afc-8425-f1106c34ded2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823316253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3823316253
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1876201924
Short name T1183
Test name
Test status
Simulation time 13478444134 ps
CPU time 13.41 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:47:10 PM PDT 24
Peak memory 237304 kb
Host smart-5cecdc5b-246c-4dcd-bf1c-1bd830fb9f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876201924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1876201924
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2940311642
Short name T1051
Test name
Test status
Simulation time 787960684 ps
CPU time 3.39 seconds
Started Mar 10 01:49:44 PM PDT 24
Finished Mar 10 01:49:49 PM PDT 24
Peak memory 232104 kb
Host smart-dca76f7b-4b72-45d3-9ed8-cd0d475fcfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940311642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2940311642
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.161091680
Short name T1156
Test name
Test status
Simulation time 18383232915 ps
CPU time 12.81 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:47:09 PM PDT 24
Peak memory 218348 kb
Host smart-be59077e-b94a-4da0-b9a9-83119c01da69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161091680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.161091680
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.58403368
Short name T228
Test name
Test status
Simulation time 6632597717 ps
CPU time 3.9 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:49:50 PM PDT 24
Peak memory 217304 kb
Host smart-5c6f3251-b10b-4eab-9598-540c2003fe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58403368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.58403368
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1915849815
Short name T471
Test name
Test status
Simulation time 35254946 ps
CPU time 0.75 seconds
Started Mar 10 01:49:45 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 215632 kb
Host smart-de25e956-1bd0-4cf0-96de-ece9ab1e26b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915849815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1915849815
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1968034613
Short name T674
Test name
Test status
Simulation time 16743668 ps
CPU time 0.77 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:46:56 PM PDT 24
Peak memory 215624 kb
Host smart-9097a377-5e56-4f4c-9f28-446e76ff9eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968034613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1968034613
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3165664118
Short name T403
Test name
Test status
Simulation time 866454458 ps
CPU time 3.7 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:49:50 PM PDT 24
Peak memory 218972 kb
Host smart-21e5a20c-b5d7-4d49-8f2b-177eda3a7a12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3165664118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3165664118
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3222255971
Short name T1534
Test name
Test status
Simulation time 866378144 ps
CPU time 3.8 seconds
Started Mar 10 02:47:02 PM PDT 24
Finished Mar 10 02:47:06 PM PDT 24
Peak memory 217840 kb
Host smart-437a8a18-f93d-4e23-bbba-f3fba99fee0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3222255971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3222255971
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.102848522
Short name T698
Test name
Test status
Simulation time 387852523960 ps
CPU time 612.14 seconds
Started Mar 10 01:49:51 PM PDT 24
Finished Mar 10 02:00:03 PM PDT 24
Peak memory 256780 kb
Host smart-627d4df0-fc92-4816-94e7-709fad858745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102848522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.102848522
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3742945839
Short name T1008
Test name
Test status
Simulation time 39757743588 ps
CPU time 53.1 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:50:40 PM PDT 24
Peak memory 215792 kb
Host smart-3705cdf5-5ecb-44be-bdfb-8581b90fd471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742945839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3742945839
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.977338733
Short name T43
Test name
Test status
Simulation time 5389539106 ps
CPU time 14.08 seconds
Started Mar 10 02:46:59 PM PDT 24
Finished Mar 10 02:47:14 PM PDT 24
Peak memory 215856 kb
Host smart-a2aa8065-2ba6-4322-b94b-816984a5b3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977338733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.977338733
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1605603113
Short name T1665
Test name
Test status
Simulation time 5884618166 ps
CPU time 12.17 seconds
Started Mar 10 02:46:49 PM PDT 24
Finished Mar 10 02:47:01 PM PDT 24
Peak memory 215840 kb
Host smart-003dd8c8-8b1a-4fe8-833f-1a70b3218f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605603113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1605603113
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1981261024
Short name T1090
Test name
Test status
Simulation time 5401888903 ps
CPU time 5.22 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:49:52 PM PDT 24
Peak memory 215768 kb
Host smart-3d18d4d5-0969-47e6-a981-8d3a2ae42192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981261024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1981261024
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4070072074
Short name T694
Test name
Test status
Simulation time 51167477 ps
CPU time 1.29 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:49:48 PM PDT 24
Peak memory 207712 kb
Host smart-02ba3508-d33c-4bfd-b334-58fee7348916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070072074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4070072074
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.479113976
Short name T988
Test name
Test status
Simulation time 985184201 ps
CPU time 8.16 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:47:05 PM PDT 24
Peak memory 217004 kb
Host smart-603f9632-64d3-45bf-888a-5352dda6aca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479113976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.479113976
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2815356300
Short name T673
Test name
Test status
Simulation time 89341038 ps
CPU time 0.7 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:46:56 PM PDT 24
Peak memory 204904 kb
Host smart-2ba8be5e-7b69-4459-9d49-bdcc6437ea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815356300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2815356300
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3465455868
Short name T958
Test name
Test status
Simulation time 262910950 ps
CPU time 0.88 seconds
Started Mar 10 01:49:45 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 205176 kb
Host smart-f22e1d01-355d-40e6-9ad0-e7faaf76c256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465455868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3465455868
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2090738875
Short name T78
Test name
Test status
Simulation time 17400140600 ps
CPU time 15.1 seconds
Started Mar 10 02:46:54 PM PDT 24
Finished Mar 10 02:47:09 PM PDT 24
Peak memory 232948 kb
Host smart-1e3d4b80-22fb-4887-9abf-3ea5d61d3449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090738875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2090738875
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_upload.3633101101
Short name T1349
Test name
Test status
Simulation time 3409914276 ps
CPU time 5.37 seconds
Started Mar 10 01:49:46 PM PDT 24
Finished Mar 10 01:49:52 PM PDT 24
Peak memory 232916 kb
Host smart-b6a0becb-d889-4df8-b8ab-5a239700c2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633101101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3633101101
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.162746115
Short name T436
Test name
Test status
Simulation time 25088951 ps
CPU time 0.71 seconds
Started Mar 10 01:49:58 PM PDT 24
Finished Mar 10 01:49:59 PM PDT 24
Peak memory 203712 kb
Host smart-59a1dc98-2dae-4047-8fcd-71a24dad1abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162746115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.162746115
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4182287741
Short name T1182
Test name
Test status
Simulation time 18613303 ps
CPU time 0.7 seconds
Started Mar 10 02:47:00 PM PDT 24
Finished Mar 10 02:47:01 PM PDT 24
Peak memory 203896 kb
Host smart-569701b6-77a3-49f5-a531-8af897fb7fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182287741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4182287741
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4245107807
Short name T350
Test name
Test status
Simulation time 214105935 ps
CPU time 2.18 seconds
Started Mar 10 02:46:56 PM PDT 24
Finished Mar 10 02:46:58 PM PDT 24
Peak memory 223772 kb
Host smart-25d2d6a1-273f-4aa2-ba98-b7b3739fecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245107807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4245107807
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.635947542
Short name T1898
Test name
Test status
Simulation time 1687918287 ps
CPU time 7.53 seconds
Started Mar 10 01:49:52 PM PDT 24
Finished Mar 10 01:50:00 PM PDT 24
Peak memory 223876 kb
Host smart-ac8aa35d-0452-43c1-8908-4dc688457e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635947542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.635947542
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.256684655
Short name T1889
Test name
Test status
Simulation time 26004604 ps
CPU time 0.75 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:46:58 PM PDT 24
Peak memory 204820 kb
Host smart-f65fab33-5e02-4040-a620-5d6937bb4f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256684655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.256684655
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3998250367
Short name T800
Test name
Test status
Simulation time 23980674 ps
CPU time 0.79 seconds
Started Mar 10 01:49:50 PM PDT 24
Finished Mar 10 01:49:51 PM PDT 24
Peak memory 205484 kb
Host smart-7a64fff5-6f52-4ead-b692-e954c8149ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998250367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3998250367
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1929724772
Short name T751
Test name
Test status
Simulation time 20635278755 ps
CPU time 96.36 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:48:35 PM PDT 24
Peak memory 248536 kb
Host smart-bd534818-efab-4df7-85b6-d34a7e032877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929724772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1929724772
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.730558503
Short name T897
Test name
Test status
Simulation time 2949815322 ps
CPU time 22.93 seconds
Started Mar 10 01:49:54 PM PDT 24
Finished Mar 10 01:50:17 PM PDT 24
Peak memory 235456 kb
Host smart-2170e3c8-c466-49f2-9ffc-19bf07b5ee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730558503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.730558503
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.139969646
Short name T1140
Test name
Test status
Simulation time 212585937469 ps
CPU time 267.75 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:51:23 PM PDT 24
Peak memory 249644 kb
Host smart-88dd4819-c9d4-4edb-93b0-df33977802b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139969646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.139969646
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2177944993
Short name T356
Test name
Test status
Simulation time 3739620051 ps
CPU time 26.47 seconds
Started Mar 10 01:49:54 PM PDT 24
Finished Mar 10 01:50:20 PM PDT 24
Peak memory 233356 kb
Host smart-45c9c5a0-8f21-4a4a-9b5f-90185f73a28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177944993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2177944993
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4209847824
Short name T748
Test name
Test status
Simulation time 236794807865 ps
CPU time 257.04 seconds
Started Mar 10 01:49:55 PM PDT 24
Finished Mar 10 01:54:12 PM PDT 24
Peak memory 255992 kb
Host smart-27d288fb-4a9d-4d6b-bf6a-1bcba17d3217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209847824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4209847824
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4219762277
Short name T168
Test name
Test status
Simulation time 55290801297 ps
CPU time 201.52 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:50:19 PM PDT 24
Peak memory 252296 kb
Host smart-560b1076-a83c-4bd6-ab52-2a08477c876f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219762277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4219762277
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2817561193
Short name T1489
Test name
Test status
Simulation time 34725919970 ps
CPU time 46.24 seconds
Started Mar 10 02:46:56 PM PDT 24
Finished Mar 10 02:47:43 PM PDT 24
Peak memory 239212 kb
Host smart-e7862f9e-d518-4efb-94da-2e540442382b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817561193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2817561193
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4191380728
Short name T1232
Test name
Test status
Simulation time 796986987 ps
CPU time 12.45 seconds
Started Mar 10 01:49:50 PM PDT 24
Finished Mar 10 01:50:02 PM PDT 24
Peak memory 240208 kb
Host smart-3d5ab881-fd69-4f02-83b2-7fffb6e760ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191380728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4191380728
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3205731592
Short name T1021
Test name
Test status
Simulation time 16330653310 ps
CPU time 10.7 seconds
Started Mar 10 02:46:59 PM PDT 24
Finished Mar 10 02:47:10 PM PDT 24
Peak memory 232468 kb
Host smart-91d8d916-9d9f-44fb-a567-4ef1da9f59c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205731592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3205731592
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3841027459
Short name T1227
Test name
Test status
Simulation time 10365425670 ps
CPU time 7.51 seconds
Started Mar 10 01:49:53 PM PDT 24
Finished Mar 10 01:50:01 PM PDT 24
Peak memory 223972 kb
Host smart-7b7c977c-50c6-46de-b8fa-dc6af14efeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841027459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3841027459
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1081755609
Short name T853
Test name
Test status
Simulation time 476500936 ps
CPU time 8.4 seconds
Started Mar 10 01:49:52 PM PDT 24
Finished Mar 10 01:50:00 PM PDT 24
Peak memory 229976 kb
Host smart-7e2fd1b2-1e94-496c-af2d-499c7b505c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081755609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1081755609
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3940987071
Short name T194
Test name
Test status
Simulation time 8121972630 ps
CPU time 18.12 seconds
Started Mar 10 02:46:59 PM PDT 24
Finished Mar 10 02:47:17 PM PDT 24
Peak memory 244476 kb
Host smart-616501af-1d46-4d93-a43c-18217dff2719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940987071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3940987071
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1298286456
Short name T1859
Test name
Test status
Simulation time 16035285 ps
CPU time 0.99 seconds
Started Mar 10 02:46:59 PM PDT 24
Finished Mar 10 02:47:00 PM PDT 24
Peak memory 217312 kb
Host smart-7127ab0e-90d6-4ab4-910b-41ad460f50b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298286456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1298286456
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2979740312
Short name T1754
Test name
Test status
Simulation time 30317215 ps
CPU time 1.11 seconds
Started Mar 10 01:49:53 PM PDT 24
Finished Mar 10 01:49:54 PM PDT 24
Peak memory 217304 kb
Host smart-32ddd60e-cced-4d33-8f8c-2d79cfad76c6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979740312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2979740312
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1353172322
Short name T1188
Test name
Test status
Simulation time 11640837023 ps
CPU time 33.47 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 229160 kb
Host smart-bc20f803-8639-4500-a7e0-39022485935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353172322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1353172322
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.296827451
Short name T1901
Test name
Test status
Simulation time 1675838777 ps
CPU time 6.46 seconds
Started Mar 10 01:49:51 PM PDT 24
Finished Mar 10 01:49:58 PM PDT 24
Peak memory 231868 kb
Host smart-5fb423dd-1fd2-415a-a322-e477256ce270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296827451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.296827451
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.272719989
Short name T1321
Test name
Test status
Simulation time 244036262 ps
CPU time 3.94 seconds
Started Mar 10 01:49:50 PM PDT 24
Finished Mar 10 01:49:54 PM PDT 24
Peak memory 223792 kb
Host smart-cc0db529-5cd7-4a7d-a334-250980b3dfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272719989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.272719989
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3988071529
Short name T347
Test name
Test status
Simulation time 491767936 ps
CPU time 2.57 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:47:01 PM PDT 24
Peak memory 232124 kb
Host smart-4b1b30c7-3b9e-432c-9af6-49c5faffdc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988071529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3988071529
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1141150877
Short name T1259
Test name
Test status
Simulation time 31731505 ps
CPU time 0.75 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:46:58 PM PDT 24
Peak memory 215640 kb
Host smart-dc7a21c9-ddf8-4ddf-9b2f-45e8d1244d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141150877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1141150877
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.267591664
Short name T305
Test name
Test status
Simulation time 91819842 ps
CPU time 0.71 seconds
Started Mar 10 01:49:52 PM PDT 24
Finished Mar 10 01:49:53 PM PDT 24
Peak memory 215624 kb
Host smart-5b27a7ec-2f96-4443-b10b-14649f84b7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267591664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.267591664
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3528726002
Short name T1491
Test name
Test status
Simulation time 514798848 ps
CPU time 3.99 seconds
Started Mar 10 01:49:56 PM PDT 24
Finished Mar 10 01:50:00 PM PDT 24
Peak memory 218472 kb
Host smart-c2801a9d-6fc1-4eb3-a136-824c0e10460a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3528726002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3528726002
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.868059522
Short name T1816
Test name
Test status
Simulation time 968449985 ps
CPU time 3.86 seconds
Started Mar 10 02:47:02 PM PDT 24
Finished Mar 10 02:47:06 PM PDT 24
Peak memory 218408 kb
Host smart-c2621f34-cabe-4b03-9202-370cf8b92c1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=868059522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.868059522
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2527717746
Short name T1016
Test name
Test status
Simulation time 634004755150 ps
CPU time 679.89 seconds
Started Mar 10 02:47:01 PM PDT 24
Finished Mar 10 02:58:21 PM PDT 24
Peak memory 270996 kb
Host smart-e02dc2e5-31b3-456d-adb3-cdf342c7208b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527717746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2527717746
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.890506810
Short name T927
Test name
Test status
Simulation time 52310191344 ps
CPU time 354.37 seconds
Started Mar 10 01:49:56 PM PDT 24
Finished Mar 10 01:55:51 PM PDT 24
Peak memory 283924 kb
Host smart-b9ea7296-0d75-4206-beb3-8a5f7d6c3aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890506810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.890506810
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1967802122
Short name T1567
Test name
Test status
Simulation time 3153416820 ps
CPU time 20.58 seconds
Started Mar 10 01:49:50 PM PDT 24
Finished Mar 10 01:50:10 PM PDT 24
Peak memory 215840 kb
Host smart-b5a653c2-4669-4137-a253-8fda15c6a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967802122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1967802122
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3997408136
Short name T1055
Test name
Test status
Simulation time 15296782304 ps
CPU time 42.44 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:47:41 PM PDT 24
Peak memory 215800 kb
Host smart-929e665d-d761-4cf0-90ce-0cf1cf3ceb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997408136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3997408136
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3771240562
Short name T559
Test name
Test status
Simulation time 40326216629 ps
CPU time 23.36 seconds
Started Mar 10 02:46:57 PM PDT 24
Finished Mar 10 02:47:21 PM PDT 24
Peak memory 215776 kb
Host smart-0c89be02-4238-4f33-b841-2c3c98209f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771240562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3771240562
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.524546543
Short name T355
Test name
Test status
Simulation time 16629208495 ps
CPU time 23.78 seconds
Started Mar 10 01:49:50 PM PDT 24
Finished Mar 10 01:50:14 PM PDT 24
Peak memory 215768 kb
Host smart-943be01e-3ec0-4ce1-bcde-ed7e8c2ad30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524546543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.524546543
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1761361329
Short name T701
Test name
Test status
Simulation time 676789497 ps
CPU time 2.51 seconds
Started Mar 10 01:49:51 PM PDT 24
Finished Mar 10 01:49:54 PM PDT 24
Peak memory 215716 kb
Host smart-54ddfc6b-ae30-445f-9cac-db891270718b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761361329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1761361329
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2055400920
Short name T1500
Test name
Test status
Simulation time 134690368 ps
CPU time 1.21 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:46:59 PM PDT 24
Peak memory 207356 kb
Host smart-85c5dbdc-ec61-47e1-a65b-27b8ac4cb41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055400920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2055400920
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1171519199
Short name T1043
Test name
Test status
Simulation time 82338071 ps
CPU time 0.79 seconds
Started Mar 10 02:46:59 PM PDT 24
Finished Mar 10 02:47:00 PM PDT 24
Peak memory 204840 kb
Host smart-ee0bf57b-8329-43e0-b5a6-daeff6f9f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171519199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1171519199
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2221799761
Short name T379
Test name
Test status
Simulation time 276333597 ps
CPU time 0.92 seconds
Started Mar 10 01:49:48 PM PDT 24
Finished Mar 10 01:49:49 PM PDT 24
Peak memory 204880 kb
Host smart-0dea47af-52e3-47f8-9c68-fbe8ce4090e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221799761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2221799761
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1448778230
Short name T161
Test name
Test status
Simulation time 7202408624 ps
CPU time 22.57 seconds
Started Mar 10 02:46:56 PM PDT 24
Finished Mar 10 02:47:19 PM PDT 24
Peak memory 234448 kb
Host smart-f98c7a42-027d-4ece-a0cb-c6e98f048785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448778230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1448778230
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_upload.3918359073
Short name T517
Test name
Test status
Simulation time 17664475975 ps
CPU time 27.26 seconds
Started Mar 10 01:49:49 PM PDT 24
Finished Mar 10 01:50:17 PM PDT 24
Peak memory 234748 kb
Host smart-d3c8cae4-3af5-4c0f-b72f-595eda018081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918359073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3918359073
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1851661247
Short name T1439
Test name
Test status
Simulation time 17830109 ps
CPU time 0.77 seconds
Started Mar 10 01:50:00 PM PDT 24
Finished Mar 10 01:50:01 PM PDT 24
Peak memory 204472 kb
Host smart-0e16e4db-fe88-44f8-be21-7f82c5933ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851661247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1851661247
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.472742068
Short name T886
Test name
Test status
Simulation time 22208425 ps
CPU time 0.72 seconds
Started Mar 10 02:47:00 PM PDT 24
Finished Mar 10 02:47:01 PM PDT 24
Peak memory 204432 kb
Host smart-0aa6a252-ee55-46c2-991a-78438834427f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472742068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.472742068
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.20842407
Short name T1804
Test name
Test status
Simulation time 487608957 ps
CPU time 2.77 seconds
Started Mar 10 01:50:00 PM PDT 24
Finished Mar 10 01:50:03 PM PDT 24
Peak memory 223908 kb
Host smart-cbe61e37-0f40-40f0-ab6d-b51a402222c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20842407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.20842407
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3003664574
Short name T1758
Test name
Test status
Simulation time 440295769 ps
CPU time 3.13 seconds
Started Mar 10 02:47:00 PM PDT 24
Finished Mar 10 02:47:03 PM PDT 24
Peak memory 217940 kb
Host smart-5a38ba91-2bde-47a5-ab5e-32af37d09213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003664574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3003664574
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2109958722
Short name T466
Test name
Test status
Simulation time 135792307 ps
CPU time 0.75 seconds
Started Mar 10 01:49:56 PM PDT 24
Finished Mar 10 01:49:58 PM PDT 24
Peak memory 204844 kb
Host smart-1f0d79ee-5fbe-44a2-b0ee-59225c071175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109958722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2109958722
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3140895899
Short name T1826
Test name
Test status
Simulation time 20883922 ps
CPU time 0.8 seconds
Started Mar 10 02:47:00 PM PDT 24
Finished Mar 10 02:47:01 PM PDT 24
Peak memory 205512 kb
Host smart-95dc05a4-1dab-47a1-90dd-507545812c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140895899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3140895899
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1757515524
Short name T213
Test name
Test status
Simulation time 86731386770 ps
CPU time 138.22 seconds
Started Mar 10 02:47:02 PM PDT 24
Finished Mar 10 02:49:20 PM PDT 24
Peak memory 248568 kb
Host smart-454ed85c-088c-4fd9-a2c7-738e20979b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757515524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1757515524
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1946400060
Short name T1774
Test name
Test status
Simulation time 238286532215 ps
CPU time 549.54 seconds
Started Mar 10 01:50:00 PM PDT 24
Finished Mar 10 01:59:10 PM PDT 24
Peak memory 256716 kb
Host smart-6fb7ee11-6f1a-4b22-b275-ebaf86df4ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946400060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1946400060
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1029139030
Short name T44
Test name
Test status
Simulation time 6552631477 ps
CPU time 57.2 seconds
Started Mar 10 01:49:59 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 233232 kb
Host smart-4dc16ba0-93e8-4dd8-bbbf-6a2021c9a542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029139030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1029139030
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1790019575
Short name T135
Test name
Test status
Simulation time 7611967906 ps
CPU time 82.53 seconds
Started Mar 10 02:46:59 PM PDT 24
Finished Mar 10 02:48:22 PM PDT 24
Peak memory 251664 kb
Host smart-d0d47ee2-d56f-4c99-93cc-9700c60b94be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790019575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1790019575
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.139707610
Short name T1589
Test name
Test status
Simulation time 25113330839 ps
CPU time 110.8 seconds
Started Mar 10 01:50:01 PM PDT 24
Finished Mar 10 01:51:52 PM PDT 24
Peak memory 272152 kb
Host smart-22e2f003-15f6-4b23-9f4a-7baa323654a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139707610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.139707610
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.306710405
Short name T204
Test name
Test status
Simulation time 61113143366 ps
CPU time 263.76 seconds
Started Mar 10 02:47:02 PM PDT 24
Finished Mar 10 02:51:27 PM PDT 24
Peak memory 254840 kb
Host smart-c951ca35-e479-48a6-8f88-d4ee27b99b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306710405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.306710405
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1280539010
Short name T481
Test name
Test status
Simulation time 6010554242 ps
CPU time 41.28 seconds
Started Mar 10 02:47:03 PM PDT 24
Finished Mar 10 02:47:44 PM PDT 24
Peak memory 240308 kb
Host smart-72b9f7bd-692e-4baa-9e55-2384ca9dbd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280539010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1280539010
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2418815833
Short name T1669
Test name
Test status
Simulation time 5963573986 ps
CPU time 16.17 seconds
Started Mar 10 01:50:01 PM PDT 24
Finished Mar 10 01:50:18 PM PDT 24
Peak memory 236340 kb
Host smart-81cb1191-299b-4098-a6e2-a31c25aeafea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418815833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2418815833
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2270797503
Short name T1284
Test name
Test status
Simulation time 1226033238 ps
CPU time 6.19 seconds
Started Mar 10 01:50:02 PM PDT 24
Finished Mar 10 01:50:08 PM PDT 24
Peak memory 217452 kb
Host smart-317cde90-ece7-449e-8bb5-369c62470e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270797503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2270797503
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3444674546
Short name T2
Test name
Test status
Simulation time 12794920947 ps
CPU time 10.37 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:47:19 PM PDT 24
Peak memory 217232 kb
Host smart-60971c1e-b4be-47f1-8443-7b8948233919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444674546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3444674546
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2083957492
Short name T351
Test name
Test status
Simulation time 17234906793 ps
CPU time 13.7 seconds
Started Mar 10 02:47:02 PM PDT 24
Finished Mar 10 02:47:17 PM PDT 24
Peak memory 216596 kb
Host smart-77850fd0-a34f-4ba8-b051-9a87780f2f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083957492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2083957492
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2103152767
Short name T1813
Test name
Test status
Simulation time 2891949418 ps
CPU time 6.4 seconds
Started Mar 10 01:50:01 PM PDT 24
Finished Mar 10 01:50:08 PM PDT 24
Peak memory 232144 kb
Host smart-7d8011f1-5db8-42bb-bda3-7067e3838654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103152767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2103152767
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.305825476
Short name T24
Test name
Test status
Simulation time 60487704 ps
CPU time 1.06 seconds
Started Mar 10 02:47:01 PM PDT 24
Finished Mar 10 02:47:02 PM PDT 24
Peak memory 215992 kb
Host smart-cfcf725d-d70d-46c8-ab82-dfa6b8a9367d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305825476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.305825476
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.4018243649
Short name T791
Test name
Test status
Simulation time 89625739 ps
CPU time 1.12 seconds
Started Mar 10 01:49:56 PM PDT 24
Finished Mar 10 01:49:57 PM PDT 24
Peak memory 216080 kb
Host smart-ee767ea3-44e1-4dfb-bbad-4691867305cc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018243649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.4018243649
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.110958015
Short name T1352
Test name
Test status
Simulation time 17194955094 ps
CPU time 11.57 seconds
Started Mar 10 01:49:58 PM PDT 24
Finished Mar 10 01:50:10 PM PDT 24
Peak memory 246752 kb
Host smart-168098b8-66f0-4b65-87c2-e895c1bda07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110958015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.110958015
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3840529120
Short name T699
Test name
Test status
Simulation time 2187620783 ps
CPU time 5.3 seconds
Started Mar 10 02:46:59 PM PDT 24
Finished Mar 10 02:47:04 PM PDT 24
Peak memory 237140 kb
Host smart-035d4f02-9616-4774-a574-c60c3fea45bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840529120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3840529120
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2476144190
Short name T529
Test name
Test status
Simulation time 24353034532 ps
CPU time 7.35 seconds
Started Mar 10 01:49:59 PM PDT 24
Finished Mar 10 01:50:07 PM PDT 24
Peak memory 232944 kb
Host smart-13a0122e-009d-4450-8dc5-39734f65496e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476144190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2476144190
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3089846548
Short name T1827
Test name
Test status
Simulation time 456077674 ps
CPU time 3.43 seconds
Started Mar 10 02:47:00 PM PDT 24
Finished Mar 10 02:47:04 PM PDT 24
Peak memory 217248 kb
Host smart-cca8dfa2-23a6-4753-9658-6888ac4534fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089846548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3089846548
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1243694571
Short name T1692
Test name
Test status
Simulation time 15733494 ps
CPU time 0.75 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:47:00 PM PDT 24
Peak memory 215644 kb
Host smart-d8de1989-5a8f-4c4a-a223-064c7ad484ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243694571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1243694571
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2565117268
Short name T616
Test name
Test status
Simulation time 36244572 ps
CPU time 0.73 seconds
Started Mar 10 01:49:57 PM PDT 24
Finished Mar 10 01:49:59 PM PDT 24
Peak memory 215584 kb
Host smart-da9a9b73-1d80-46ae-84e9-362105c76073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565117268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2565117268
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1125669158
Short name T1094
Test name
Test status
Simulation time 15924430086 ps
CPU time 6.48 seconds
Started Mar 10 02:47:00 PM PDT 24
Finished Mar 10 02:47:06 PM PDT 24
Peak memory 222420 kb
Host smart-cd35c6c4-d40f-475f-88c5-456db9cd47af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1125669158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1125669158
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1328295626
Short name T1335
Test name
Test status
Simulation time 2037852561 ps
CPU time 5.37 seconds
Started Mar 10 01:50:00 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 221512 kb
Host smart-91437954-ca18-4755-bbff-270210ae2f05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1328295626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1328295626
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2013313444
Short name T1792
Test name
Test status
Simulation time 201752341 ps
CPU time 1.23 seconds
Started Mar 10 02:47:01 PM PDT 24
Finished Mar 10 02:47:02 PM PDT 24
Peak memory 206376 kb
Host smart-46a14787-85b9-4bac-b755-aa15aa52d42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013313444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2013313444
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.652747796
Short name T270
Test name
Test status
Simulation time 242875292894 ps
CPU time 456.85 seconds
Started Mar 10 01:49:59 PM PDT 24
Finished Mar 10 01:57:36 PM PDT 24
Peak memory 266704 kb
Host smart-50d39a12-8100-492f-9ddb-547d59ae09eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652747796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.652747796
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1164905590
Short name T278
Test name
Test status
Simulation time 3897129226 ps
CPU time 26.41 seconds
Started Mar 10 01:49:55 PM PDT 24
Finished Mar 10 01:50:22 PM PDT 24
Peak memory 215760 kb
Host smart-4208f24f-ee08-4163-818c-7a8cf5c5cc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164905590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1164905590
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.292128301
Short name T905
Test name
Test status
Simulation time 2276911166 ps
CPU time 31.38 seconds
Started Mar 10 02:47:00 PM PDT 24
Finished Mar 10 02:47:32 PM PDT 24
Peak memory 215796 kb
Host smart-cf1436ae-9d96-4234-af38-8cc2519c0d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292128301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.292128301
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2227513627
Short name T1435
Test name
Test status
Simulation time 1221928784 ps
CPU time 6.27 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:47:04 PM PDT 24
Peak memory 215768 kb
Host smart-b8a164c6-137c-42eb-8233-a286692e1e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227513627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2227513627
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.993467353
Short name T1779
Test name
Test status
Simulation time 3176050990 ps
CPU time 3.83 seconds
Started Mar 10 01:49:54 PM PDT 24
Finished Mar 10 01:49:58 PM PDT 24
Peak memory 215768 kb
Host smart-1e273d7f-dabd-499e-97e0-0d63c8e75864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993467353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.993467353
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1774078650
Short name T1127
Test name
Test status
Simulation time 59656284 ps
CPU time 1.27 seconds
Started Mar 10 01:49:57 PM PDT 24
Finished Mar 10 01:49:59 PM PDT 24
Peak memory 207588 kb
Host smart-7494d770-c35a-496c-90f1-451c20e0bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774078650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1774078650
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3537325558
Short name T527
Test name
Test status
Simulation time 60343112 ps
CPU time 2.85 seconds
Started Mar 10 02:47:04 PM PDT 24
Finished Mar 10 02:47:07 PM PDT 24
Peak memory 215732 kb
Host smart-8df4f1c1-4f93-402c-ac22-1ab43942e881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537325558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3537325558
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3045083492
Short name T1710
Test name
Test status
Simulation time 128695819 ps
CPU time 1.21 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:47:11 PM PDT 24
Peak memory 205876 kb
Host smart-ab0ad0da-2004-4c68-bde0-293ce2f1e96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045083492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3045083492
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.944554416
Short name T1609
Test name
Test status
Simulation time 423707169 ps
CPU time 1.09 seconds
Started Mar 10 01:49:56 PM PDT 24
Finished Mar 10 01:49:57 PM PDT 24
Peak memory 205888 kb
Host smart-e2d045c6-548a-4db8-bdd7-846a00463200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944554416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.944554416
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3053534547
Short name T1471
Test name
Test status
Simulation time 9663507951 ps
CPU time 30.75 seconds
Started Mar 10 02:47:03 PM PDT 24
Finished Mar 10 02:47:34 PM PDT 24
Peak memory 217128 kb
Host smart-6e03f378-64b6-4eb0-b5d3-0a48243fa77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053534547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3053534547
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_upload.338489852
Short name T1339
Test name
Test status
Simulation time 2484398983 ps
CPU time 10.66 seconds
Started Mar 10 01:49:59 PM PDT 24
Finished Mar 10 01:50:10 PM PDT 24
Peak memory 232616 kb
Host smart-f26cc348-5da6-4e03-94c5-e621be8f6842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338489852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.338489852
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2240853493
Short name T444
Test name
Test status
Simulation time 25512813 ps
CPU time 0.72 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 204284 kb
Host smart-95741494-7c7e-4523-b72b-c3b47432137d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240853493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2240853493
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3884125073
Short name T1508
Test name
Test status
Simulation time 14847491 ps
CPU time 0.77 seconds
Started Mar 10 02:47:06 PM PDT 24
Finished Mar 10 02:47:07 PM PDT 24
Peak memory 204784 kb
Host smart-11272079-0a05-4d8f-8f4f-81724bfc3906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884125073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3884125073
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1005500760
Short name T1619
Test name
Test status
Simulation time 4849608761 ps
CPU time 5.48 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:47:14 PM PDT 24
Peak memory 217536 kb
Host smart-d1b557fb-2c4c-44ec-bac8-4fd9c80807a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005500760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1005500760
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2193507869
Short name T614
Test name
Test status
Simulation time 195717180 ps
CPU time 2.98 seconds
Started Mar 10 01:50:08 PM PDT 24
Finished Mar 10 01:50:11 PM PDT 24
Peak memory 223828 kb
Host smart-538e1345-ac83-4555-9c73-efe2fc245fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193507869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2193507869
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.282380742
Short name T416
Test name
Test status
Simulation time 26930692 ps
CPU time 0.77 seconds
Started Mar 10 02:47:02 PM PDT 24
Finished Mar 10 02:47:04 PM PDT 24
Peak memory 205496 kb
Host smart-5a02fdfc-3106-4cd4-9841-fc7345f2a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282380742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.282380742
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4159922800
Short name T1453
Test name
Test status
Simulation time 61737687 ps
CPU time 0.78 seconds
Started Mar 10 01:50:00 PM PDT 24
Finished Mar 10 01:50:01 PM PDT 24
Peak memory 205864 kb
Host smart-70c36661-4bd8-4347-ace1-531dbc15e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159922800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4159922800
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1398247045
Short name T1515
Test name
Test status
Simulation time 25018959613 ps
CPU time 40.72 seconds
Started Mar 10 02:47:08 PM PDT 24
Finished Mar 10 02:47:49 PM PDT 24
Peak memory 236312 kb
Host smart-3dcb3f95-b26d-4392-b303-5055378eb500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398247045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1398247045
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3873182139
Short name T1424
Test name
Test status
Simulation time 31115335559 ps
CPU time 153.45 seconds
Started Mar 10 01:50:03 PM PDT 24
Finished Mar 10 01:52:37 PM PDT 24
Peak memory 240372 kb
Host smart-86b1dda5-bca3-4f3a-9193-8d02083dbb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873182139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3873182139
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1682603603
Short name T598
Test name
Test status
Simulation time 57566073315 ps
CPU time 61.63 seconds
Started Mar 10 02:47:05 PM PDT 24
Finished Mar 10 02:48:07 PM PDT 24
Peak memory 222124 kb
Host smart-900566ef-b343-4dd9-abc0-d9fed361e5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682603603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1682603603
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1842436942
Short name T738
Test name
Test status
Simulation time 82677948710 ps
CPU time 310.12 seconds
Started Mar 10 01:50:04 PM PDT 24
Finished Mar 10 01:55:15 PM PDT 24
Peak memory 259568 kb
Host smart-a6fdab10-2667-45d3-a554-77b2afbdb945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842436942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1842436942
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2600598050
Short name T845
Test name
Test status
Simulation time 26173010929 ps
CPU time 194.84 seconds
Started Mar 10 01:50:04 PM PDT 24
Finished Mar 10 01:53:20 PM PDT 24
Peak memory 248672 kb
Host smart-32861f68-7915-4dd5-8bf6-a76aa8558422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600598050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2600598050
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.937767109
Short name T1643
Test name
Test status
Simulation time 27791567279 ps
CPU time 174.91 seconds
Started Mar 10 02:47:06 PM PDT 24
Finished Mar 10 02:50:01 PM PDT 24
Peak memory 250224 kb
Host smart-f06acba9-bf2e-499f-8830-a4917d1a84fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937767109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.937767109
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1242242490
Short name T1254
Test name
Test status
Simulation time 1726112842 ps
CPU time 23.21 seconds
Started Mar 10 02:47:06 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 247860 kb
Host smart-cc015384-e38b-450b-ab4f-143f4880d9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242242490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1242242490
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2686018473
Short name T1158
Test name
Test status
Simulation time 19872630002 ps
CPU time 46.16 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:51 PM PDT 24
Peak memory 239600 kb
Host smart-024a4feb-3c2a-4fce-892f-5b4c03fdecd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686018473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2686018473
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1071184126
Short name T854
Test name
Test status
Simulation time 86533567 ps
CPU time 2.59 seconds
Started Mar 10 02:47:07 PM PDT 24
Finished Mar 10 02:47:10 PM PDT 24
Peak memory 217288 kb
Host smart-dcb36c65-c533-416e-af65-58aff4954a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071184126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1071184126
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3232690464
Short name T770
Test name
Test status
Simulation time 2853155229 ps
CPU time 9.36 seconds
Started Mar 10 01:50:08 PM PDT 24
Finished Mar 10 01:50:17 PM PDT 24
Peak memory 219796 kb
Host smart-4629f904-5d12-4ab3-904b-1501f414a072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232690464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3232690464
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1664563749
Short name T338
Test name
Test status
Simulation time 13456150548 ps
CPU time 21.8 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:27 PM PDT 24
Peak memory 240328 kb
Host smart-f818092f-0a71-4603-8ec7-f03a058cc363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664563749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1664563749
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3675491504
Short name T990
Test name
Test status
Simulation time 1677772037 ps
CPU time 5.06 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:47:16 PM PDT 24
Peak memory 218872 kb
Host smart-3d14b9a0-df4e-4722-b3c1-308edcbc4a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675491504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3675491504
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3709706678
Short name T1256
Test name
Test status
Simulation time 30608175 ps
CPU time 1.03 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 217280 kb
Host smart-9c4ad1cb-38d4-4413-b83d-2dcc8cccde2e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709706678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3709706678
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3887048267
Short name T370
Test name
Test status
Simulation time 27417590 ps
CPU time 1.07 seconds
Started Mar 10 02:47:05 PM PDT 24
Finished Mar 10 02:47:06 PM PDT 24
Peak memory 217296 kb
Host smart-2ecc7185-3842-4291-994a-1d79a7b3e81b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887048267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3887048267
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2716515995
Short name T271
Test name
Test status
Simulation time 11121282225 ps
CPU time 9.53 seconds
Started Mar 10 02:47:08 PM PDT 24
Finished Mar 10 02:47:17 PM PDT 24
Peak memory 233656 kb
Host smart-f8cceda9-60bf-4a3c-82d3-12f9e87331d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716515995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2716515995
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3007012349
Short name T314
Test name
Test status
Simulation time 4734152365 ps
CPU time 5.08 seconds
Started Mar 10 01:50:03 PM PDT 24
Finished Mar 10 01:50:09 PM PDT 24
Peak memory 223948 kb
Host smart-40e5221b-f901-4c8d-aeb6-fc647d550770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007012349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3007012349
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1734530749
Short name T469
Test name
Test status
Simulation time 4223571006 ps
CPU time 10.1 seconds
Started Mar 10 02:47:05 PM PDT 24
Finished Mar 10 02:47:15 PM PDT 24
Peak memory 221944 kb
Host smart-bb632968-8912-4ead-8b71-0abf2023b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734530749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1734530749
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1999078769
Short name T1040
Test name
Test status
Simulation time 2199723374 ps
CPU time 10.11 seconds
Started Mar 10 01:50:07 PM PDT 24
Finished Mar 10 01:50:18 PM PDT 24
Peak memory 232080 kb
Host smart-30ed8763-f3a7-4b0f-b5f7-ff7fb550052e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999078769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1999078769
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2956849135
Short name T1019
Test name
Test status
Simulation time 16393597 ps
CPU time 0.75 seconds
Started Mar 10 02:47:01 PM PDT 24
Finished Mar 10 02:47:02 PM PDT 24
Peak memory 215612 kb
Host smart-06b10926-6942-46d6-8c15-6b5118291e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956849135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2956849135
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.966145154
Short name T570
Test name
Test status
Simulation time 47795790 ps
CPU time 0.74 seconds
Started Mar 10 01:50:07 PM PDT 24
Finished Mar 10 01:50:09 PM PDT 24
Peak memory 215608 kb
Host smart-eb6fa29d-2fe7-4c50-9f5a-d96578ac94b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966145154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.966145154
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2541448709
Short name T1393
Test name
Test status
Simulation time 2523870041 ps
CPU time 4.98 seconds
Started Mar 10 02:47:05 PM PDT 24
Finished Mar 10 02:47:10 PM PDT 24
Peak memory 216088 kb
Host smart-e941c5ac-57bc-4d64-ba58-4cd3b5150cf7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2541448709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2541448709
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3116705599
Short name T1302
Test name
Test status
Simulation time 208653289 ps
CPU time 4.42 seconds
Started Mar 10 01:50:04 PM PDT 24
Finished Mar 10 01:50:09 PM PDT 24
Peak memory 221940 kb
Host smart-e08eb811-92a9-4491-82d1-1b15e7d705ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3116705599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3116705599
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2593744410
Short name T150
Test name
Test status
Simulation time 20741260854 ps
CPU time 182.51 seconds
Started Mar 10 01:50:04 PM PDT 24
Finished Mar 10 01:53:07 PM PDT 24
Peak memory 256772 kb
Host smart-6d16d05c-8243-46b9-bafc-16273084cdaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593744410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2593744410
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3749457034
Short name T1510
Test name
Test status
Simulation time 327886936867 ps
CPU time 662.4 seconds
Started Mar 10 02:47:11 PM PDT 24
Finished Mar 10 02:58:14 PM PDT 24
Peak memory 257308 kb
Host smart-923810fc-42d2-4d83-995d-af9b456e9ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749457034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3749457034
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3187205371
Short name T989
Test name
Test status
Simulation time 4705752533 ps
CPU time 29.27 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:35 PM PDT 24
Peak memory 215772 kb
Host smart-61ca8ccc-fae8-4149-a76d-77b504fbf0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187205371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3187205371
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4071496681
Short name T574
Test name
Test status
Simulation time 2179926547 ps
CPU time 9.22 seconds
Started Mar 10 02:47:05 PM PDT 24
Finished Mar 10 02:47:15 PM PDT 24
Peak memory 209204 kb
Host smart-e442334f-adb6-4fd2-a32b-f612c7afea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071496681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4071496681
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.11087665
Short name T1786
Test name
Test status
Simulation time 5064396818 ps
CPU time 6.41 seconds
Started Mar 10 02:46:58 PM PDT 24
Finished Mar 10 02:47:05 PM PDT 24
Peak memory 215784 kb
Host smart-fe480c14-552c-41ec-a951-c6aff4eada2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11087665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.11087665
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2837780240
Short name T1421
Test name
Test status
Simulation time 198390076 ps
CPU time 2.09 seconds
Started Mar 10 01:50:06 PM PDT 24
Finished Mar 10 01:50:09 PM PDT 24
Peak memory 215568 kb
Host smart-91b0e302-b660-44ec-9f95-47352bee8bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837780240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2837780240
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1219104596
Short name T130
Test name
Test status
Simulation time 187698104 ps
CPU time 1.35 seconds
Started Mar 10 02:47:06 PM PDT 24
Finished Mar 10 02:47:07 PM PDT 24
Peak memory 215728 kb
Host smart-31bb7792-040c-4840-ae2a-6c50a6d0670d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219104596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1219104596
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3394498406
Short name T998
Test name
Test status
Simulation time 265549293 ps
CPU time 1.41 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:07 PM PDT 24
Peak memory 207464 kb
Host smart-c82a8aeb-2a25-44aa-a3fa-7b3901ddd90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394498406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3394498406
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1076200957
Short name T1660
Test name
Test status
Simulation time 172706742 ps
CPU time 0.73 seconds
Started Mar 10 02:47:06 PM PDT 24
Finished Mar 10 02:47:07 PM PDT 24
Peak memory 204856 kb
Host smart-834e4061-fe99-4b71-98b2-247cf0e9fc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076200957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1076200957
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.249688316
Short name T1269
Test name
Test status
Simulation time 140871047 ps
CPU time 0.9 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 204888 kb
Host smart-01f9a776-92e3-4e10-b7f1-d9508274ed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249688316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.249688316
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1371352670
Short name T1694
Test name
Test status
Simulation time 1420392845 ps
CPU time 10.16 seconds
Started Mar 10 01:50:06 PM PDT 24
Finished Mar 10 01:50:17 PM PDT 24
Peak memory 237772 kb
Host smart-a1e6ea4b-0aff-453c-8836-31a047c25cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371352670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1371352670
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_upload.342885955
Short name T1330
Test name
Test status
Simulation time 3105727875 ps
CPU time 5.01 seconds
Started Mar 10 02:47:08 PM PDT 24
Finished Mar 10 02:47:14 PM PDT 24
Peak memory 216784 kb
Host smart-3d2f1fa8-5e6c-4989-a01b-cb2b6951737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342885955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.342885955
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1011358196
Short name T1678
Test name
Test status
Simulation time 13196819 ps
CPU time 0.74 seconds
Started Mar 10 01:50:07 PM PDT 24
Finished Mar 10 01:50:08 PM PDT 24
Peak memory 204440 kb
Host smart-1feead79-c90d-4a52-a8e0-c893afb94261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011358196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1011358196
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1689171556
Short name T1741
Test name
Test status
Simulation time 14098779 ps
CPU time 0.72 seconds
Started Mar 10 02:47:16 PM PDT 24
Finished Mar 10 02:47:17 PM PDT 24
Peak memory 204400 kb
Host smart-290aafa4-7add-4944-ba90-b3c99eeab030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689171556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1689171556
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1660848927
Short name T291
Test name
Test status
Simulation time 5305616493 ps
CPU time 6.4 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:47:16 PM PDT 24
Peak memory 233184 kb
Host smart-d227c3c8-c334-46f7-9194-24a80cd9f058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660848927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1660848927
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3766499879
Short name T1709
Test name
Test status
Simulation time 159766903 ps
CPU time 2.35 seconds
Started Mar 10 01:50:11 PM PDT 24
Finished Mar 10 01:50:14 PM PDT 24
Peak memory 216932 kb
Host smart-4f43f3d4-6ff2-4627-bab5-916b83b23575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766499879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3766499879
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2118021318
Short name T313
Test name
Test status
Simulation time 22372676 ps
CPU time 0.81 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 205512 kb
Host smart-46a0ed5b-ddc9-40c4-a4dd-bb03aa1bec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118021318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2118021318
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2583380380
Short name T16
Test name
Test status
Simulation time 53810132 ps
CPU time 0.79 seconds
Started Mar 10 02:47:06 PM PDT 24
Finished Mar 10 02:47:07 PM PDT 24
Peak memory 204824 kb
Host smart-66b74d3b-008f-4b15-b18b-d75b62fcbc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583380380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2583380380
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1908637443
Short name T644
Test name
Test status
Simulation time 193268624358 ps
CPU time 106.92 seconds
Started Mar 10 01:50:10 PM PDT 24
Finished Mar 10 01:51:57 PM PDT 24
Peak memory 248548 kb
Host smart-0532aaad-874e-439a-b074-5db191a38467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908637443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1908637443
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2529689115
Short name T1625
Test name
Test status
Simulation time 47733460254 ps
CPU time 217.35 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:50:48 PM PDT 24
Peak memory 256104 kb
Host smart-99046c73-f8da-4efa-9780-3eee5dfa950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529689115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2529689115
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1871292836
Short name T1095
Test name
Test status
Simulation time 77733173348 ps
CPU time 189.27 seconds
Started Mar 10 01:50:11 PM PDT 24
Finished Mar 10 01:53:20 PM PDT 24
Peak memory 256216 kb
Host smart-323c0b48-2ae2-4f8c-b14c-94364cfd815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871292836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1871292836
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.480326982
Short name T1788
Test name
Test status
Simulation time 30777492345 ps
CPU time 263.91 seconds
Started Mar 10 02:47:15 PM PDT 24
Finished Mar 10 02:51:39 PM PDT 24
Peak memory 265096 kb
Host smart-d24747b1-ede1-4d59-84f8-10cb25d939ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480326982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.480326982
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1289573334
Short name T558
Test name
Test status
Simulation time 124429018270 ps
CPU time 159.31 seconds
Started Mar 10 02:47:12 PM PDT 24
Finished Mar 10 02:49:51 PM PDT 24
Peak memory 256920 kb
Host smart-274578f4-4643-4b91-8d5b-7c910a217e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289573334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1289573334
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2048512619
Short name T1724
Test name
Test status
Simulation time 19963947160 ps
CPU time 27.47 seconds
Started Mar 10 01:50:11 PM PDT 24
Finished Mar 10 01:50:39 PM PDT 24
Peak memory 237632 kb
Host smart-b697d3f4-c62c-4307-9955-caa2e06de20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048512619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2048512619
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.302543505
Short name T737
Test name
Test status
Simulation time 2002496274 ps
CPU time 22.06 seconds
Started Mar 10 02:47:07 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 247280 kb
Host smart-d07272bf-8203-4f2e-bd24-893993bfab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302543505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.302543505
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2486135285
Short name T202
Test name
Test status
Simulation time 3260013189 ps
CPU time 5.68 seconds
Started Mar 10 02:47:04 PM PDT 24
Finished Mar 10 02:47:10 PM PDT 24
Peak memory 217348 kb
Host smart-4be08836-a63f-4220-91ef-0216f1a5f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486135285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2486135285
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3962764091
Short name T198
Test name
Test status
Simulation time 23070292282 ps
CPU time 5.6 seconds
Started Mar 10 01:50:10 PM PDT 24
Finished Mar 10 01:50:16 PM PDT 24
Peak memory 217196 kb
Host smart-e12157e3-2c1a-4b00-8912-d5df9bdf1050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962764091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3962764091
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1114675689
Short name T1778
Test name
Test status
Simulation time 738182301 ps
CPU time 11.98 seconds
Started Mar 10 02:47:11 PM PDT 24
Finished Mar 10 02:47:23 PM PDT 24
Peak memory 235148 kb
Host smart-de1d3301-118f-4fcf-8d92-dbb07ae2c0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114675689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1114675689
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.749491674
Short name T864
Test name
Test status
Simulation time 1116426697 ps
CPU time 3.89 seconds
Started Mar 10 01:50:10 PM PDT 24
Finished Mar 10 01:50:14 PM PDT 24
Peak memory 232088 kb
Host smart-b1de4585-d26f-4a15-8f40-941e9c29a8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749491674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.749491674
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2168911071
Short name T383
Test name
Test status
Simulation time 198378208 ps
CPU time 1.04 seconds
Started Mar 10 01:50:07 PM PDT 24
Finished Mar 10 01:50:09 PM PDT 24
Peak memory 217196 kb
Host smart-37ac2793-c623-44ae-ba3e-034655827cf8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168911071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2168911071
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2450020538
Short name T1081
Test name
Test status
Simulation time 27419033 ps
CPU time 1 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:47:11 PM PDT 24
Peak memory 216008 kb
Host smart-93ec0223-33d9-4468-9472-63ad87d0556b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450020538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2450020538
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3060930905
Short name T631
Test name
Test status
Simulation time 50682217281 ps
CPU time 26.78 seconds
Started Mar 10 02:47:07 PM PDT 24
Finished Mar 10 02:47:34 PM PDT 24
Peak memory 252084 kb
Host smart-e3237ca9-755c-43c9-9c03-b71e31b20c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060930905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3060930905
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.32197034
Short name T1241
Test name
Test status
Simulation time 19945048293 ps
CPU time 19.04 seconds
Started Mar 10 01:50:14 PM PDT 24
Finished Mar 10 01:50:33 PM PDT 24
Peak memory 237380 kb
Host smart-0f223be2-b208-4a4f-a64f-5bca25b4e849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32197034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.32197034
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3353118948
Short name T1031
Test name
Test status
Simulation time 365667458 ps
CPU time 2.85 seconds
Started Mar 10 02:47:06 PM PDT 24
Finished Mar 10 02:47:09 PM PDT 24
Peak memory 217316 kb
Host smart-fc156511-3d43-4143-abaa-0c66e2e59507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353118948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3353118948
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.454446738
Short name T1002
Test name
Test status
Simulation time 22691318063 ps
CPU time 63.97 seconds
Started Mar 10 01:50:07 PM PDT 24
Finished Mar 10 01:51:12 PM PDT 24
Peak memory 239992 kb
Host smart-521aef08-68f6-4690-b25c-2f076cf5778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454446738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.454446738
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1869483087
Short name T77
Test name
Test status
Simulation time 19327628 ps
CPU time 0.74 seconds
Started Mar 10 02:47:04 PM PDT 24
Finished Mar 10 02:47:06 PM PDT 24
Peak memory 215616 kb
Host smart-d9f502ed-cd41-483e-bf1a-59f878f2f1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869483087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1869483087
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.3843886361
Short name T1042
Test name
Test status
Simulation time 15189566 ps
CPU time 0.73 seconds
Started Mar 10 01:50:05 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 215652 kb
Host smart-66f0cc62-44da-425d-afed-0fe8959a35d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843886361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.3843886361
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.313017125
Short name T810
Test name
Test status
Simulation time 2183677696 ps
CPU time 4.05 seconds
Started Mar 10 01:50:10 PM PDT 24
Finished Mar 10 01:50:14 PM PDT 24
Peak memory 215912 kb
Host smart-c38810c9-c272-4f09-9e38-a1532e38b0d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=313017125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.313017125
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4259712309
Short name T726
Test name
Test status
Simulation time 1044278597 ps
CPU time 3.63 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:47:13 PM PDT 24
Peak memory 219068 kb
Host smart-3597a016-e327-444d-9a81-d67eb2167a10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4259712309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4259712309
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2563714830
Short name T53
Test name
Test status
Simulation time 74159016218 ps
CPU time 334.98 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:52:44 PM PDT 24
Peak memory 265044 kb
Host smart-fadd0927-63b3-4677-a097-87bba48b5026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563714830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2563714830
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2693646498
Short name T1214
Test name
Test status
Simulation time 34769934035 ps
CPU time 203.61 seconds
Started Mar 10 01:50:08 PM PDT 24
Finished Mar 10 01:53:32 PM PDT 24
Peak memory 253792 kb
Host smart-0f857c92-6ac0-4397-8e2d-1348e4ff4d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693646498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2693646498
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1414134903
Short name T1920
Test name
Test status
Simulation time 4001281282 ps
CPU time 15.03 seconds
Started Mar 10 02:47:07 PM PDT 24
Finished Mar 10 02:47:22 PM PDT 24
Peak memory 215704 kb
Host smart-ca2ad846-3f60-43b8-b892-02b22c7bbc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414134903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1414134903
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2177764765
Short name T821
Test name
Test status
Simulation time 4584217256 ps
CPU time 29.84 seconds
Started Mar 10 01:50:08 PM PDT 24
Finished Mar 10 01:50:38 PM PDT 24
Peak memory 215860 kb
Host smart-1bca09a1-ee51-488e-a2d4-1a6c36241be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177764765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2177764765
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3854937209
Short name T1310
Test name
Test status
Simulation time 16427095019 ps
CPU time 18.58 seconds
Started Mar 10 01:50:06 PM PDT 24
Finished Mar 10 01:50:25 PM PDT 24
Peak memory 215868 kb
Host smart-da67bd08-a223-4f5f-9efa-ee47e6f48be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854937209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3854937209
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.588353699
Short name T398
Test name
Test status
Simulation time 32244443669 ps
CPU time 22.03 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:47:31 PM PDT 24
Peak memory 215792 kb
Host smart-5630abb9-60ab-45c3-a660-f6f7abeb1520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588353699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.588353699
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2316940340
Short name T1639
Test name
Test status
Simulation time 772563423 ps
CPU time 2.24 seconds
Started Mar 10 02:47:11 PM PDT 24
Finished Mar 10 02:47:13 PM PDT 24
Peak memory 215876 kb
Host smart-506d5e41-b533-45f5-87e1-fa7834a64396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316940340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2316940340
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.285274601
Short name T17
Test name
Test status
Simulation time 1377876749 ps
CPU time 2.21 seconds
Started Mar 10 01:50:14 PM PDT 24
Finished Mar 10 01:50:16 PM PDT 24
Peak memory 215780 kb
Host smart-3a6ab79b-1beb-42c3-b73f-f49e0ee6d688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285274601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.285274601
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3145795340
Short name T1224
Test name
Test status
Simulation time 125968950 ps
CPU time 0.93 seconds
Started Mar 10 01:50:10 PM PDT 24
Finished Mar 10 01:50:11 PM PDT 24
Peak memory 204804 kb
Host smart-c802ea8d-3b8e-405e-9816-c6979033d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145795340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3145795340
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3768771641
Short name T1652
Test name
Test status
Simulation time 244562530 ps
CPU time 1.41 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:47:12 PM PDT 24
Peak memory 205912 kb
Host smart-75075136-2be7-4fd1-a74d-2dcc77926a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768771641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3768771641
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1420104122
Short name T1602
Test name
Test status
Simulation time 860745846 ps
CPU time 9.58 seconds
Started Mar 10 01:50:08 PM PDT 24
Finished Mar 10 01:50:18 PM PDT 24
Peak memory 237764 kb
Host smart-29229025-145a-4ff0-aa1c-cea30c1d25bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420104122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1420104122
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_upload.880734739
Short name T1394
Test name
Test status
Simulation time 7187394322 ps
CPU time 7.18 seconds
Started Mar 10 02:47:08 PM PDT 24
Finished Mar 10 02:47:16 PM PDT 24
Peak memory 236484 kb
Host smart-b337d549-e065-4e05-b172-0d2c08a2dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880734739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.880734739
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3577513781
Short name T1894
Test name
Test status
Simulation time 38656424 ps
CPU time 0.72 seconds
Started Mar 10 01:50:20 PM PDT 24
Finished Mar 10 01:50:21 PM PDT 24
Peak memory 204800 kb
Host smart-302e0ab7-6435-4f4b-90ac-89eecc5c6933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577513781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3577513781
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3734134859
Short name T823
Test name
Test status
Simulation time 22660909 ps
CPU time 0.74 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:47:10 PM PDT 24
Peak memory 203884 kb
Host smart-6e44293c-1acf-48ca-977a-1e5ad57fd2f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734134859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3734134859
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1687431757
Short name T650
Test name
Test status
Simulation time 2802346096 ps
CPU time 8.48 seconds
Started Mar 10 01:50:16 PM PDT 24
Finished Mar 10 01:50:25 PM PDT 24
Peak memory 218288 kb
Host smart-f27f8e9c-c7e9-48c7-b2f8-e59ffbbd8536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687431757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1687431757
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2538718124
Short name T225
Test name
Test status
Simulation time 251282598 ps
CPU time 2.83 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:47:12 PM PDT 24
Peak memory 233940 kb
Host smart-0a022905-c655-4d97-9194-810e2eed83c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538718124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2538718124
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2695618481
Short name T1553
Test name
Test status
Simulation time 32780646 ps
CPU time 0.79 seconds
Started Mar 10 01:50:13 PM PDT 24
Finished Mar 10 01:50:14 PM PDT 24
Peak memory 204836 kb
Host smart-0bb4733d-62a9-4080-bb47-69cbd82b972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695618481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2695618481
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.383197490
Short name T1136
Test name
Test status
Simulation time 25770990 ps
CPU time 0.78 seconds
Started Mar 10 02:47:15 PM PDT 24
Finished Mar 10 02:47:16 PM PDT 24
Peak memory 205512 kb
Host smart-060b02ea-1cd6-4f38-bbfc-5ec6caf24aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383197490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.383197490
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1693441285
Short name T1379
Test name
Test status
Simulation time 11212950192 ps
CPU time 16.81 seconds
Started Mar 10 01:50:19 PM PDT 24
Finished Mar 10 01:50:36 PM PDT 24
Peak memory 240352 kb
Host smart-269ea3a1-cc4b-4249-9f6c-52c4456c15a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693441285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1693441285
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2287174652
Short name T812
Test name
Test status
Simulation time 10764829661 ps
CPU time 31 seconds
Started Mar 10 02:47:13 PM PDT 24
Finished Mar 10 02:47:44 PM PDT 24
Peak memory 240316 kb
Host smart-b06c31bd-c221-40a3-ab4d-487ce9c512c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287174652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2287174652
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.225256150
Short name T1524
Test name
Test status
Simulation time 14630717982 ps
CPU time 56.02 seconds
Started Mar 10 02:47:13 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 234856 kb
Host smart-06c371e8-6349-4707-a7a3-85aeeeeef695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225256150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.225256150
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.999605543
Short name T267
Test name
Test status
Simulation time 10669858976 ps
CPU time 87.7 seconds
Started Mar 10 01:50:19 PM PDT 24
Finished Mar 10 01:51:47 PM PDT 24
Peak memory 256580 kb
Host smart-e2538927-9d3d-42bd-bb5e-a6505c68080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999605543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.999605543
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.258881486
Short name T262
Test name
Test status
Simulation time 49436561151 ps
CPU time 60.43 seconds
Started Mar 10 01:50:19 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 261048 kb
Host smart-953897a3-94c8-438d-b328-1f12a7068578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258881486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.258881486
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.47705921
Short name T1406
Test name
Test status
Simulation time 135065920280 ps
CPU time 261.58 seconds
Started Mar 10 02:47:11 PM PDT 24
Finished Mar 10 02:51:33 PM PDT 24
Peak memory 254668 kb
Host smart-3cdf7fe4-9d2e-460b-ae8a-0880bbedb4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47705921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.47705921
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2338094212
Short name T542
Test name
Test status
Simulation time 831647767 ps
CPU time 16.58 seconds
Started Mar 10 01:50:19 PM PDT 24
Finished Mar 10 01:50:36 PM PDT 24
Peak memory 253508 kb
Host smart-88b183b2-abaa-4647-97e1-11269101685f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338094212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2338094212
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2703534617
Short name T128
Test name
Test status
Simulation time 8215966846 ps
CPU time 29.7 seconds
Started Mar 10 02:47:11 PM PDT 24
Finished Mar 10 02:47:41 PM PDT 24
Peak memory 232776 kb
Host smart-5fd48fd1-e36b-411e-8f38-95869a9717cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703534617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2703534617
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2391151059
Short name T1812
Test name
Test status
Simulation time 4969097627 ps
CPU time 4.38 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:47:15 PM PDT 24
Peak memory 236100 kb
Host smart-517c856f-d1a6-4fa3-b187-befff3ac6f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391151059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2391151059
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intercept.424041758
Short name T1163
Test name
Test status
Simulation time 1505933223 ps
CPU time 6.57 seconds
Started Mar 10 01:50:13 PM PDT 24
Finished Mar 10 01:50:20 PM PDT 24
Peak memory 232348 kb
Host smart-f4f5e9f0-8cf8-4182-9dbe-7d3783543671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424041758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.424041758
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2065255296
Short name T541
Test name
Test status
Simulation time 3076804978 ps
CPU time 6.45 seconds
Started Mar 10 02:47:12 PM PDT 24
Finished Mar 10 02:47:19 PM PDT 24
Peak memory 216356 kb
Host smart-6be1093a-fd56-486e-9d43-f2db040a2e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065255296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2065255296
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3001140743
Short name T844
Test name
Test status
Simulation time 20094325915 ps
CPU time 62.08 seconds
Started Mar 10 01:50:19 PM PDT 24
Finished Mar 10 01:51:21 PM PDT 24
Peak memory 251144 kb
Host smart-dd7bd365-3811-4e78-8fdc-be9facbab594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001140743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3001140743
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2212071370
Short name T1437
Test name
Test status
Simulation time 49708545 ps
CPU time 1.09 seconds
Started Mar 10 02:47:12 PM PDT 24
Finished Mar 10 02:47:13 PM PDT 24
Peak memory 216060 kb
Host smart-2eee5ea2-94d7-45df-b795-a56461866a8b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212071370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2212071370
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.772935840
Short name T1272
Test name
Test status
Simulation time 17286958 ps
CPU time 1.06 seconds
Started Mar 10 01:50:12 PM PDT 24
Finished Mar 10 01:50:13 PM PDT 24
Peak memory 216068 kb
Host smart-92c20175-6fcf-478a-b30a-b3aff5a9c80c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772935840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.772935840
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1136275033
Short name T1184
Test name
Test status
Simulation time 22827439935 ps
CPU time 27.73 seconds
Started Mar 10 02:47:12 PM PDT 24
Finished Mar 10 02:47:40 PM PDT 24
Peak memory 240228 kb
Host smart-9d645415-3df9-4189-9e25-594a8fdc5105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136275033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1136275033
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3553538020
Short name T1280
Test name
Test status
Simulation time 558652069 ps
CPU time 7.58 seconds
Started Mar 10 01:50:14 PM PDT 24
Finished Mar 10 01:50:22 PM PDT 24
Peak memory 233044 kb
Host smart-210c9b93-825e-4847-9891-b92e95db8d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553538020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3553538020
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2108201062
Short name T600
Test name
Test status
Simulation time 1899444301 ps
CPU time 9.77 seconds
Started Mar 10 01:50:13 PM PDT 24
Finished Mar 10 01:50:23 PM PDT 24
Peak memory 239168 kb
Host smart-b8626805-83ae-4605-95e5-05d9d036725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108201062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2108201062
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3692168971
Short name T127
Test name
Test status
Simulation time 1115149933 ps
CPU time 11.43 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:47:22 PM PDT 24
Peak memory 249312 kb
Host smart-172e509a-8810-43d2-9129-6ff202049294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692168971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3692168971
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.1533464371
Short name T852
Test name
Test status
Simulation time 19305068 ps
CPU time 0.75 seconds
Started Mar 10 02:47:11 PM PDT 24
Finished Mar 10 02:47:12 PM PDT 24
Peak memory 215620 kb
Host smart-001c36da-cdbc-473e-9eb3-0d0d5969db63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533464371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.1533464371
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3385691102
Short name T1699
Test name
Test status
Simulation time 17284523 ps
CPU time 0.72 seconds
Started Mar 10 01:50:12 PM PDT 24
Finished Mar 10 01:50:13 PM PDT 24
Peak memory 215612 kb
Host smart-9bb8bb5b-e114-46e1-bb3a-565d3e0cf0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385691102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3385691102
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2332048016
Short name T423
Test name
Test status
Simulation time 3010787143 ps
CPU time 5.46 seconds
Started Mar 10 01:50:19 PM PDT 24
Finished Mar 10 01:50:25 PM PDT 24
Peak memory 221580 kb
Host smart-3c554189-0f87-4b44-9cbd-e7711e2aa5dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2332048016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2332048016
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3409620455
Short name T1668
Test name
Test status
Simulation time 598947232 ps
CPU time 4.45 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:47:14 PM PDT 24
Peak memory 219628 kb
Host smart-76496fb1-8d4b-4239-bb67-47c717fd1d20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3409620455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3409620455
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3544542170
Short name T978
Test name
Test status
Simulation time 54075721582 ps
CPU time 27.9 seconds
Started Mar 10 01:50:14 PM PDT 24
Finished Mar 10 01:50:42 PM PDT 24
Peak memory 215696 kb
Host smart-4b2a51d3-4a12-43ee-bce5-1f3bed774080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544542170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3544542170
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3988290839
Short name T1913
Test name
Test status
Simulation time 4437798071 ps
CPU time 30.28 seconds
Started Mar 10 02:47:11 PM PDT 24
Finished Mar 10 02:47:42 PM PDT 24
Peak memory 215812 kb
Host smart-0ed72c18-92c9-4ad0-bc43-7a7ba46b651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988290839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3988290839
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1673386949
Short name T1833
Test name
Test status
Simulation time 5498884395 ps
CPU time 20.05 seconds
Started Mar 10 01:50:12 PM PDT 24
Finished Mar 10 01:50:32 PM PDT 24
Peak memory 215916 kb
Host smart-07faa256-690b-4b79-ab5f-3ae3e87efd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673386949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1673386949
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4232721562
Short name T1139
Test name
Test status
Simulation time 1927758315 ps
CPU time 7.81 seconds
Started Mar 10 02:47:15 PM PDT 24
Finished Mar 10 02:47:24 PM PDT 24
Peak memory 215728 kb
Host smart-6acd92fc-0c5a-43e3-8989-2a698c1c7c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232721562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4232721562
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3137552409
Short name T1631
Test name
Test status
Simulation time 105895474 ps
CPU time 2.15 seconds
Started Mar 10 01:50:14 PM PDT 24
Finished Mar 10 01:50:16 PM PDT 24
Peak memory 215736 kb
Host smart-ba81a1bf-30b8-4e3f-8ced-1736a8fb7f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137552409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3137552409
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.590260561
Short name T280
Test name
Test status
Simulation time 1104211064 ps
CPU time 2.42 seconds
Started Mar 10 02:47:12 PM PDT 24
Finished Mar 10 02:47:14 PM PDT 24
Peak memory 215784 kb
Host smart-b00f290b-2339-4a47-ae06-588474eb1ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590260561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.590260561
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1860237002
Short name T1721
Test name
Test status
Simulation time 82616387 ps
CPU time 0.83 seconds
Started Mar 10 02:47:09 PM PDT 24
Finished Mar 10 02:47:11 PM PDT 24
Peak memory 204928 kb
Host smart-c79da71a-1997-4d16-903f-54b06c4bb404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860237002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1860237002
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3937146853
Short name T658
Test name
Test status
Simulation time 102688631 ps
CPU time 1.11 seconds
Started Mar 10 01:50:13 PM PDT 24
Finished Mar 10 01:50:15 PM PDT 24
Peak memory 205176 kb
Host smart-10cc06fa-28a0-4ed7-82b8-e4c5f981f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937146853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3937146853
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2708874674
Short name T1196
Test name
Test status
Simulation time 24349046826 ps
CPU time 16.87 seconds
Started Mar 10 01:50:21 PM PDT 24
Finished Mar 10 01:50:38 PM PDT 24
Peak memory 233644 kb
Host smart-174c0833-350b-4669-9c15-4ae09eac483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708874674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2708874674
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_upload.59543009
Short name T1929
Test name
Test status
Simulation time 10364765496 ps
CPU time 12.48 seconds
Started Mar 10 02:47:10 PM PDT 24
Finished Mar 10 02:47:23 PM PDT 24
Peak memory 232748 kb
Host smart-1a928613-4073-4fb5-8452-61f07953246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59543009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.59543009
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2262564200
Short name T756
Test name
Test status
Simulation time 132132203 ps
CPU time 0.73 seconds
Started Mar 10 01:50:23 PM PDT 24
Finished Mar 10 01:50:24 PM PDT 24
Peak memory 204400 kb
Host smart-0dbe7751-9b12-4e86-8d7c-0cedd94ebdf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262564200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2262564200
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2426924306
Short name T319
Test name
Test status
Simulation time 14240340 ps
CPU time 0.71 seconds
Started Mar 10 02:47:21 PM PDT 24
Finished Mar 10 02:47:22 PM PDT 24
Peak memory 204420 kb
Host smart-41267b67-13c7-438a-80f3-5445d6e8f1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426924306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2426924306
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.119642184
Short name T1767
Test name
Test status
Simulation time 479601798 ps
CPU time 4.88 seconds
Started Mar 10 02:47:17 PM PDT 24
Finished Mar 10 02:47:22 PM PDT 24
Peak memory 223760 kb
Host smart-f5b44b61-d42a-4608-ae6f-70c2de733e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119642184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.119642184
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3974885082
Short name T434
Test name
Test status
Simulation time 2529007147 ps
CPU time 5.36 seconds
Started Mar 10 01:50:29 PM PDT 24
Finished Mar 10 01:50:34 PM PDT 24
Peak memory 223876 kb
Host smart-14ec3b2d-f48f-44b8-9764-8db9fd7d44a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974885082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3974885082
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1511157747
Short name T1796
Test name
Test status
Simulation time 42031811 ps
CPU time 0.79 seconds
Started Mar 10 02:47:13 PM PDT 24
Finished Mar 10 02:47:14 PM PDT 24
Peak memory 205548 kb
Host smart-1231ca90-3cbb-4bfd-8f7e-495be0b7c4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511157747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1511157747
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.609384592
Short name T1748
Test name
Test status
Simulation time 12432857 ps
CPU time 0.77 seconds
Started Mar 10 01:50:19 PM PDT 24
Finished Mar 10 01:50:20 PM PDT 24
Peak memory 204484 kb
Host smart-639c3170-cc02-4745-8b96-8b947fa18838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609384592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.609384592
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1260699907
Short name T475
Test name
Test status
Simulation time 6932948753 ps
CPU time 59.57 seconds
Started Mar 10 02:47:16 PM PDT 24
Finished Mar 10 02:48:16 PM PDT 24
Peak memory 253516 kb
Host smart-b28834c0-5643-4571-95be-fb7f2d40becb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260699907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1260699907
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3138240282
Short name T659
Test name
Test status
Simulation time 31269563628 ps
CPU time 189.6 seconds
Started Mar 10 01:50:25 PM PDT 24
Finished Mar 10 01:53:35 PM PDT 24
Peak memory 264672 kb
Host smart-6b7ae7f4-071a-47e3-9240-97c4156030be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138240282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3138240282
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2657475848
Short name T1815
Test name
Test status
Simulation time 15068131536 ps
CPU time 76.39 seconds
Started Mar 10 02:47:16 PM PDT 24
Finished Mar 10 02:48:33 PM PDT 24
Peak memory 256544 kb
Host smart-60f6f0bd-c827-4df7-819b-bd5874214a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657475848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2657475848
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3704194841
Short name T182
Test name
Test status
Simulation time 61634595622 ps
CPU time 176.62 seconds
Started Mar 10 01:50:22 PM PDT 24
Finished Mar 10 01:53:19 PM PDT 24
Peak memory 250896 kb
Host smart-391fa5aa-e7ed-409b-838d-2b8decca66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704194841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3704194841
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3359307216
Short name T500
Test name
Test status
Simulation time 70324276591 ps
CPU time 150.05 seconds
Started Mar 10 01:50:25 PM PDT 24
Finished Mar 10 01:52:55 PM PDT 24
Peak memory 248656 kb
Host smart-04cfc96b-8068-4261-b93c-c34f4a0a2015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359307216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3359307216
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3892689696
Short name T1565
Test name
Test status
Simulation time 10453753694 ps
CPU time 92.68 seconds
Started Mar 10 02:47:13 PM PDT 24
Finished Mar 10 02:48:46 PM PDT 24
Peak memory 248628 kb
Host smart-e765de58-fbde-472f-a5c8-ebc9ae4185c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892689696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3892689696
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2896007505
Short name T428
Test name
Test status
Simulation time 3496376216 ps
CPU time 20.26 seconds
Started Mar 10 01:50:22 PM PDT 24
Finished Mar 10 01:50:43 PM PDT 24
Peak memory 246568 kb
Host smart-00264700-26a7-487a-85d2-bb4ef8445ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896007505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2896007505
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.57886535
Short name T856
Test name
Test status
Simulation time 5523233563 ps
CPU time 19.57 seconds
Started Mar 10 02:47:17 PM PDT 24
Finished Mar 10 02:47:37 PM PDT 24
Peak memory 249832 kb
Host smart-cf0215d4-4cec-4e49-8ae2-0841a8fe7233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57886535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.57886535
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3553667958
Short name T1519
Test name
Test status
Simulation time 1332647617 ps
CPU time 3.39 seconds
Started Mar 10 01:50:22 PM PDT 24
Finished Mar 10 01:50:26 PM PDT 24
Peak memory 223740 kb
Host smart-fe838ebe-b12a-40f5-b7af-1df00579ed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553667958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3553667958
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intercept.631894120
Short name T1169
Test name
Test status
Simulation time 10599519285 ps
CPU time 9.41 seconds
Started Mar 10 02:47:15 PM PDT 24
Finished Mar 10 02:47:25 PM PDT 24
Peak memory 223916 kb
Host smart-65fa7d03-8521-432a-904b-783b9871d20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631894120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.631894120
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2176372421
Short name T1122
Test name
Test status
Simulation time 819568020 ps
CPU time 9.57 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:41 PM PDT 24
Peak memory 233500 kb
Host smart-99eb1888-d7b1-4ce9-8223-042674074aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176372421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2176372421
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.386623167
Short name T1482
Test name
Test status
Simulation time 16577008587 ps
CPU time 16.6 seconds
Started Mar 10 02:47:18 PM PDT 24
Finished Mar 10 02:47:35 PM PDT 24
Peak memory 239120 kb
Host smart-de97a235-b300-4c91-9d9a-2bdec89a5c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386623167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.386623167
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2027493639
Short name T1644
Test name
Test status
Simulation time 28770694 ps
CPU time 1.04 seconds
Started Mar 10 02:47:12 PM PDT 24
Finished Mar 10 02:47:13 PM PDT 24
Peak memory 217228 kb
Host smart-c8ffd32b-47cc-43d5-a4c9-7abc2f11e5d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027493639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2027493639
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.612504544
Short name T358
Test name
Test status
Simulation time 22266168 ps
CPU time 1.04 seconds
Started Mar 10 01:50:18 PM PDT 24
Finished Mar 10 01:50:19 PM PDT 24
Peak memory 216072 kb
Host smart-a539475f-ea92-4c77-9173-9163cf0bd6b5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612504544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.612504544
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2778325370
Short name T739
Test name
Test status
Simulation time 12190462359 ps
CPU time 19.29 seconds
Started Mar 10 01:50:17 PM PDT 24
Finished Mar 10 01:50:36 PM PDT 24
Peak memory 236044 kb
Host smart-978bbd01-a9cf-43cf-81e6-98d70a955a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778325370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2778325370
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.857793977
Short name T507
Test name
Test status
Simulation time 94853742 ps
CPU time 2.45 seconds
Started Mar 10 02:47:17 PM PDT 24
Finished Mar 10 02:47:20 PM PDT 24
Peak memory 216156 kb
Host smart-e4c58eb3-2b54-4715-abb9-992c7ee89b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857793977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.857793977
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2973057475
Short name T216
Test name
Test status
Simulation time 2005142620 ps
CPU time 5.91 seconds
Started Mar 10 02:47:16 PM PDT 24
Finished Mar 10 02:47:22 PM PDT 24
Peak memory 217352 kb
Host smart-736c2f7a-2528-44c0-b743-271723490599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973057475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2973057475
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.375629198
Short name T687
Test name
Test status
Simulation time 241353808 ps
CPU time 3.08 seconds
Started Mar 10 01:50:21 PM PDT 24
Finished Mar 10 01:50:24 PM PDT 24
Peak memory 232988 kb
Host smart-7e0cf274-8338-4530-ad0a-0b312154fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375629198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.375629198
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1186124029
Short name T427
Test name
Test status
Simulation time 39649782 ps
CPU time 0.75 seconds
Started Mar 10 02:47:16 PM PDT 24
Finished Mar 10 02:47:17 PM PDT 24
Peak memory 215632 kb
Host smart-cee48888-1067-4f43-a575-4a9e2046b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186124029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1186124029
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3857013585
Short name T741
Test name
Test status
Simulation time 18445639 ps
CPU time 0.75 seconds
Started Mar 10 01:50:18 PM PDT 24
Finished Mar 10 01:50:19 PM PDT 24
Peak memory 215608 kb
Host smart-6a062942-5e2d-4861-84c4-0f26d37b4797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857013585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3857013585
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1860103230
Short name T35
Test name
Test status
Simulation time 307686476 ps
CPU time 3.09 seconds
Started Mar 10 01:50:22 PM PDT 24
Finished Mar 10 01:50:26 PM PDT 24
Peak memory 217796 kb
Host smart-5d1c3dc0-bd45-4069-ae21-fec450e7c72c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1860103230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1860103230
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2901488075
Short name T1490
Test name
Test status
Simulation time 544645536 ps
CPU time 4.06 seconds
Started Mar 10 02:47:14 PM PDT 24
Finished Mar 10 02:47:19 PM PDT 24
Peak memory 222060 kb
Host smart-5c4024c1-8cac-41b7-a9a3-e07ae8bce3b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2901488075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2901488075
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3385675357
Short name T923
Test name
Test status
Simulation time 3830285228 ps
CPU time 49.12 seconds
Started Mar 10 01:50:23 PM PDT 24
Finished Mar 10 01:51:12 PM PDT 24
Peak memory 239020 kb
Host smart-cd8918ee-8e14-4314-a46d-96492631c3ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385675357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3385675357
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3521689834
Short name T777
Test name
Test status
Simulation time 6849040942 ps
CPU time 56.09 seconds
Started Mar 10 02:47:15 PM PDT 24
Finished Mar 10 02:48:11 PM PDT 24
Peak memory 222352 kb
Host smart-068e25f7-f526-423d-aa8a-71146471ef78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521689834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3521689834
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2476529916
Short name T889
Test name
Test status
Simulation time 38325322823 ps
CPU time 31.44 seconds
Started Mar 10 02:47:19 PM PDT 24
Finished Mar 10 02:47:51 PM PDT 24
Peak memory 215828 kb
Host smart-5cfc4849-a322-4f77-8fd4-2afffb9db2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476529916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2476529916
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3398072574
Short name T1312
Test name
Test status
Simulation time 5785095906 ps
CPU time 40.68 seconds
Started Mar 10 01:50:17 PM PDT 24
Finished Mar 10 01:50:58 PM PDT 24
Peak memory 215788 kb
Host smart-39c46331-7d87-4d2e-8117-9c48093d2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398072574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3398072574
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1537654429
Short name T1755
Test name
Test status
Simulation time 3827938007 ps
CPU time 8.14 seconds
Started Mar 10 02:47:17 PM PDT 24
Finished Mar 10 02:47:25 PM PDT 24
Peak memory 215752 kb
Host smart-2f07c472-c373-4cd3-bc99-497d27910fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537654429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1537654429
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1877452516
Short name T824
Test name
Test status
Simulation time 21089217506 ps
CPU time 14.45 seconds
Started Mar 10 01:50:18 PM PDT 24
Finished Mar 10 01:50:33 PM PDT 24
Peak memory 215812 kb
Host smart-8fc5c3fd-7c87-41b7-8207-de116dd17aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877452516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1877452516
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1839201382
Short name T470
Test name
Test status
Simulation time 22566267 ps
CPU time 0.8 seconds
Started Mar 10 02:47:18 PM PDT 24
Finished Mar 10 02:47:19 PM PDT 24
Peak memory 204888 kb
Host smart-1b972158-e2de-47cf-b0f5-69aaab304c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839201382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1839201382
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2992441570
Short name T1367
Test name
Test status
Simulation time 134096954 ps
CPU time 1.92 seconds
Started Mar 10 01:50:21 PM PDT 24
Finished Mar 10 01:50:23 PM PDT 24
Peak memory 207700 kb
Host smart-cc29d974-afe5-4fef-b74d-7b2d907d5758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992441570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2992441570
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2448575287
Short name T80
Test name
Test status
Simulation time 31075482 ps
CPU time 0.76 seconds
Started Mar 10 01:50:18 PM PDT 24
Finished Mar 10 01:50:19 PM PDT 24
Peak memory 204864 kb
Host smart-8f88f078-f0a7-40db-b92a-bd60cc03ddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448575287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2448575287
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3577319742
Short name T1711
Test name
Test status
Simulation time 65764764 ps
CPU time 0.78 seconds
Started Mar 10 02:47:20 PM PDT 24
Finished Mar 10 02:47:22 PM PDT 24
Peak memory 204792 kb
Host smart-822f9287-fb68-45ac-b065-0104d33f7379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577319742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3577319742
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4017423522
Short name T959
Test name
Test status
Simulation time 1385276259 ps
CPU time 11.57 seconds
Started Mar 10 02:47:23 PM PDT 24
Finished Mar 10 02:47:34 PM PDT 24
Peak memory 240020 kb
Host smart-bcc0ec04-bc28-45a8-912e-b31c3a06566d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017423522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4017423522
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_upload.4091547782
Short name T1610
Test name
Test status
Simulation time 1136320164 ps
CPU time 4.2 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:35 PM PDT 24
Peak memory 223864 kb
Host smart-e4ecf8bd-82d4-4085-ba7c-b325dd9dd500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091547782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4091547782
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1412849350
Short name T991
Test name
Test status
Simulation time 28596641 ps
CPU time 0.72 seconds
Started Mar 10 01:50:24 PM PDT 24
Finished Mar 10 01:50:25 PM PDT 24
Peak memory 204804 kb
Host smart-3f2b3c4d-d179-41e3-a0be-ed224f4857dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412849350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1412849350
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.584195986
Short name T848
Test name
Test status
Simulation time 30075590 ps
CPU time 0.73 seconds
Started Mar 10 02:47:28 PM PDT 24
Finished Mar 10 02:47:28 PM PDT 24
Peak memory 204460 kb
Host smart-f81c8226-a94d-4eaf-80ad-9fd866019461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584195986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.584195986
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2622775227
Short name T1166
Test name
Test status
Simulation time 37975231 ps
CPU time 2.4 seconds
Started Mar 10 01:50:24 PM PDT 24
Finished Mar 10 01:50:27 PM PDT 24
Peak memory 216188 kb
Host smart-1e39f2c5-d70e-4143-a482-94f04781a2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622775227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2622775227
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4138374588
Short name T243
Test name
Test status
Simulation time 952392124 ps
CPU time 4 seconds
Started Mar 10 02:47:21 PM PDT 24
Finished Mar 10 02:47:25 PM PDT 24
Peak memory 232432 kb
Host smart-5a90430b-67bb-4979-bfa1-b2e0d9b34bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138374588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4138374588
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1558777032
Short name T303
Test name
Test status
Simulation time 66208674 ps
CPU time 0.77 seconds
Started Mar 10 02:47:19 PM PDT 24
Finished Mar 10 02:47:21 PM PDT 24
Peak memory 205500 kb
Host smart-1fe30eb1-07c9-4c80-b3e8-e96b9b10746d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558777032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1558777032
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2248055249
Short name T1125
Test name
Test status
Simulation time 28620871 ps
CPU time 0.8 seconds
Started Mar 10 01:50:24 PM PDT 24
Finished Mar 10 01:50:25 PM PDT 24
Peak memory 205428 kb
Host smart-7ff81724-43ae-4a71-99a7-e80f21bfc610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248055249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2248055249
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2382595241
Short name T502
Test name
Test status
Simulation time 9922359211 ps
CPU time 31.98 seconds
Started Mar 10 02:47:23 PM PDT 24
Finished Mar 10 02:47:55 PM PDT 24
Peak memory 237876 kb
Host smart-95b44dc6-5060-4e24-94df-fff3ce625cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382595241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2382595241
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.796909862
Short name T744
Test name
Test status
Simulation time 103511762366 ps
CPU time 95.21 seconds
Started Mar 10 01:50:25 PM PDT 24
Finished Mar 10 01:52:00 PM PDT 24
Peak memory 249464 kb
Host smart-a1bdbcf6-4284-4e3d-ac87-48df9992a782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796909862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.796909862
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1403354206
Short name T1598
Test name
Test status
Simulation time 12694709386 ps
CPU time 127.2 seconds
Started Mar 10 02:47:22 PM PDT 24
Finished Mar 10 02:49:29 PM PDT 24
Peak memory 264484 kb
Host smart-83410877-4fcd-4bf8-b209-1fd6510634f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403354206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1403354206
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.953019615
Short name T548
Test name
Test status
Simulation time 97689140311 ps
CPU time 175.98 seconds
Started Mar 10 01:50:22 PM PDT 24
Finished Mar 10 01:53:18 PM PDT 24
Peak memory 248596 kb
Host smart-04cc5252-9acc-453c-8dea-e0a72a7694a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953019615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.953019615
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1208453128
Short name T1150
Test name
Test status
Simulation time 226728099657 ps
CPU time 427.24 seconds
Started Mar 10 02:47:22 PM PDT 24
Finished Mar 10 02:54:30 PM PDT 24
Peak memory 251076 kb
Host smart-14a6d461-e214-4ca9-bfc7-1113ce76ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208453128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1208453128
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2493535072
Short name T1037
Test name
Test status
Simulation time 510541086130 ps
CPU time 522.02 seconds
Started Mar 10 01:50:24 PM PDT 24
Finished Mar 10 01:59:06 PM PDT 24
Peak memory 252828 kb
Host smart-69cc38ba-5393-4b6c-94e5-5b87c7283af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493535072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2493535072
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1556681730
Short name T1219
Test name
Test status
Simulation time 22522147518 ps
CPU time 34.75 seconds
Started Mar 10 01:50:22 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 247240 kb
Host smart-8687a5bb-e844-43af-b4ac-c6bf83c03bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556681730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1556681730
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2096840408
Short name T1649
Test name
Test status
Simulation time 28133078339 ps
CPU time 25.83 seconds
Started Mar 10 02:47:21 PM PDT 24
Finished Mar 10 02:47:47 PM PDT 24
Peak memory 247412 kb
Host smart-99b93202-74dc-4857-9fdd-364f4eec4663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096840408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2096840408
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.469854574
Short name T1752
Test name
Test status
Simulation time 4482462655 ps
CPU time 8.62 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:47:36 PM PDT 24
Peak memory 223952 kb
Host smart-a7c72af7-ea33-4312-ab68-dfd48ba8da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469854574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.469854574
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intercept.877297744
Short name T727
Test name
Test status
Simulation time 2123258845 ps
CPU time 9.01 seconds
Started Mar 10 01:50:29 PM PDT 24
Finished Mar 10 01:50:38 PM PDT 24
Peak memory 232788 kb
Host smart-21092f3a-e345-44b3-9282-19c43fc973da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877297744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.877297744
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2684047094
Short name T37
Test name
Test status
Simulation time 2373400540 ps
CPU time 9.53 seconds
Started Mar 10 02:47:24 PM PDT 24
Finished Mar 10 02:47:33 PM PDT 24
Peak memory 247744 kb
Host smart-ea485c92-faab-427f-abbc-bdc5a477e554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684047094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2684047094
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.55538957
Short name T743
Test name
Test status
Simulation time 3572566036 ps
CPU time 12.8 seconds
Started Mar 10 01:50:23 PM PDT 24
Finished Mar 10 01:50:36 PM PDT 24
Peak memory 248028 kb
Host smart-2feebb5f-2edc-40d1-a520-4f9dcb4ee48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55538957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.55538957
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3313857603
Short name T604
Test name
Test status
Simulation time 15576402 ps
CPU time 1.1 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:32 PM PDT 24
Peak memory 217268 kb
Host smart-a14566ae-c872-43ac-993f-44792f8cf4d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313857603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3313857603
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2116606935
Short name T532
Test name
Test status
Simulation time 12521993141 ps
CPU time 10.26 seconds
Started Mar 10 01:50:22 PM PDT 24
Finished Mar 10 01:50:32 PM PDT 24
Peak memory 232924 kb
Host smart-f9f3c533-b03f-4a29-a49a-256ecee21304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116606935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2116606935
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2390147364
Short name T1745
Test name
Test status
Simulation time 4568324098 ps
CPU time 14.48 seconds
Started Mar 10 02:47:20 PM PDT 24
Finished Mar 10 02:47:35 PM PDT 24
Peak memory 223924 kb
Host smart-c8a48e11-a992-46a2-ab72-36a5bcd4fa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390147364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2390147364
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2191285190
Short name T1885
Test name
Test status
Simulation time 2807819419 ps
CPU time 10.88 seconds
Started Mar 10 01:50:25 PM PDT 24
Finished Mar 10 01:50:36 PM PDT 24
Peak memory 236900 kb
Host smart-49155b4b-e9e9-475b-87cb-eb1e17533009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191285190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2191285190
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.774477656
Short name T728
Test name
Test status
Simulation time 149573026 ps
CPU time 2.66 seconds
Started Mar 10 02:47:24 PM PDT 24
Finished Mar 10 02:47:27 PM PDT 24
Peak memory 215748 kb
Host smart-85bb66b6-253f-4193-9339-1e02b1add940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774477656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.774477656
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.1377141483
Short name T1363
Test name
Test status
Simulation time 30615384 ps
CPU time 0.73 seconds
Started Mar 10 01:50:29 PM PDT 24
Finished Mar 10 01:50:30 PM PDT 24
Peak memory 215620 kb
Host smart-365967b1-b4e3-46a3-bda5-f04c5ee3426c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377141483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.1377141483
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.811715910
Short name T654
Test name
Test status
Simulation time 39073773 ps
CPU time 0.73 seconds
Started Mar 10 02:47:22 PM PDT 24
Finished Mar 10 02:47:23 PM PDT 24
Peak memory 215616 kb
Host smart-fc6dcda3-a5c2-414c-bbf7-c7e299d31b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811715910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.811715910
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1429043788
Short name T467
Test name
Test status
Simulation time 426637479 ps
CPU time 3.82 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:35 PM PDT 24
Peak memory 221332 kb
Host smart-62e43962-9f9b-4158-9c3c-903268b617f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1429043788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1429043788
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.894486637
Short name T686
Test name
Test status
Simulation time 5362670927 ps
CPU time 5.21 seconds
Started Mar 10 02:47:22 PM PDT 24
Finished Mar 10 02:47:28 PM PDT 24
Peak memory 222108 kb
Host smart-cec85ecf-d9c8-4f72-b21a-fa2bf95cfcd7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=894486637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.894486637
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.109309870
Short name T1759
Test name
Test status
Simulation time 54212888 ps
CPU time 1.06 seconds
Started Mar 10 01:50:23 PM PDT 24
Finished Mar 10 01:50:24 PM PDT 24
Peak memory 205932 kb
Host smart-bc569b90-a418-4024-81c5-884b89d11a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109309870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.109309870
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.438953652
Short name T1681
Test name
Test status
Simulation time 90584776 ps
CPU time 0.99 seconds
Started Mar 10 02:47:24 PM PDT 24
Finished Mar 10 02:47:25 PM PDT 24
Peak memory 205916 kb
Host smart-dae5b877-2336-4a3d-8e2b-1268b7ffc8ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438953652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.438953652
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2241596380
Short name T1737
Test name
Test status
Simulation time 946646957 ps
CPU time 9.99 seconds
Started Mar 10 02:47:22 PM PDT 24
Finished Mar 10 02:47:32 PM PDT 24
Peak memory 215728 kb
Host smart-c0520ef1-c0c7-43ce-ae41-4ac2d3b4697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241596380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2241596380
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2256858156
Short name T1822
Test name
Test status
Simulation time 4922079723 ps
CPU time 30.81 seconds
Started Mar 10 01:50:24 PM PDT 24
Finished Mar 10 01:50:55 PM PDT 24
Peak memory 215732 kb
Host smart-fdb27a1a-6e0c-4f29-ad05-4b42460b8c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256858156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2256858156
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2079353308
Short name T1142
Test name
Test status
Simulation time 1564175630 ps
CPU time 8.83 seconds
Started Mar 10 02:47:23 PM PDT 24
Finished Mar 10 02:47:32 PM PDT 24
Peak memory 207608 kb
Host smart-d95ed7b1-bed8-486a-9608-38ba0aecad68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079353308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2079353308
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3375058935
Short name T344
Test name
Test status
Simulation time 103037715342 ps
CPU time 29.15 seconds
Started Mar 10 01:50:24 PM PDT 24
Finished Mar 10 01:50:54 PM PDT 24
Peak memory 215804 kb
Host smart-44713490-eb05-47c3-ab20-069e3525a33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375058935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3375058935
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1659519714
Short name T641
Test name
Test status
Simulation time 1759938129 ps
CPU time 2.52 seconds
Started Mar 10 01:50:25 PM PDT 24
Finished Mar 10 01:50:27 PM PDT 24
Peak memory 215728 kb
Host smart-28dbc9a2-5cff-4275-8e78-ca83c1d62751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659519714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1659519714
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2613135204
Short name T882
Test name
Test status
Simulation time 76750453 ps
CPU time 1.14 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:47:29 PM PDT 24
Peak memory 206436 kb
Host smart-fa36ae1a-2f0a-4942-85c3-6ad5fc9455ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613135204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2613135204
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1872100034
Short name T310
Test name
Test status
Simulation time 162982670 ps
CPU time 1.18 seconds
Started Mar 10 01:50:28 PM PDT 24
Finished Mar 10 01:50:30 PM PDT 24
Peak memory 205888 kb
Host smart-ddf41b49-0d78-4220-aa29-78bf298bba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872100034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1872100034
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2984920784
Short name T1022
Test name
Test status
Simulation time 53377613 ps
CPU time 0.82 seconds
Started Mar 10 02:47:21 PM PDT 24
Finished Mar 10 02:47:22 PM PDT 24
Peak memory 204856 kb
Host smart-6bfaf747-aa49-4a60-9c23-a4548c50860d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984920784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2984920784
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3556810208
Short name T627
Test name
Test status
Simulation time 634522617 ps
CPU time 5.97 seconds
Started Mar 10 01:50:24 PM PDT 24
Finished Mar 10 01:50:30 PM PDT 24
Peak memory 233136 kb
Host smart-1e052597-d215-4a2e-adde-5bff1f35fdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556810208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3556810208
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_upload.4251015186
Short name T1857
Test name
Test status
Simulation time 413011947 ps
CPU time 2.86 seconds
Started Mar 10 02:47:19 PM PDT 24
Finished Mar 10 02:47:23 PM PDT 24
Peak memory 223928 kb
Host smart-3e4671ef-d114-4e33-8894-add5afdd062f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251015186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4251015186
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1263386762
Short name T1400
Test name
Test status
Simulation time 13865248 ps
CPU time 0.71 seconds
Started Mar 10 02:46:12 PM PDT 24
Finished Mar 10 02:46:14 PM PDT 24
Peak memory 204436 kb
Host smart-e1b25da7-f919-4233-b312-5c3371edd579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263386762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
263386762
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.442343390
Short name T1359
Test name
Test status
Simulation time 22613036 ps
CPU time 0.75 seconds
Started Mar 10 01:49:00 PM PDT 24
Finished Mar 10 01:49:01 PM PDT 24
Peak memory 204764 kb
Host smart-e9365831-0ad9-4ae6-9270-464b7eaf29a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442343390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.442343390
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1132549935
Short name T1542
Test name
Test status
Simulation time 1449657256 ps
CPU time 5.9 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:22 PM PDT 24
Peak memory 218200 kb
Host smart-0cd62aca-813c-4b4a-9a8b-8039b526b185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132549935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1132549935
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2128707538
Short name T388
Test name
Test status
Simulation time 796366144 ps
CPU time 3.62 seconds
Started Mar 10 01:48:56 PM PDT 24
Finished Mar 10 01:49:00 PM PDT 24
Peak memory 233028 kb
Host smart-7c1b9383-5795-49e2-954a-800340e9e5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128707538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2128707538
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1253373703
Short name T1342
Test name
Test status
Simulation time 12197367 ps
CPU time 0.74 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:08 PM PDT 24
Peak memory 204480 kb
Host smart-923f39da-d9ab-4ff0-842b-69343f731c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253373703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1253373703
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.764322531
Short name T1110
Test name
Test status
Simulation time 19772743 ps
CPU time 0.76 seconds
Started Mar 10 01:48:54 PM PDT 24
Finished Mar 10 01:48:55 PM PDT 24
Peak memory 204412 kb
Host smart-111777cd-cbbd-4292-a35d-009d575c15b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764322531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.764322531
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3038132209
Short name T1273
Test name
Test status
Simulation time 60237323066 ps
CPU time 77.71 seconds
Started Mar 10 02:46:11 PM PDT 24
Finished Mar 10 02:47:29 PM PDT 24
Peak memory 248536 kb
Host smart-75c4476e-1e9e-4da3-9b29-e8e04c928f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038132209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3038132209
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3992428331
Short name T1648
Test name
Test status
Simulation time 36844233330 ps
CPU time 94.16 seconds
Started Mar 10 01:49:00 PM PDT 24
Finished Mar 10 01:50:34 PM PDT 24
Peak memory 254692 kb
Host smart-0913f261-56c8-43d7-b9be-d2ac61a6f3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992428331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3992428331
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1199138607
Short name T265
Test name
Test status
Simulation time 27813285674 ps
CPU time 229.93 seconds
Started Mar 10 02:46:20 PM PDT 24
Finished Mar 10 02:50:10 PM PDT 24
Peak memory 264720 kb
Host smart-e79f19e1-240c-4e56-9847-7ee17b8007e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199138607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1199138607
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4171285487
Short name T1167
Test name
Test status
Simulation time 113360036253 ps
CPU time 161.8 seconds
Started Mar 10 01:49:00 PM PDT 24
Finished Mar 10 01:51:42 PM PDT 24
Peak memory 248688 kb
Host smart-9fd1423d-2e5c-4d96-b524-1b08d339b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171285487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4171285487
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1330621130
Short name T718
Test name
Test status
Simulation time 128287231712 ps
CPU time 160.18 seconds
Started Mar 10 01:49:00 PM PDT 24
Finished Mar 10 01:51:41 PM PDT 24
Peak memory 249056 kb
Host smart-588ceca7-8ad0-4de1-8bce-d91f406f3e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330621130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1330621130
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2112842758
Short name T268
Test name
Test status
Simulation time 52804195063 ps
CPU time 142.92 seconds
Started Mar 10 02:46:13 PM PDT 24
Finished Mar 10 02:48:36 PM PDT 24
Peak memory 250720 kb
Host smart-0556da97-ecea-4d38-97f6-97c84a827a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112842758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2112842758
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2499732641
Short name T1597
Test name
Test status
Simulation time 24616658823 ps
CPU time 56.24 seconds
Started Mar 10 02:46:13 PM PDT 24
Finished Mar 10 02:47:10 PM PDT 24
Peak memory 239964 kb
Host smart-74b03ea3-e1d8-479f-8f7e-62a68618823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499732641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2499732641
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.951830132
Short name T1897
Test name
Test status
Simulation time 8725104046 ps
CPU time 19.15 seconds
Started Mar 10 01:49:00 PM PDT 24
Finished Mar 10 01:49:19 PM PDT 24
Peak memory 223940 kb
Host smart-6338fb1a-8818-431c-b6e9-6dcf43dfdc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951830132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.951830132
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1112418549
Short name T1050
Test name
Test status
Simulation time 261326019 ps
CPU time 4.27 seconds
Started Mar 10 02:46:14 PM PDT 24
Finished Mar 10 02:46:19 PM PDT 24
Peak memory 220456 kb
Host smart-de85fbc2-ca88-4f48-b531-1b70db3a34da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112418549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1112418549
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2778429659
Short name T74
Test name
Test status
Simulation time 7672140968 ps
CPU time 10.83 seconds
Started Mar 10 01:48:55 PM PDT 24
Finished Mar 10 01:49:06 PM PDT 24
Peak memory 217540 kb
Host smart-ae0ef186-eb15-44fb-8ecf-93dea4e88297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778429659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2778429659
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1437106472
Short name T1727
Test name
Test status
Simulation time 3364719290 ps
CPU time 5.7 seconds
Started Mar 10 02:46:17 PM PDT 24
Finished Mar 10 02:46:23 PM PDT 24
Peak memory 233380 kb
Host smart-2b7b1b27-d771-4040-9340-c3d7a9574f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437106472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1437106472
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2776394254
Short name T190
Test name
Test status
Simulation time 6270188847 ps
CPU time 17.3 seconds
Started Mar 10 01:48:56 PM PDT 24
Finished Mar 10 01:49:14 PM PDT 24
Peak memory 236996 kb
Host smart-f00de581-5875-46fa-9a99-1bbd25cf7008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776394254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2776394254
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2099487829
Short name T944
Test name
Test status
Simulation time 15675678 ps
CPU time 1.02 seconds
Started Mar 10 02:46:07 PM PDT 24
Finished Mar 10 02:46:08 PM PDT 24
Peak memory 216056 kb
Host smart-e31ee5d9-1dd2-4203-b4d6-af6b1a749b09
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099487829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2099487829
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.709973370
Short name T859
Test name
Test status
Simulation time 105874278 ps
CPU time 1.05 seconds
Started Mar 10 01:48:55 PM PDT 24
Finished Mar 10 01:48:56 PM PDT 24
Peak memory 217264 kb
Host smart-617628fa-35de-4c03-9ecf-575ddc053fad
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709973370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.709973370
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.111758135
Short name T1049
Test name
Test status
Simulation time 14676134430 ps
CPU time 40.68 seconds
Started Mar 10 01:48:55 PM PDT 24
Finished Mar 10 01:49:36 PM PDT 24
Peak memory 245424 kb
Host smart-0159a5a8-6eb8-49a1-a15b-671174278c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111758135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
111758135
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2096410803
Short name T193
Test name
Test status
Simulation time 83938902930 ps
CPU time 30.94 seconds
Started Mar 10 02:46:10 PM PDT 24
Finished Mar 10 02:46:41 PM PDT 24
Peak memory 240184 kb
Host smart-e46a8b26-adb9-4a46-b2e0-f7dbfa2a0c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096410803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2096410803
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1037793275
Short name T1322
Test name
Test status
Simulation time 21330122439 ps
CPU time 15.14 seconds
Started Mar 10 01:48:55 PM PDT 24
Finished Mar 10 01:49:10 PM PDT 24
Peak memory 237712 kb
Host smart-6efd8935-15f6-4575-94a9-af0f5d4cf0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037793275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1037793275
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1149814419
Short name T487
Test name
Test status
Simulation time 3071966740 ps
CPU time 17.36 seconds
Started Mar 10 02:46:14 PM PDT 24
Finished Mar 10 02:46:31 PM PDT 24
Peak memory 233028 kb
Host smart-88af9092-11d2-4768-abd5-be621b9e5845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149814419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1149814419
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2506750180
Short name T1650
Test name
Test status
Simulation time 78340008 ps
CPU time 0.72 seconds
Started Mar 10 02:46:09 PM PDT 24
Finished Mar 10 02:46:10 PM PDT 24
Peak memory 215624 kb
Host smart-0d4e73b6-cb80-4d7e-86fc-4b5ea1f0233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506750180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2506750180
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.270414139
Short name T764
Test name
Test status
Simulation time 24737534 ps
CPU time 0.77 seconds
Started Mar 10 01:48:57 PM PDT 24
Finished Mar 10 01:48:58 PM PDT 24
Peak memory 215672 kb
Host smart-bdec8d01-0275-4aaf-8c39-3814a466c945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270414139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.270414139
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3787612761
Short name T1702
Test name
Test status
Simulation time 2190307719 ps
CPU time 4.16 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:20 PM PDT 24
Peak memory 222200 kb
Host smart-8ebea58c-0f58-4091-ac3b-d2b14bde3956
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3787612761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3787612761
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4256377520
Short name T1205
Test name
Test status
Simulation time 116064193 ps
CPU time 3.11 seconds
Started Mar 10 01:48:58 PM PDT 24
Finished Mar 10 01:49:02 PM PDT 24
Peak memory 218292 kb
Host smart-70d6a3db-fe8a-4804-ac3b-86b1cb896c21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4256377520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4256377520
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.163676446
Short name T65
Test name
Test status
Simulation time 113004894 ps
CPU time 1.21 seconds
Started Mar 10 01:49:02 PM PDT 24
Finished Mar 10 01:49:04 PM PDT 24
Peak memory 236568 kb
Host smart-de34a2c0-8c40-49ce-bfce-e09e3e8ec241
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163676446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.163676446
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.639621854
Short name T64
Test name
Test status
Simulation time 171820214 ps
CPU time 1.25 seconds
Started Mar 10 02:46:20 PM PDT 24
Finished Mar 10 02:46:21 PM PDT 24
Peak memory 235668 kb
Host smart-01b7f40d-512c-41f1-b7af-3dd13d5b2835
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639621854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.639621854
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1747988410
Short name T252
Test name
Test status
Simulation time 66365589385 ps
CPU time 505.41 seconds
Started Mar 10 01:48:58 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 272660 kb
Host smart-58f82b00-03fe-4028-97bf-0e7771ab42c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747988410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1747988410
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2957825198
Short name T1268
Test name
Test status
Simulation time 111527023820 ps
CPU time 303.06 seconds
Started Mar 10 02:46:11 PM PDT 24
Finished Mar 10 02:51:14 PM PDT 24
Peak memory 288752 kb
Host smart-fd52c21c-f04c-45df-946c-7263f7d9622a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957825198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2957825198
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3350091648
Short name T1191
Test name
Test status
Simulation time 14193557201 ps
CPU time 34.53 seconds
Started Mar 10 02:46:16 PM PDT 24
Finished Mar 10 02:46:51 PM PDT 24
Peak memory 215892 kb
Host smart-ea6fe7dc-f500-47d5-8c96-ab65042d531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350091648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3350091648
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.776648819
Short name T1566
Test name
Test status
Simulation time 12099758439 ps
CPU time 33.78 seconds
Started Mar 10 01:48:57 PM PDT 24
Finished Mar 10 01:49:31 PM PDT 24
Peak memory 215860 kb
Host smart-f25523df-65a2-4dec-bfad-a04003a8341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776648819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.776648819
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3245355886
Short name T1287
Test name
Test status
Simulation time 24606714500 ps
CPU time 16.87 seconds
Started Mar 10 01:48:55 PM PDT 24
Finished Mar 10 01:49:12 PM PDT 24
Peak memory 215800 kb
Host smart-fc8c31e7-ad38-4dec-a283-b79847992552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245355886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3245355886
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.91447269
Short name T591
Test name
Test status
Simulation time 6741694487 ps
CPU time 20.63 seconds
Started Mar 10 02:46:16 PM PDT 24
Finished Mar 10 02:46:37 PM PDT 24
Peak memory 215828 kb
Host smart-80bc9bad-66f4-4d2d-98e2-2a0f299c0f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91447269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.91447269
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2792759922
Short name T579
Test name
Test status
Simulation time 65735964 ps
CPU time 0.81 seconds
Started Mar 10 01:48:57 PM PDT 24
Finished Mar 10 01:48:58 PM PDT 24
Peak memory 204904 kb
Host smart-3bdf4dc3-ad9f-4929-a660-6faba82d1fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792759922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2792759922
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.80158793
Short name T1344
Test name
Test status
Simulation time 52508370 ps
CPU time 0.82 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:16 PM PDT 24
Peak memory 205708 kb
Host smart-e37210ab-36f4-459c-ac33-fc3e19caa97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80158793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.80158793
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1050597246
Short name T1891
Test name
Test status
Simulation time 89874807 ps
CPU time 1.03 seconds
Started Mar 10 02:46:20 PM PDT 24
Finished Mar 10 02:46:21 PM PDT 24
Peak memory 205204 kb
Host smart-02e505a7-d57e-4ff7-9843-020a69d268c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050597246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1050597246
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2450097107
Short name T1084
Test name
Test status
Simulation time 307431174 ps
CPU time 1.03 seconds
Started Mar 10 01:48:55 PM PDT 24
Finished Mar 10 01:48:56 PM PDT 24
Peak memory 205888 kb
Host smart-0407b24e-03c7-4787-81fc-21301d611ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450097107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2450097107
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2300460213
Short name T1744
Test name
Test status
Simulation time 1437937300 ps
CPU time 7.06 seconds
Started Mar 10 02:46:12 PM PDT 24
Finished Mar 10 02:46:19 PM PDT 24
Peak memory 233188 kb
Host smart-9c2e00b0-1f9c-4f69-a7f9-12d111709ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300460213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2300460213
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_upload.877436744
Short name T703
Test name
Test status
Simulation time 14073966655 ps
CPU time 18.94 seconds
Started Mar 10 01:48:56 PM PDT 24
Finished Mar 10 01:49:15 PM PDT 24
Peak memory 233136 kb
Host smart-bd9a1f79-0cce-4f08-bbf5-3c3bda0ca168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877436744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.877436744
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2543479372
Short name T1535
Test name
Test status
Simulation time 13713752 ps
CPU time 0.74 seconds
Started Mar 10 02:47:26 PM PDT 24
Finished Mar 10 02:47:27 PM PDT 24
Peak memory 204776 kb
Host smart-045319eb-2c94-42d6-a97c-3e3c9ff96207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543479372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2543479372
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.88411796
Short name T1383
Test name
Test status
Simulation time 158530973 ps
CPU time 0.73 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:32 PM PDT 24
Peak memory 204760 kb
Host smart-d7dfb4ca-4e84-4dfd-ba4d-71ee286d25bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88411796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.88411796
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3870542867
Short name T385
Test name
Test status
Simulation time 592780812 ps
CPU time 3.74 seconds
Started Mar 10 02:47:24 PM PDT 24
Finished Mar 10 02:47:28 PM PDT 24
Peak memory 218020 kb
Host smart-ae24b95b-4090-4ce2-b532-4af75377aefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870542867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3870542867
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.873524045
Short name T1743
Test name
Test status
Simulation time 694917244 ps
CPU time 4.68 seconds
Started Mar 10 01:50:25 PM PDT 24
Finished Mar 10 01:50:30 PM PDT 24
Peak memory 223924 kb
Host smart-c5c2b611-5e6e-485d-9ea8-d2383f3af2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873524045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.873524045
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3406602502
Short name T636
Test name
Test status
Simulation time 20456969 ps
CPU time 0.76 seconds
Started Mar 10 02:47:24 PM PDT 24
Finished Mar 10 02:47:25 PM PDT 24
Peak memory 205840 kb
Host smart-ff7dddbd-125f-4d57-8e61-806d957a2ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406602502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3406602502
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.773794547
Short name T373
Test name
Test status
Simulation time 13005435 ps
CPU time 0.76 seconds
Started Mar 10 01:50:22 PM PDT 24
Finished Mar 10 01:50:23 PM PDT 24
Peak memory 204836 kb
Host smart-7b8b674c-be9e-4108-8e9b-b55eb8d638d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773794547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.773794547
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1494972298
Short name T28
Test name
Test status
Simulation time 33072263510 ps
CPU time 88.34 seconds
Started Mar 10 02:47:24 PM PDT 24
Finished Mar 10 02:48:53 PM PDT 24
Peak memory 256700 kb
Host smart-bbf049ce-3d26-4289-a639-129a88e20674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494972298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1494972298
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2077643752
Short name T666
Test name
Test status
Simulation time 32083898764 ps
CPU time 137.02 seconds
Started Mar 10 01:50:38 PM PDT 24
Finished Mar 10 01:52:55 PM PDT 24
Peak memory 248572 kb
Host smart-58424697-d340-4524-9e7a-de167fd499c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077643752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2077643752
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1298174171
Short name T914
Test name
Test status
Simulation time 7838691386 ps
CPU time 89.98 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:52:01 PM PDT 24
Peak memory 264336 kb
Host smart-bd0750a0-9ff8-4727-9c3c-5cc9866b1c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298174171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1298174171
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3170486627
Short name T1513
Test name
Test status
Simulation time 10580857152 ps
CPU time 58.03 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:48:25 PM PDT 24
Peak memory 253780 kb
Host smart-c3ab973d-9fe5-4e5b-bf83-30a8ad733ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170486627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3170486627
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.156757209
Short name T375
Test name
Test status
Simulation time 49039858623 ps
CPU time 97.97 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:49:06 PM PDT 24
Peak memory 256872 kb
Host smart-ee4e962c-75af-4ce4-80d4-36e674b89b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156757209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.156757209
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.928822499
Short name T1460
Test name
Test status
Simulation time 1496234146 ps
CPU time 33.37 seconds
Started Mar 10 01:50:32 PM PDT 24
Finished Mar 10 01:51:06 PM PDT 24
Peak memory 248624 kb
Host smart-14af3fc4-b4f8-4e9a-8574-1e0ab5200e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928822499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.928822499
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1546278141
Short name T805
Test name
Test status
Simulation time 2135887256 ps
CPU time 14.75 seconds
Started Mar 10 01:50:25 PM PDT 24
Finished Mar 10 01:50:40 PM PDT 24
Peak memory 234084 kb
Host smart-d4116601-66ad-4e48-ba13-78eac1287402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546278141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1546278141
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3332224335
Short name T1770
Test name
Test status
Simulation time 28279873185 ps
CPU time 38.16 seconds
Started Mar 10 02:47:24 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 245432 kb
Host smart-a6352cbf-f6aa-47c7-afa8-a6fa828dde76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332224335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3332224335
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1468234855
Short name T982
Test name
Test status
Simulation time 113375712 ps
CPU time 2.73 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 232112 kb
Host smart-1cca6920-5d4a-4d2f-8d1a-95e5e8279d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468234855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1468234855
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3255079043
Short name T1529
Test name
Test status
Simulation time 534541916 ps
CPU time 2.84 seconds
Started Mar 10 01:50:27 PM PDT 24
Finished Mar 10 01:50:30 PM PDT 24
Peak memory 215948 kb
Host smart-337ad7d2-9cc1-4b93-bf23-4f98493f4e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255079043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3255079043
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2196765473
Short name T724
Test name
Test status
Simulation time 9768146951 ps
CPU time 16.91 seconds
Started Mar 10 02:47:25 PM PDT 24
Finished Mar 10 02:47:42 PM PDT 24
Peak memory 232160 kb
Host smart-5fe910d4-cf0b-44c0-b653-e8b65406a2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196765473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2196765473
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.321776527
Short name T895
Test name
Test status
Simulation time 15039233789 ps
CPU time 42.53 seconds
Started Mar 10 01:50:27 PM PDT 24
Finished Mar 10 01:51:09 PM PDT 24
Peak memory 234868 kb
Host smart-a23ab368-23f9-4ba6-9aa9-6314783a9539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321776527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.321776527
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2685952023
Short name T1911
Test name
Test status
Simulation time 1551831114 ps
CPU time 5.56 seconds
Started Mar 10 01:50:28 PM PDT 24
Finished Mar 10 01:50:34 PM PDT 24
Peak memory 233016 kb
Host smart-fc5bedcb-bdff-4489-8292-ee3f423951d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685952023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2685952023
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.638238847
Short name T1282
Test name
Test status
Simulation time 16344096991 ps
CPU time 14.92 seconds
Started Mar 10 02:47:25 PM PDT 24
Finished Mar 10 02:47:40 PM PDT 24
Peak memory 234036 kb
Host smart-9b769def-3ccc-4dc8-a8da-f1d6b72be346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638238847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.638238847
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1071371051
Short name T1622
Test name
Test status
Simulation time 1687966621 ps
CPU time 7.01 seconds
Started Mar 10 02:47:25 PM PDT 24
Finished Mar 10 02:47:32 PM PDT 24
Peak memory 220784 kb
Host smart-7874856c-41bc-4faf-a3a2-e0d7254c3d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071371051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1071371051
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.480757990
Short name T1442
Test name
Test status
Simulation time 3926773527 ps
CPU time 8.03 seconds
Started Mar 10 01:50:27 PM PDT 24
Finished Mar 10 01:50:35 PM PDT 24
Peak memory 234408 kb
Host smart-68b7cf98-2739-4d9f-af2d-a6de00bbfd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480757990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.480757990
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2302592009
Short name T1243
Test name
Test status
Simulation time 808884538 ps
CPU time 4.49 seconds
Started Mar 10 02:47:25 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 217816 kb
Host smart-d5b29a0b-705b-4ec1-8ccc-f12ebefc969c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2302592009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2302592009
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3708503453
Short name T1769
Test name
Test status
Simulation time 3717927076 ps
CPU time 5.25 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:36 PM PDT 24
Peak memory 217828 kb
Host smart-4f07d680-1cc3-4633-bbf1-bba4683df3b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3708503453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3708503453
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2291199014
Short name T828
Test name
Test status
Simulation time 5053010013 ps
CPU time 93.25 seconds
Started Mar 10 02:47:23 PM PDT 24
Finished Mar 10 02:48:56 PM PDT 24
Peak memory 248680 kb
Host smart-ff40e69b-6c53-4c1b-9ad5-51ec2d69337f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291199014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2291199014
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3647017980
Short name T1452
Test name
Test status
Simulation time 335399589800 ps
CPU time 532.58 seconds
Started Mar 10 01:50:33 PM PDT 24
Finished Mar 10 01:59:25 PM PDT 24
Peak memory 252872 kb
Host smart-f3f0eccb-9973-4dba-bd50-05e04708116e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647017980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3647017980
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2865492883
Short name T1564
Test name
Test status
Simulation time 13747181674 ps
CPU time 12.95 seconds
Started Mar 10 02:47:28 PM PDT 24
Finished Mar 10 02:47:41 PM PDT 24
Peak memory 215844 kb
Host smart-3e3c42d2-8e2a-4080-9f38-c6282db86946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865492883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2865492883
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3635664510
Short name T447
Test name
Test status
Simulation time 35210862751 ps
CPU time 44.24 seconds
Started Mar 10 01:50:27 PM PDT 24
Finished Mar 10 01:51:11 PM PDT 24
Peak memory 215836 kb
Host smart-c1120119-5b92-4667-ac55-418d159e7e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635664510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3635664510
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2747672071
Short name T519
Test name
Test status
Simulation time 1431963166 ps
CPU time 7.31 seconds
Started Mar 10 01:50:28 PM PDT 24
Finished Mar 10 01:50:35 PM PDT 24
Peak memory 215736 kb
Host smart-876119b7-0871-4ce0-bd98-2c1260f3783e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747672071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2747672071
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2964452951
Short name T612
Test name
Test status
Simulation time 15258457305 ps
CPU time 10.99 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:47:39 PM PDT 24
Peak memory 215768 kb
Host smart-cd4bb6b7-ef3e-41f4-bd6c-d4b20ef2dae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964452951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2964452951
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3502761875
Short name T284
Test name
Test status
Simulation time 66520993 ps
CPU time 1.09 seconds
Started Mar 10 01:50:27 PM PDT 24
Finished Mar 10 01:50:28 PM PDT 24
Peak memory 206004 kb
Host smart-4eb03749-734d-45fd-88b4-8d146271dce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502761875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3502761875
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4171290319
Short name T783
Test name
Test status
Simulation time 388945983 ps
CPU time 9.28 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:47:36 PM PDT 24
Peak memory 216188 kb
Host smart-73447cd0-48bb-4b44-99be-7e781286467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171290319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4171290319
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.398772775
Short name T1005
Test name
Test status
Simulation time 341652130 ps
CPU time 1 seconds
Started Mar 10 01:50:26 PM PDT 24
Finished Mar 10 01:50:28 PM PDT 24
Peak memory 204804 kb
Host smart-08719caa-56d4-4b97-9b1a-be360d14a848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398772775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.398772775
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.6024994
Short name T597
Test name
Test status
Simulation time 106906319 ps
CPU time 0.85 seconds
Started Mar 10 02:47:28 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 204836 kb
Host smart-103fa1e6-1f2b-4c14-8e97-d7921a3d026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6024994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.6024994
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1326604332
Short name T1245
Test name
Test status
Simulation time 4486798858 ps
CPU time 15.31 seconds
Started Mar 10 01:50:28 PM PDT 24
Finished Mar 10 01:50:44 PM PDT 24
Peak memory 219364 kb
Host smart-9ffad30a-5b94-473c-8f44-bc9db6f1d82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326604332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1326604332
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_upload.586170605
Short name T1134
Test name
Test status
Simulation time 288560223 ps
CPU time 6.48 seconds
Started Mar 10 02:47:25 PM PDT 24
Finished Mar 10 02:47:32 PM PDT 24
Peak memory 232592 kb
Host smart-3aa1847b-9483-4b35-befe-333929982d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586170605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.586170605
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1945415902
Short name T1516
Test name
Test status
Simulation time 43018386 ps
CPU time 0.72 seconds
Started Mar 10 02:47:38 PM PDT 24
Finished Mar 10 02:47:39 PM PDT 24
Peak memory 204432 kb
Host smart-abd12803-d0f0-44a4-a690-916915cfb7b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945415902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1945415902
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2089438851
Short name T79
Test name
Test status
Simulation time 41447852 ps
CPU time 0.71 seconds
Started Mar 10 01:50:40 PM PDT 24
Finished Mar 10 01:50:40 PM PDT 24
Peak memory 204836 kb
Host smart-151048ff-1f70-4601-9185-9e944efe7323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089438851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2089438851
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1169133102
Short name T1735
Test name
Test status
Simulation time 262090456 ps
CPU time 4.29 seconds
Started Mar 10 01:50:36 PM PDT 24
Finished Mar 10 01:50:41 PM PDT 24
Peak memory 233528 kb
Host smart-bc9fec92-2973-421d-a050-d121e37d550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169133102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1169133102
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.541999896
Short name T1539
Test name
Test status
Simulation time 8478350737 ps
CPU time 8.02 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:39 PM PDT 24
Peak memory 232616 kb
Host smart-fe7ea6a8-881e-4f71-b57b-b581d8c50738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541999896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.541999896
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1182173853
Short name T938
Test name
Test status
Simulation time 52558439 ps
CPU time 0.73 seconds
Started Mar 10 02:47:28 PM PDT 24
Finished Mar 10 02:47:29 PM PDT 24
Peak memory 204824 kb
Host smart-4f6d6a14-d73f-427f-b53e-db51ba5f26bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182173853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1182173853
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3001250911
Short name T307
Test name
Test status
Simulation time 58271057 ps
CPU time 0.89 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:33 PM PDT 24
Peak memory 205828 kb
Host smart-e4840a2d-004f-4a3e-8de6-4f40d9e9bb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001250911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3001250911
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3098739974
Short name T1877
Test name
Test status
Simulation time 25885011663 ps
CPU time 129.49 seconds
Started Mar 10 01:50:37 PM PDT 24
Finished Mar 10 01:52:47 PM PDT 24
Peak memory 262956 kb
Host smart-c8466677-d849-45d3-9f36-ab81b2bdd916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098739974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3098739974
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4171983881
Short name T248
Test name
Test status
Simulation time 5722349263 ps
CPU time 38.83 seconds
Started Mar 10 02:47:32 PM PDT 24
Finished Mar 10 02:48:11 PM PDT 24
Peak memory 248572 kb
Host smart-b46420ea-d795-409d-9214-fcf6fd4cb06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171983881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4171983881
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3639580867
Short name T1563
Test name
Test status
Simulation time 126287542668 ps
CPU time 328.89 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:53:00 PM PDT 24
Peak memory 269912 kb
Host smart-837f8f0f-4494-4ab6-a45e-ae66b4c499b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639580867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3639580867
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.965104557
Short name T1014
Test name
Test status
Simulation time 9505413874 ps
CPU time 51.26 seconds
Started Mar 10 01:50:36 PM PDT 24
Finished Mar 10 01:51:28 PM PDT 24
Peak memory 248600 kb
Host smart-88118705-cda7-4a31-b471-a4cc77022c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965104557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.965104557
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2598827612
Short name T817
Test name
Test status
Simulation time 5900836390 ps
CPU time 66.8 seconds
Started Mar 10 01:50:37 PM PDT 24
Finished Mar 10 01:51:44 PM PDT 24
Peak memory 236936 kb
Host smart-36e40478-b7de-41fa-abbe-dc997089d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598827612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2598827612
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2823430299
Short name T1155
Test name
Test status
Simulation time 5020735360 ps
CPU time 24.17 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:56 PM PDT 24
Peak memory 248052 kb
Host smart-61358ff5-7efa-44e1-886c-5348ca23f34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823430299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2823430299
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1041679023
Short name T1835
Test name
Test status
Simulation time 7233330252 ps
CPU time 45.48 seconds
Started Mar 10 01:50:35 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 239516 kb
Host smart-f23767db-9bff-4815-b904-cdf720fa2db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041679023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1041679023
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2299323953
Short name T1624
Test name
Test status
Simulation time 832994074 ps
CPU time 15.22 seconds
Started Mar 10 02:47:28 PM PDT 24
Finished Mar 10 02:47:44 PM PDT 24
Peak memory 254840 kb
Host smart-db8ebb0a-c252-4b85-b415-7585f59af405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299323953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2299323953
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1634149047
Short name T957
Test name
Test status
Simulation time 395697787 ps
CPU time 3.07 seconds
Started Mar 10 02:47:30 PM PDT 24
Finished Mar 10 02:47:33 PM PDT 24
Peak memory 217268 kb
Host smart-f3be2beb-63c8-465f-86ba-189f0563ff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634149047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1634149047
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1830314591
Short name T819
Test name
Test status
Simulation time 597921030 ps
CPU time 3.7 seconds
Started Mar 10 01:50:32 PM PDT 24
Finished Mar 10 01:50:36 PM PDT 24
Peak memory 223888 kb
Host smart-28e1ce97-6a77-4495-ae7d-2429e452e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830314591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1830314591
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2308715308
Short name T1318
Test name
Test status
Simulation time 193030706 ps
CPU time 4.05 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:35 PM PDT 24
Peak memory 217432 kb
Host smart-ea61eed0-6ae3-440b-a35a-bafda7f95912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308715308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2308715308
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.647521059
Short name T1802
Test name
Test status
Simulation time 3038572998 ps
CPU time 9.88 seconds
Started Mar 10 01:50:34 PM PDT 24
Finished Mar 10 01:50:44 PM PDT 24
Peak memory 232928 kb
Host smart-dc444e3a-9206-427f-b9c7-cfde5970d3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647521059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.647521059
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1708307517
Short name T208
Test name
Test status
Simulation time 3299577095 ps
CPU time 9.4 seconds
Started Mar 10 02:47:38 PM PDT 24
Finished Mar 10 02:47:47 PM PDT 24
Peak memory 217996 kb
Host smart-8b40ad47-ce89-4347-a3f8-e64f1b9fec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708307517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1708307517
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.479478712
Short name T795
Test name
Test status
Simulation time 37792885661 ps
CPU time 30.71 seconds
Started Mar 10 01:50:32 PM PDT 24
Finished Mar 10 01:51:03 PM PDT 24
Peak memory 222424 kb
Host smart-863f6c74-39bd-49aa-9a73-b075e05f5b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479478712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.479478712
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1008558695
Short name T234
Test name
Test status
Simulation time 16891296347 ps
CPU time 7.98 seconds
Started Mar 10 02:47:30 PM PDT 24
Finished Mar 10 02:47:38 PM PDT 24
Peak memory 220012 kb
Host smart-fbecbd6a-13c7-4528-a93c-dfcf5f7baa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008558695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1008558695
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3872493559
Short name T528
Test name
Test status
Simulation time 1192623829 ps
CPU time 3.67 seconds
Started Mar 10 01:50:38 PM PDT 24
Finished Mar 10 01:50:42 PM PDT 24
Peak memory 232896 kb
Host smart-7e7702c6-749b-4616-abf8-10ca15ea276f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872493559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3872493559
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2905523134
Short name T1888
Test name
Test status
Simulation time 1772773873 ps
CPU time 4.71 seconds
Started Mar 10 01:50:36 PM PDT 24
Finished Mar 10 01:50:41 PM PDT 24
Peak memory 218420 kb
Host smart-7713cf56-e6e8-45ef-906a-9ba69a96f2eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2905523134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2905523134
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.835388099
Short name T1661
Test name
Test status
Simulation time 597827583 ps
CPU time 4.49 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:36 PM PDT 24
Peak memory 219696 kb
Host smart-e75c2437-4920-4e85-8bd7-ec11db3afe21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=835388099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.835388099
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3216717451
Short name T1893
Test name
Test status
Simulation time 18429934950 ps
CPU time 127.3 seconds
Started Mar 10 01:50:37 PM PDT 24
Finished Mar 10 01:52:45 PM PDT 24
Peak memory 265140 kb
Host smart-aff343fa-5958-48de-8861-ef6ecb45a27a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216717451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3216717451
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3544172010
Short name T1440
Test name
Test status
Simulation time 151559019 ps
CPU time 1.16 seconds
Started Mar 10 02:47:28 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 206052 kb
Host smart-f37917f6-216a-49b7-b9b6-4f65ac514058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544172010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3544172010
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1743257450
Short name T1011
Test name
Test status
Simulation time 129545936579 ps
CPU time 35.14 seconds
Started Mar 10 02:47:26 PM PDT 24
Finished Mar 10 02:48:01 PM PDT 24
Peak memory 215768 kb
Host smart-7ee5fa2d-01b7-48f9-a547-28e657bbaca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743257450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1743257450
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1750204047
Short name T494
Test name
Test status
Simulation time 9732498498 ps
CPU time 17.7 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:48 PM PDT 24
Peak memory 215796 kb
Host smart-593e6810-ef10-4b8e-8029-6522511e9f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750204047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1750204047
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1595113650
Short name T1740
Test name
Test status
Simulation time 4894357560 ps
CPU time 19.34 seconds
Started Mar 10 01:50:32 PM PDT 24
Finished Mar 10 01:50:52 PM PDT 24
Peak memory 215828 kb
Host smart-3f8f2058-5094-467b-884d-57353b3a3484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595113650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1595113650
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2586995323
Short name T1162
Test name
Test status
Simulation time 1101117961 ps
CPU time 4.54 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:47:31 PM PDT 24
Peak memory 215724 kb
Host smart-c5f9c9f9-ed9b-47ba-aec2-9914777b20e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586995323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2586995323
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3689381271
Short name T1100
Test name
Test status
Simulation time 71481955 ps
CPU time 1 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:47:28 PM PDT 24
Peak memory 205916 kb
Host smart-728e94a2-0324-4fa8-86b8-26da00a905fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689381271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3689381271
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3785507887
Short name T449
Test name
Test status
Simulation time 808758108 ps
CPU time 3.17 seconds
Started Mar 10 01:50:32 PM PDT 24
Finished Mar 10 01:50:35 PM PDT 24
Peak memory 216144 kb
Host smart-faa59912-2e4f-44a3-a4d3-7d130cdc0ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785507887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3785507887
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1608772235
Short name T90
Test name
Test status
Simulation time 80679433 ps
CPU time 0.99 seconds
Started Mar 10 01:50:31 PM PDT 24
Finished Mar 10 01:50:32 PM PDT 24
Peak memory 204892 kb
Host smart-5e6a20ad-a8c3-4f41-a64b-ba82085953b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608772235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1608772235
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.910802966
Short name T635
Test name
Test status
Simulation time 356569547 ps
CPU time 0.79 seconds
Started Mar 10 02:47:27 PM PDT 24
Finished Mar 10 02:47:28 PM PDT 24
Peak memory 204888 kb
Host smart-5b67da2e-a8e9-4f44-902d-c1347aae4544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910802966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.910802966
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1765926240
Short name T1160
Test name
Test status
Simulation time 2230335511 ps
CPU time 10.34 seconds
Started Mar 10 01:50:39 PM PDT 24
Finished Mar 10 01:50:49 PM PDT 24
Peak memory 233328 kb
Host smart-bd6b3802-4485-4762-adc1-1a94604e03f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765926240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1765926240
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_upload.23508610
Short name T1930
Test name
Test status
Simulation time 9024352346 ps
CPU time 16.25 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:48 PM PDT 24
Peak memory 217260 kb
Host smart-76921e3e-98b0-4e6b-a174-af1f170ba221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23508610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.23508610
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1600418346
Short name T1419
Test name
Test status
Simulation time 12076157 ps
CPU time 0.71 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:47:36 PM PDT 24
Peak memory 204812 kb
Host smart-c681ec12-ea46-4b26-ae68-9298983ff78b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600418346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1600418346
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2614982361
Short name T1733
Test name
Test status
Simulation time 14220882 ps
CPU time 0.74 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:50:43 PM PDT 24
Peak memory 204364 kb
Host smart-ddfae2b2-dc02-4e9b-acdc-e6cfae884e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614982361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2614982361
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1600196257
Short name T1760
Test name
Test status
Simulation time 40226120 ps
CPU time 2.44 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:34 PM PDT 24
Peak memory 232984 kb
Host smart-122ae8fe-9011-448b-8f0b-fa0169321329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600196257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1600196257
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2059749198
Short name T332
Test name
Test status
Simulation time 274832614 ps
CPU time 3.07 seconds
Started Mar 10 01:50:47 PM PDT 24
Finished Mar 10 01:50:50 PM PDT 24
Peak memory 216172 kb
Host smart-cc369e6b-e6bc-447a-811c-8965f46d953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059749198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2059749198
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1160789641
Short name T1658
Test name
Test status
Simulation time 55896381 ps
CPU time 0.8 seconds
Started Mar 10 01:50:34 PM PDT 24
Finished Mar 10 01:50:35 PM PDT 24
Peak memory 205476 kb
Host smart-c2d4d05b-2234-4747-b032-8dc9fd1feeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160789641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1160789641
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1421438132
Short name T814
Test name
Test status
Simulation time 140947412 ps
CPU time 0.76 seconds
Started Mar 10 02:47:29 PM PDT 24
Finished Mar 10 02:47:30 PM PDT 24
Peak memory 204464 kb
Host smart-d1b2a10d-b753-4e16-b8eb-fdf8419ba56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421438132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1421438132
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1962009975
Short name T1549
Test name
Test status
Simulation time 13592703664 ps
CPU time 71.96 seconds
Started Mar 10 01:50:46 PM PDT 24
Finished Mar 10 01:51:58 PM PDT 24
Peak memory 239212 kb
Host smart-9aacdf55-3873-4ca0-b8dc-e8bed4f86496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962009975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1962009975
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2337005315
Short name T731
Test name
Test status
Simulation time 1314012610 ps
CPU time 11.77 seconds
Started Mar 10 02:47:40 PM PDT 24
Finished Mar 10 02:47:51 PM PDT 24
Peak memory 248492 kb
Host smart-55d32dcd-3591-4cc1-8e9e-db47202a7c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337005315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2337005315
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3372152266
Short name T1594
Test name
Test status
Simulation time 46875085945 ps
CPU time 295.78 seconds
Started Mar 10 01:50:47 PM PDT 24
Finished Mar 10 01:55:43 PM PDT 24
Peak memory 251480 kb
Host smart-f3f8d806-a559-41b0-9a72-d2552d8a6d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372152266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3372152266
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.480292488
Short name T1247
Test name
Test status
Simulation time 4851747830 ps
CPU time 33.61 seconds
Started Mar 10 02:47:36 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 240484 kb
Host smart-de5a922a-6229-4fc9-96ea-80ace51044bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480292488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.480292488
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2655307115
Short name T1722
Test name
Test status
Simulation time 8841839329 ps
CPU time 38.77 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 233228 kb
Host smart-e96a4b0f-529f-41e8-bfc4-edcf23373a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655307115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2655307115
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3625069965
Short name T48
Test name
Test status
Simulation time 16816835278 ps
CPU time 122.98 seconds
Started Mar 10 02:47:34 PM PDT 24
Finished Mar 10 02:49:38 PM PDT 24
Peak memory 256096 kb
Host smart-cfb4b714-190a-471d-b422-7bee6eff85a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625069965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3625069965
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3085793011
Short name T596
Test name
Test status
Simulation time 52461020285 ps
CPU time 54.2 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:48:29 PM PDT 24
Peak memory 234916 kb
Host smart-d4a67759-1491-4d84-9184-728941ba4673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085793011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3085793011
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.51761247
Short name T901
Test name
Test status
Simulation time 6162804634 ps
CPU time 30.93 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:51:13 PM PDT 24
Peak memory 237764 kb
Host smart-23aa550a-ed21-4acd-be8f-ccc67a94c2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51761247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.51761247
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2041503996
Short name T1080
Test name
Test status
Simulation time 107103456 ps
CPU time 2.94 seconds
Started Mar 10 02:47:29 PM PDT 24
Finished Mar 10 02:47:32 PM PDT 24
Peak memory 232816 kb
Host smart-8cb6b4c7-a34c-4d50-a3d6-a45f2943363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041503996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2041503996
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intercept.69685569
Short name T187
Test name
Test status
Simulation time 4368264990 ps
CPU time 11.12 seconds
Started Mar 10 01:50:43 PM PDT 24
Finished Mar 10 01:50:54 PM PDT 24
Peak memory 233736 kb
Host smart-3fd29b4f-ca63-4b7b-9ac1-53fe13fba20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69685569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.69685569
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3470572720
Short name T1507
Test name
Test status
Simulation time 2605932417 ps
CPU time 4.86 seconds
Started Mar 10 02:47:38 PM PDT 24
Finished Mar 10 02:47:43 PM PDT 24
Peak memory 223920 kb
Host smart-8dbac6a4-3e07-4ee0-9a6e-9cc32999c8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470572720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3470572720
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4152944048
Short name T531
Test name
Test status
Simulation time 15866171518 ps
CPU time 16.39 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 233288 kb
Host smart-058777c3-3f8e-4027-b75d-8d9af16feaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152944048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4152944048
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1912774391
Short name T1757
Test name
Test status
Simulation time 32761900 ps
CPU time 2.59 seconds
Started Mar 10 02:47:38 PM PDT 24
Finished Mar 10 02:47:41 PM PDT 24
Peak memory 233032 kb
Host smart-7796582c-b183-40cb-9a1e-86ca58123348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912774391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1912774391
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.212723575
Short name T1842
Test name
Test status
Simulation time 3058574861 ps
CPU time 7.94 seconds
Started Mar 10 01:50:39 PM PDT 24
Finished Mar 10 01:50:47 PM PDT 24
Peak memory 223916 kb
Host smart-1c59463e-fda7-4c47-b814-5ecda3b17455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212723575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.212723575
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1288862613
Short name T950
Test name
Test status
Simulation time 121403724 ps
CPU time 3.13 seconds
Started Mar 10 02:47:30 PM PDT 24
Finished Mar 10 02:47:33 PM PDT 24
Peak memory 233096 kb
Host smart-099342d0-8608-4c14-9497-c86fc13c91ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288862613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1288862613
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.494054376
Short name T993
Test name
Test status
Simulation time 155594781 ps
CPU time 4.11 seconds
Started Mar 10 01:50:36 PM PDT 24
Finished Mar 10 01:50:40 PM PDT 24
Peak memory 232020 kb
Host smart-13030111-8fa7-434f-a533-929b1cad9067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494054376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.494054376
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2138176166
Short name T871
Test name
Test status
Simulation time 846058734 ps
CPU time 5.03 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:36 PM PDT 24
Peak memory 219816 kb
Host smart-f82a144e-401f-4794-b310-40151768c691
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2138176166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2138176166
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.409737252
Short name T898
Test name
Test status
Simulation time 845439244 ps
CPU time 5.31 seconds
Started Mar 10 01:50:43 PM PDT 24
Finished Mar 10 01:50:49 PM PDT 24
Peak memory 217920 kb
Host smart-d5d7588f-493e-4f73-8543-0234bc7eef21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409737252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.409737252
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1495501060
Short name T1317
Test name
Test status
Simulation time 4458378000 ps
CPU time 72.17 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:48:47 PM PDT 24
Peak memory 265048 kb
Host smart-afacd6ad-5762-4859-acc0-c30f7b51d60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495501060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1495501060
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1608893546
Short name T1414
Test name
Test status
Simulation time 41711151367 ps
CPU time 33.93 seconds
Started Mar 10 01:50:35 PM PDT 24
Finished Mar 10 01:51:09 PM PDT 24
Peak memory 215876 kb
Host smart-91f44170-e530-45f4-b5d2-ef411fa5e948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608893546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1608893546
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.327186139
Short name T620
Test name
Test status
Simulation time 3274517128 ps
CPU time 25.28 seconds
Started Mar 10 02:47:29 PM PDT 24
Finished Mar 10 02:47:54 PM PDT 24
Peak memory 215864 kb
Host smart-311a71ee-97fe-483f-802c-bf813aa4ebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327186139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.327186139
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1016444762
Short name T286
Test name
Test status
Simulation time 4818653342 ps
CPU time 14.02 seconds
Started Mar 10 02:47:32 PM PDT 24
Finished Mar 10 02:47:47 PM PDT 24
Peak memory 215864 kb
Host smart-9d743870-1d51-45b3-8539-791ef6cf7e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016444762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1016444762
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2806087947
Short name T1578
Test name
Test status
Simulation time 1979214650 ps
CPU time 7.93 seconds
Started Mar 10 01:50:38 PM PDT 24
Finished Mar 10 01:50:47 PM PDT 24
Peak memory 215740 kb
Host smart-587bcbf7-015e-44c1-ad84-1791be5273db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806087947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2806087947
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2087336388
Short name T1370
Test name
Test status
Simulation time 191537346 ps
CPU time 6.15 seconds
Started Mar 10 02:47:30 PM PDT 24
Finished Mar 10 02:47:36 PM PDT 24
Peak memory 215924 kb
Host smart-d672a051-40a0-4f95-a70c-a8589e19d5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087336388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2087336388
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3999569183
Short name T1401
Test name
Test status
Simulation time 110773576 ps
CPU time 1.4 seconds
Started Mar 10 01:50:36 PM PDT 24
Finished Mar 10 01:50:38 PM PDT 24
Peak memory 207704 kb
Host smart-54c406f0-d66d-40e6-b394-f2ed3aa4a8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999569183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3999569183
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1905087314
Short name T1193
Test name
Test status
Simulation time 146860690 ps
CPU time 0.92 seconds
Started Mar 10 01:50:36 PM PDT 24
Finished Mar 10 01:50:38 PM PDT 24
Peak memory 205900 kb
Host smart-99643726-e779-47b7-b924-176bf410fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905087314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1905087314
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2317480057
Short name T1250
Test name
Test status
Simulation time 197005536 ps
CPU time 0.81 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:32 PM PDT 24
Peak memory 204828 kb
Host smart-5c27d40f-ca51-4ff1-8a8e-1ba1c3bd8320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317480057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2317480057
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.229164906
Short name T1468
Test name
Test status
Simulation time 6994585029 ps
CPU time 10.39 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:50:51 PM PDT 24
Peak memory 233652 kb
Host smart-d0d96c17-8a97-4718-aecd-24b78c90cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229164906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.229164906
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_upload.2404560610
Short name T1033
Test name
Test status
Simulation time 1541800474 ps
CPU time 3.45 seconds
Started Mar 10 02:47:31 PM PDT 24
Finished Mar 10 02:47:35 PM PDT 24
Peak memory 232744 kb
Host smart-11dc4032-53fd-4957-9a3c-47d7e642478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404560610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2404560610
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2170482806
Short name T1366
Test name
Test status
Simulation time 27516230 ps
CPU time 0.69 seconds
Started Mar 10 02:47:34 PM PDT 24
Finished Mar 10 02:47:35 PM PDT 24
Peak memory 203856 kb
Host smart-b8be7f1a-06c0-4d87-a4bc-96acc964a46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170482806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2170482806
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3786658978
Short name T758
Test name
Test status
Simulation time 14228414 ps
CPU time 0.79 seconds
Started Mar 10 01:50:47 PM PDT 24
Finished Mar 10 01:50:48 PM PDT 24
Peak memory 204420 kb
Host smart-d74e20d1-5ade-4276-8eb3-3bb789dac9d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786658978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3786658978
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1710529543
Short name T655
Test name
Test status
Simulation time 680308387 ps
CPU time 4.24 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:47:39 PM PDT 24
Peak memory 218244 kb
Host smart-2cde49b6-3366-4b90-812b-4a7c0ee84c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710529543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1710529543
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2644787633
Short name T1006
Test name
Test status
Simulation time 232753410 ps
CPU time 2.84 seconds
Started Mar 10 01:50:44 PM PDT 24
Finished Mar 10 01:50:47 PM PDT 24
Peak memory 233080 kb
Host smart-97da2e8c-9cbd-4f7b-8f62-48cf4ab57e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644787633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2644787633
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.190049158
Short name T442
Test name
Test status
Simulation time 32652242 ps
CPU time 0.76 seconds
Started Mar 10 02:47:36 PM PDT 24
Finished Mar 10 02:47:37 PM PDT 24
Peak memory 204864 kb
Host smart-133d267c-e9b3-43a0-b62e-eba679989d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190049158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.190049158
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3075129864
Short name T1089
Test name
Test status
Simulation time 61440320 ps
CPU time 0.76 seconds
Started Mar 10 01:50:46 PM PDT 24
Finished Mar 10 01:50:47 PM PDT 24
Peak memory 204796 kb
Host smart-b33c7313-7994-40c0-95fe-0e932e8c25b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075129864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3075129864
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.482963934
Short name T1236
Test name
Test status
Simulation time 6532984315 ps
CPU time 78.12 seconds
Started Mar 10 02:47:38 PM PDT 24
Finished Mar 10 02:48:57 PM PDT 24
Peak memory 245572 kb
Host smart-652e95b3-6d91-412e-b6a2-2d1fb123038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482963934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.482963934
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.516481347
Short name T1731
Test name
Test status
Simulation time 46237105019 ps
CPU time 120.67 seconds
Started Mar 10 01:50:45 PM PDT 24
Finished Mar 10 01:52:46 PM PDT 24
Peak memory 268936 kb
Host smart-06f4c949-6476-4ea9-a2bf-340c16078887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516481347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.516481347
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.540835615
Short name T1381
Test name
Test status
Simulation time 4884340398 ps
CPU time 94.39 seconds
Started Mar 10 01:50:45 PM PDT 24
Finished Mar 10 01:52:19 PM PDT 24
Peak memory 252936 kb
Host smart-c3ccc91d-aeed-4e24-a18b-f7249ae6bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540835615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.540835615
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.803362618
Short name T160
Test name
Test status
Simulation time 253273529283 ps
CPU time 309.66 seconds
Started Mar 10 02:47:43 PM PDT 24
Finished Mar 10 02:52:53 PM PDT 24
Peak memory 272380 kb
Host smart-36b86e49-24c7-45ee-ab78-56e803aef35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803362618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.803362618
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1207852294
Short name T648
Test name
Test status
Simulation time 42315024410 ps
CPU time 144.95 seconds
Started Mar 10 01:50:46 PM PDT 24
Finished Mar 10 01:53:11 PM PDT 24
Peak memory 252356 kb
Host smart-0df269af-c7dc-47f4-b4f9-e3f826f55b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207852294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1207852294
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2325114623
Short name T1664
Test name
Test status
Simulation time 1331713315 ps
CPU time 6.49 seconds
Started Mar 10 01:50:47 PM PDT 24
Finished Mar 10 01:50:54 PM PDT 24
Peak memory 232076 kb
Host smart-c0d1823f-9df3-4c8b-968d-80b67e238a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325114623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2325114623
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.392657910
Short name T276
Test name
Test status
Simulation time 6249853266 ps
CPU time 34.45 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:48:13 PM PDT 24
Peak memory 247428 kb
Host smart-c2b39ef5-ebf0-496b-982d-69a6acd29c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392657910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.392657910
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2505652221
Short name T672
Test name
Test status
Simulation time 927788100 ps
CPU time 6.14 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:50:47 PM PDT 24
Peak memory 217888 kb
Host smart-8da7dacf-5316-4692-a5e5-30fe0562e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505652221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2505652221
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intercept.666807897
Short name T752
Test name
Test status
Simulation time 645219874 ps
CPU time 5.67 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:47:44 PM PDT 24
Peak memory 223904 kb
Host smart-07d9a1e5-49d2-40da-8336-b266a8853335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666807897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.666807897
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2964829270
Short name T1199
Test name
Test status
Simulation time 1490825066 ps
CPU time 10.57 seconds
Started Mar 10 01:50:40 PM PDT 24
Finished Mar 10 01:50:51 PM PDT 24
Peak memory 246504 kb
Host smart-804edfa3-c4e5-467e-b770-f63a202b574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964829270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2964829270
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3269247507
Short name T826
Test name
Test status
Simulation time 165905486702 ps
CPU time 37.85 seconds
Started Mar 10 02:47:37 PM PDT 24
Finished Mar 10 02:48:15 PM PDT 24
Peak memory 240160 kb
Host smart-8ec6b5b0-544e-468f-90b6-57496bcc6361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269247507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3269247507
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2473274238
Short name T239
Test name
Test status
Simulation time 660835424 ps
CPU time 4.25 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:50:45 PM PDT 24
Peak memory 232712 kb
Host smart-46321257-dccb-440c-9123-18c1cbdc7d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473274238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2473274238
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3666253029
Short name T1497
Test name
Test status
Simulation time 162700721 ps
CPU time 2.69 seconds
Started Mar 10 02:47:33 PM PDT 24
Finished Mar 10 02:47:36 PM PDT 24
Peak memory 223844 kb
Host smart-c6c1d436-4bfb-4532-9fc0-d681cd7976fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666253029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3666253029
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2978147941
Short name T707
Test name
Test status
Simulation time 60462216625 ps
CPU time 37.54 seconds
Started Mar 10 01:50:43 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 234736 kb
Host smart-bd6f40e6-f098-4a06-8490-ab4e09eed544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978147941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2978147941
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3099767870
Short name T661
Test name
Test status
Simulation time 1211477277 ps
CPU time 10.23 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:47:46 PM PDT 24
Peak memory 239676 kb
Host smart-33bec976-bddc-47f5-909a-2a2be565a737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099767870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3099767870
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1368028232
Short name T1444
Test name
Test status
Simulation time 228383407 ps
CPU time 3.56 seconds
Started Mar 10 02:47:43 PM PDT 24
Finished Mar 10 02:47:47 PM PDT 24
Peak memory 218152 kb
Host smart-1c1c0dbc-078b-4a8c-b62c-d9de4dfff014
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1368028232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1368028232
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1459357472
Short name T1667
Test name
Test status
Simulation time 150813106 ps
CPU time 3.72 seconds
Started Mar 10 01:50:44 PM PDT 24
Finished Mar 10 01:50:48 PM PDT 24
Peak memory 221644 kb
Host smart-9f681328-1a2f-4aee-9749-8c75cf2adac1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1459357472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1459357472
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.774669572
Short name T45
Test name
Test status
Simulation time 305828482954 ps
CPU time 411.54 seconds
Started Mar 10 02:47:38 PM PDT 24
Finished Mar 10 02:54:30 PM PDT 24
Peak memory 264964 kb
Host smart-e8afa29a-66ae-4ec0-a949-5dca6720de20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774669572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.774669572
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2627831628
Short name T566
Test name
Test status
Simulation time 5111154116 ps
CPU time 31.81 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:48:07 PM PDT 24
Peak memory 215860 kb
Host smart-4e498aaf-fb10-4b9a-9b32-e7331aa0d529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627831628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2627831628
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.595688788
Short name T1569
Test name
Test status
Simulation time 2434840530 ps
CPU time 16.26 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 215756 kb
Host smart-89e88449-9ead-40ec-afe5-02185d610ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595688788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.595688788
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1076899230
Short name T1130
Test name
Test status
Simulation time 5926285324 ps
CPU time 20.81 seconds
Started Mar 10 01:50:43 PM PDT 24
Finished Mar 10 01:51:04 PM PDT 24
Peak memory 215812 kb
Host smart-8d660b8b-c683-452a-b1d7-cfb5ca860d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076899230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1076899230
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3689031780
Short name T1806
Test name
Test status
Simulation time 3703960450 ps
CPU time 13 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:47:48 PM PDT 24
Peak memory 215712 kb
Host smart-3398cf3c-3bf8-41f3-a9ae-d27d14d47381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689031780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3689031780
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2347681976
Short name T1675
Test name
Test status
Simulation time 32373021 ps
CPU time 1.62 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:50:43 PM PDT 24
Peak memory 207824 kb
Host smart-f39fe80c-6b23-4b13-9aa2-8d7a71bbbea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347681976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2347681976
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.832387932
Short name T4
Test name
Test status
Simulation time 1041939883 ps
CPU time 3.01 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:47:38 PM PDT 24
Peak memory 215872 kb
Host smart-a5248274-9e12-462a-b7e2-ae10a66f2cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832387932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.832387932
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1009255881
Short name T785
Test name
Test status
Simulation time 26345058 ps
CPU time 0.8 seconds
Started Mar 10 02:47:43 PM PDT 24
Finished Mar 10 02:47:45 PM PDT 24
Peak memory 204852 kb
Host smart-741fb213-59f6-4783-8dd7-90811ce10d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009255881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1009255881
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3640461172
Short name T1331
Test name
Test status
Simulation time 67733837 ps
CPU time 0.83 seconds
Started Mar 10 01:50:41 PM PDT 24
Finished Mar 10 01:50:42 PM PDT 24
Peak memory 204884 kb
Host smart-396e6acd-6a2a-430b-94c7-8013a304e54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640461172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3640461172
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3008853222
Short name T1329
Test name
Test status
Simulation time 17424084401 ps
CPU time 24.3 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:48:04 PM PDT 24
Peak memory 218848 kb
Host smart-40ea7385-9cda-4dd7-8563-fee238e4b515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008853222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3008853222
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_upload.3012602498
Short name T1253
Test name
Test status
Simulation time 587214929 ps
CPU time 3.75 seconds
Started Mar 10 01:50:43 PM PDT 24
Finished Mar 10 01:50:47 PM PDT 24
Peak memory 217020 kb
Host smart-34e34357-4ca0-4fe1-9487-9afbfe55b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012602498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3012602498
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1572743457
Short name T335
Test name
Test status
Simulation time 34224256 ps
CPU time 0.71 seconds
Started Mar 10 01:50:56 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 203856 kb
Host smart-41007ae0-0cd2-4ca5-8f5f-4ff6fdf9f712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572743457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1572743457
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.393438509
Short name T1459
Test name
Test status
Simulation time 25556492 ps
CPU time 0.77 seconds
Started Mar 10 02:47:40 PM PDT 24
Finished Mar 10 02:47:41 PM PDT 24
Peak memory 204424 kb
Host smart-86d4a388-e17c-45ba-b3fb-6bc098327657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393438509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.393438509
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1189225822
Short name T10
Test name
Test status
Simulation time 251376516 ps
CPU time 2.41 seconds
Started Mar 10 02:47:38 PM PDT 24
Finished Mar 10 02:47:41 PM PDT 24
Peak memory 233076 kb
Host smart-8354686a-002e-4560-8c8e-540987cde208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189225822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1189225822
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2008128941
Short name T985
Test name
Test status
Simulation time 1311991205 ps
CPU time 3.43 seconds
Started Mar 10 01:50:54 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 218632 kb
Host smart-24dd6d2f-6830-44b6-9512-903b9b803542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008128941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2008128941
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1192015989
Short name T1670
Test name
Test status
Simulation time 46245649 ps
CPU time 0.77 seconds
Started Mar 10 02:47:33 PM PDT 24
Finished Mar 10 02:47:35 PM PDT 24
Peak memory 204808 kb
Host smart-7d58a955-3f99-4c08-a01d-552d8fc964fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192015989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1192015989
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2312385729
Short name T1116
Test name
Test status
Simulation time 25683690 ps
CPU time 0.74 seconds
Started Mar 10 01:50:47 PM PDT 24
Finished Mar 10 01:50:48 PM PDT 24
Peak memory 204484 kb
Host smart-d0abf90d-21ff-439c-95dd-6827a9042eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312385729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2312385729
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2713128405
Short name T967
Test name
Test status
Simulation time 11781651520 ps
CPU time 89.55 seconds
Started Mar 10 01:50:53 PM PDT 24
Finished Mar 10 01:52:23 PM PDT 24
Peak memory 255580 kb
Host smart-aabce2dd-db86-42f9-b6bf-378fd9c449d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713128405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2713128405
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4177175019
Short name T211
Test name
Test status
Simulation time 33563058477 ps
CPU time 98.45 seconds
Started Mar 10 02:47:40 PM PDT 24
Finished Mar 10 02:49:19 PM PDT 24
Peak memory 248484 kb
Host smart-8670ca61-4843-4b79-bfcc-9ba584d52098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177175019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4177175019
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1021498502
Short name T437
Test name
Test status
Simulation time 6610949886 ps
CPU time 56.93 seconds
Started Mar 10 01:50:49 PM PDT 24
Finished Mar 10 01:51:46 PM PDT 24
Peak memory 252828 kb
Host smart-0b09eac8-04ad-4806-936f-9ab1ee7b7135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021498502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1021498502
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.34820652
Short name T47
Test name
Test status
Simulation time 5409769717 ps
CPU time 55.84 seconds
Started Mar 10 02:47:42 PM PDT 24
Finished Mar 10 02:48:38 PM PDT 24
Peak memory 249760 kb
Host smart-ce6304c4-a2ca-4d8e-ab76-c84d5e1b4745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34820652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.34820652
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1243374105
Short name T1020
Test name
Test status
Simulation time 23868477566 ps
CPU time 249.23 seconds
Started Mar 10 01:50:50 PM PDT 24
Finished Mar 10 01:54:59 PM PDT 24
Peak memory 256000 kb
Host smart-dcbe5321-f564-409a-ab93-7ef98476f163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243374105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1243374105
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4005735286
Short name T1847
Test name
Test status
Simulation time 33966217634 ps
CPU time 117.08 seconds
Started Mar 10 02:47:43 PM PDT 24
Finished Mar 10 02:49:40 PM PDT 24
Peak memory 236572 kb
Host smart-c49977d7-c779-42ac-af6c-915f0aa730a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005735286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4005735286
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2428022075
Short name T1264
Test name
Test status
Simulation time 23433940913 ps
CPU time 28.01 seconds
Started Mar 10 02:47:41 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 248168 kb
Host smart-7616cd7d-577f-4acf-9144-780713900361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428022075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2428022075
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2894160403
Short name T142
Test name
Test status
Simulation time 6601815693 ps
CPU time 21.36 seconds
Started Mar 10 01:50:52 PM PDT 24
Finished Mar 10 01:51:13 PM PDT 24
Peak memory 233128 kb
Host smart-bbdb671b-793c-4585-929b-f7d620c05c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894160403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2894160403
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.317763213
Short name T1537
Test name
Test status
Simulation time 18552820655 ps
CPU time 6.79 seconds
Started Mar 10 02:47:42 PM PDT 24
Finished Mar 10 02:47:49 PM PDT 24
Peak memory 223916 kb
Host smart-ae493e7c-b30e-4315-a88f-7b296f96f32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317763213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.317763213
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4226599121
Short name T1091
Test name
Test status
Simulation time 917713091 ps
CPU time 5.19 seconds
Started Mar 10 01:50:46 PM PDT 24
Finished Mar 10 01:50:51 PM PDT 24
Peak memory 233096 kb
Host smart-ffb5652a-31d3-4354-9bc1-0b9d78ea1690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226599121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4226599121
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2149390254
Short name T787
Test name
Test status
Simulation time 213634590 ps
CPU time 3.66 seconds
Started Mar 10 01:50:50 PM PDT 24
Finished Mar 10 01:50:54 PM PDT 24
Peak memory 232088 kb
Host smart-ffce7359-ff3c-4bfe-a4ce-a97704e61874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149390254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2149390254
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3206312929
Short name T880
Test name
Test status
Simulation time 1280788207 ps
CPU time 12.73 seconds
Started Mar 10 02:47:44 PM PDT 24
Finished Mar 10 02:47:57 PM PDT 24
Peak memory 240240 kb
Host smart-e18e74be-07f1-4a9c-86a0-15e4ffc9704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206312929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3206312929
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1710508265
Short name T934
Test name
Test status
Simulation time 2096799816 ps
CPU time 9.33 seconds
Started Mar 10 01:50:45 PM PDT 24
Finished Mar 10 01:50:55 PM PDT 24
Peak memory 220324 kb
Host smart-00938fab-c2c9-4370-9b4f-a2f42f873a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710508265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1710508265
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.55148665
Short name T1177
Test name
Test status
Simulation time 2988315862 ps
CPU time 3.74 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:47:43 PM PDT 24
Peak memory 216976 kb
Host smart-b74425e7-a227-4f06-b46e-cb7df4811c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55148665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.55148665
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1832967479
Short name T430
Test name
Test status
Simulation time 345847560 ps
CPU time 2.4 seconds
Started Mar 10 02:47:41 PM PDT 24
Finished Mar 10 02:47:44 PM PDT 24
Peak memory 223808 kb
Host smart-de8dc908-5c49-4ef8-9f6a-7c20afc2b08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832967479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1832967479
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3867933327
Short name T1416
Test name
Test status
Simulation time 898168815 ps
CPU time 4.23 seconds
Started Mar 10 01:50:47 PM PDT 24
Finished Mar 10 01:50:52 PM PDT 24
Peak memory 215796 kb
Host smart-a428cb0d-1718-486d-8581-f991993ab8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867933327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3867933327
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1550787646
Short name T408
Test name
Test status
Simulation time 1176393326 ps
CPU time 5.66 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:47:45 PM PDT 24
Peak memory 219544 kb
Host smart-d148c199-6867-4f36-9a77-02321da32f74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1550787646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1550787646
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3263708853
Short name T830
Test name
Test status
Simulation time 15349007862 ps
CPU time 5.35 seconds
Started Mar 10 01:50:53 PM PDT 24
Finished Mar 10 01:50:58 PM PDT 24
Peak memory 217780 kb
Host smart-8ab4eadb-033f-451e-b928-b066ac30deea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3263708853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3263708853
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1155317926
Short name T152
Test name
Test status
Simulation time 67903401545 ps
CPU time 308.61 seconds
Started Mar 10 01:50:53 PM PDT 24
Finished Mar 10 01:56:01 PM PDT 24
Peak memory 271392 kb
Host smart-7c8b4042-8913-4e7e-b3ba-241d7e977459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155317926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1155317926
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4235405807
Short name T669
Test name
Test status
Simulation time 133132876 ps
CPU time 0.89 seconds
Started Mar 10 02:47:40 PM PDT 24
Finished Mar 10 02:47:41 PM PDT 24
Peak memory 204676 kb
Host smart-b4450331-dd28-450c-800f-b4e945753406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235405807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4235405807
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3532000873
Short name T943
Test name
Test status
Simulation time 12127441986 ps
CPU time 47.09 seconds
Started Mar 10 01:50:46 PM PDT 24
Finished Mar 10 01:51:33 PM PDT 24
Peak memory 215792 kb
Host smart-63114d0b-45a9-4779-a0f3-110d7a86ee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532000873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3532000873
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3535819846
Short name T884
Test name
Test status
Simulation time 5255400577 ps
CPU time 41.06 seconds
Started Mar 10 02:47:35 PM PDT 24
Finished Mar 10 02:48:16 PM PDT 24
Peak memory 215876 kb
Host smart-27a8cc90-c847-45d9-87e0-bfb646bf90ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535819846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3535819846
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1568960714
Short name T1820
Test name
Test status
Simulation time 4875693698 ps
CPU time 16.32 seconds
Started Mar 10 01:50:46 PM PDT 24
Finished Mar 10 01:51:03 PM PDT 24
Peak memory 215824 kb
Host smart-9fca1881-810e-4bb2-9c22-26b50581e89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568960714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1568960714
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.73439247
Short name T524
Test name
Test status
Simulation time 1175192938 ps
CPU time 5.56 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:47:45 PM PDT 24
Peak memory 207600 kb
Host smart-63788517-9901-43e5-9d64-68cd702837c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73439247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.73439247
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1560196307
Short name T780
Test name
Test status
Simulation time 206521223 ps
CPU time 1.52 seconds
Started Mar 10 02:47:44 PM PDT 24
Finished Mar 10 02:47:46 PM PDT 24
Peak memory 207444 kb
Host smart-6be728ca-a13f-4384-9e5e-95757a1dc009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560196307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1560196307
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.835833892
Short name T349
Test name
Test status
Simulation time 1010426889 ps
CPU time 3.07 seconds
Started Mar 10 01:50:44 PM PDT 24
Finished Mar 10 01:50:47 PM PDT 24
Peak memory 215808 kb
Host smart-52ca25e5-ef52-4961-b82c-6d74998ceac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835833892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.835833892
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1442171012
Short name T329
Test name
Test status
Simulation time 82565039 ps
CPU time 0.79 seconds
Started Mar 10 01:50:47 PM PDT 24
Finished Mar 10 01:50:48 PM PDT 24
Peak memory 204892 kb
Host smart-e4f98077-95a7-4bed-a365-9dd08749340d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442171012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1442171012
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.924499109
Short name T1148
Test name
Test status
Simulation time 409521025 ps
CPU time 0.97 seconds
Started Mar 10 02:47:40 PM PDT 24
Finished Mar 10 02:47:41 PM PDT 24
Peak memory 205896 kb
Host smart-004211c7-f1a5-4398-9010-8d8123edf516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924499109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.924499109
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2736308560
Short name T1581
Test name
Test status
Simulation time 22343838815 ps
CPU time 17.41 seconds
Started Mar 10 01:50:50 PM PDT 24
Finished Mar 10 01:51:07 PM PDT 24
Peak memory 231564 kb
Host smart-60462383-c3b6-4198-ae91-a4b239718828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736308560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2736308560
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_upload.3019476059
Short name T219
Test name
Test status
Simulation time 3304604306 ps
CPU time 8.68 seconds
Started Mar 10 02:47:41 PM PDT 24
Finished Mar 10 02:47:50 PM PDT 24
Peak memory 219004 kb
Host smart-3421c21b-93d7-449c-b50f-2059816c805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019476059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3019476059
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4032713022
Short name T384
Test name
Test status
Simulation time 43096062 ps
CPU time 0.72 seconds
Started Mar 10 02:47:49 PM PDT 24
Finished Mar 10 02:47:49 PM PDT 24
Peak memory 204760 kb
Host smart-4aa777ee-00f3-49ba-a510-715569a6f053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032713022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4032713022
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1728815166
Short name T829
Test name
Test status
Simulation time 176173325 ps
CPU time 2.72 seconds
Started Mar 10 02:47:45 PM PDT 24
Finished Mar 10 02:47:48 PM PDT 24
Peak memory 233008 kb
Host smart-0fc55137-48fe-4d87-8b30-c56e1c83ed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728815166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1728815166
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1820595361
Short name T1306
Test name
Test status
Simulation time 1352418386 ps
CPU time 5.14 seconds
Started Mar 10 01:50:55 PM PDT 24
Finished Mar 10 01:51:00 PM PDT 24
Peak memory 233020 kb
Host smart-4605cbc4-bdbd-420a-bc4c-71f7085d2149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820595361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1820595361
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2630378356
Short name T320
Test name
Test status
Simulation time 69714262 ps
CPU time 0.78 seconds
Started Mar 10 01:50:51 PM PDT 24
Finished Mar 10 01:50:52 PM PDT 24
Peak memory 205852 kb
Host smart-b12b82d9-f7e1-4f8e-9804-bac42c97845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630378356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2630378356
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3748899650
Short name T1899
Test name
Test status
Simulation time 37703383 ps
CPU time 0.79 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:47:39 PM PDT 24
Peak memory 205544 kb
Host smart-39d2cbcc-02fb-4d0e-b6db-6cf237f17f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748899650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3748899650
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1147277609
Short name T1605
Test name
Test status
Simulation time 1571002370 ps
CPU time 25.76 seconds
Started Mar 10 01:50:56 PM PDT 24
Finished Mar 10 01:51:22 PM PDT 24
Peak memory 238316 kb
Host smart-6d78a4ca-e966-4aff-9db9-8414fc2e4d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147277609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1147277609
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1534025365
Short name T793
Test name
Test status
Simulation time 9036185218 ps
CPU time 41.65 seconds
Started Mar 10 02:47:47 PM PDT 24
Finished Mar 10 02:48:29 PM PDT 24
Peak memory 255504 kb
Host smart-8bd5ddfe-d76e-4fed-a5e0-e53f91e4db5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534025365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1534025365
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3652412341
Short name T870
Test name
Test status
Simulation time 14013955197 ps
CPU time 46.29 seconds
Started Mar 10 02:47:46 PM PDT 24
Finished Mar 10 02:48:32 PM PDT 24
Peak memory 221676 kb
Host smart-e3d4785f-56e0-4c04-b768-9250fb868f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652412341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3652412341
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4288696690
Short name T1309
Test name
Test status
Simulation time 44144013294 ps
CPU time 311.89 seconds
Started Mar 10 02:47:46 PM PDT 24
Finished Mar 10 02:52:58 PM PDT 24
Peak memory 254012 kb
Host smart-21365988-1ea7-43d2-9230-776a1a0da7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288696690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4288696690
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2082967896
Short name T1164
Test name
Test status
Simulation time 1730741886 ps
CPU time 15.1 seconds
Started Mar 10 01:50:56 PM PDT 24
Finished Mar 10 01:51:11 PM PDT 24
Peak memory 231988 kb
Host smart-3751cf3c-24a9-4c0a-98ca-37084f53fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082967896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2082967896
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2891239
Short name T902
Test name
Test status
Simulation time 1639860694 ps
CPU time 18.29 seconds
Started Mar 10 02:47:46 PM PDT 24
Finished Mar 10 02:48:04 PM PDT 24
Peak memory 221516 kb
Host smart-12b7d097-744a-459e-897e-281f5f0bf037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2891239
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1771464496
Short name T584
Test name
Test status
Simulation time 1897705781 ps
CPU time 4.38 seconds
Started Mar 10 02:47:40 PM PDT 24
Finished Mar 10 02:47:44 PM PDT 24
Peak memory 218232 kb
Host smart-80e80eb1-7184-49be-88b9-a3eebd6f0d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771464496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1771464496
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4223613785
Short name T1324
Test name
Test status
Simulation time 4263583338 ps
CPU time 5 seconds
Started Mar 10 01:50:50 PM PDT 24
Finished Mar 10 01:50:55 PM PDT 24
Peak memory 237308 kb
Host smart-c7d4acc9-9156-4e0b-b588-464e244a0828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223613785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4223613785
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2752950
Short name T1025
Test name
Test status
Simulation time 710090343 ps
CPU time 3.56 seconds
Started Mar 10 01:50:53 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 223908 kb
Host smart-733c20d9-0d5a-4c7b-b3fa-e6e916e43ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2752950
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3514221665
Short name T533
Test name
Test status
Simulation time 33493719959 ps
CPU time 33 seconds
Started Mar 10 02:47:43 PM PDT 24
Finished Mar 10 02:48:17 PM PDT 24
Peak memory 248168 kb
Host smart-415c46b4-ea16-45a0-a623-58ebecb61834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514221665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3514221665
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1970382310
Short name T933
Test name
Test status
Simulation time 58301196 ps
CPU time 2.62 seconds
Started Mar 10 01:50:49 PM PDT 24
Finished Mar 10 01:50:52 PM PDT 24
Peak memory 232680 kb
Host smart-08b114f4-4f51-46f0-b7cb-7789c343e8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970382310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1970382310
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1562901678
Short name T1017
Test name
Test status
Simulation time 21970573882 ps
CPU time 14.9 seconds
Started Mar 10 02:47:41 PM PDT 24
Finished Mar 10 02:47:56 PM PDT 24
Peak memory 217512 kb
Host smart-0092a750-d514-40e4-a03f-7b9c901b7104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562901678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1562901678
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.243777868
Short name T708
Test name
Test status
Simulation time 287833610 ps
CPU time 3.92 seconds
Started Mar 10 01:50:49 PM PDT 24
Finished Mar 10 01:50:53 PM PDT 24
Peak memory 232300 kb
Host smart-db316266-3a5a-4660-a4ea-a58cecb00869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243777868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.243777868
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4080381694
Short name T452
Test name
Test status
Simulation time 213139303 ps
CPU time 3.44 seconds
Started Mar 10 02:47:47 PM PDT 24
Finished Mar 10 02:47:50 PM PDT 24
Peak memory 219212 kb
Host smart-55e8bb8e-c07e-4690-b37d-cb281b968f1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4080381694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4080381694
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.475703154
Short name T1854
Test name
Test status
Simulation time 128427542 ps
CPU time 3.36 seconds
Started Mar 10 01:50:54 PM PDT 24
Finished Mar 10 01:50:58 PM PDT 24
Peak memory 217744 kb
Host smart-00f997a5-6de0-4e80-8a66-a8016a81425d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=475703154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.475703154
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1669390485
Short name T1725
Test name
Test status
Simulation time 140650995 ps
CPU time 1.01 seconds
Started Mar 10 01:50:54 PM PDT 24
Finished Mar 10 01:50:55 PM PDT 24
Peak memory 205936 kb
Host smart-dbd856f1-6778-4eff-a924-b95c47a15ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669390485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1669390485
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2331897011
Short name T1194
Test name
Test status
Simulation time 67803369 ps
CPU time 1.29 seconds
Started Mar 10 02:47:49 PM PDT 24
Finished Mar 10 02:47:50 PM PDT 24
Peak memory 206244 kb
Host smart-adb8d3d8-115e-40dd-9977-68fd014be6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331897011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2331897011
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3661384583
Short name T1010
Test name
Test status
Simulation time 525870446 ps
CPU time 6.84 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:47:46 PM PDT 24
Peak memory 215760 kb
Host smart-b75faccb-f170-43f3-9023-f723dcfd00d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661384583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3661384583
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.72830208
Short name T1886
Test name
Test status
Simulation time 10626435249 ps
CPU time 20.36 seconds
Started Mar 10 01:50:48 PM PDT 24
Finished Mar 10 01:51:08 PM PDT 24
Peak memory 215812 kb
Host smart-ccece832-e5f0-418c-a9ba-9ee6074607c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72830208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.72830208
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1057559159
Short name T425
Test name
Test status
Simulation time 34208887942 ps
CPU time 12.53 seconds
Started Mar 10 01:50:54 PM PDT 24
Finished Mar 10 01:51:06 PM PDT 24
Peak memory 215856 kb
Host smart-68b808dd-8585-407f-8b32-96f400f79c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057559159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1057559159
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1108774800
Short name T1124
Test name
Test status
Simulation time 3312383486 ps
CPU time 8.97 seconds
Started Mar 10 02:47:39 PM PDT 24
Finished Mar 10 02:47:48 PM PDT 24
Peak memory 215776 kb
Host smart-42442c79-7aac-40a0-b03e-6e7bd97f55f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108774800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1108774800
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2900696964
Short name T435
Test name
Test status
Simulation time 18784005 ps
CPU time 0.76 seconds
Started Mar 10 01:50:50 PM PDT 24
Finished Mar 10 01:50:50 PM PDT 24
Peak memory 204876 kb
Host smart-fb6851ac-38f3-4789-9377-ed1c44afa4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900696964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2900696964
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4106205925
Short name T1203
Test name
Test status
Simulation time 292728580 ps
CPU time 2.93 seconds
Started Mar 10 02:47:41 PM PDT 24
Finished Mar 10 02:47:44 PM PDT 24
Peak memory 215720 kb
Host smart-c6753550-1f7e-4871-8f9f-81f584e70b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106205925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4106205925
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1557762278
Short name T1716
Test name
Test status
Simulation time 45137957 ps
CPU time 0.77 seconds
Started Mar 10 01:50:52 PM PDT 24
Finished Mar 10 01:50:53 PM PDT 24
Peak memory 204892 kb
Host smart-b246fecb-bc1a-4ee1-879d-fcd7aa4d022d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557762278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1557762278
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.766466496
Short name T1455
Test name
Test status
Simulation time 40491447 ps
CPU time 0.75 seconds
Started Mar 10 02:47:42 PM PDT 24
Finished Mar 10 02:47:43 PM PDT 24
Peak memory 204884 kb
Host smart-aaa6177d-078d-40fa-9f9f-d80947c2108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766466496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.766466496
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.332757825
Short name T1443
Test name
Test status
Simulation time 30852410951 ps
CPU time 26.83 seconds
Started Mar 10 01:50:56 PM PDT 24
Finished Mar 10 01:51:23 PM PDT 24
Peak memory 236260 kb
Host smart-8c87a033-93b2-475a-97f7-10ffa82586a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332757825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.332757825
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_upload.880865917
Short name T1235
Test name
Test status
Simulation time 2817981201 ps
CPU time 7.65 seconds
Started Mar 10 02:47:45 PM PDT 24
Finished Mar 10 02:47:53 PM PDT 24
Peak memory 232792 kb
Host smart-2032743b-5067-4749-9486-5f980025ecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880865917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.880865917
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3693932846
Short name T369
Test name
Test status
Simulation time 13257406 ps
CPU time 0.72 seconds
Started Mar 10 01:51:00 PM PDT 24
Finished Mar 10 01:51:02 PM PDT 24
Peak memory 204468 kb
Host smart-3af37fe9-b9a6-4815-a49c-910f174e28ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693932846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3693932846
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.73907521
Short name T1511
Test name
Test status
Simulation time 179124678 ps
CPU time 0.7 seconds
Started Mar 10 02:47:50 PM PDT 24
Finished Mar 10 02:47:51 PM PDT 24
Peak memory 204400 kb
Host smart-4c7a69f1-3362-47b6-930a-8b9b3230c05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73907521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.73907521
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2349504921
Short name T893
Test name
Test status
Simulation time 297521746 ps
CPU time 5.71 seconds
Started Mar 10 02:47:48 PM PDT 24
Finished Mar 10 02:47:54 PM PDT 24
Peak memory 232712 kb
Host smart-180765fe-c1e5-491e-92c4-8bbadebd2858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349504921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2349504921
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.763282879
Short name T1533
Test name
Test status
Simulation time 1670325357 ps
CPU time 5.13 seconds
Started Mar 10 01:50:59 PM PDT 24
Finished Mar 10 01:51:05 PM PDT 24
Peak memory 232928 kb
Host smart-eb1c7c6e-fe90-4dae-9232-56ed740f3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763282879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.763282879
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2799672681
Short name T1613
Test name
Test status
Simulation time 35533378 ps
CPU time 0.82 seconds
Started Mar 10 01:50:56 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 205820 kb
Host smart-fbcc0768-c48e-48c0-8756-9b898943b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799672681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2799672681
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.727495119
Short name T866
Test name
Test status
Simulation time 18052729 ps
CPU time 0.77 seconds
Started Mar 10 02:47:43 PM PDT 24
Finished Mar 10 02:47:43 PM PDT 24
Peak memory 204488 kb
Host smart-734f7534-dfb3-4dcc-ac3e-96e44e14ec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727495119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.727495119
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1374014458
Short name T1707
Test name
Test status
Simulation time 117874323599 ps
CPU time 136.86 seconds
Started Mar 10 01:50:59 PM PDT 24
Finished Mar 10 01:53:16 PM PDT 24
Peak memory 254432 kb
Host smart-5d98f3d0-d23b-4362-b34f-c6ad6b62e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374014458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1374014458
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.29905695
Short name T1841
Test name
Test status
Simulation time 38668041509 ps
CPU time 191.16 seconds
Started Mar 10 02:47:45 PM PDT 24
Finished Mar 10 02:50:57 PM PDT 24
Peak memory 265776 kb
Host smart-3b6f0085-5166-4bed-b283-66243ca3d083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29905695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.29905695
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1387929323
Short name T813
Test name
Test status
Simulation time 6185287681 ps
CPU time 36.22 seconds
Started Mar 10 01:51:00 PM PDT 24
Finished Mar 10 01:51:37 PM PDT 24
Peak memory 251936 kb
Host smart-75add13b-35d2-4a07-be5d-6d0cd9eaa7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387929323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1387929323
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3515045237
Short name T1915
Test name
Test status
Simulation time 645933976421 ps
CPU time 738.8 seconds
Started Mar 10 02:47:48 PM PDT 24
Finished Mar 10 03:00:08 PM PDT 24
Peak memory 256356 kb
Host smart-fde90120-e854-4051-b027-27b53bcdc9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515045237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3515045237
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1149572252
Short name T1705
Test name
Test status
Simulation time 40970054142 ps
CPU time 342.69 seconds
Started Mar 10 01:51:00 PM PDT 24
Finished Mar 10 01:56:43 PM PDT 24
Peak memory 255800 kb
Host smart-e3f5edb0-5ae8-4015-ae08-d0b71b55198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149572252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1149572252
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3241039478
Short name T22
Test name
Test status
Simulation time 33847202553 ps
CPU time 263.09 seconds
Started Mar 10 02:47:49 PM PDT 24
Finished Mar 10 02:52:12 PM PDT 24
Peak memory 250824 kb
Host smart-88cbce2d-6955-4e1b-a9b7-f37cd892ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241039478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3241039478
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1466958997
Short name T735
Test name
Test status
Simulation time 1945192659 ps
CPU time 19.28 seconds
Started Mar 10 02:47:48 PM PDT 24
Finished Mar 10 02:48:08 PM PDT 24
Peak memory 237476 kb
Host smart-2bcb403e-b465-4019-afc2-0389bf88e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466958997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1466958997
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.163811124
Short name T1389
Test name
Test status
Simulation time 831336880 ps
CPU time 10.55 seconds
Started Mar 10 01:50:59 PM PDT 24
Finished Mar 10 01:51:09 PM PDT 24
Peak memory 232012 kb
Host smart-260b54ba-8b89-4d3c-815b-0d6995a57e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163811124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.163811124
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1305244263
Short name T1756
Test name
Test status
Simulation time 1350175429 ps
CPU time 6.05 seconds
Started Mar 10 02:47:47 PM PDT 24
Finished Mar 10 02:47:53 PM PDT 24
Peak memory 223848 kb
Host smart-19a73fec-935f-4707-af62-b761eb8784c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305244263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1305244263
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2969392997
Short name T1402
Test name
Test status
Simulation time 1407886460 ps
CPU time 5.53 seconds
Started Mar 10 01:50:58 PM PDT 24
Finished Mar 10 01:51:04 PM PDT 24
Peak memory 232776 kb
Host smart-55fe99bc-8322-4326-97d7-42d1188e451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969392997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2969392997
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1518572902
Short name T1355
Test name
Test status
Simulation time 577590355 ps
CPU time 10.26 seconds
Started Mar 10 02:47:45 PM PDT 24
Finished Mar 10 02:47:56 PM PDT 24
Peak memory 240252 kb
Host smart-091edbdd-5a15-4511-8275-7b6f72ae7456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518572902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1518572902
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4119398300
Short name T227
Test name
Test status
Simulation time 423058977 ps
CPU time 2.42 seconds
Started Mar 10 01:51:01 PM PDT 24
Finished Mar 10 01:51:05 PM PDT 24
Peak memory 232064 kb
Host smart-3ebc43ed-83fe-40c9-8d72-cef882edafe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119398300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4119398300
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1395994144
Short name T185
Test name
Test status
Simulation time 1127880004 ps
CPU time 5.04 seconds
Started Mar 10 01:51:01 PM PDT 24
Finished Mar 10 01:51:06 PM PDT 24
Peak memory 225548 kb
Host smart-129831ee-4f6e-42ee-af58-dc17ab49d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395994144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1395994144
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2909921649
Short name T491
Test name
Test status
Simulation time 768864186 ps
CPU time 5.73 seconds
Started Mar 10 02:47:47 PM PDT 24
Finished Mar 10 02:47:54 PM PDT 24
Peak memory 218212 kb
Host smart-a664c994-3653-4e45-be7f-a9762ca081f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909921649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2909921649
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1594078733
Short name T8
Test name
Test status
Simulation time 753440161 ps
CPU time 6.78 seconds
Started Mar 10 02:47:46 PM PDT 24
Finished Mar 10 02:47:53 PM PDT 24
Peak memory 229412 kb
Host smart-4aa5aa6d-dfd1-4c80-ad13-02ea864203e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594078733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1594078733
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.18476507
Short name T1151
Test name
Test status
Simulation time 285004613 ps
CPU time 3.15 seconds
Started Mar 10 01:50:54 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 215780 kb
Host smart-c54fed0b-5012-443d-9712-4776dab5b72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18476507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.18476507
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.122989948
Short name T1614
Test name
Test status
Simulation time 9738150867 ps
CPU time 5.16 seconds
Started Mar 10 01:51:00 PM PDT 24
Finished Mar 10 01:51:06 PM PDT 24
Peak memory 221580 kb
Host smart-4c14e819-1c28-4ea7-88fe-259879a570c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=122989948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.122989948
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3766129065
Short name T1632
Test name
Test status
Simulation time 602822115 ps
CPU time 4.29 seconds
Started Mar 10 02:47:48 PM PDT 24
Finished Mar 10 02:47:52 PM PDT 24
Peak memory 218916 kb
Host smart-9631f68a-acb9-4827-a3d2-7d585d6fc73d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3766129065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3766129065
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4189345643
Short name T59
Test name
Test status
Simulation time 7869665158 ps
CPU time 88.27 seconds
Started Mar 10 02:48:02 PM PDT 24
Finished Mar 10 02:49:30 PM PDT 24
Peak memory 256520 kb
Host smart-30b22d6c-1372-40e0-a991-10ebf50b500a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189345643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4189345643
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2005124083
Short name T546
Test name
Test status
Simulation time 2066766265 ps
CPU time 3.63 seconds
Started Mar 10 02:47:48 PM PDT 24
Finished Mar 10 02:47:52 PM PDT 24
Peak memory 215684 kb
Host smart-700c36d9-6881-436d-b122-4b91917f0ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005124083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2005124083
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.516749617
Short name T1864
Test name
Test status
Simulation time 13138734801 ps
CPU time 43.23 seconds
Started Mar 10 01:50:57 PM PDT 24
Finished Mar 10 01:51:40 PM PDT 24
Peak memory 215776 kb
Host smart-359d8781-317e-4256-b33c-9b2dc4c86c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516749617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.516749617
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2428354087
Short name T1230
Test name
Test status
Simulation time 689263043 ps
CPU time 1.97 seconds
Started Mar 10 01:50:56 PM PDT 24
Finished Mar 10 01:50:59 PM PDT 24
Peak memory 206300 kb
Host smart-dbfbc892-47f6-41cd-bcb7-a0b510b3f4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428354087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2428354087
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2432549766
Short name T1573
Test name
Test status
Simulation time 4608150282 ps
CPU time 6.4 seconds
Started Mar 10 02:47:43 PM PDT 24
Finished Mar 10 02:47:50 PM PDT 24
Peak memory 215792 kb
Host smart-72538efc-32be-465f-abe9-d89c39b2fd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432549766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2432549766
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3715030238
Short name T1216
Test name
Test status
Simulation time 16758991 ps
CPU time 0.88 seconds
Started Mar 10 02:47:45 PM PDT 24
Finished Mar 10 02:47:46 PM PDT 24
Peak memory 205568 kb
Host smart-c92d1048-2f9f-4eea-8f36-94976b52797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715030238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3715030238
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.388483463
Short name T1764
Test name
Test status
Simulation time 640287838 ps
CPU time 6.68 seconds
Started Mar 10 01:50:55 PM PDT 24
Finished Mar 10 01:51:02 PM PDT 24
Peak memory 215720 kb
Host smart-201b2a6e-fd47-4e65-8970-341e1f34f1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388483463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.388483463
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1097394406
Short name T1671
Test name
Test status
Simulation time 99944189 ps
CPU time 0.98 seconds
Started Mar 10 01:50:53 PM PDT 24
Finished Mar 10 01:50:55 PM PDT 24
Peak memory 205820 kb
Host smart-513bb6b1-aafd-47be-8154-f3336403975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097394406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1097394406
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3491856671
Short name T1293
Test name
Test status
Simulation time 286778609 ps
CPU time 0.8 seconds
Started Mar 10 02:47:47 PM PDT 24
Finished Mar 10 02:47:48 PM PDT 24
Peak memory 204880 kb
Host smart-13c0ffd4-aa5a-446a-a92d-91741d7f5879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491856671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3491856671
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1475741245
Short name T1814
Test name
Test status
Simulation time 7733122272 ps
CPU time 23.54 seconds
Started Mar 10 02:47:45 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 233404 kb
Host smart-0fd454e5-8308-47b2-968f-de18c4233a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475741245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1475741245
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_upload.4242881570
Short name T1777
Test name
Test status
Simulation time 912882318 ps
CPU time 7.52 seconds
Started Mar 10 01:51:00 PM PDT 24
Finished Mar 10 01:51:08 PM PDT 24
Peak memory 218460 kb
Host smart-06a362be-35b7-4c7b-9c9e-aec489f50d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242881570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4242881570
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1128413976
Short name T1493
Test name
Test status
Simulation time 31348904 ps
CPU time 0.7 seconds
Started Mar 10 02:47:51 PM PDT 24
Finished Mar 10 02:47:52 PM PDT 24
Peak memory 204780 kb
Host smart-0e17626c-ec59-49f9-8908-6ea23b6a5747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128413976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1128413976
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2206279217
Short name T431
Test name
Test status
Simulation time 14435228 ps
CPU time 0.72 seconds
Started Mar 10 01:51:04 PM PDT 24
Finished Mar 10 01:51:06 PM PDT 24
Peak memory 204424 kb
Host smart-b08190ce-2eff-4e6c-b36d-cb5968aaea6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206279217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2206279217
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1381541371
Short name T1220
Test name
Test status
Simulation time 599074912 ps
CPU time 4.08 seconds
Started Mar 10 02:47:48 PM PDT 24
Finished Mar 10 02:47:53 PM PDT 24
Peak memory 233116 kb
Host smart-43f9ddab-5090-41c0-9ec7-5fc2a9b56559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381541371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1381541371
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.273564496
Short name T1870
Test name
Test status
Simulation time 404534619 ps
CPU time 4.28 seconds
Started Mar 10 01:51:01 PM PDT 24
Finished Mar 10 01:51:07 PM PDT 24
Peak memory 232728 kb
Host smart-e1d3a15d-606a-4556-9cfb-d83d8ed9fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273564496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.273564496
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3531206936
Short name T1065
Test name
Test status
Simulation time 19929151 ps
CPU time 0.78 seconds
Started Mar 10 02:48:01 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 204484 kb
Host smart-38c3687a-a013-46a6-b413-5613a7e93957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531206936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3531206936
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3891439195
Short name T1775
Test name
Test status
Simulation time 18915097 ps
CPU time 0.78 seconds
Started Mar 10 01:51:01 PM PDT 24
Finished Mar 10 01:51:03 PM PDT 24
Peak memory 204480 kb
Host smart-879ccf1a-8812-4c70-acf1-436f543da6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891439195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3891439195
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.696721236
Short name T258
Test name
Test status
Simulation time 37992808895 ps
CPU time 226.94 seconds
Started Mar 10 01:51:04 PM PDT 24
Finished Mar 10 01:54:52 PM PDT 24
Peak memory 269188 kb
Host smart-226c75cd-fe91-4427-ba01-69a7a99c8ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696721236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.696721236
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2704066860
Short name T410
Test name
Test status
Simulation time 9508096248 ps
CPU time 77.64 seconds
Started Mar 10 01:51:04 PM PDT 24
Finished Mar 10 01:52:23 PM PDT 24
Peak memory 254376 kb
Host smart-2f917877-a313-4a45-b8cf-92ed8009007a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704066860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2704066860
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3378922128
Short name T1701
Test name
Test status
Simulation time 46204938211 ps
CPU time 68.55 seconds
Started Mar 10 02:47:50 PM PDT 24
Finished Mar 10 02:48:59 PM PDT 24
Peak memory 255684 kb
Host smart-176e0ddc-0ca2-4e2b-8623-d21d0db0f43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378922128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3378922128
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.162442222
Short name T1044
Test name
Test status
Simulation time 5753202323 ps
CPU time 113.73 seconds
Started Mar 10 01:51:06 PM PDT 24
Finished Mar 10 01:53:00 PM PDT 24
Peak memory 264780 kb
Host smart-5ed7cf6d-3e91-4c97-8dc3-b7c9ab367611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162442222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.162442222
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2780343883
Short name T839
Test name
Test status
Simulation time 5538025694 ps
CPU time 29.58 seconds
Started Mar 10 02:47:50 PM PDT 24
Finished Mar 10 02:48:20 PM PDT 24
Peak memory 240460 kb
Host smart-4fd29e91-9dcf-49f6-ba29-79d8b092367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780343883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2780343883
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3992621847
Short name T1908
Test name
Test status
Simulation time 12831204120 ps
CPU time 12.28 seconds
Started Mar 10 01:51:05 PM PDT 24
Finished Mar 10 01:51:18 PM PDT 24
Peak memory 236160 kb
Host smart-b0228521-dd04-47ef-b8b1-206cfe25acce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992621847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3992621847
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.711613477
Short name T1647
Test name
Test status
Simulation time 9497660203 ps
CPU time 15.52 seconds
Started Mar 10 02:47:52 PM PDT 24
Finished Mar 10 02:48:08 PM PDT 24
Peak memory 231476 kb
Host smart-686ce6ba-69c4-410a-b9d2-d43f4810540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711613477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.711613477
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1366971978
Short name T1638
Test name
Test status
Simulation time 7399490684 ps
CPU time 7.92 seconds
Started Mar 10 01:51:01 PM PDT 24
Finished Mar 10 01:51:10 PM PDT 24
Peak memory 223852 kb
Host smart-541d7f35-a1cd-41de-b7f0-90313be1fae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366971978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1366971978
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4110744238
Short name T1492
Test name
Test status
Simulation time 447481251 ps
CPU time 5.38 seconds
Started Mar 10 02:47:50 PM PDT 24
Finished Mar 10 02:47:55 PM PDT 24
Peak memory 217056 kb
Host smart-b89ed298-adb7-4f85-83fd-0ff406fc1b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110744238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4110744238
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2478891118
Short name T747
Test name
Test status
Simulation time 15034763843 ps
CPU time 17.99 seconds
Started Mar 10 02:47:50 PM PDT 24
Finished Mar 10 02:48:08 PM PDT 24
Peak memory 232160 kb
Host smart-78ccddb9-8cb2-48bf-9216-8810cb43d3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478891118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2478891118
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2898923259
Short name T1555
Test name
Test status
Simulation time 2588408351 ps
CPU time 15.67 seconds
Started Mar 10 01:51:00 PM PDT 24
Finished Mar 10 01:51:17 PM PDT 24
Peak memory 232100 kb
Host smart-46da784b-b1d2-470c-9f78-fa3347f5ef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898923259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2898923259
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1178496179
Short name T1883
Test name
Test status
Simulation time 12446384454 ps
CPU time 18.84 seconds
Started Mar 10 02:47:52 PM PDT 24
Finished Mar 10 02:48:11 PM PDT 24
Peak memory 235264 kb
Host smart-323578cc-227e-42da-a40c-e1d9db9c0816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178496179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1178496179
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4109485600
Short name T380
Test name
Test status
Simulation time 2293710142 ps
CPU time 6.16 seconds
Started Mar 10 01:50:58 PM PDT 24
Finished Mar 10 01:51:05 PM PDT 24
Peak memory 233148 kb
Host smart-4d1a0028-c39a-4b51-bec9-a4850a2c89e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109485600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4109485600
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2938389614
Short name T1693
Test name
Test status
Simulation time 599231828 ps
CPU time 4.13 seconds
Started Mar 10 02:47:58 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 232868 kb
Host smart-25308416-04f3-47d7-b5f6-1fe9fdc67a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938389614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2938389614
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.892400358
Short name T1628
Test name
Test status
Simulation time 6097175809 ps
CPU time 12.99 seconds
Started Mar 10 01:51:02 PM PDT 24
Finished Mar 10 01:51:16 PM PDT 24
Peak memory 232968 kb
Host smart-93ed4396-eeac-458d-83c8-ba7fc785850f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892400358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.892400358
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1131799500
Short name T143
Test name
Test status
Simulation time 117201644 ps
CPU time 3.99 seconds
Started Mar 10 01:51:06 PM PDT 24
Finished Mar 10 01:51:10 PM PDT 24
Peak memory 221440 kb
Host smart-dfbd0bc3-be34-460c-8880-4a12e035c178
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1131799500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1131799500
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4077541531
Short name T1067
Test name
Test status
Simulation time 1194616628 ps
CPU time 3.66 seconds
Started Mar 10 02:47:52 PM PDT 24
Finished Mar 10 02:47:55 PM PDT 24
Peak memory 219036 kb
Host smart-75977b9e-5ae9-434e-b205-714fe4e4ef41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4077541531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4077541531
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4006917305
Short name T164
Test name
Test status
Simulation time 34001454113 ps
CPU time 66.32 seconds
Started Mar 10 01:51:04 PM PDT 24
Finished Mar 10 01:52:12 PM PDT 24
Peak memory 265040 kb
Host smart-a07ccce8-1bda-42e2-9f41-c619dbd3818c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006917305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4006917305
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4087626161
Short name T1791
Test name
Test status
Simulation time 232013493015 ps
CPU time 102.75 seconds
Started Mar 10 02:48:09 PM PDT 24
Finished Mar 10 02:49:52 PM PDT 24
Peak memory 242636 kb
Host smart-4543f5cc-89a9-440d-9c2b-b7c0463047d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087626161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4087626161
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2932390733
Short name T1753
Test name
Test status
Simulation time 410861241 ps
CPU time 5.18 seconds
Started Mar 10 02:48:01 PM PDT 24
Finished Mar 10 02:48:06 PM PDT 24
Peak memory 215732 kb
Host smart-18ddc523-6e66-41c7-81db-3b9f0297b97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932390733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2932390733
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4079880504
Short name T433
Test name
Test status
Simulation time 23659377640 ps
CPU time 33.57 seconds
Started Mar 10 01:50:59 PM PDT 24
Finished Mar 10 01:51:33 PM PDT 24
Peak memory 215872 kb
Host smart-8f4f337a-4c21-4313-94e7-d67a6125f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079880504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4079880504
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1090718629
Short name T1102
Test name
Test status
Simulation time 6893705767 ps
CPU time 8.69 seconds
Started Mar 10 01:51:01 PM PDT 24
Finished Mar 10 01:51:12 PM PDT 24
Peak memory 215808 kb
Host smart-227a181c-077f-40e2-882c-63b9be6a4bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090718629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1090718629
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2111228638
Short name T301
Test name
Test status
Simulation time 2858489576 ps
CPU time 6.67 seconds
Started Mar 10 02:47:51 PM PDT 24
Finished Mar 10 02:47:58 PM PDT 24
Peak memory 216068 kb
Host smart-4ae02dbf-b629-4b9d-8f24-94b6bf9ee3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111228638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2111228638
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2480944900
Short name T1408
Test name
Test status
Simulation time 1229399470 ps
CPU time 2.18 seconds
Started Mar 10 02:48:01 PM PDT 24
Finished Mar 10 02:48:03 PM PDT 24
Peak memory 215948 kb
Host smart-34f9a282-58a6-4336-97d2-a326ae763b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480944900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2480944900
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2504281660
Short name T1574
Test name
Test status
Simulation time 1418264422 ps
CPU time 13.25 seconds
Started Mar 10 01:51:04 PM PDT 24
Finished Mar 10 01:51:18 PM PDT 24
Peak memory 215732 kb
Host smart-99f78f04-5680-4de0-9c91-0ea325e9a400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504281660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2504281660
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3106923651
Short name T1172
Test name
Test status
Simulation time 261531655 ps
CPU time 0.94 seconds
Started Mar 10 02:48:02 PM PDT 24
Finished Mar 10 02:48:03 PM PDT 24
Peak memory 204880 kb
Host smart-d6242097-47e8-445a-91da-d8bcc44f36e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106923651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3106923651
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3567686631
Short name T1289
Test name
Test status
Simulation time 481570283 ps
CPU time 0.99 seconds
Started Mar 10 01:51:01 PM PDT 24
Finished Mar 10 01:51:04 PM PDT 24
Peak memory 205916 kb
Host smart-e13c504a-cb93-45b4-aaa0-bc052eb2df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567686631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3567686631
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1868945400
Short name T1161
Test name
Test status
Simulation time 5976841733 ps
CPU time 22.97 seconds
Started Mar 10 02:47:54 PM PDT 24
Finished Mar 10 02:48:17 PM PDT 24
Peak memory 248520 kb
Host smart-fe3423f9-bb35-47b9-9ab3-fb860e6e3cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868945400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1868945400
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_upload.2983422321
Short name T245
Test name
Test status
Simulation time 4177948610 ps
CPU time 17.44 seconds
Started Mar 10 01:51:01 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 233944 kb
Host smart-137d3947-36c7-47fd-95db-b6920a24e7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983422321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2983422321
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.225636234
Short name T1905
Test name
Test status
Simulation time 76649207 ps
CPU time 0.69 seconds
Started Mar 10 01:51:10 PM PDT 24
Finished Mar 10 01:51:11 PM PDT 24
Peak memory 204724 kb
Host smart-713e164d-567c-4e5d-a1bd-e6b52e2fb968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225636234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.225636234
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3673453172
Short name T311
Test name
Test status
Simulation time 44748955 ps
CPU time 0.69 seconds
Started Mar 10 02:47:54 PM PDT 24
Finished Mar 10 02:47:55 PM PDT 24
Peak memory 204456 kb
Host smart-f7cf673b-a390-4260-9c12-d43c7aaa76cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673453172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3673453172
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3321173800
Short name T36
Test name
Test status
Simulation time 620671931 ps
CPU time 4.08 seconds
Started Mar 10 01:51:10 PM PDT 24
Finished Mar 10 01:51:15 PM PDT 24
Peak memory 223836 kb
Host smart-9e0ab51d-de33-4985-b3bd-eec9ff461ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321173800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3321173800
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.802589934
Short name T1374
Test name
Test status
Simulation time 3742196455 ps
CPU time 4.6 seconds
Started Mar 10 02:47:57 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 223888 kb
Host smart-50c2eb7e-2e5f-4f1a-b6d3-0375a52757e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802589934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.802589934
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3736332568
Short name T1413
Test name
Test status
Simulation time 15347390 ps
CPU time 0.74 seconds
Started Mar 10 02:48:01 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 205852 kb
Host smart-a0d27503-8d8e-4b6f-80d2-712925a1e47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736332568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3736332568
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4272512670
Short name T1703
Test name
Test status
Simulation time 22624515 ps
CPU time 0.81 seconds
Started Mar 10 01:51:06 PM PDT 24
Finished Mar 10 01:51:07 PM PDT 24
Peak memory 205452 kb
Host smart-27bb96ed-b4b2-45aa-8211-ef42f074987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272512670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4272512670
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.834529343
Short name T569
Test name
Test status
Simulation time 49143497098 ps
CPU time 218.03 seconds
Started Mar 10 02:47:57 PM PDT 24
Finished Mar 10 02:51:35 PM PDT 24
Peak memory 264312 kb
Host smart-e2b29ba7-996c-4d3b-a5ff-316643302030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834529343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.834529343
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3111327412
Short name T183
Test name
Test status
Simulation time 91096385538 ps
CPU time 208.39 seconds
Started Mar 10 02:47:56 PM PDT 24
Finished Mar 10 02:51:24 PM PDT 24
Peak memory 252824 kb
Host smart-abd21506-5a8c-4a49-be35-75487e34afa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111327412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3111327412
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3468446494
Short name T721
Test name
Test status
Simulation time 31435437960 ps
CPU time 98.65 seconds
Started Mar 10 01:51:10 PM PDT 24
Finished Mar 10 01:52:49 PM PDT 24
Peak memory 256676 kb
Host smart-59602462-7468-4432-a35f-8e22b47e7765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468446494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3468446494
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.178038971
Short name T269
Test name
Test status
Simulation time 32401907277 ps
CPU time 45.44 seconds
Started Mar 10 02:47:56 PM PDT 24
Finished Mar 10 02:48:42 PM PDT 24
Peak memory 250268 kb
Host smart-b9c669dc-3c6f-4d98-86a2-0e1a888dc4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178038971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.178038971
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.327944618
Short name T426
Test name
Test status
Simulation time 3468701685 ps
CPU time 60.65 seconds
Started Mar 10 01:51:12 PM PDT 24
Finished Mar 10 01:52:12 PM PDT 24
Peak memory 248692 kb
Host smart-717cf942-7a81-4caa-a375-3c6261d8540f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327944618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.327944618
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2837493511
Short name T768
Test name
Test status
Simulation time 35734892124 ps
CPU time 50.73 seconds
Started Mar 10 02:47:53 PM PDT 24
Finished Mar 10 02:48:44 PM PDT 24
Peak memory 240288 kb
Host smart-2525ce0b-60eb-4cb7-97ba-e2ec01757015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837493511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2837493511
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4267347434
Short name T962
Test name
Test status
Simulation time 24338748739 ps
CPU time 38.58 seconds
Started Mar 10 01:51:10 PM PDT 24
Finished Mar 10 01:51:49 PM PDT 24
Peak memory 247340 kb
Host smart-7a9aca5e-27f6-4fcd-a965-3ce17835a006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267347434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4267347434
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2949192210
Short name T1925
Test name
Test status
Simulation time 454682405 ps
CPU time 4.01 seconds
Started Mar 10 02:47:50 PM PDT 24
Finished Mar 10 02:47:54 PM PDT 24
Peak memory 217052 kb
Host smart-5a3ff63a-02e1-4cc2-a3b1-a69b85884e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949192210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2949192210
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intercept.33812272
Short name T642
Test name
Test status
Simulation time 222309691 ps
CPU time 2.59 seconds
Started Mar 10 01:51:09 PM PDT 24
Finished Mar 10 01:51:12 PM PDT 24
Peak memory 216124 kb
Host smart-1aed712a-5879-45a9-a8cf-d59c5c84e4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33812272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.33812272
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2268586426
Short name T1895
Test name
Test status
Simulation time 58775806177 ps
CPU time 41.58 seconds
Started Mar 10 01:51:09 PM PDT 24
Finished Mar 10 01:51:52 PM PDT 24
Peak memory 248536 kb
Host smart-18996eb8-6872-4d23-9658-03a8777919fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268586426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2268586426
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.626231551
Short name T671
Test name
Test status
Simulation time 1453895079 ps
CPU time 10.42 seconds
Started Mar 10 02:47:54 PM PDT 24
Finished Mar 10 02:48:05 PM PDT 24
Peak memory 232456 kb
Host smart-487d1404-f9d9-4ab2-9140-2ad2a5676cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626231551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.626231551
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2353514016
Short name T972
Test name
Test status
Simulation time 25363660882 ps
CPU time 19.72 seconds
Started Mar 10 02:47:51 PM PDT 24
Finished Mar 10 02:48:11 PM PDT 24
Peak memory 233272 kb
Host smart-4f6d1262-c5da-403b-9010-84deda512253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353514016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2353514016
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2419853358
Short name T916
Test name
Test status
Simulation time 2857186510 ps
CPU time 9.29 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:24 PM PDT 24
Peak memory 223888 kb
Host smart-1db402a2-f51f-4300-b3e1-c1e70058ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419853358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2419853358
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2707210223
Short name T354
Test name
Test status
Simulation time 3905059089 ps
CPU time 16.49 seconds
Started Mar 10 01:51:12 PM PDT 24
Finished Mar 10 01:51:29 PM PDT 24
Peak memory 246076 kb
Host smart-99a603a2-671b-4446-b8b4-b18db6f66355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707210223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2707210223
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.83666633
Short name T1316
Test name
Test status
Simulation time 11928601924 ps
CPU time 9.81 seconds
Started Mar 10 02:47:51 PM PDT 24
Finished Mar 10 02:48:01 PM PDT 24
Peak memory 233348 kb
Host smart-872fd60e-eb2a-4506-9f71-9b30a93a4752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83666633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.83666633
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1424702398
Short name T1075
Test name
Test status
Simulation time 182129939 ps
CPU time 3.91 seconds
Started Mar 10 02:47:54 PM PDT 24
Finished Mar 10 02:47:58 PM PDT 24
Peak memory 220916 kb
Host smart-1d4c98eb-ae94-4725-9785-19f856a536b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1424702398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1424702398
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2033272330
Short name T41
Test name
Test status
Simulation time 1474116900 ps
CPU time 4.26 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:19 PM PDT 24
Peak memory 219432 kb
Host smart-49cc90f3-be67-4f4f-b918-2a031bb7b7e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2033272330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2033272330
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2607250351
Short name T249
Test name
Test status
Simulation time 22890963923 ps
CPU time 78.94 seconds
Started Mar 10 01:51:12 PM PDT 24
Finished Mar 10 01:52:31 PM PDT 24
Peak memory 255920 kb
Host smart-220274bc-fb4a-48f2-b89f-d823ba84c15d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607250351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2607250351
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4047007817
Short name T1697
Test name
Test status
Simulation time 93370451 ps
CPU time 1.07 seconds
Started Mar 10 02:47:55 PM PDT 24
Finished Mar 10 02:47:57 PM PDT 24
Peak memory 205960 kb
Host smart-e077445b-c18e-4616-8aba-1acb72540f4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047007817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4047007817
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2113776174
Short name T1595
Test name
Test status
Simulation time 6554784038 ps
CPU time 14.42 seconds
Started Mar 10 02:48:01 PM PDT 24
Finished Mar 10 02:48:16 PM PDT 24
Peak memory 215808 kb
Host smart-e5a73d41-e50d-4a46-9cd7-cdd14ec9fb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113776174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2113776174
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.459993552
Short name T1559
Test name
Test status
Simulation time 18110097010 ps
CPU time 41.37 seconds
Started Mar 10 01:51:04 PM PDT 24
Finished Mar 10 01:51:46 PM PDT 24
Peak memory 215816 kb
Host smart-6d853f8f-4b94-4112-93c9-5d7bf39572f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459993552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.459993552
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3043672008
Short name T1186
Test name
Test status
Simulation time 4230045425 ps
CPU time 12.27 seconds
Started Mar 10 01:51:07 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 215820 kb
Host smart-749a3f38-2f20-46bf-835a-9e1fc26639fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043672008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3043672008
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4010686341
Short name T530
Test name
Test status
Simulation time 5612559611 ps
CPU time 17.23 seconds
Started Mar 10 02:47:51 PM PDT 24
Finished Mar 10 02:48:08 PM PDT 24
Peak memory 216364 kb
Host smart-f10735a2-57b6-485e-87d8-17dc73ed48e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010686341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4010686341
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3319184888
Short name T1231
Test name
Test status
Simulation time 59688109 ps
CPU time 1.29 seconds
Started Mar 10 01:51:12 PM PDT 24
Finished Mar 10 01:51:14 PM PDT 24
Peak memory 207348 kb
Host smart-face5875-498e-40ce-b467-860bfdefeb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319184888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3319184888
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4216643690
Short name T1645
Test name
Test status
Simulation time 287297585 ps
CPU time 1.3 seconds
Started Mar 10 02:47:50 PM PDT 24
Finished Mar 10 02:47:52 PM PDT 24
Peak memory 207544 kb
Host smart-fef9f54c-cb91-4ebb-ba15-4aa2b5f0f5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216643690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4216643690
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1283700386
Short name T684
Test name
Test status
Simulation time 382413610 ps
CPU time 1.04 seconds
Started Mar 10 02:47:51 PM PDT 24
Finished Mar 10 02:47:52 PM PDT 24
Peak memory 205340 kb
Host smart-f28d7a8a-13cf-4020-bf60-5d5323940cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283700386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1283700386
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2745693059
Short name T1927
Test name
Test status
Simulation time 226122810 ps
CPU time 0.93 seconds
Started Mar 10 01:51:05 PM PDT 24
Finished Mar 10 01:51:07 PM PDT 24
Peak memory 204904 kb
Host smart-8a373c44-4e20-4b15-a990-ce761132c730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745693059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2745693059
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3728462996
Short name T1141
Test name
Test status
Simulation time 620112581 ps
CPU time 6.85 seconds
Started Mar 10 02:47:54 PM PDT 24
Finished Mar 10 02:48:01 PM PDT 24
Peak memory 228688 kb
Host smart-a6941192-2747-4a3d-af51-9a5510de9cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728462996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3728462996
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_upload.4122514184
Short name T1478
Test name
Test status
Simulation time 6893410804 ps
CPU time 7.46 seconds
Started Mar 10 01:51:12 PM PDT 24
Finished Mar 10 01:51:19 PM PDT 24
Peak memory 218864 kb
Host smart-2dc4a68e-477a-4d20-b620-c74baf09e9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122514184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4122514184
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2285905874
Short name T1212
Test name
Test status
Simulation time 39352253 ps
CPU time 0.7 seconds
Started Mar 10 02:48:00 PM PDT 24
Finished Mar 10 02:48:01 PM PDT 24
Peak memory 203848 kb
Host smart-c987dd71-85d1-4feb-b0e3-f35f5bbeed61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285905874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2285905874
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3888919783
Short name T327
Test name
Test status
Simulation time 24277315 ps
CPU time 0.81 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:17 PM PDT 24
Peak memory 204480 kb
Host smart-471d941b-356d-45bd-9c04-38767b1522bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888919783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3888919783
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1134028096
Short name T1240
Test name
Test status
Simulation time 312953615 ps
CPU time 2.05 seconds
Started Mar 10 02:47:59 PM PDT 24
Finished Mar 10 02:48:01 PM PDT 24
Peak memory 216316 kb
Host smart-a628274d-7cf1-4d3a-b303-a04e126b4b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134028096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1134028096
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3650112986
Short name T455
Test name
Test status
Simulation time 765396582 ps
CPU time 2.92 seconds
Started Mar 10 01:51:09 PM PDT 24
Finished Mar 10 01:51:12 PM PDT 24
Peak memory 218668 kb
Host smart-d3080e9e-50fd-4a7b-83fb-941b6435c5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650112986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3650112986
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1212012322
Short name T608
Test name
Test status
Simulation time 95553998 ps
CPU time 0.81 seconds
Started Mar 10 02:47:55 PM PDT 24
Finished Mar 10 02:47:56 PM PDT 24
Peak memory 204824 kb
Host smart-8f38b73c-58bf-4432-8499-c3e548109edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212012322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1212012322
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2550380432
Short name T695
Test name
Test status
Simulation time 50833003 ps
CPU time 0.77 seconds
Started Mar 10 01:51:11 PM PDT 24
Finished Mar 10 01:51:12 PM PDT 24
Peak memory 204480 kb
Host smart-77024fdc-d1fa-459d-813d-75d280171159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550380432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2550380432
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1287533455
Short name T535
Test name
Test status
Simulation time 17149491244 ps
CPU time 123.89 seconds
Started Mar 10 01:51:17 PM PDT 24
Finished Mar 10 01:53:22 PM PDT 24
Peak memory 248412 kb
Host smart-553ba34d-335d-492c-a480-27d40c0ee2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287533455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1287533455
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3885550274
Short name T489
Test name
Test status
Simulation time 2378321379 ps
CPU time 8.25 seconds
Started Mar 10 02:48:00 PM PDT 24
Finished Mar 10 02:48:08 PM PDT 24
Peak memory 232100 kb
Host smart-12b62063-8300-40ee-967b-fe3d6c56b6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885550274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3885550274
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2442456702
Short name T520
Test name
Test status
Simulation time 65331304381 ps
CPU time 78.9 seconds
Started Mar 10 02:48:02 PM PDT 24
Finished Mar 10 02:49:21 PM PDT 24
Peak memory 248656 kb
Host smart-6a873718-810b-40d9-9f74-a33f98f30f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442456702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2442456702
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3158029328
Short name T231
Test name
Test status
Simulation time 6011978066 ps
CPU time 75.86 seconds
Started Mar 10 01:51:14 PM PDT 24
Finished Mar 10 01:52:30 PM PDT 24
Peak memory 253864 kb
Host smart-7c8e8083-1d9c-472a-8df0-6425c2c05198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158029328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3158029328
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.556863604
Short name T256
Test name
Test status
Simulation time 10803363520 ps
CPU time 172.76 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:54:08 PM PDT 24
Peak memory 265060 kb
Host smart-0f21189c-1c97-41f2-9a42-254ed02f11d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556863604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.556863604
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1039302569
Short name T1314
Test name
Test status
Simulation time 8228883595 ps
CPU time 13.63 seconds
Started Mar 10 01:51:09 PM PDT 24
Finished Mar 10 01:51:23 PM PDT 24
Peak memory 232180 kb
Host smart-29e336e2-9e93-4708-88a8-6b9f7e52b4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039302569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1039302569
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3927482935
Short name T937
Test name
Test status
Simulation time 496046468 ps
CPU time 8.44 seconds
Started Mar 10 02:48:01 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 236576 kb
Host smart-34fcb18a-1e13-46ec-9b35-536eb7c951eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927482935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3927482935
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2463024753
Short name T1009
Test name
Test status
Simulation time 5076721386 ps
CPU time 16.4 seconds
Started Mar 10 02:47:59 PM PDT 24
Finished Mar 10 02:48:16 PM PDT 24
Peak memory 233360 kb
Host smart-9ead1228-9312-4331-88ac-972df6e12156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463024753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2463024753
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4077700275
Short name T1525
Test name
Test status
Simulation time 2783505782 ps
CPU time 10.3 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:26 PM PDT 24
Peak memory 232712 kb
Host smart-fe2d4bc0-9a7e-4110-91b3-bba32500bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077700275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4077700275
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1904648216
Short name T913
Test name
Test status
Simulation time 10519222529 ps
CPU time 11.3 seconds
Started Mar 10 01:51:11 PM PDT 24
Finished Mar 10 01:51:23 PM PDT 24
Peak memory 234060 kb
Host smart-be2dde0e-7d77-409e-8d61-02cc3bb47c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904648216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1904648216
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.969766659
Short name T304
Test name
Test status
Simulation time 39532137626 ps
CPU time 25.09 seconds
Started Mar 10 02:47:59 PM PDT 24
Finished Mar 10 02:48:24 PM PDT 24
Peak memory 232084 kb
Host smart-22b39f0d-4a4a-4ed2-a31f-37494b8c1bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969766659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.969766659
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1024456549
Short name T206
Test name
Test status
Simulation time 2094363424 ps
CPU time 12.73 seconds
Started Mar 10 02:47:59 PM PDT 24
Finished Mar 10 02:48:12 PM PDT 24
Peak memory 223788 kb
Host smart-47bb3c04-ff19-40f7-99bc-d18f39380a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024456549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1024456549
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1140176181
Short name T928
Test name
Test status
Simulation time 122061496 ps
CPU time 2.4 seconds
Started Mar 10 01:51:09 PM PDT 24
Finished Mar 10 01:51:12 PM PDT 24
Peak memory 223724 kb
Host smart-96415f7a-2944-4453-b6c1-c902a401884c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140176181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1140176181
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3609136779
Short name T1451
Test name
Test status
Simulation time 4472490143 ps
CPU time 17.02 seconds
Started Mar 10 02:47:52 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 237676 kb
Host smart-bf72104c-d53c-4d84-8321-d0ebac88f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609136779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3609136779
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.776748974
Short name T1903
Test name
Test status
Simulation time 9954682798 ps
CPU time 27.6 seconds
Started Mar 10 01:51:10 PM PDT 24
Finished Mar 10 01:51:38 PM PDT 24
Peak memory 237528 kb
Host smart-79aa8183-6593-4ca2-b89f-45339b8367bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776748974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.776748974
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2997891245
Short name T767
Test name
Test status
Simulation time 278158464 ps
CPU time 3.82 seconds
Started Mar 10 01:51:12 PM PDT 24
Finished Mar 10 01:51:16 PM PDT 24
Peak memory 219384 kb
Host smart-fa6ce8fc-63d3-424e-bc33-90bb05549454
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2997891245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2997891245
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3622800363
Short name T1343
Test name
Test status
Simulation time 246568391 ps
CPU time 3.34 seconds
Started Mar 10 02:47:59 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 217836 kb
Host smart-83d36571-2cdc-4b05-85ea-160be04e7b74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3622800363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3622800363
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1489301964
Short name T1079
Test name
Test status
Simulation time 125197109 ps
CPU time 1.14 seconds
Started Mar 10 02:48:01 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 206204 kb
Host smart-cb9488d5-4a64-42c2-8fb1-552912d8500b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489301964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1489301964
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3225329203
Short name T966
Test name
Test status
Simulation time 5291903180 ps
CPU time 44.74 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:52:00 PM PDT 24
Peak memory 235604 kb
Host smart-5e236141-2b4f-4722-bfce-ff6a3d6dcbe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225329203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3225329203
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1187738292
Short name T1387
Test name
Test status
Simulation time 6771930837 ps
CPU time 30.83 seconds
Started Mar 10 02:48:00 PM PDT 24
Finished Mar 10 02:48:30 PM PDT 24
Peak memory 216016 kb
Host smart-eb73691d-1681-47b8-8daf-e7235de90d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187738292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1187738292
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3902744648
Short name T1334
Test name
Test status
Simulation time 4185704107 ps
CPU time 26.67 seconds
Started Mar 10 01:51:10 PM PDT 24
Finished Mar 10 01:51:37 PM PDT 24
Peak memory 215780 kb
Host smart-bf173e38-d51a-4808-883a-65f8fb944420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902744648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3902744648
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1861434659
Short name T786
Test name
Test status
Simulation time 3101805590 ps
CPU time 10.81 seconds
Started Mar 10 02:47:59 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 215808 kb
Host smart-f2f5bf30-722d-4e82-8cc4-949252dc6e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861434659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1861434659
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3203585141
Short name T920
Test name
Test status
Simulation time 11197214648 ps
CPU time 27.42 seconds
Started Mar 10 01:51:09 PM PDT 24
Finished Mar 10 01:51:37 PM PDT 24
Peak memory 215864 kb
Host smart-e0a8140b-99d1-4659-aeda-e0168d3e0bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203585141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3203585141
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1219933176
Short name T516
Test name
Test status
Simulation time 1019898093 ps
CPU time 10.14 seconds
Started Mar 10 02:47:58 PM PDT 24
Finished Mar 10 02:48:08 PM PDT 24
Peak memory 215760 kb
Host smart-f0d75c3f-1d38-4faf-8f2b-79e7ead34602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219933176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1219933176
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.309387775
Short name T1041
Test name
Test status
Simulation time 152428591 ps
CPU time 2.33 seconds
Started Mar 10 01:51:12 PM PDT 24
Finished Mar 10 01:51:14 PM PDT 24
Peak memory 208040 kb
Host smart-0a8d10f4-2426-4571-a365-5b143f08da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309387775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.309387775
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3253998549
Short name T312
Test name
Test status
Simulation time 29512753 ps
CPU time 0.84 seconds
Started Mar 10 01:51:10 PM PDT 24
Finished Mar 10 01:51:11 PM PDT 24
Peak memory 204844 kb
Host smart-73e0c4d9-e33e-43a4-a025-8893c0c472df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253998549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3253998549
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3784027142
Short name T495
Test name
Test status
Simulation time 194778507 ps
CPU time 0.97 seconds
Started Mar 10 02:47:56 PM PDT 24
Finished Mar 10 02:47:57 PM PDT 24
Peak memory 205888 kb
Host smart-1752b3f7-18df-4852-8337-ff76eacdd333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784027142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3784027142
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3356200964
Short name T1333
Test name
Test status
Simulation time 10731653755 ps
CPU time 10.02 seconds
Started Mar 10 02:47:59 PM PDT 24
Finished Mar 10 02:48:09 PM PDT 24
Peak memory 232380 kb
Host smart-bd176709-4eab-473a-b5d8-ee3f1bf43734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356200964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3356200964
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_upload.57313415
Short name T1919
Test name
Test status
Simulation time 1884184495 ps
CPU time 7.67 seconds
Started Mar 10 01:51:10 PM PDT 24
Finished Mar 10 01:51:18 PM PDT 24
Peak memory 237740 kb
Host smart-bddcd02a-bd68-422c-9855-f0ed8ab320b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57313415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.57313415
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.445477294
Short name T1751
Test name
Test status
Simulation time 17138752 ps
CPU time 0.73 seconds
Started Mar 10 01:49:05 PM PDT 24
Finished Mar 10 01:49:06 PM PDT 24
Peak memory 204388 kb
Host smart-512931b1-fb1d-45f5-a049-5d465532f686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445477294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.445477294
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.855018214
Short name T1637
Test name
Test status
Simulation time 38083447 ps
CPU time 0.71 seconds
Started Mar 10 02:46:16 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 203868 kb
Host smart-108e0c4d-75c1-4b5d-9830-36b075135654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855018214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.855018214
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1480003304
Short name T402
Test name
Test status
Simulation time 6077077941 ps
CPU time 16.02 seconds
Started Mar 10 02:46:18 PM PDT 24
Finished Mar 10 02:46:34 PM PDT 24
Peak memory 223884 kb
Host smart-71759fd3-c5fe-4da7-924e-1c1da33217ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480003304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1480003304
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2175877102
Short name T1207
Test name
Test status
Simulation time 134119988 ps
CPU time 3.35 seconds
Started Mar 10 01:49:01 PM PDT 24
Finished Mar 10 01:49:04 PM PDT 24
Peak memory 218248 kb
Host smart-bd9f0dce-040a-417d-97fb-a51330983697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175877102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2175877102
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4166851809
Short name T1663
Test name
Test status
Simulation time 54705215 ps
CPU time 0.77 seconds
Started Mar 10 02:46:10 PM PDT 24
Finished Mar 10 02:46:11 PM PDT 24
Peak memory 204488 kb
Host smart-41331845-66e0-4a20-8a0a-656a132850f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166851809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4166851809
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.888001304
Short name T348
Test name
Test status
Simulation time 20921341 ps
CPU time 0.76 seconds
Started Mar 10 01:49:00 PM PDT 24
Finished Mar 10 01:49:01 PM PDT 24
Peak memory 204828 kb
Host smart-9bf5bbab-a884-4ec0-a873-d0675c4dbaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888001304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.888001304
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1765744139
Short name T1695
Test name
Test status
Simulation time 21381880124 ps
CPU time 85.89 seconds
Started Mar 10 01:49:02 PM PDT 24
Finished Mar 10 01:50:28 PM PDT 24
Peak memory 252248 kb
Host smart-8fbb657c-8697-4361-a757-44245f95de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765744139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1765744139
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4271222507
Short name T561
Test name
Test status
Simulation time 6479826186 ps
CPU time 54.26 seconds
Started Mar 10 02:46:17 PM PDT 24
Finished Mar 10 02:47:12 PM PDT 24
Peak memory 262340 kb
Host smart-4401142e-05be-4dbd-a536-654937f916a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271222507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4271222507
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2198967149
Short name T951
Test name
Test status
Simulation time 472816136806 ps
CPU time 342.04 seconds
Started Mar 10 01:49:02 PM PDT 24
Finished Mar 10 01:54:45 PM PDT 24
Peak memory 254096 kb
Host smart-500adfc8-c337-4d4a-a7fe-69578278d3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198967149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2198967149
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2715333703
Short name T1657
Test name
Test status
Simulation time 568054529726 ps
CPU time 505.7 seconds
Started Mar 10 02:46:17 PM PDT 24
Finished Mar 10 02:54:43 PM PDT 24
Peak memory 273240 kb
Host smart-e1451e72-5f66-4b1e-a859-b4bd6beeed64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715333703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2715333703
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2150296783
Short name T1399
Test name
Test status
Simulation time 104132894792 ps
CPU time 169.91 seconds
Started Mar 10 02:46:18 PM PDT 24
Finished Mar 10 02:49:08 PM PDT 24
Peak memory 239524 kb
Host smart-0e9a5f15-d375-4852-b6ff-dd74452ea31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150296783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2150296783
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3106241953
Short name T753
Test name
Test status
Simulation time 24698017019 ps
CPU time 111.52 seconds
Started Mar 10 01:48:56 PM PDT 24
Finished Mar 10 01:50:48 PM PDT 24
Peak memory 270108 kb
Host smart-f01215b4-5696-40ba-90fe-f9f4317e1a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106241953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3106241953
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3649907752
Short name T1105
Test name
Test status
Simulation time 8721529234 ps
CPU time 16.42 seconds
Started Mar 10 02:46:18 PM PDT 24
Finished Mar 10 02:46:35 PM PDT 24
Peak memory 223952 kb
Host smart-83a8104d-28df-4c4c-8f6f-c7001a6d183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649907752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3649907752
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4208110454
Short name T909
Test name
Test status
Simulation time 3967636018 ps
CPU time 13 seconds
Started Mar 10 01:49:03 PM PDT 24
Finished Mar 10 01:49:16 PM PDT 24
Peak memory 233768 kb
Host smart-89737a0e-419c-4ebb-b624-53bd4b676200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208110454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4208110454
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2389701371
Short name T448
Test name
Test status
Simulation time 290425137 ps
CPU time 2.89 seconds
Started Mar 10 01:49:00 PM PDT 24
Finished Mar 10 01:49:03 PM PDT 24
Peak memory 218592 kb
Host smart-c920bfef-b971-49f7-b090-e9d420ba104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389701371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2389701371
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intercept.621892492
Short name T765
Test name
Test status
Simulation time 35111199 ps
CPU time 2.5 seconds
Started Mar 10 02:46:12 PM PDT 24
Finished Mar 10 02:46:15 PM PDT 24
Peak memory 232036 kb
Host smart-965d52b8-2977-4489-9d5a-e1c872af15f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621892492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.621892492
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1905287347
Short name T1790
Test name
Test status
Simulation time 23438304495 ps
CPU time 32.99 seconds
Started Mar 10 01:49:02 PM PDT 24
Finished Mar 10 01:49:35 PM PDT 24
Peak memory 233220 kb
Host smart-4f733c36-637c-486b-afcc-9515d02befe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905287347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1905287347
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4139390534
Short name T1274
Test name
Test status
Simulation time 5612679371 ps
CPU time 6.91 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:46:26 PM PDT 24
Peak memory 223292 kb
Host smart-bfc38805-baf7-466f-a489-e3f0de50f43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139390534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4139390534
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2818570441
Short name T1720
Test name
Test status
Simulation time 47837022 ps
CPU time 1.05 seconds
Started Mar 10 01:48:57 PM PDT 24
Finished Mar 10 01:48:58 PM PDT 24
Peak memory 216044 kb
Host smart-55dc18d8-1996-48a6-acbc-157479eb3bf3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818570441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2818570441
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3688202337
Short name T639
Test name
Test status
Simulation time 105617579 ps
CPU time 1.06 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:16 PM PDT 24
Peak memory 217284 kb
Host smart-d6de3f77-85f5-45e4-9d95-b50adda5ff29
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688202337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3688202337
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.550561092
Short name T508
Test name
Test status
Simulation time 1076120889 ps
CPU time 5.28 seconds
Started Mar 10 02:46:13 PM PDT 24
Finished Mar 10 02:46:18 PM PDT 24
Peak memory 217204 kb
Host smart-48a85656-65a8-48cd-822c-9d0924bcd484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550561092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
550561092
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.563345352
Short name T1138
Test name
Test status
Simulation time 35820571341 ps
CPU time 24.71 seconds
Started Mar 10 01:49:01 PM PDT 24
Finished Mar 10 01:49:26 PM PDT 24
Peak memory 232984 kb
Host smart-c2ba08dc-b0af-4bee-b779-4b9c8785966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563345352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
563345352
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1029914116
Short name T1361
Test name
Test status
Simulation time 316303992 ps
CPU time 4.89 seconds
Started Mar 10 01:48:59 PM PDT 24
Finished Mar 10 01:49:04 PM PDT 24
Peak memory 232532 kb
Host smart-03f38cd8-64d4-443e-a3a1-881c48e60dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029914116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1029914116
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3057852037
Short name T1591
Test name
Test status
Simulation time 2290022000 ps
CPU time 8.91 seconds
Started Mar 10 02:46:13 PM PDT 24
Finished Mar 10 02:46:22 PM PDT 24
Peak memory 239760 kb
Host smart-5402eefe-759f-4fe0-931d-c9da00201992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057852037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3057852037
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.32370313
Short name T593
Test name
Test status
Simulation time 33965991 ps
CPU time 0.77 seconds
Started Mar 10 02:46:14 PM PDT 24
Finished Mar 10 02:46:16 PM PDT 24
Peak memory 215624 kb
Host smart-499bdd3d-9a96-4287-8ab8-9176be200b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32370313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.32370313
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.363629641
Short name T141
Test name
Test status
Simulation time 817671185 ps
CPU time 4.12 seconds
Started Mar 10 02:46:21 PM PDT 24
Finished Mar 10 02:46:25 PM PDT 24
Peak memory 221944 kb
Host smart-cf4ce840-267b-49b3-bd41-99ab506f65c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=363629641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.363629641
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.966141572
Short name T1410
Test name
Test status
Simulation time 1387332040 ps
CPU time 6.31 seconds
Started Mar 10 01:49:01 PM PDT 24
Finished Mar 10 01:49:07 PM PDT 24
Peak memory 215936 kb
Host smart-872d0917-4cee-4910-bbe5-78fa17dd508a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=966141572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.966141572
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1120170532
Short name T63
Test name
Test status
Simulation time 167690829 ps
CPU time 1.19 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:46:20 PM PDT 24
Peak memory 233904 kb
Host smart-1e446176-3453-48de-8fb8-e3f1488737a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120170532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1120170532
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.433870891
Short name T69
Test name
Test status
Simulation time 166115355 ps
CPU time 0.96 seconds
Started Mar 10 01:49:03 PM PDT 24
Finished Mar 10 01:49:04 PM PDT 24
Peak memory 234532 kb
Host smart-86232abb-77b3-4dd2-b2d3-ac50e0ed380e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433870891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.433870891
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2124290518
Short name T1197
Test name
Test status
Simulation time 88166046107 ps
CPU time 328.44 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:51:48 PM PDT 24
Peak memory 255108 kb
Host smart-eb8c7138-9b80-47ac-abba-b28b4573b91b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124290518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2124290518
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2524334547
Short name T153
Test name
Test status
Simulation time 275110086224 ps
CPU time 353.93 seconds
Started Mar 10 01:49:00 PM PDT 24
Finished Mar 10 01:54:54 PM PDT 24
Peak memory 252036 kb
Host smart-a066d9de-4587-44d1-a55f-c925edda9af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524334547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2524334547
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2413100207
Short name T1328
Test name
Test status
Simulation time 8088302025 ps
CPU time 17.73 seconds
Started Mar 10 01:48:57 PM PDT 24
Finished Mar 10 01:49:15 PM PDT 24
Peak memory 215784 kb
Host smart-52e9b110-24b0-4b0b-90b0-e486b1e0a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413100207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2413100207
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.508288243
Short name T1604
Test name
Test status
Simulation time 640813452 ps
CPU time 5.51 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:21 PM PDT 24
Peak memory 215732 kb
Host smart-26ee3dc7-6aff-4095-bfdd-439e6b77403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508288243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.508288243
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1282623070
Short name T940
Test name
Test status
Simulation time 2841310777 ps
CPU time 3.57 seconds
Started Mar 10 02:46:13 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 215868 kb
Host smart-b70a29d1-d799-42f8-98ac-701840a777ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282623070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1282623070
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4196014568
Short name T1338
Test name
Test status
Simulation time 840467450 ps
CPU time 5.4 seconds
Started Mar 10 01:49:02 PM PDT 24
Finished Mar 10 01:49:08 PM PDT 24
Peak memory 215692 kb
Host smart-62be296f-a840-47c4-abbf-a40db94b9511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196014568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4196014568
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1961723661
Short name T498
Test name
Test status
Simulation time 191141842 ps
CPU time 2.16 seconds
Started Mar 10 01:49:02 PM PDT 24
Finished Mar 10 01:49:04 PM PDT 24
Peak memory 215692 kb
Host smart-3523eb7d-a521-4352-a3ac-a12c3ec49b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961723661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1961723661
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3278147823
Short name T941
Test name
Test status
Simulation time 125725835 ps
CPU time 1.89 seconds
Started Mar 10 02:46:15 PM PDT 24
Finished Mar 10 02:46:17 PM PDT 24
Peak memory 215776 kb
Host smart-38df90e4-7918-4f5f-900d-b25da667b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278147823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3278147823
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1337076583
Short name T1209
Test name
Test status
Simulation time 95459469 ps
CPU time 0.87 seconds
Started Mar 10 02:46:11 PM PDT 24
Finished Mar 10 02:46:12 PM PDT 24
Peak memory 204884 kb
Host smart-223cf8ff-4533-4a8f-a773-4a2d398970f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337076583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1337076583
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.177665456
Short name T1145
Test name
Test status
Simulation time 39582462 ps
CPU time 0.73 seconds
Started Mar 10 01:48:58 PM PDT 24
Finished Mar 10 01:48:59 PM PDT 24
Peak memory 204892 kb
Host smart-3b1598fa-0c43-4f18-b59a-69af2a54fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177665456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.177665456
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.221398727
Short name T1384
Test name
Test status
Simulation time 2762365371 ps
CPU time 8.32 seconds
Started Mar 10 01:49:01 PM PDT 24
Finished Mar 10 01:49:09 PM PDT 24
Peak memory 235992 kb
Host smart-5c07b2c3-af7d-4202-a4ce-5849cefe539b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221398727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.221398727
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_upload.3061166472
Short name T719
Test name
Test status
Simulation time 58529338307 ps
CPU time 41.69 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:47:00 PM PDT 24
Peak memory 237748 kb
Host smart-c502eab5-aae5-4a1c-b297-96de375e605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061166472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3061166472
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2348697549
Short name T1917
Test name
Test status
Simulation time 26481430 ps
CPU time 0.75 seconds
Started Mar 10 02:48:09 PM PDT 24
Finished Mar 10 02:48:10 PM PDT 24
Peak memory 204780 kb
Host smart-5fac77c6-f366-4c04-88e8-3702a21f3eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348697549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2348697549
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4033465541
Short name T857
Test name
Test status
Simulation time 25137774 ps
CPU time 0.7 seconds
Started Mar 10 01:51:22 PM PDT 24
Finished Mar 10 01:51:23 PM PDT 24
Peak memory 204708 kb
Host smart-97bff46c-117e-4fc1-a69d-5eb8277af5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033465541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4033465541
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2845610787
Short name T609
Test name
Test status
Simulation time 920639935 ps
CPU time 4.85 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 218748 kb
Host smart-ea5fe094-13db-44de-98d1-3ad517b35b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845610787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2845610787
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4269668585
Short name T1878
Test name
Test status
Simulation time 94571880 ps
CPU time 2.6 seconds
Started Mar 10 02:48:05 PM PDT 24
Finished Mar 10 02:48:08 PM PDT 24
Peak memory 216748 kb
Host smart-a5a29b21-05b5-4deb-a548-11201a2d38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269668585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4269668585
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1515476237
Short name T573
Test name
Test status
Simulation time 19011898 ps
CPU time 0.77 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:16 PM PDT 24
Peak memory 204812 kb
Host smart-6a414c1d-282a-4a2e-8358-2987ef174c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515476237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1515476237
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.547290226
Short name T577
Test name
Test status
Simulation time 15389330 ps
CPU time 0.76 seconds
Started Mar 10 02:48:00 PM PDT 24
Finished Mar 10 02:48:01 PM PDT 24
Peak memory 204792 kb
Host smart-27fdf4d2-8a49-4f5b-bfb7-592776b1249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547290226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.547290226
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1460285264
Short name T587
Test name
Test status
Simulation time 1939772298 ps
CPU time 18.45 seconds
Started Mar 10 02:48:05 PM PDT 24
Finished Mar 10 02:48:24 PM PDT 24
Peak memory 237852 kb
Host smart-a031b8d5-138f-418b-859b-6f894ad58858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460285264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1460285264
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4109254715
Short name T792
Test name
Test status
Simulation time 8116334003 ps
CPU time 35.53 seconds
Started Mar 10 01:51:24 PM PDT 24
Finished Mar 10 01:52:00 PM PDT 24
Peak memory 244788 kb
Host smart-0afbd6bf-4eea-4911-8d84-b49fcecff1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109254715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4109254715
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4118303902
Short name T975
Test name
Test status
Simulation time 21168177653 ps
CPU time 64.67 seconds
Started Mar 10 02:48:06 PM PDT 24
Finished Mar 10 02:49:10 PM PDT 24
Peak memory 248652 kb
Host smart-d79478f0-5c40-43a5-b0b3-e970d4f9049d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118303902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4118303902
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.477912273
Short name T214
Test name
Test status
Simulation time 4386429170 ps
CPU time 59.81 seconds
Started Mar 10 01:51:19 PM PDT 24
Finished Mar 10 01:52:19 PM PDT 24
Peak memory 256176 kb
Host smart-01746985-af10-42e7-b2ad-7041e027a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477912273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.477912273
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1610369427
Short name T454
Test name
Test status
Simulation time 31803189947 ps
CPU time 115.88 seconds
Started Mar 10 02:48:05 PM PDT 24
Finished Mar 10 02:50:01 PM PDT 24
Peak memory 240412 kb
Host smart-eb0fce98-3235-49c5-8e77-502afbe2d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610369427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1610369427
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2558901301
Short name T1431
Test name
Test status
Simulation time 35634964764 ps
CPU time 218.46 seconds
Started Mar 10 01:51:22 PM PDT 24
Finished Mar 10 01:55:01 PM PDT 24
Peak memory 253416 kb
Host smart-72e43e04-1e05-419e-ba0c-70c28bdb0f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558901301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2558901301
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2301051493
Short name T1233
Test name
Test status
Simulation time 3878983441 ps
CPU time 31.84 seconds
Started Mar 10 01:51:14 PM PDT 24
Finished Mar 10 01:51:46 PM PDT 24
Peak memory 246952 kb
Host smart-5c095079-2ec3-42d1-bec6-58aedb8fa261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301051493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2301051493
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.833050538
Short name T1242
Test name
Test status
Simulation time 5709304769 ps
CPU time 16.37 seconds
Started Mar 10 02:48:06 PM PDT 24
Finished Mar 10 02:48:22 PM PDT 24
Peak memory 248508 kb
Host smart-8b4913c8-2d5b-4575-a9da-2a7cb86f6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833050538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.833050538
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2548397030
Short name T681
Test name
Test status
Simulation time 1280740744 ps
CPU time 3.33 seconds
Started Mar 10 02:48:01 PM PDT 24
Finished Mar 10 02:48:04 PM PDT 24
Peak memory 216368 kb
Host smart-eb490724-761b-46b0-ac77-9e3e6025402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548397030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2548397030
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intercept.65048941
Short name T678
Test name
Test status
Simulation time 363141305 ps
CPU time 3.7 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 232952 kb
Host smart-1ae5a70a-2f95-4ad3-97bf-1da9080f8bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65048941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.65048941
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3874149157
Short name T1570
Test name
Test status
Simulation time 1117280306 ps
CPU time 10.19 seconds
Started Mar 10 01:51:17 PM PDT 24
Finished Mar 10 01:51:28 PM PDT 24
Peak memory 217944 kb
Host smart-654f289b-4ee6-455d-a3d2-ffe3a57b96a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874149157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3874149157
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.677448022
Short name T842
Test name
Test status
Simulation time 5059623666 ps
CPU time 9.18 seconds
Started Mar 10 02:48:07 PM PDT 24
Finished Mar 10 02:48:16 PM PDT 24
Peak memory 233052 kb
Host smart-7b36cfae-c78f-4a35-b771-2d9453f57888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677448022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.677448022
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1583924324
Short name T188
Test name
Test status
Simulation time 7119686635 ps
CPU time 8.79 seconds
Started Mar 10 01:51:16 PM PDT 24
Finished Mar 10 01:51:26 PM PDT 24
Peak memory 232848 kb
Host smart-2cd217e7-df3a-4fc6-b827-2bbf138603ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583924324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1583924324
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2986341446
Short name T808
Test name
Test status
Simulation time 2022307377 ps
CPU time 6.37 seconds
Started Mar 10 02:47:59 PM PDT 24
Finished Mar 10 02:48:05 PM PDT 24
Peak memory 223796 kb
Host smart-d112bb07-d124-4d62-8826-e0ec61a78e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986341446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2986341446
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2440870612
Short name T1060
Test name
Test status
Simulation time 1140922701 ps
CPU time 3.32 seconds
Started Mar 10 02:48:00 PM PDT 24
Finished Mar 10 02:48:03 PM PDT 24
Peak memory 233012 kb
Host smart-04557f06-923c-429c-9c1f-8ee7b17b83ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440870612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2440870612
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2873976802
Short name T170
Test name
Test status
Simulation time 7952177913 ps
CPU time 26.03 seconds
Started Mar 10 01:51:17 PM PDT 24
Finished Mar 10 01:51:44 PM PDT 24
Peak memory 230624 kb
Host smart-7de6a039-958e-4833-a10c-6450f8fc5de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873976802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2873976802
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2512873952
Short name T1875
Test name
Test status
Simulation time 1674389328 ps
CPU time 7.54 seconds
Started Mar 10 01:51:19 PM PDT 24
Finished Mar 10 01:51:27 PM PDT 24
Peak memory 222024 kb
Host smart-ddd351cf-45a2-4a6b-97ef-52c5f3050cfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2512873952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2512873952
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2564485710
Short name T1446
Test name
Test status
Simulation time 1086531097 ps
CPU time 6.38 seconds
Started Mar 10 02:48:04 PM PDT 24
Finished Mar 10 02:48:11 PM PDT 24
Peak memory 221976 kb
Host smart-527b5cec-4c4f-468c-940f-0160797b6148
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2564485710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2564485710
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2065314629
Short name T660
Test name
Test status
Simulation time 33174660860 ps
CPU time 211.93 seconds
Started Mar 10 01:51:19 PM PDT 24
Finished Mar 10 01:54:51 PM PDT 24
Peak memory 265980 kb
Host smart-9087be67-54c7-47ad-829c-ac240b3bb171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065314629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2065314629
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.593804662
Short name T58
Test name
Test status
Simulation time 45613526 ps
CPU time 0.98 seconds
Started Mar 10 02:48:05 PM PDT 24
Finished Mar 10 02:48:06 PM PDT 24
Peak memory 205824 kb
Host smart-43dd92bd-b6f1-439b-bfdf-1f0494398e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593804662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.593804662
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2960517685
Short name T1686
Test name
Test status
Simulation time 3030607881 ps
CPU time 21.05 seconds
Started Mar 10 02:48:02 PM PDT 24
Finished Mar 10 02:48:23 PM PDT 24
Peak memory 215740 kb
Host smart-87dff539-5f46-45a6-980e-78c21e4fe3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960517685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2960517685
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3990400352
Short name T458
Test name
Test status
Simulation time 2989051410 ps
CPU time 16.36 seconds
Started Mar 10 01:51:13 PM PDT 24
Finished Mar 10 01:51:30 PM PDT 24
Peak memory 215860 kb
Host smart-ac2da8b0-3b33-45f3-bd62-1bd040537f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990400352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3990400352
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2265872283
Short name T1843
Test name
Test status
Simulation time 29770927658 ps
CPU time 21.59 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:37 PM PDT 24
Peak memory 215852 kb
Host smart-39168a42-a95f-4532-a32c-4e5efc770f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265872283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2265872283
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2276508041
Short name T7
Test name
Test status
Simulation time 125765839 ps
CPU time 1.37 seconds
Started Mar 10 02:48:00 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 206284 kb
Host smart-2ee3275b-afa9-49d6-be60-5b866b965381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276508041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2276508041
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.148665358
Short name T401
Test name
Test status
Simulation time 42869016 ps
CPU time 1.25 seconds
Started Mar 10 02:48:00 PM PDT 24
Finished Mar 10 02:48:02 PM PDT 24
Peak memory 216108 kb
Host smart-c2a5c7f2-2615-4591-b51a-6c45a637aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148665358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.148665358
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.83575986
Short name T1654
Test name
Test status
Simulation time 35650403 ps
CPU time 0.94 seconds
Started Mar 10 01:51:13 PM PDT 24
Finished Mar 10 01:51:14 PM PDT 24
Peak memory 205816 kb
Host smart-0bfb2c17-9139-4233-a7de-ff980c0f34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83575986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.83575986
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1094324112
Short name T1465
Test name
Test status
Simulation time 39071854 ps
CPU time 0.75 seconds
Started Mar 10 01:51:17 PM PDT 24
Finished Mar 10 01:51:19 PM PDT 24
Peak memory 204864 kb
Host smart-ddbf096a-a631-448e-a218-48ea9a370fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094324112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1094324112
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1500497240
Short name T1297
Test name
Test status
Simulation time 94940059 ps
CPU time 0.96 seconds
Started Mar 10 02:48:02 PM PDT 24
Finished Mar 10 02:48:03 PM PDT 24
Peak memory 204864 kb
Host smart-5d598380-f976-4e05-8ad5-9965e1268dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500497240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1500497240
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1548645665
Short name T1746
Test name
Test status
Simulation time 27006008557 ps
CPU time 14.77 seconds
Started Mar 10 02:48:08 PM PDT 24
Finished Mar 10 02:48:23 PM PDT 24
Peak memory 236752 kb
Host smart-47411370-7b34-4468-98fc-b4882ab1d928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548645665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1548645665
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_upload.628090758
Short name T1677
Test name
Test status
Simulation time 2016818151 ps
CPU time 4.74 seconds
Started Mar 10 01:51:15 PM PDT 24
Finished Mar 10 01:51:20 PM PDT 24
Peak memory 216640 kb
Host smart-0ba11c0c-2098-4b4f-9071-f8b0b22591a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628090758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.628090758
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1869755
Short name T919
Test name
Test status
Simulation time 16663827 ps
CPU time 0.71 seconds
Started Mar 10 02:48:06 PM PDT 24
Finished Mar 10 02:48:06 PM PDT 24
Peak memory 204436 kb
Host smart-e7de33c1-5124-4e28-b273-1fa275f27ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.1869755
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2488508203
Short name T903
Test name
Test status
Simulation time 13759282 ps
CPU time 0.71 seconds
Started Mar 10 01:51:24 PM PDT 24
Finished Mar 10 01:51:25 PM PDT 24
Peak memory 204280 kb
Host smart-8e512bc1-0f3b-4423-9e34-2e52f174e3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488508203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2488508203
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2691091749
Short name T1291
Test name
Test status
Simulation time 1902422059 ps
CPU time 4.99 seconds
Started Mar 10 01:51:22 PM PDT 24
Finished Mar 10 01:51:27 PM PDT 24
Peak memory 233124 kb
Host smart-99e8e7d5-1e47-4536-aa0d-f7fb6870cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691091749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2691091749
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.461592693
Short name T486
Test name
Test status
Simulation time 853749590 ps
CPU time 4.63 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:48:15 PM PDT 24
Peak memory 219204 kb
Host smart-dc50f0cd-9bff-4488-9a5c-1ce91c4050db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461592693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.461592693
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.271893349
Short name T1099
Test name
Test status
Simulation time 24220381 ps
CPU time 0.84 seconds
Started Mar 10 02:48:06 PM PDT 24
Finished Mar 10 02:48:07 PM PDT 24
Peak memory 205520 kb
Host smart-e04baafd-d869-4ef0-b1b3-1416bc9c85c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271893349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.271893349
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3261499039
Short name T490
Test name
Test status
Simulation time 33819762 ps
CPU time 0.76 seconds
Started Mar 10 01:51:20 PM PDT 24
Finished Mar 10 01:51:21 PM PDT 24
Peak memory 205516 kb
Host smart-f9a3ef99-3e22-4d30-a066-775346d3bfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261499039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3261499039
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.194232851
Short name T1420
Test name
Test status
Simulation time 172199445003 ps
CPU time 200.66 seconds
Started Mar 10 01:51:28 PM PDT 24
Finished Mar 10 01:54:48 PM PDT 24
Peak memory 256756 kb
Host smart-b0ecad6e-9868-407f-a826-247848648d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194232851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.194232851
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3992048995
Short name T488
Test name
Test status
Simulation time 3045803798 ps
CPU time 14.51 seconds
Started Mar 10 02:48:04 PM PDT 24
Finished Mar 10 02:48:19 PM PDT 24
Peak memory 232160 kb
Host smart-df3abd4d-fc76-4ff6-884e-5a7dec666213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992048995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3992048995
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.228806977
Short name T960
Test name
Test status
Simulation time 5696290919 ps
CPU time 58.01 seconds
Started Mar 10 01:51:22 PM PDT 24
Finished Mar 10 01:52:21 PM PDT 24
Peak memory 236620 kb
Host smart-4066d457-3256-4dcb-b58e-a4bbeda3d3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228806977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.228806977
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1548167466
Short name T1916
Test name
Test status
Simulation time 13637859275 ps
CPU time 70.82 seconds
Started Mar 10 02:48:07 PM PDT 24
Finished Mar 10 02:49:18 PM PDT 24
Peak memory 249524 kb
Host smart-0c409b5c-9d89-415e-a5e3-84d2fbae58ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548167466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1548167466
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1960133637
Short name T918
Test name
Test status
Simulation time 23208137696 ps
CPU time 206.09 seconds
Started Mar 10 01:51:25 PM PDT 24
Finished Mar 10 01:54:51 PM PDT 24
Peak memory 251216 kb
Host smart-542d1731-8150-4f0f-a4a3-752bf08e6648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960133637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1960133637
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1051916084
Short name T1445
Test name
Test status
Simulation time 5146394340 ps
CPU time 29.54 seconds
Started Mar 10 01:51:20 PM PDT 24
Finished Mar 10 01:51:50 PM PDT 24
Peak memory 238296 kb
Host smart-2391e05b-2adf-4b4a-b703-c4d1dbba4d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051916084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1051916084
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3804884937
Short name T1463
Test name
Test status
Simulation time 7212195796 ps
CPU time 42.58 seconds
Started Mar 10 02:48:09 PM PDT 24
Finished Mar 10 02:48:52 PM PDT 24
Peak memory 235964 kb
Host smart-a6886990-7d9e-4fed-8855-b5b137c5a2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804884937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3804884937
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2676838168
Short name T6
Test name
Test status
Simulation time 3404932492 ps
CPU time 4.93 seconds
Started Mar 10 02:48:05 PM PDT 24
Finished Mar 10 02:48:10 PM PDT 24
Peak memory 233956 kb
Host smart-19fb0ad8-b399-48c1-9c34-19965aa64896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676838168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2676838168
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intercept.345471631
Short name T1409
Test name
Test status
Simulation time 27431204483 ps
CPU time 14.95 seconds
Started Mar 10 01:51:21 PM PDT 24
Finished Mar 10 01:51:37 PM PDT 24
Peak memory 218136 kb
Host smart-b93a82ae-0233-49b5-b81b-a7254dceaf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345471631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.345471631
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1924657614
Short name T1862
Test name
Test status
Simulation time 28366885319 ps
CPU time 24.42 seconds
Started Mar 10 01:51:21 PM PDT 24
Finished Mar 10 01:51:46 PM PDT 24
Peak memory 233248 kb
Host smart-c9d018f7-8a6c-4094-b3c2-9aed7fadf6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924657614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1924657614
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4225214189
Short name T1457
Test name
Test status
Simulation time 431584816 ps
CPU time 4.93 seconds
Started Mar 10 02:48:07 PM PDT 24
Finished Mar 10 02:48:12 PM PDT 24
Peak memory 219560 kb
Host smart-71566042-54b2-4982-a380-14fc5fcdb957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225214189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4225214189
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1050847492
Short name T1345
Test name
Test status
Simulation time 331915716 ps
CPU time 5.96 seconds
Started Mar 10 01:51:21 PM PDT 24
Finished Mar 10 01:51:27 PM PDT 24
Peak memory 232648 kb
Host smart-6c1e8e9b-4bac-4e2a-ba55-6fd7ab44f06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050847492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1050847492
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.685852040
Short name T1633
Test name
Test status
Simulation time 2154187606 ps
CPU time 8.19 seconds
Started Mar 10 02:48:05 PM PDT 24
Finished Mar 10 02:48:14 PM PDT 24
Peak memory 229640 kb
Host smart-7a2fa56b-ebf2-4b05-9a56-922f0819d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685852040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.685852040
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3101634812
Short name T1469
Test name
Test status
Simulation time 3765372566 ps
CPU time 5.04 seconds
Started Mar 10 01:51:20 PM PDT 24
Finished Mar 10 01:51:25 PM PDT 24
Peak memory 233152 kb
Host smart-2f04a929-0243-4345-8c9c-5293879bff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101634812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3101634812
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3236428252
Short name T1074
Test name
Test status
Simulation time 1221256261 ps
CPU time 5.21 seconds
Started Mar 10 02:48:06 PM PDT 24
Finished Mar 10 02:48:11 PM PDT 24
Peak memory 219892 kb
Host smart-30ab47d2-346c-4d43-aca2-252723c2c658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236428252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3236428252
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1990645266
Short name T1092
Test name
Test status
Simulation time 188906514 ps
CPU time 3.52 seconds
Started Mar 10 01:51:22 PM PDT 24
Finished Mar 10 01:51:26 PM PDT 24
Peak memory 221932 kb
Host smart-130f72c1-9af7-424f-a323-86896892a93a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1990645266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1990645266
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4036861531
Short name T140
Test name
Test status
Simulation time 312757797 ps
CPU time 3.91 seconds
Started Mar 10 02:48:07 PM PDT 24
Finished Mar 10 02:48:11 PM PDT 24
Peak memory 218428 kb
Host smart-cdec4add-ea91-46f6-9d53-3acb697d2e2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4036861531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4036861531
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2727244301
Short name T1673
Test name
Test status
Simulation time 14520438006 ps
CPU time 179.44 seconds
Started Mar 10 02:48:07 PM PDT 24
Finished Mar 10 02:51:07 PM PDT 24
Peak memory 256000 kb
Host smart-d20b4bd2-eedd-453b-b847-4a905330630b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727244301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2727244301
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2864058465
Short name T279
Test name
Test status
Simulation time 36211590504 ps
CPU time 62.19 seconds
Started Mar 10 02:48:09 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 215792 kb
Host smart-e6933847-314f-454e-a2e1-888ee45dcfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864058465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2864058465
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3357768370
Short name T484
Test name
Test status
Simulation time 3340152564 ps
CPU time 31.56 seconds
Started Mar 10 01:51:20 PM PDT 24
Finished Mar 10 01:51:51 PM PDT 24
Peak memory 215788 kb
Host smart-77acb892-4d0f-44bd-a2d3-57e6b192eeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357768370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3357768370
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2136902808
Short name T1890
Test name
Test status
Simulation time 418361677 ps
CPU time 2.63 seconds
Started Mar 10 01:51:21 PM PDT 24
Finished Mar 10 01:51:24 PM PDT 24
Peak memory 215572 kb
Host smart-cea1267b-9d29-4aeb-9d31-1400259351bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136902808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2136902808
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2151282604
Short name T1385
Test name
Test status
Simulation time 9746919166 ps
CPU time 7.42 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:48:17 PM PDT 24
Peak memory 215800 kb
Host smart-6e0b4b19-aac1-4593-9efc-661ddc7a13ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151282604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2151282604
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2326478205
Short name T613
Test name
Test status
Simulation time 376752897 ps
CPU time 4.5 seconds
Started Mar 10 02:48:06 PM PDT 24
Finished Mar 10 02:48:10 PM PDT 24
Peak memory 215840 kb
Host smart-977d08e1-a65b-4673-81b7-ed794fa61a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326478205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2326478205
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2757250752
Short name T395
Test name
Test status
Simulation time 126051201 ps
CPU time 4.6 seconds
Started Mar 10 01:51:20 PM PDT 24
Finished Mar 10 01:51:25 PM PDT 24
Peak memory 215952 kb
Host smart-4d65351d-8922-4c72-a223-3211fbd721f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757250752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2757250752
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3410196295
Short name T1834
Test name
Test status
Simulation time 186693385 ps
CPU time 0.9 seconds
Started Mar 10 02:48:05 PM PDT 24
Finished Mar 10 02:48:06 PM PDT 24
Peak memory 204816 kb
Host smart-9d1a03ca-8c39-4825-834b-b7c7b1245a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410196295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3410196295
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.817597823
Short name T628
Test name
Test status
Simulation time 15772493 ps
CPU time 0.73 seconds
Started Mar 10 01:51:21 PM PDT 24
Finished Mar 10 01:51:22 PM PDT 24
Peak memory 204892 kb
Host smart-71238248-6412-4c95-a653-b6e28d1e0be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817597823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.817597823
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4019572995
Short name T1249
Test name
Test status
Simulation time 522615573 ps
CPU time 8.18 seconds
Started Mar 10 01:51:21 PM PDT 24
Finished Mar 10 01:51:30 PM PDT 24
Peak memory 217340 kb
Host smart-a2483b6f-8d68-46bd-9f41-772f5ad22811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019572995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4019572995
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_upload.611054092
Short name T931
Test name
Test status
Simulation time 1480511083 ps
CPU time 7.7 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:48:17 PM PDT 24
Peak memory 223524 kb
Host smart-3e4d4001-f8ea-46f1-bf03-d63f827058ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611054092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.611054092
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1638597409
Short name T72
Test name
Test status
Simulation time 80760740 ps
CPU time 0.71 seconds
Started Mar 10 02:48:15 PM PDT 24
Finished Mar 10 02:48:15 PM PDT 24
Peak memory 204456 kb
Host smart-51411c0e-1ccb-4371-badd-2eb6a8659511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638597409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1638597409
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2968170374
Short name T585
Test name
Test status
Simulation time 15616427 ps
CPU time 0.68 seconds
Started Mar 10 01:51:31 PM PDT 24
Finished Mar 10 01:51:32 PM PDT 24
Peak memory 203848 kb
Host smart-60a9e3a2-ad2b-4c9a-8006-c48b85109d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968170374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2968170374
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1535984283
Short name T1348
Test name
Test status
Simulation time 625999151 ps
CPU time 3.58 seconds
Started Mar 10 02:48:11 PM PDT 24
Finished Mar 10 02:48:15 PM PDT 24
Peak memory 236784 kb
Host smart-7ccbe81f-7ee8-48e1-a967-9fc6946cee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535984283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1535984283
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.875732471
Short name T1853
Test name
Test status
Simulation time 108924154207 ps
CPU time 20.88 seconds
Started Mar 10 01:51:27 PM PDT 24
Finished Mar 10 01:51:48 PM PDT 24
Peak memory 223900 kb
Host smart-a5fa7ebe-bc90-4fd2-b298-422dcfa9e4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875732471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.875732471
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2943560402
Short name T716
Test name
Test status
Simulation time 22309789 ps
CPU time 0.79 seconds
Started Mar 10 01:51:24 PM PDT 24
Finished Mar 10 01:51:24 PM PDT 24
Peak memory 205540 kb
Host smart-eaa58a4f-b26b-4e24-b0ed-d079ec96f990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943560402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2943560402
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3202808181
Short name T1914
Test name
Test status
Simulation time 14907692 ps
CPU time 0.76 seconds
Started Mar 10 02:48:08 PM PDT 24
Finished Mar 10 02:48:08 PM PDT 24
Peak memory 205504 kb
Host smart-136e32e5-02dd-4029-8593-cb47e1047d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202808181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3202808181
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2735081322
Short name T1481
Test name
Test status
Simulation time 227691479082 ps
CPU time 261.72 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:52:32 PM PDT 24
Peak memory 256524 kb
Host smart-52c36204-d896-48dc-a9e6-9c13489c6df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735081322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2735081322
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3722718891
Short name T1682
Test name
Test status
Simulation time 11232018255 ps
CPU time 49.81 seconds
Started Mar 10 01:51:26 PM PDT 24
Finished Mar 10 01:52:15 PM PDT 24
Peak memory 239808 kb
Host smart-80803cbd-be15-4692-9ce4-38be4a0b325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722718891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3722718891
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1459106390
Short name T215
Test name
Test status
Simulation time 304115052398 ps
CPU time 566.67 seconds
Started Mar 10 02:48:12 PM PDT 24
Finished Mar 10 02:57:39 PM PDT 24
Peak memory 254092 kb
Host smart-f1a33995-8bae-4706-b718-2b5d5da38fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459106390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1459106390
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2837584816
Short name T199
Test name
Test status
Simulation time 27714315462 ps
CPU time 135.99 seconds
Started Mar 10 01:51:30 PM PDT 24
Finished Mar 10 01:53:46 PM PDT 24
Peak memory 265012 kb
Host smart-20763db5-6e0c-4dca-94f1-397715d05991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837584816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2837584816
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2070532554
Short name T389
Test name
Test status
Simulation time 5134047383 ps
CPU time 97.49 seconds
Started Mar 10 01:51:24 PM PDT 24
Finished Mar 10 01:53:02 PM PDT 24
Peak memory 261392 kb
Host smart-649a0ca5-6276-447d-afac-c0995b8335de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070532554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2070532554
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3957212598
Short name T1362
Test name
Test status
Simulation time 71754972959 ps
CPU time 123.07 seconds
Started Mar 10 02:48:14 PM PDT 24
Finished Mar 10 02:50:18 PM PDT 24
Peak memory 248768 kb
Host smart-b782e19f-c141-4bad-bd29-f9aa312ec30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957212598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3957212598
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.732875625
Short name T1275
Test name
Test status
Simulation time 4374920970 ps
CPU time 19.69 seconds
Started Mar 10 01:51:25 PM PDT 24
Finished Mar 10 01:51:44 PM PDT 24
Peak memory 248368 kb
Host smart-04e6de64-2ff9-4416-bd48-4bc862460ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732875625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.732875625
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.791145718
Short name T799
Test name
Test status
Simulation time 676311322 ps
CPU time 9.18 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:48:19 PM PDT 24
Peak memory 232904 kb
Host smart-82e04df4-8208-45ec-95f8-cb275b888063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791145718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.791145718
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3307174609
Short name T1073
Test name
Test status
Simulation time 1342057018 ps
CPU time 6.8 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:48:17 PM PDT 24
Peak memory 217160 kb
Host smart-dc5098b3-3f5a-44f1-abbe-53961f61c129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307174609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3307174609
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3371032905
Short name T1588
Test name
Test status
Simulation time 823563023 ps
CPU time 4.84 seconds
Started Mar 10 01:51:25 PM PDT 24
Finished Mar 10 01:51:30 PM PDT 24
Peak memory 233020 kb
Host smart-3d1c0b9c-5212-44b3-8abd-2926bf71a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371032905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3371032905
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2217621280
Short name T157
Test name
Test status
Simulation time 183739103062 ps
CPU time 62.58 seconds
Started Mar 10 02:48:11 PM PDT 24
Finished Mar 10 02:49:13 PM PDT 24
Peak memory 248940 kb
Host smart-0108dfe3-187b-4af1-b623-8c02fb9f2af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217621280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2217621280
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.878174405
Short name T477
Test name
Test status
Simulation time 35942429652 ps
CPU time 28.11 seconds
Started Mar 10 01:51:26 PM PDT 24
Finished Mar 10 01:51:55 PM PDT 24
Peak memory 244708 kb
Host smart-e2742afc-b726-408c-a4a3-2a8c9a29f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878174405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.878174405
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1733484684
Short name T796
Test name
Test status
Simulation time 1860208071 ps
CPU time 9.25 seconds
Started Mar 10 01:51:27 PM PDT 24
Finished Mar 10 01:51:36 PM PDT 24
Peak memory 232516 kb
Host smart-cbff3941-b3e3-48b3-b190-ebffcf845364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733484684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1733484684
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2399721995
Short name T999
Test name
Test status
Simulation time 1067943404 ps
CPU time 4.82 seconds
Started Mar 10 02:48:08 PM PDT 24
Finished Mar 10 02:48:13 PM PDT 24
Peak memory 232664 kb
Host smart-9100d4fa-1029-4f91-86de-1aacd4de2f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399721995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2399721995
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2947482714
Short name T746
Test name
Test status
Simulation time 802396543 ps
CPU time 2.44 seconds
Started Mar 10 01:51:27 PM PDT 24
Finished Mar 10 01:51:29 PM PDT 24
Peak memory 223832 kb
Host smart-84f64577-dd51-4aef-8905-9169e71f8424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947482714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2947482714
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3815266157
Short name T224
Test name
Test status
Simulation time 80528011 ps
CPU time 2.47 seconds
Started Mar 10 02:48:11 PM PDT 24
Finished Mar 10 02:48:13 PM PDT 24
Peak memory 232952 kb
Host smart-207c10c8-54b2-4ff7-97b7-da36213947fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815266157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3815266157
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1816894525
Short name T414
Test name
Test status
Simulation time 446440860 ps
CPU time 5.11 seconds
Started Mar 10 01:51:27 PM PDT 24
Finished Mar 10 01:51:33 PM PDT 24
Peak memory 221612 kb
Host smart-3c54ceba-ae8d-4f0b-b198-b6da68711e80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1816894525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1816894525
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4257015049
Short name T565
Test name
Test status
Simulation time 204642426 ps
CPU time 3.52 seconds
Started Mar 10 02:48:14 PM PDT 24
Finished Mar 10 02:48:17 PM PDT 24
Peak memory 216012 kb
Host smart-570d22a8-e592-4523-8066-6009f7f24136
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4257015049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4257015049
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.428853083
Short name T165
Test name
Test status
Simulation time 93642798044 ps
CPU time 674.34 seconds
Started Mar 10 01:51:24 PM PDT 24
Finished Mar 10 02:02:38 PM PDT 24
Peak memory 286832 kb
Host smart-828c759f-bba8-4fea-a0f9-70e97dddb7cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428853083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.428853083
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.682265184
Short name T1528
Test name
Test status
Simulation time 73091368605 ps
CPU time 415.98 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:55:06 PM PDT 24
Peak memory 264252 kb
Host smart-2a1b82d2-0711-4eef-b0fb-d2e2429c062d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682265184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.682265184
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3557050447
Short name T1234
Test name
Test status
Simulation time 7069691462 ps
CPU time 30.63 seconds
Started Mar 10 02:48:12 PM PDT 24
Finished Mar 10 02:48:43 PM PDT 24
Peak memory 215964 kb
Host smart-c5bb2652-5f38-494b-a2d2-cf87594a71dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557050447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3557050447
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4258997545
Short name T1358
Test name
Test status
Simulation time 13996738334 ps
CPU time 71.67 seconds
Started Mar 10 01:51:24 PM PDT 24
Finished Mar 10 01:52:36 PM PDT 24
Peak memory 215816 kb
Host smart-2eb15737-debc-4547-8bc6-73986af3fab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258997545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4258997545
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1110215116
Short name T1292
Test name
Test status
Simulation time 3306698260 ps
CPU time 11.14 seconds
Started Mar 10 02:48:12 PM PDT 24
Finished Mar 10 02:48:24 PM PDT 24
Peak memory 215728 kb
Host smart-c1f3d823-dd5e-4846-a448-8c9eea9dbf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110215116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1110215116
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2432503634
Short name T438
Test name
Test status
Simulation time 1564384621 ps
CPU time 6.91 seconds
Started Mar 10 01:51:24 PM PDT 24
Finished Mar 10 01:51:31 PM PDT 24
Peak memory 215736 kb
Host smart-0c5dc512-4f51-4c72-b5d4-69402d81b442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432503634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2432503634
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2042875160
Short name T1062
Test name
Test status
Simulation time 320008368 ps
CPU time 7.99 seconds
Started Mar 10 01:51:25 PM PDT 24
Finished Mar 10 01:51:33 PM PDT 24
Peak memory 215928 kb
Host smart-eafd0ef9-a334-4942-a67f-a5999b251983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042875160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2042875160
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.988286360
Short name T1301
Test name
Test status
Simulation time 13287363 ps
CPU time 0.81 seconds
Started Mar 10 02:48:12 PM PDT 24
Finished Mar 10 02:48:13 PM PDT 24
Peak memory 204836 kb
Host smart-f7d33697-4d3c-46b2-b58b-46d54b9a989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988286360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.988286360
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3355718300
Short name T601
Test name
Test status
Simulation time 25711490 ps
CPU time 0.73 seconds
Started Mar 10 02:48:09 PM PDT 24
Finished Mar 10 02:48:10 PM PDT 24
Peak memory 204896 kb
Host smart-06bfb8a3-b29c-4b3f-809d-015be53c9ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355718300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3355718300
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.4123982498
Short name T733
Test name
Test status
Simulation time 16081994 ps
CPU time 0.71 seconds
Started Mar 10 01:51:24 PM PDT 24
Finished Mar 10 01:51:25 PM PDT 24
Peak memory 204836 kb
Host smart-d31c5ab6-df30-47fd-a6f7-096d7c67b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123982498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4123982498
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2494056945
Short name T1640
Test name
Test status
Simulation time 210325165 ps
CPU time 2.59 seconds
Started Mar 10 01:51:25 PM PDT 24
Finished Mar 10 01:51:28 PM PDT 24
Peak memory 215696 kb
Host smart-29afb6f4-534a-45b0-b7c4-bfbdf1a3e331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494056945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2494056945
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_upload.3471747524
Short name T1502
Test name
Test status
Simulation time 593288260 ps
CPU time 4.61 seconds
Started Mar 10 02:48:11 PM PDT 24
Finished Mar 10 02:48:16 PM PDT 24
Peak memory 217456 kb
Host smart-4e497d28-e4e7-471b-bef9-cdfad9529c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471747524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3471747524
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1962299384
Short name T834
Test name
Test status
Simulation time 26453960 ps
CPU time 0.69 seconds
Started Mar 10 02:48:18 PM PDT 24
Finished Mar 10 02:48:19 PM PDT 24
Peak memory 204760 kb
Host smart-3bd1f5da-a18d-451e-811f-0a301b288917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962299384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1962299384
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3439046415
Short name T1655
Test name
Test status
Simulation time 49978633 ps
CPU time 0.71 seconds
Started Mar 10 01:51:30 PM PDT 24
Finished Mar 10 01:51:30 PM PDT 24
Peak memory 203820 kb
Host smart-6449d0d3-a3da-4573-8aee-89db3068b581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439046415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3439046415
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1956059811
Short name T754
Test name
Test status
Simulation time 43271159 ps
CPU time 2.61 seconds
Started Mar 10 02:48:15 PM PDT 24
Finished Mar 10 02:48:19 PM PDT 24
Peak memory 232712 kb
Host smart-db6cf9d7-385a-4def-9fe0-248c1b7eccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956059811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1956059811
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3211999999
Short name T1129
Test name
Test status
Simulation time 495966700 ps
CPU time 3.43 seconds
Started Mar 10 01:51:30 PM PDT 24
Finished Mar 10 01:51:34 PM PDT 24
Peak memory 216716 kb
Host smart-5748d5eb-cdc2-47f2-861f-4ff0ada7db2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211999999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3211999999
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2712038249
Short name T1218
Test name
Test status
Simulation time 21236978 ps
CPU time 0.83 seconds
Started Mar 10 02:48:09 PM PDT 24
Finished Mar 10 02:48:10 PM PDT 24
Peak memory 205516 kb
Host smart-c69db8ad-569a-479a-bb22-9f1d8b9e952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712038249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2712038249
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.926276751
Short name T1653
Test name
Test status
Simulation time 31013629 ps
CPU time 0.75 seconds
Started Mar 10 01:51:29 PM PDT 24
Finished Mar 10 01:51:30 PM PDT 24
Peak memory 204820 kb
Host smart-59c687fc-62b8-42b3-a0f5-f3205e118ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926276751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.926276751
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2650776166
Short name T1536
Test name
Test status
Simulation time 75674174655 ps
CPU time 93.6 seconds
Started Mar 10 02:48:15 PM PDT 24
Finished Mar 10 02:49:50 PM PDT 24
Peak memory 235280 kb
Host smart-49ea0f4d-ca97-4054-b758-d34204c8de98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650776166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2650776166
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3952486983
Short name T1213
Test name
Test status
Simulation time 493125026116 ps
CPU time 236.03 seconds
Started Mar 10 01:51:31 PM PDT 24
Finished Mar 10 01:55:27 PM PDT 24
Peak memory 253248 kb
Host smart-cfadfc97-4dd0-4612-a75c-742c6595a5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952486983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3952486983
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.183415943
Short name T789
Test name
Test status
Simulation time 2097760252 ps
CPU time 13.57 seconds
Started Mar 10 01:51:29 PM PDT 24
Finished Mar 10 01:51:43 PM PDT 24
Peak memory 239832 kb
Host smart-34948dd6-7cba-4004-96d7-7055174f8a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183415943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.183415943
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.5959904
Short name T554
Test name
Test status
Simulation time 24491347933 ps
CPU time 82.83 seconds
Started Mar 10 02:48:13 PM PDT 24
Finished Mar 10 02:49:36 PM PDT 24
Peak memory 237056 kb
Host smart-69e2b745-7c77-45ee-98dd-6acb51e8f34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5959904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.5959904
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1349330864
Short name T137
Test name
Test status
Simulation time 25519863486 ps
CPU time 184.49 seconds
Started Mar 10 01:51:32 PM PDT 24
Finished Mar 10 01:54:36 PM PDT 24
Peak memory 256804 kb
Host smart-85ee6198-18be-47d0-9aa4-1184ff80b7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349330864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1349330864
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3634040044
Short name T1456
Test name
Test status
Simulation time 36131794801 ps
CPU time 150.09 seconds
Started Mar 10 02:48:21 PM PDT 24
Finished Mar 10 02:50:52 PM PDT 24
Peak memory 252532 kb
Host smart-02bf3bfc-f78c-4f25-af43-27349694fe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634040044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3634040044
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1273550225
Short name T1438
Test name
Test status
Simulation time 528663227 ps
CPU time 8.79 seconds
Started Mar 10 02:48:16 PM PDT 24
Finished Mar 10 02:48:26 PM PDT 24
Peak memory 234784 kb
Host smart-3a859ce4-caee-4b9d-8e72-d43deb743d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273550225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1273550225
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1454232651
Short name T1101
Test name
Test status
Simulation time 18548266212 ps
CPU time 30.79 seconds
Started Mar 10 01:51:28 PM PDT 24
Finished Mar 10 01:51:59 PM PDT 24
Peak memory 236700 kb
Host smart-4a47b3ee-3b37-4390-8f13-fdf5edc3bdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454232651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1454232651
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2906070832
Short name T421
Test name
Test status
Simulation time 426116809 ps
CPU time 4.17 seconds
Started Mar 10 01:51:30 PM PDT 24
Finished Mar 10 01:51:35 PM PDT 24
Peak memory 233004 kb
Host smart-fca3d562-9680-4afb-8b48-2b64ea178b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906070832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2906070832
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3646210832
Short name T1684
Test name
Test status
Simulation time 659348252 ps
CPU time 2.77 seconds
Started Mar 10 02:48:11 PM PDT 24
Finished Mar 10 02:48:14 PM PDT 24
Peak memory 232796 kb
Host smart-01b60d56-a979-44f2-b70f-be945a33a48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646210832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3646210832
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2921596351
Short name T1874
Test name
Test status
Simulation time 2595472556 ps
CPU time 12.41 seconds
Started Mar 10 02:48:15 PM PDT 24
Finished Mar 10 02:48:28 PM PDT 24
Peak memory 217496 kb
Host smart-546f7920-e37b-4412-883d-19932ef9cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921596351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2921596351
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.96219315
Short name T581
Test name
Test status
Simulation time 1002698833 ps
CPU time 5.34 seconds
Started Mar 10 01:51:31 PM PDT 24
Finished Mar 10 01:51:36 PM PDT 24
Peak memory 223820 kb
Host smart-cf79573c-15a2-45b3-affc-0485c6a9d347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96219315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.96219315
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3429219108
Short name T692
Test name
Test status
Simulation time 1018090493 ps
CPU time 3.69 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:48:14 PM PDT 24
Peak memory 217108 kb
Host smart-d3a25d3e-b002-404a-8826-b4fd36794b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429219108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3429219108
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3913480018
Short name T827
Test name
Test status
Simulation time 4384037064 ps
CPU time 5.23 seconds
Started Mar 10 01:51:31 PM PDT 24
Finished Mar 10 01:51:36 PM PDT 24
Peak memory 216248 kb
Host smart-c10c09ba-65b7-46db-9465-70cb2893854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913480018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3913480018
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2902098335
Short name T1672
Test name
Test status
Simulation time 482744114 ps
CPU time 7.42 seconds
Started Mar 10 02:48:11 PM PDT 24
Finished Mar 10 02:48:18 PM PDT 24
Peak memory 232020 kb
Host smart-d98b61fe-f13e-460a-95f1-f2e547696403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902098335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2902098335
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.35882242
Short name T1483
Test name
Test status
Simulation time 8913253428 ps
CPU time 5.17 seconds
Started Mar 10 01:51:31 PM PDT 24
Finished Mar 10 01:51:36 PM PDT 24
Peak memory 215968 kb
Host smart-8d3511f3-6ce5-461e-9cde-8f44f55f5d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35882242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.35882242
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3259437148
Short name T415
Test name
Test status
Simulation time 539974181 ps
CPU time 3.91 seconds
Started Mar 10 02:48:18 PM PDT 24
Finished Mar 10 02:48:22 PM PDT 24
Peak memory 222000 kb
Host smart-21a80fa0-a99d-42b7-9dfc-58cce7f87a9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3259437148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3259437148
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4080180775
Short name T816
Test name
Test status
Simulation time 1178115714 ps
CPU time 4.28 seconds
Started Mar 10 01:51:28 PM PDT 24
Finished Mar 10 01:51:33 PM PDT 24
Peak memory 221916 kb
Host smart-358c33be-a055-4913-a564-f4508dd74dc0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4080180775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4080180775
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1199066308
Short name T1831
Test name
Test status
Simulation time 195736052262 ps
CPU time 325.72 seconds
Started Mar 10 02:48:16 PM PDT 24
Finished Mar 10 02:53:42 PM PDT 24
Peak memory 271508 kb
Host smart-291f8287-a4dd-4477-850a-6c417b2f7dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199066308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1199066308
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1674957900
Short name T1283
Test name
Test status
Simulation time 5453514261 ps
CPU time 74.28 seconds
Started Mar 10 01:51:32 PM PDT 24
Finished Mar 10 01:52:46 PM PDT 24
Peak memory 265000 kb
Host smart-1f29842c-19dc-4a71-844f-d3bdd2ea7db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674957900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1674957900
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1536106363
Short name T322
Test name
Test status
Simulation time 30816004839 ps
CPU time 47.87 seconds
Started Mar 10 02:48:08 PM PDT 24
Finished Mar 10 02:48:56 PM PDT 24
Peak memory 215772 kb
Host smart-e97c1342-caa1-4249-8694-216b0637499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536106363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1536106363
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3657455344
Short name T163
Test name
Test status
Simulation time 10792001686 ps
CPU time 24.42 seconds
Started Mar 10 01:51:29 PM PDT 24
Finished Mar 10 01:51:53 PM PDT 24
Peak memory 215704 kb
Host smart-fb8b9d44-ec8a-44c6-891b-91fab45a8b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657455344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3657455344
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1607225262
Short name T1618
Test name
Test status
Simulation time 3727330935 ps
CPU time 11.23 seconds
Started Mar 10 01:51:29 PM PDT 24
Finished Mar 10 01:51:40 PM PDT 24
Peak memory 215796 kb
Host smart-576255b4-f23a-460e-ab97-890d584a2a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607225262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1607225262
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1791136895
Short name T1001
Test name
Test status
Simulation time 23523796890 ps
CPU time 21.97 seconds
Started Mar 10 02:48:10 PM PDT 24
Finished Mar 10 02:48:32 PM PDT 24
Peak memory 215792 kb
Host smart-76b3799b-5d70-4bde-a6a3-76f531f6c977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791136895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1791136895
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.278216149
Short name T1217
Test name
Test status
Simulation time 507268673 ps
CPU time 4.21 seconds
Started Mar 10 02:48:15 PM PDT 24
Finished Mar 10 02:48:19 PM PDT 24
Peak memory 215740 kb
Host smart-53b803f0-135d-464c-8027-201b61ef10af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278216149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.278216149
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3840900432
Short name T392
Test name
Test status
Simulation time 676702274 ps
CPU time 2.71 seconds
Started Mar 10 01:51:28 PM PDT 24
Finished Mar 10 01:51:31 PM PDT 24
Peak memory 215712 kb
Host smart-4cfba21f-45d0-4fd6-bbba-be816b84391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840900432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3840900432
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2383514053
Short name T798
Test name
Test status
Simulation time 126323301 ps
CPU time 0.88 seconds
Started Mar 10 02:48:15 PM PDT 24
Finished Mar 10 02:48:16 PM PDT 24
Peak memory 205368 kb
Host smart-1ef86797-8ae4-44f7-910d-800ba3d4fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383514053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2383514053
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3089288395
Short name T1838
Test name
Test status
Simulation time 15675939 ps
CPU time 0.72 seconds
Started Mar 10 01:51:29 PM PDT 24
Finished Mar 10 01:51:30 PM PDT 24
Peak memory 204868 kb
Host smart-f2fd9d51-decc-436d-9eec-182f73f4788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089288395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3089288395
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.112252668
Short name T1551
Test name
Test status
Simulation time 2468282549 ps
CPU time 7.03 seconds
Started Mar 10 02:48:18 PM PDT 24
Finished Mar 10 02:48:26 PM PDT 24
Peak memory 232908 kb
Host smart-5405d1b2-fb8f-467e-9e8b-47b55bbfd839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112252668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.112252668
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_upload.189637389
Short name T1717
Test name
Test status
Simulation time 1954248062 ps
CPU time 11.52 seconds
Started Mar 10 01:51:30 PM PDT 24
Finished Mar 10 01:51:42 PM PDT 24
Peak memory 239000 kb
Host smart-a25213c9-6620-4fda-b2cb-1a4c676f5df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189637389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.189637389
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3368161354
Short name T1817
Test name
Test status
Simulation time 24281130 ps
CPU time 0.72 seconds
Started Mar 10 02:48:20 PM PDT 24
Finished Mar 10 02:48:21 PM PDT 24
Peak memory 204448 kb
Host smart-748ccc79-b20a-4470-8fbb-b4dedadef500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368161354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3368161354
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.401582010
Short name T1499
Test name
Test status
Simulation time 108959026 ps
CPU time 0.73 seconds
Started Mar 10 01:51:40 PM PDT 24
Finished Mar 10 01:51:41 PM PDT 24
Peak memory 204424 kb
Host smart-6369b591-6064-4e33-924d-25acba4b7b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401582010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.401582010
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1419329550
Short name T1350
Test name
Test status
Simulation time 428716432 ps
CPU time 2.78 seconds
Started Mar 10 01:51:34 PM PDT 24
Finished Mar 10 01:51:37 PM PDT 24
Peak memory 223800 kb
Host smart-4acbf730-4467-47b2-af28-17b0e20757ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419329550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1419329550
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.907348228
Short name T1176
Test name
Test status
Simulation time 325863004 ps
CPU time 2.91 seconds
Started Mar 10 02:48:20 PM PDT 24
Finished Mar 10 02:48:23 PM PDT 24
Peak memory 232968 kb
Host smart-805b7d9d-c9df-47a1-b790-1c15376cf328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907348228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.907348228
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1464136338
Short name T1896
Test name
Test status
Simulation time 20789260 ps
CPU time 0.79 seconds
Started Mar 10 01:51:33 PM PDT 24
Finished Mar 10 01:51:35 PM PDT 24
Peak memory 205480 kb
Host smart-067e79db-38a2-4863-952a-bb46c5cb131f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464136338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1464136338
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2250240596
Short name T1137
Test name
Test status
Simulation time 16048892 ps
CPU time 0.8 seconds
Started Mar 10 02:48:17 PM PDT 24
Finished Mar 10 02:48:19 PM PDT 24
Peak memory 204828 kb
Host smart-8a1f0218-4fa7-4012-a721-e88525f2d6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250240596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2250240596
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1414684511
Short name T779
Test name
Test status
Simulation time 7297021681 ps
CPU time 62.67 seconds
Started Mar 10 01:51:33 PM PDT 24
Finished Mar 10 01:52:36 PM PDT 24
Peak memory 254652 kb
Host smart-01626696-9856-4713-9243-dbe6651f8e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414684511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1414684511
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1590369291
Short name T1912
Test name
Test status
Simulation time 6692039377 ps
CPU time 33.98 seconds
Started Mar 10 02:48:22 PM PDT 24
Finished Mar 10 02:48:56 PM PDT 24
Peak memory 236204 kb
Host smart-05b8db27-0e2f-401e-b3f1-f4370a9a329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590369291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1590369291
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3464397270
Short name T1365
Test name
Test status
Simulation time 9222754487 ps
CPU time 80.39 seconds
Started Mar 10 02:48:22 PM PDT 24
Finished Mar 10 02:49:43 PM PDT 24
Peak memory 258428 kb
Host smart-41839c07-9384-446b-9faa-91577540bf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464397270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3464397270
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3934673259
Short name T643
Test name
Test status
Simulation time 22619728284 ps
CPU time 148.84 seconds
Started Mar 10 01:51:34 PM PDT 24
Finished Mar 10 01:54:03 PM PDT 24
Peak memory 248696 kb
Host smart-68bd6df7-1a13-49a7-bc61-4462ce15aa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934673259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3934673259
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3810453785
Short name T1562
Test name
Test status
Simulation time 862433245531 ps
CPU time 645.01 seconds
Started Mar 10 02:48:22 PM PDT 24
Finished Mar 10 02:59:07 PM PDT 24
Peak memory 282540 kb
Host smart-96dee78d-0ee8-4b14-b8e8-d8a4d9abd37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810453785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3810453785
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1001396594
Short name T790
Test name
Test status
Simulation time 2477518703 ps
CPU time 20.97 seconds
Started Mar 10 02:48:22 PM PDT 24
Finished Mar 10 02:48:43 PM PDT 24
Peak memory 235888 kb
Host smart-d832987b-cb49-4254-bc24-ebdefe68e0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001396594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1001396594
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1944635507
Short name T1858
Test name
Test status
Simulation time 5042676485 ps
CPU time 25.46 seconds
Started Mar 10 01:51:33 PM PDT 24
Finished Mar 10 01:51:59 PM PDT 24
Peak memory 233924 kb
Host smart-ab958c8c-855b-4e12-80df-402eadb32481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944635507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1944635507
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1036286640
Short name T1412
Test name
Test status
Simulation time 679945342 ps
CPU time 4.2 seconds
Started Mar 10 01:51:32 PM PDT 24
Finished Mar 10 01:51:36 PM PDT 24
Peak memory 218200 kb
Host smart-42bcc88c-9af3-4384-b8e1-3e5e923c534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036286640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1036286640
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1197471570
Short name T1449
Test name
Test status
Simulation time 65450569 ps
CPU time 2.64 seconds
Started Mar 10 02:48:14 PM PDT 24
Finished Mar 10 02:48:17 PM PDT 24
Peak memory 232092 kb
Host smart-25d8c46b-d2c0-4126-9bc7-a5eee70694db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197471570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1197471570
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1068101999
Short name T583
Test name
Test status
Simulation time 21938139292 ps
CPU time 27.7 seconds
Started Mar 10 01:51:35 PM PDT 24
Finished Mar 10 01:52:03 PM PDT 24
Peak memory 231208 kb
Host smart-cec02006-3e3d-4e25-990e-f758ba20276f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068101999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1068101999
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2517592414
Short name T1676
Test name
Test status
Simulation time 3870431450 ps
CPU time 5.68 seconds
Started Mar 10 02:48:16 PM PDT 24
Finished Mar 10 02:48:23 PM PDT 24
Peak memory 217364 kb
Host smart-41e9d2e1-b6fc-4c74-b046-b98773c2c96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517592414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2517592414
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2059910689
Short name T837
Test name
Test status
Simulation time 11168588892 ps
CPU time 21.82 seconds
Started Mar 10 02:48:14 PM PDT 24
Finished Mar 10 02:48:36 PM PDT 24
Peak memory 239744 kb
Host smart-d3ac3639-ea4f-4efe-b1cf-a5fb8b201ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059910689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2059910689
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2796217342
Short name T522
Test name
Test status
Simulation time 150661542 ps
CPU time 3.29 seconds
Started Mar 10 01:51:31 PM PDT 24
Finished Mar 10 01:51:34 PM PDT 24
Peak memory 232624 kb
Host smart-43815388-bdf0-4ca0-a390-2014cb1ccc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796217342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2796217342
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.182096198
Short name T760
Test name
Test status
Simulation time 5528695007 ps
CPU time 15.02 seconds
Started Mar 10 02:48:19 PM PDT 24
Finished Mar 10 02:48:35 PM PDT 24
Peak memory 235728 kb
Host smart-28ea2da1-3ee6-418d-9289-4ac23b4139a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182096198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.182096198
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.575116767
Short name T1575
Test name
Test status
Simulation time 5476007733 ps
CPU time 8.29 seconds
Started Mar 10 01:51:32 PM PDT 24
Finished Mar 10 01:51:40 PM PDT 24
Peak memory 233108 kb
Host smart-d717cec4-7d65-43fa-ac97-5cc0e5068456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575116767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.575116767
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.33677147
Short name T1159
Test name
Test status
Simulation time 361376678 ps
CPU time 3.91 seconds
Started Mar 10 01:51:33 PM PDT 24
Finished Mar 10 01:51:38 PM PDT 24
Peak memory 221480 kb
Host smart-5276e85c-bedb-46be-9cce-d86d94c00ee5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=33677147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.33677147
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4267876564
Short name T634
Test name
Test status
Simulation time 705483124 ps
CPU time 4.06 seconds
Started Mar 10 02:48:20 PM PDT 24
Finished Mar 10 02:48:24 PM PDT 24
Peak memory 217940 kb
Host smart-5e82a475-6608-4748-9ae6-056598e980ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4267876564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4267876564
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1398831551
Short name T1498
Test name
Test status
Simulation time 18641753901 ps
CPU time 116.98 seconds
Started Mar 10 02:48:20 PM PDT 24
Finished Mar 10 02:50:19 PM PDT 24
Peak memory 255236 kb
Host smart-e7644879-33f2-4abe-ac66-5d6aa9328b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398831551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1398831551
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3160525571
Short name T1013
Test name
Test status
Simulation time 23461974590 ps
CPU time 136.7 seconds
Started Mar 10 01:51:39 PM PDT 24
Finished Mar 10 01:53:56 PM PDT 24
Peak memory 250116 kb
Host smart-e7c3e60b-12d5-43ce-b826-78e1d8681bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160525571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3160525571
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1827023963
Short name T1206
Test name
Test status
Simulation time 2451820072 ps
CPU time 13.46 seconds
Started Mar 10 02:48:16 PM PDT 24
Finished Mar 10 02:48:30 PM PDT 24
Peak memory 215776 kb
Host smart-fd5841b2-4261-45c2-b6e5-0ab40801965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827023963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1827023963
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3043278979
Short name T424
Test name
Test status
Simulation time 1539974519 ps
CPU time 13.92 seconds
Started Mar 10 01:51:33 PM PDT 24
Finished Mar 10 01:51:47 PM PDT 24
Peak memory 215748 kb
Host smart-47b143e2-63b5-40dc-8130-694bfbfadc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043278979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3043278979
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3521432424
Short name T1470
Test name
Test status
Simulation time 4127549970 ps
CPU time 14.8 seconds
Started Mar 10 01:51:32 PM PDT 24
Finished Mar 10 01:51:47 PM PDT 24
Peak memory 216120 kb
Host smart-97c7cad7-bcca-4f3b-ac09-65c99cac05d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521432424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3521432424
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.646967322
Short name T511
Test name
Test status
Simulation time 1574222929 ps
CPU time 8.81 seconds
Started Mar 10 02:48:16 PM PDT 24
Finished Mar 10 02:48:25 PM PDT 24
Peak memory 207612 kb
Host smart-a234872b-6d5f-4499-8ee4-23a8dd6f60b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646967322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.646967322
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1030791193
Short name T863
Test name
Test status
Simulation time 144987638 ps
CPU time 3.1 seconds
Started Mar 10 02:48:13 PM PDT 24
Finished Mar 10 02:48:16 PM PDT 24
Peak memory 215756 kb
Host smart-c70d0cd0-c5bd-4e0f-8ceb-64abbb7ee702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030791193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1030791193
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3136932983
Short name T1612
Test name
Test status
Simulation time 14396930 ps
CPU time 0.77 seconds
Started Mar 10 01:51:30 PM PDT 24
Finished Mar 10 01:51:31 PM PDT 24
Peak memory 204860 kb
Host smart-2671c44d-fa3e-4ee3-8d98-3f975725933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136932983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3136932983
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2496935680
Short name T965
Test name
Test status
Simulation time 149674467 ps
CPU time 0.97 seconds
Started Mar 10 01:51:31 PM PDT 24
Finished Mar 10 01:51:33 PM PDT 24
Peak memory 204912 kb
Host smart-38254467-de99-4dae-970f-e93facc4d230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496935680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2496935680
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2985226241
Short name T868
Test name
Test status
Simulation time 52274012 ps
CPU time 0.97 seconds
Started Mar 10 02:48:18 PM PDT 24
Finished Mar 10 02:48:20 PM PDT 24
Peak memory 205852 kb
Host smart-36ab58e7-eccc-4f08-a5b9-ad92ee72d6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985226241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2985226241
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1597038071
Short name T1646
Test name
Test status
Simulation time 1694557240 ps
CPU time 5.9 seconds
Started Mar 10 01:51:35 PM PDT 24
Finished Mar 10 01:51:41 PM PDT 24
Peak memory 236884 kb
Host smart-ef23136b-c702-4980-a743-6050a1b6c016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597038071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1597038071
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_upload.2739228952
Short name T539
Test name
Test status
Simulation time 1197331340 ps
CPU time 4.33 seconds
Started Mar 10 02:48:18 PM PDT 24
Finished Mar 10 02:48:24 PM PDT 24
Peak memory 217912 kb
Host smart-12a56417-fd12-427d-a7ef-6ec41c902de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739228952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2739228952
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2162590144
Short name T536
Test name
Test status
Simulation time 146108573 ps
CPU time 0.72 seconds
Started Mar 10 02:48:18 PM PDT 24
Finished Mar 10 02:48:19 PM PDT 24
Peak memory 203860 kb
Host smart-11f184e2-dadf-4563-b390-d89ce016ce67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162590144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2162590144
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4205846530
Short name T757
Test name
Test status
Simulation time 12328162 ps
CPU time 0.71 seconds
Started Mar 10 01:51:46 PM PDT 24
Finished Mar 10 01:51:46 PM PDT 24
Peak memory 204384 kb
Host smart-1ffba010-9ad3-482a-bed9-f09a5a25bbd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205846530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4205846530
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1764258604
Short name T1086
Test name
Test status
Simulation time 284379445 ps
CPU time 2.43 seconds
Started Mar 10 01:51:40 PM PDT 24
Finished Mar 10 01:51:42 PM PDT 24
Peak memory 217728 kb
Host smart-cb9fcfd8-42c6-45c1-b7bd-2574ac4d7ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764258604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1764258604
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.519817651
Short name T222
Test name
Test status
Simulation time 3321378156 ps
CPU time 4.65 seconds
Started Mar 10 02:48:22 PM PDT 24
Finished Mar 10 02:48:27 PM PDT 24
Peak memory 232908 kb
Host smart-e2afd225-51a1-4eb4-9d90-3a78fc2ec140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519817651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.519817651
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4151268781
Short name T736
Test name
Test status
Simulation time 36029981 ps
CPU time 0.79 seconds
Started Mar 10 02:48:19 PM PDT 24
Finished Mar 10 02:48:21 PM PDT 24
Peak memory 205500 kb
Host smart-4f45c84e-71d0-49d4-982d-44a8ebad67eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151268781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4151268781
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.823587867
Short name T576
Test name
Test status
Simulation time 19650613 ps
CPU time 0.82 seconds
Started Mar 10 01:51:39 PM PDT 24
Finished Mar 10 01:51:40 PM PDT 24
Peak memory 205504 kb
Host smart-9964f6c8-c024-4a72-8745-c0013f02ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823587867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.823587867
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1044960766
Short name T1337
Test name
Test status
Simulation time 21290443538 ps
CPU time 49.31 seconds
Started Mar 10 01:51:38 PM PDT 24
Finished Mar 10 01:52:28 PM PDT 24
Peak memory 252512 kb
Host smart-c90c10bf-d905-4411-a025-e844e051fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044960766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1044960766
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2288548328
Short name T1621
Test name
Test status
Simulation time 1901433313 ps
CPU time 32.95 seconds
Started Mar 10 02:48:19 PM PDT 24
Finished Mar 10 02:48:53 PM PDT 24
Peak memory 248496 kb
Host smart-11aa9388-93d0-4eb7-b4bd-5ff222475b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288548328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2288548328
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3245399420
Short name T1851
Test name
Test status
Simulation time 219114448186 ps
CPU time 281.18 seconds
Started Mar 10 02:48:22 PM PDT 24
Finished Mar 10 02:53:03 PM PDT 24
Peak memory 253400 kb
Host smart-0f03b9fd-c619-472c-a31f-9f7efc54e123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245399420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3245399420
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3702579956
Short name T1418
Test name
Test status
Simulation time 23121238760 ps
CPU time 67.63 seconds
Started Mar 10 01:51:45 PM PDT 24
Finished Mar 10 01:52:53 PM PDT 24
Peak memory 234224 kb
Host smart-6625de18-0679-4ea5-89c2-aa36626fab02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702579956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3702579956
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3444162260
Short name T1108
Test name
Test status
Simulation time 75945338015 ps
CPU time 79.49 seconds
Started Mar 10 02:48:21 PM PDT 24
Finished Mar 10 02:49:42 PM PDT 24
Peak memory 236384 kb
Host smart-12a29b75-1638-4e31-b5f3-57bc2c54a8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444162260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3444162260
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.718723472
Short name T1248
Test name
Test status
Simulation time 110418697057 ps
CPU time 392.75 seconds
Started Mar 10 01:51:44 PM PDT 24
Finished Mar 10 01:58:16 PM PDT 24
Peak memory 256248 kb
Host smart-a656d1f5-d9ed-4daf-95d6-b94bfda0482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718723472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.718723472
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1074441775
Short name T460
Test name
Test status
Simulation time 958297596 ps
CPU time 7.95 seconds
Started Mar 10 02:48:20 PM PDT 24
Finished Mar 10 02:48:30 PM PDT 24
Peak memory 234816 kb
Host smart-bba2445f-8a19-4013-ace4-c81442b0fb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074441775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1074441775
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3456678586
Short name T917
Test name
Test status
Simulation time 121722136 ps
CPU time 3.98 seconds
Started Mar 10 02:48:21 PM PDT 24
Finished Mar 10 02:48:26 PM PDT 24
Peak memory 234316 kb
Host smart-00c03b20-0a8e-4d7b-b844-aff904647de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456678586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3456678586
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4173926967
Short name T492
Test name
Test status
Simulation time 19622594145 ps
CPU time 10.46 seconds
Started Mar 10 01:51:42 PM PDT 24
Finished Mar 10 01:51:52 PM PDT 24
Peak memory 223940 kb
Host smart-34b2a6e7-44ad-4152-8319-b4bbecc1c712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173926967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4173926967
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1896926920
Short name T1298
Test name
Test status
Simulation time 25448004241 ps
CPU time 23.98 seconds
Started Mar 10 02:48:23 PM PDT 24
Finished Mar 10 02:48:47 PM PDT 24
Peak memory 233340 kb
Host smart-b9c93665-260d-4545-ad96-156a337a848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896926920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1896926920
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4232119412
Short name T200
Test name
Test status
Simulation time 9920641709 ps
CPU time 11.98 seconds
Started Mar 10 01:51:40 PM PDT 24
Finished Mar 10 01:51:52 PM PDT 24
Peak memory 234176 kb
Host smart-d413890d-fa2b-408c-ad79-349cb4d9d4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232119412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4232119412
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.222658142
Short name T1679
Test name
Test status
Simulation time 150616410 ps
CPU time 2.58 seconds
Started Mar 10 02:48:21 PM PDT 24
Finished Mar 10 02:48:25 PM PDT 24
Peak memory 232064 kb
Host smart-d6ef4e29-b8c4-4ac3-aa39-571f3a832ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222658142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.222658142
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4184095615
Short name T1518
Test name
Test status
Simulation time 25733615339 ps
CPU time 17.55 seconds
Started Mar 10 01:51:43 PM PDT 24
Finished Mar 10 01:52:01 PM PDT 24
Peak memory 219548 kb
Host smart-7fc34e03-e452-4686-a18f-ff390d9cd322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184095615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4184095615
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2314117647
Short name T167
Test name
Test status
Simulation time 3063409853 ps
CPU time 9.38 seconds
Started Mar 10 02:48:20 PM PDT 24
Finished Mar 10 02:48:31 PM PDT 24
Peak memory 232048 kb
Host smart-2f929a44-85ac-4ed5-b86d-c73ad0ad1632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314117647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2314117647
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2757117975
Short name T326
Test name
Test status
Simulation time 934776946 ps
CPU time 8.77 seconds
Started Mar 10 01:51:38 PM PDT 24
Finished Mar 10 01:51:47 PM PDT 24
Peak memory 246588 kb
Host smart-f65520cd-73ec-4f7d-b9c7-dba68cd7d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757117975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2757117975
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3654563445
Short name T396
Test name
Test status
Simulation time 274271631 ps
CPU time 4.34 seconds
Started Mar 10 01:51:38 PM PDT 24
Finished Mar 10 01:51:43 PM PDT 24
Peak memory 221904 kb
Host smart-f1e1c9ec-1726-497d-895e-a8ef65a792a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654563445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3654563445
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4092821820
Short name T691
Test name
Test status
Simulation time 944143232 ps
CPU time 3.79 seconds
Started Mar 10 02:48:21 PM PDT 24
Finished Mar 10 02:48:26 PM PDT 24
Peak memory 221684 kb
Host smart-7c55068e-f9f2-40ba-962b-9e093d92c870
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4092821820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4092821820
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2785337863
Short name T1873
Test name
Test status
Simulation time 30432582263 ps
CPU time 33.44 seconds
Started Mar 10 01:51:46 PM PDT 24
Finished Mar 10 01:52:19 PM PDT 24
Peak memory 250288 kb
Host smart-1f564d3a-13a6-427b-a7f4-24d638818622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785337863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2785337863
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2987996233
Short name T1674
Test name
Test status
Simulation time 6524009826 ps
CPU time 25.53 seconds
Started Mar 10 01:51:44 PM PDT 24
Finished Mar 10 01:52:09 PM PDT 24
Peak memory 215740 kb
Host smart-eb9e4060-c229-487d-a649-7bf3864be167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987996233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2987996233
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.442370309
Short name T378
Test name
Test status
Simulation time 1259089546 ps
CPU time 5.86 seconds
Started Mar 10 02:48:19 PM PDT 24
Finished Mar 10 02:48:26 PM PDT 24
Peak memory 215780 kb
Host smart-f087b0a0-a734-4b3a-992e-48bf2980b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442370309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.442370309
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.150857148
Short name T88
Test name
Test status
Simulation time 6405104555 ps
CPU time 3.59 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:29 PM PDT 24
Peak memory 207408 kb
Host smart-9dc11222-e4a9-46aa-8c53-7ba2b2a31864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150857148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.150857148
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.274110289
Short name T465
Test name
Test status
Simulation time 4520299684 ps
CPU time 7.09 seconds
Started Mar 10 01:51:39 PM PDT 24
Finished Mar 10 01:51:46 PM PDT 24
Peak memory 215992 kb
Host smart-f6e41783-c7d9-4e95-a6ab-59838466ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274110289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.274110289
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3196540290
Short name T679
Test name
Test status
Simulation time 1209115368 ps
CPU time 1.9 seconds
Started Mar 10 02:48:20 PM PDT 24
Finished Mar 10 02:48:23 PM PDT 24
Peak memory 215756 kb
Host smart-1f4bbccb-419f-439f-8024-3067a3b5f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196540290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3196540290
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3361631874
Short name T729
Test name
Test status
Simulation time 150993469 ps
CPU time 0.87 seconds
Started Mar 10 01:51:38 PM PDT 24
Finished Mar 10 01:51:39 PM PDT 24
Peak memory 206304 kb
Host smart-f474aa34-c107-46fe-882b-234fcb4145db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361631874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3361631874
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3267381213
Short name T1623
Test name
Test status
Simulation time 28729701 ps
CPU time 0.76 seconds
Started Mar 10 02:48:20 PM PDT 24
Finished Mar 10 02:48:23 PM PDT 24
Peak memory 204888 kb
Host smart-16384aa7-d5a9-486d-88cd-8bbdff28b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267381213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3267381213
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.529645000
Short name T1461
Test name
Test status
Simulation time 150056957 ps
CPU time 1.17 seconds
Started Mar 10 01:51:41 PM PDT 24
Finished Mar 10 01:51:43 PM PDT 24
Peak memory 205868 kb
Host smart-dfd4b67b-251e-4ff5-8030-f7f776e1a010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529645000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.529645000
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2027158353
Short name T317
Test name
Test status
Simulation time 318673933 ps
CPU time 3.83 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:29 PM PDT 24
Peak memory 223880 kb
Host smart-e0f97627-7994-4e02-a166-c1165115aec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027158353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2027158353
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_upload.2185019946
Short name T230
Test name
Test status
Simulation time 15468062252 ps
CPU time 13.3 seconds
Started Mar 10 01:51:37 PM PDT 24
Finished Mar 10 01:51:50 PM PDT 24
Peak memory 233696 kb
Host smart-de065153-ad2f-43f8-83ed-5c969862adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185019946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2185019946
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3622637174
Short name T302
Test name
Test status
Simulation time 14333098 ps
CPU time 0.71 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:26 PM PDT 24
Peak memory 204456 kb
Host smart-fb9a1ed1-fccb-4038-bc84-0e8dc92b8a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622637174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3622637174
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3786975093
Short name T1004
Test name
Test status
Simulation time 67592093 ps
CPU time 0.76 seconds
Started Mar 10 01:51:49 PM PDT 24
Finished Mar 10 01:51:50 PM PDT 24
Peak memory 204460 kb
Host smart-dc3f7f9d-ec94-46d1-be8e-5ecb3d667e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786975093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3786975093
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2035511022
Short name T218
Test name
Test status
Simulation time 1144067811 ps
CPU time 2.91 seconds
Started Mar 10 02:48:29 PM PDT 24
Finished Mar 10 02:48:32 PM PDT 24
Peak memory 223880 kb
Host smart-b0d4d7d8-825c-42d9-ab8a-c23cdbbb715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035511022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2035511022
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2746632876
Short name T1072
Test name
Test status
Simulation time 638909224 ps
CPU time 2.45 seconds
Started Mar 10 01:51:46 PM PDT 24
Finished Mar 10 01:51:48 PM PDT 24
Peak memory 223764 kb
Host smart-a3185f1b-0033-4182-80d1-bcfc67f5d768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746632876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2746632876
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2103720154
Short name T1488
Test name
Test status
Simulation time 15667352 ps
CPU time 0.78 seconds
Started Mar 10 02:48:29 PM PDT 24
Finished Mar 10 02:48:30 PM PDT 24
Peak memory 204484 kb
Host smart-5914fdf2-e186-4a50-849b-ac276682cdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103720154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2103720154
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3485884714
Short name T1829
Test name
Test status
Simulation time 24047072 ps
CPU time 0.73 seconds
Started Mar 10 01:51:44 PM PDT 24
Finished Mar 10 01:51:45 PM PDT 24
Peak memory 204452 kb
Host smart-5fe664d3-2169-4e11-9b4e-bfa57c03d21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485884714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3485884714
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.180337771
Short name T1736
Test name
Test status
Simulation time 2653678694 ps
CPU time 45.28 seconds
Started Mar 10 02:48:24 PM PDT 24
Finished Mar 10 02:49:09 PM PDT 24
Peak memory 248532 kb
Host smart-043f20e1-ac89-4a59-9bf0-e7a54caf7777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180337771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.180337771
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.723460365
Short name T1064
Test name
Test status
Simulation time 270405675836 ps
CPU time 344.62 seconds
Started Mar 10 01:51:47 PM PDT 24
Finished Mar 10 01:57:31 PM PDT 24
Peak memory 264944 kb
Host smart-5a8e578b-2415-479a-8ae8-4616a1be82ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723460365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.723460365
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1751243105
Short name T361
Test name
Test status
Simulation time 27827496030 ps
CPU time 92.18 seconds
Started Mar 10 02:48:28 PM PDT 24
Finished Mar 10 02:50:00 PM PDT 24
Peak memory 248672 kb
Host smart-f2de449d-737a-4384-b0d0-953a21f0e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751243105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1751243105
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3229727263
Short name T273
Test name
Test status
Simulation time 175269436963 ps
CPU time 262.41 seconds
Started Mar 10 01:51:48 PM PDT 24
Finished Mar 10 01:56:11 PM PDT 24
Peak memory 251920 kb
Host smart-d3fd24f3-5d5c-4ecf-8e7a-f679d1ab0e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229727263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3229727263
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1892565495
Short name T1787
Test name
Test status
Simulation time 13362771344 ps
CPU time 72.64 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:49:38 PM PDT 24
Peak memory 248776 kb
Host smart-df25463c-a9fe-4427-a3b1-e63b50ec9a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892565495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1892565495
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4011568905
Short name T1093
Test name
Test status
Simulation time 27710264548 ps
CPU time 183.6 seconds
Started Mar 10 01:51:47 PM PDT 24
Finished Mar 10 01:54:51 PM PDT 24
Peak memory 251808 kb
Host smart-e3da6781-8c55-4300-8f35-b234af46c436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011568905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4011568905
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2773167648
Short name T1680
Test name
Test status
Simulation time 661422439 ps
CPU time 7.33 seconds
Started Mar 10 01:51:43 PM PDT 24
Finished Mar 10 01:51:50 PM PDT 24
Peak memory 232048 kb
Host smart-ca0bfe5c-fc6e-4192-adfd-b4091a84c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773167648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2773167648
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.452994700
Short name T1825
Test name
Test status
Simulation time 2278764456 ps
CPU time 8.47 seconds
Started Mar 10 02:48:24 PM PDT 24
Finished Mar 10 02:48:32 PM PDT 24
Peak memory 223940 kb
Host smart-4145b552-0396-41de-a1d2-2a5511436e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452994700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.452994700
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2552623706
Short name T496
Test name
Test status
Simulation time 1405246908 ps
CPU time 4.67 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:30 PM PDT 24
Peak memory 233080 kb
Host smart-020754f6-70bf-4dac-b544-100cfeb402a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552623706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2552623706
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2996778163
Short name T885
Test name
Test status
Simulation time 523996785 ps
CPU time 5.5 seconds
Started Mar 10 01:51:45 PM PDT 24
Finished Mar 10 01:51:51 PM PDT 24
Peak memory 233192 kb
Host smart-93024e74-cfac-4b61-9227-28a45e5ded9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996778163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2996778163
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3778491893
Short name T1290
Test name
Test status
Simulation time 1473837173 ps
CPU time 4.58 seconds
Started Mar 10 01:51:43 PM PDT 24
Finished Mar 10 01:51:48 PM PDT 24
Peak memory 232896 kb
Host smart-c7c1ec9b-1ea4-4a18-a84d-1af7d1808030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778491893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3778491893
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3984374501
Short name T1404
Test name
Test status
Simulation time 40387225437 ps
CPU time 17.74 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:43 PM PDT 24
Peak memory 223892 kb
Host smart-9f081627-985d-4587-bc6e-b7ad01ebb9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984374501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3984374501
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2019940584
Short name T441
Test name
Test status
Simulation time 874294149 ps
CPU time 7.41 seconds
Started Mar 10 01:51:47 PM PDT 24
Finished Mar 10 01:51:54 PM PDT 24
Peak memory 239832 kb
Host smart-2eda8de3-c97f-4fd4-980d-2ae052f20592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019940584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2019940584
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3559982120
Short name T368
Test name
Test status
Simulation time 19327283467 ps
CPU time 15.04 seconds
Started Mar 10 02:48:22 PM PDT 24
Finished Mar 10 02:48:37 PM PDT 24
Peak memory 235044 kb
Host smart-7fadb23f-527b-4138-a5e0-48a8f49b2d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559982120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3559982120
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1449766487
Short name T801
Test name
Test status
Simulation time 1089298998 ps
CPU time 3.63 seconds
Started Mar 10 01:51:46 PM PDT 24
Finished Mar 10 01:51:50 PM PDT 24
Peak memory 232260 kb
Host smart-a8a45992-b4e3-4b63-b059-9185e18bcebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449766487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1449766487
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1700604380
Short name T818
Test name
Test status
Simulation time 23069836221 ps
CPU time 25.58 seconds
Started Mar 10 02:48:27 PM PDT 24
Finished Mar 10 02:48:53 PM PDT 24
Peak memory 247392 kb
Host smart-77517216-bc66-4809-98b6-12266aef3cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700604380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1700604380
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1010383974
Short name T139
Test name
Test status
Simulation time 2001507457 ps
CPU time 5.35 seconds
Started Mar 10 02:48:24 PM PDT 24
Finished Mar 10 02:48:30 PM PDT 24
Peak memory 219680 kb
Host smart-68fc7cc8-2e1a-4cf2-b009-448140272277
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1010383974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1010383974
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1183878145
Short name T595
Test name
Test status
Simulation time 502377351 ps
CPU time 4.25 seconds
Started Mar 10 01:51:45 PM PDT 24
Finished Mar 10 01:51:49 PM PDT 24
Peak memory 216780 kb
Host smart-d27a42e9-3cea-4dd4-8d97-8df57ae5a831
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1183878145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1183878145
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.903835016
Short name T1120
Test name
Test status
Simulation time 226324553792 ps
CPU time 280.25 seconds
Started Mar 10 01:51:51 PM PDT 24
Finished Mar 10 01:56:31 PM PDT 24
Peak memory 252784 kb
Host smart-8c93189a-64d3-4fbb-bc91-a513151a4d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903835016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.903835016
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.70649607
Short name T1034
Test name
Test status
Simulation time 5396074620 ps
CPU time 31.92 seconds
Started Mar 10 01:51:45 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 215744 kb
Host smart-2f38bf90-d4e9-4efa-9bd2-0fd76107dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70649607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.70649607
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.782518460
Short name T483
Test name
Test status
Simulation time 18279305383 ps
CPU time 28.2 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:53 PM PDT 24
Peak memory 215852 kb
Host smart-e04f6953-651f-4018-ad47-70155329a600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782518460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.782518460
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3942038572
Short name T900
Test name
Test status
Simulation time 1139650028 ps
CPU time 4.41 seconds
Started Mar 10 02:48:24 PM PDT 24
Finished Mar 10 02:48:29 PM PDT 24
Peak memory 215812 kb
Host smart-8b3ec7a7-1a61-47d5-a02b-0f9e7920bf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942038572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3942038572
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.761679439
Short name T580
Test name
Test status
Simulation time 2787287010 ps
CPU time 4.37 seconds
Started Mar 10 01:51:45 PM PDT 24
Finished Mar 10 01:51:50 PM PDT 24
Peak memory 215620 kb
Host smart-e72ae267-a7b6-4d36-87f4-8394e7a96726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761679439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.761679439
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1469472550
Short name T717
Test name
Test status
Simulation time 20819877 ps
CPU time 0.82 seconds
Started Mar 10 02:48:27 PM PDT 24
Finished Mar 10 02:48:28 PM PDT 24
Peak memory 204840 kb
Host smart-af3192f1-9f19-4310-85a7-5b25ea994e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469472550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1469472550
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.179323224
Short name T1600
Test name
Test status
Simulation time 138519645 ps
CPU time 1.44 seconds
Started Mar 10 01:51:46 PM PDT 24
Finished Mar 10 01:51:47 PM PDT 24
Peak memory 216096 kb
Host smart-1225ed03-7e42-4b1a-9375-5f37bea3c33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179323224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.179323224
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3386558222
Short name T308
Test name
Test status
Simulation time 172293070 ps
CPU time 0.83 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:26 PM PDT 24
Peak memory 204800 kb
Host smart-926bcf40-fe4c-4bf6-862c-3e9a600bd89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386558222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3386558222
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4116945345
Short name T806
Test name
Test status
Simulation time 80681285 ps
CPU time 0.98 seconds
Started Mar 10 01:51:45 PM PDT 24
Finished Mar 10 01:51:46 PM PDT 24
Peak memory 205900 kb
Host smart-70c1f37e-42d8-4df8-898d-5d6d44fcd544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116945345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4116945345
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2887726033
Short name T540
Test name
Test status
Simulation time 928182335 ps
CPU time 5.52 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:30 PM PDT 24
Peak memory 235012 kb
Host smart-9000f2dd-8e44-4991-a1c2-1b81997206ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887726033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2887726033
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_upload.3193742054
Short name T974
Test name
Test status
Simulation time 3822499524 ps
CPU time 10.08 seconds
Started Mar 10 01:51:46 PM PDT 24
Finished Mar 10 01:51:57 PM PDT 24
Peak memory 231908 kb
Host smart-00dfa1b1-d221-4e74-9961-9ae64382adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193742054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3193742054
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1610767922
Short name T987
Test name
Test status
Simulation time 13316568 ps
CPU time 0.72 seconds
Started Mar 10 01:51:56 PM PDT 24
Finished Mar 10 01:51:57 PM PDT 24
Peak memory 204440 kb
Host smart-3859c533-f66a-4bb4-8ba3-4e5f080f8898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610767922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1610767922
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3526724426
Short name T57
Test name
Test status
Simulation time 14050080 ps
CPU time 0.75 seconds
Started Mar 10 02:48:30 PM PDT 24
Finished Mar 10 02:48:31 PM PDT 24
Peak memory 204460 kb
Host smart-bdbb8a72-066c-4b94-a3d8-f10ec6605878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526724426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3526724426
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1456093638
Short name T1881
Test name
Test status
Simulation time 2713200374 ps
CPU time 5.19 seconds
Started Mar 10 01:51:50 PM PDT 24
Finished Mar 10 01:51:55 PM PDT 24
Peak memory 218648 kb
Host smart-646bb852-73b9-441d-b7e3-1b927312ec13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456093638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1456093638
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.205198350
Short name T1226
Test name
Test status
Simulation time 831481712 ps
CPU time 4.65 seconds
Started Mar 10 02:48:33 PM PDT 24
Finished Mar 10 02:48:39 PM PDT 24
Peak memory 217272 kb
Host smart-c4ad6070-1236-4d52-92d2-0434a00b03b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205198350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.205198350
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2746314907
Short name T372
Test name
Test status
Simulation time 15190455 ps
CPU time 0.79 seconds
Started Mar 10 02:48:27 PM PDT 24
Finished Mar 10 02:48:28 PM PDT 24
Peak memory 205852 kb
Host smart-4073ba11-afba-4100-96b8-fa6a8393b9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746314907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2746314907
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.572308873
Short name T1728
Test name
Test status
Simulation time 114768947 ps
CPU time 0.82 seconds
Started Mar 10 01:51:54 PM PDT 24
Finished Mar 10 01:51:56 PM PDT 24
Peak memory 205484 kb
Host smart-1b1995bf-cd64-4820-bf6d-91fdaa265a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572308873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.572308873
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.146035629
Short name T339
Test name
Test status
Simulation time 16653014783 ps
CPU time 57.89 seconds
Started Mar 10 01:51:49 PM PDT 24
Finished Mar 10 01:52:47 PM PDT 24
Peak memory 264388 kb
Host smart-1dc77d26-6bae-4f77-a93a-c9203bed85f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146035629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.146035629
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1822935014
Short name T1304
Test name
Test status
Simulation time 3540762291 ps
CPU time 16.23 seconds
Started Mar 10 02:48:29 PM PDT 24
Finished Mar 10 02:48:45 PM PDT 24
Peak memory 245776 kb
Host smart-c9e509a2-fbe3-472a-aa3b-fafd157a0ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822935014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1822935014
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2722135476
Short name T575
Test name
Test status
Simulation time 108931100437 ps
CPU time 307.22 seconds
Started Mar 10 01:51:52 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 250516 kb
Host smart-24011ebf-e4eb-4522-90bf-7269b5667423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722135476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2722135476
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3404955845
Short name T453
Test name
Test status
Simulation time 5040410079 ps
CPU time 47.87 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:49:19 PM PDT 24
Peak memory 248684 kb
Host smart-6c79b278-1f51-408c-8904-a494da42aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404955845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3404955845
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2124129548
Short name T50
Test name
Test status
Simulation time 5899665332 ps
CPU time 128.72 seconds
Started Mar 10 01:51:56 PM PDT 24
Finished Mar 10 01:54:05 PM PDT 24
Peak memory 269976 kb
Host smart-b2850c62-9989-40bd-a17b-e736cf75dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124129548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2124129548
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2995867807
Short name T1173
Test name
Test status
Simulation time 216331173020 ps
CPU time 391.55 seconds
Started Mar 10 02:48:32 PM PDT 24
Finished Mar 10 02:55:04 PM PDT 24
Peak memory 264792 kb
Host smart-100146b9-34de-448c-b7fe-5956e831ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995867807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2995867807
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1941848134
Short name T289
Test name
Test status
Simulation time 6340457059 ps
CPU time 29.67 seconds
Started Mar 10 01:51:48 PM PDT 24
Finished Mar 10 01:52:18 PM PDT 24
Peak memory 223928 kb
Host smart-28457144-d198-45d5-ac25-f70d760a11a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941848134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1941848134
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.731674320
Short name T1531
Test name
Test status
Simulation time 1339450313 ps
CPU time 12 seconds
Started Mar 10 02:48:37 PM PDT 24
Finished Mar 10 02:48:49 PM PDT 24
Peak memory 223856 kb
Host smart-fd79b584-f23d-466a-adac-65c6fd6850be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731674320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.731674320
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.555253899
Short name T1464
Test name
Test status
Simulation time 15414593344 ps
CPU time 7.57 seconds
Started Mar 10 02:48:27 PM PDT 24
Finished Mar 10 02:48:35 PM PDT 24
Peak memory 218444 kb
Host smart-3bd1344f-355a-4f3b-9e29-4f1d13e33b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555253899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.555253899
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intercept.806436817
Short name T1262
Test name
Test status
Simulation time 1785015391 ps
CPU time 8.57 seconds
Started Mar 10 01:51:48 PM PDT 24
Finished Mar 10 01:51:57 PM PDT 24
Peak memory 232672 kb
Host smart-6581d123-c02b-4730-8196-7b05d9fe08f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806436817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.806436817
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2525598094
Short name T1107
Test name
Test status
Simulation time 6766765391 ps
CPU time 31.95 seconds
Started Mar 10 02:48:34 PM PDT 24
Finished Mar 10 02:49:06 PM PDT 24
Peak memory 250276 kb
Host smart-905b6de0-d4c5-494d-b3d2-a4d92895db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525598094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2525598094
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.551545746
Short name T34
Test name
Test status
Simulation time 150942579 ps
CPU time 2.81 seconds
Started Mar 10 01:51:48 PM PDT 24
Finished Mar 10 01:51:51 PM PDT 24
Peak memory 232092 kb
Host smart-0aba06ee-18c0-4a3e-87a6-7a7559070cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551545746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.551545746
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.961867544
Short name T1436
Test name
Test status
Simulation time 2956573265 ps
CPU time 11.96 seconds
Started Mar 10 01:51:48 PM PDT 24
Finished Mar 10 01:52:01 PM PDT 24
Peak memory 225708 kb
Host smart-1feab9e1-2a87-4545-a07a-c5c168f406aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961867544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.961867544
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.976464032
Short name T979
Test name
Test status
Simulation time 1651499164 ps
CPU time 3.9 seconds
Started Mar 10 02:48:27 PM PDT 24
Finished Mar 10 02:48:31 PM PDT 24
Peak memory 217836 kb
Host smart-c6622c0f-7cc4-4625-83c5-03c0d3c4c5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976464032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.976464032
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2590628285
Short name T676
Test name
Test status
Simulation time 628129557 ps
CPU time 3.31 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:48:28 PM PDT 24
Peak memory 232924 kb
Host smart-45d92ca3-2749-4fc8-ac45-32c4b2989d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590628285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2590628285
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3123923873
Short name T1872
Test name
Test status
Simulation time 2246026231 ps
CPU time 10.26 seconds
Started Mar 10 01:51:50 PM PDT 24
Finished Mar 10 01:52:00 PM PDT 24
Peak memory 232332 kb
Host smart-2c6c3915-af44-454a-8217-41a53d5fd461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123923873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3123923873
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2008142290
Short name T1168
Test name
Test status
Simulation time 1276778716 ps
CPU time 6.14 seconds
Started Mar 10 01:51:51 PM PDT 24
Finished Mar 10 01:51:57 PM PDT 24
Peak memory 215812 kb
Host smart-10163176-582a-47bb-8345-e8ca4bb109ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2008142290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2008142290
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2122065308
Short name T1266
Test name
Test status
Simulation time 282454089 ps
CPU time 3.64 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:48:35 PM PDT 24
Peak memory 217688 kb
Host smart-4fb20b3a-2145-4584-89ab-9ae1d2b93e7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2122065308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2122065308
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3995643586
Short name T869
Test name
Test status
Simulation time 83258837 ps
CPU time 1.08 seconds
Started Mar 10 02:48:32 PM PDT 24
Finished Mar 10 02:48:34 PM PDT 24
Peak memory 205976 kb
Host smart-2c534d47-37ee-44ea-9385-ee00b2c4c4fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995643586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3995643586
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.581214453
Short name T296
Test name
Test status
Simulation time 45005119 ps
CPU time 0.97 seconds
Started Mar 10 01:51:54 PM PDT 24
Finished Mar 10 01:51:56 PM PDT 24
Peak memory 205680 kb
Host smart-ac255c9c-48ac-454a-b9fe-95740d1b4e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581214453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.581214453
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2481059205
Short name T1396
Test name
Test status
Simulation time 19317255136 ps
CPU time 38.87 seconds
Started Mar 10 02:48:25 PM PDT 24
Finished Mar 10 02:49:04 PM PDT 24
Peak memory 215876 kb
Host smart-9b754077-26f3-4a53-a0b3-4a44e4d4508a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481059205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2481059205
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3746748092
Short name T1766
Test name
Test status
Simulation time 4252625967 ps
CPU time 39.9 seconds
Started Mar 10 01:51:48 PM PDT 24
Finished Mar 10 01:52:28 PM PDT 24
Peak memory 215684 kb
Host smart-7eec0bb5-4779-4b89-8c7c-e4f6283d75cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746748092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3746748092
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2240276916
Short name T1509
Test name
Test status
Simulation time 9392077157 ps
CPU time 7.52 seconds
Started Mar 10 02:48:28 PM PDT 24
Finished Mar 10 02:48:36 PM PDT 24
Peak memory 215756 kb
Host smart-bfc61a50-7c0d-4136-9822-be94f7f1540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240276916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2240276916
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.712404399
Short name T342
Test name
Test status
Simulation time 637310928 ps
CPU time 3.8 seconds
Started Mar 10 01:51:50 PM PDT 24
Finished Mar 10 01:51:54 PM PDT 24
Peak memory 215768 kb
Host smart-5b4e7ac6-e736-4a71-af7e-8159a3aa06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712404399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.712404399
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1158087122
Short name T1296
Test name
Test status
Simulation time 22143425 ps
CPU time 0.86 seconds
Started Mar 10 02:48:27 PM PDT 24
Finished Mar 10 02:48:28 PM PDT 24
Peak memory 205888 kb
Host smart-5640dbe8-6699-4fe1-ac6a-b23f5b52e797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158087122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1158087122
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2044913726
Short name T281
Test name
Test status
Simulation time 53670587 ps
CPU time 1.4 seconds
Started Mar 10 01:51:48 PM PDT 24
Finished Mar 10 01:51:49 PM PDT 24
Peak memory 207292 kb
Host smart-cbf6a09c-a287-4e4b-9e83-81f2bcfe7748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044913726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2044913726
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2588281599
Short name T890
Test name
Test status
Simulation time 248490213 ps
CPU time 0.94 seconds
Started Mar 10 01:51:49 PM PDT 24
Finished Mar 10 01:51:50 PM PDT 24
Peak memory 205868 kb
Host smart-064ecb19-d548-4485-a243-424e3cae8710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588281599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2588281599
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4128520466
Short name T766
Test name
Test status
Simulation time 59483940 ps
CPU time 0.87 seconds
Started Mar 10 02:48:28 PM PDT 24
Finished Mar 10 02:48:29 PM PDT 24
Peak memory 204860 kb
Host smart-c37126df-6954-4712-8435-d387c8ce4882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128520466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4128520466
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3466687923
Short name T946
Test name
Test status
Simulation time 996788847 ps
CPU time 6.57 seconds
Started Mar 10 02:48:37 PM PDT 24
Finished Mar 10 02:48:43 PM PDT 24
Peak memory 219288 kb
Host smart-454d92c9-2c63-487e-bff9-a8922366acae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466687923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3466687923
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_upload.4176131055
Short name T1805
Test name
Test status
Simulation time 951369751 ps
CPU time 3.99 seconds
Started Mar 10 01:51:55 PM PDT 24
Finished Mar 10 01:51:59 PM PDT 24
Peak memory 233180 kb
Host smart-3662d9fe-a448-4b14-aeb7-512ff0f90e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176131055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4176131055
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4255689995
Short name T1828
Test name
Test status
Simulation time 30816359 ps
CPU time 0.69 seconds
Started Mar 10 02:48:33 PM PDT 24
Finished Mar 10 02:48:34 PM PDT 24
Peak memory 204452 kb
Host smart-7341a024-2723-4877-ae96-15f6567168b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255689995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4255689995
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.491145507
Short name T318
Test name
Test status
Simulation time 15037610 ps
CPU time 0.73 seconds
Started Mar 10 01:51:53 PM PDT 24
Finished Mar 10 01:51:54 PM PDT 24
Peak memory 204760 kb
Host smart-2625aa46-04d2-4532-bf42-d837222d2187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491145507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.491145507
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1939384318
Short name T364
Test name
Test status
Simulation time 689122718 ps
CPU time 4.25 seconds
Started Mar 10 02:48:30 PM PDT 24
Finished Mar 10 02:48:35 PM PDT 24
Peak memory 217476 kb
Host smart-8f6d6a7a-f89f-4dc9-b969-dc36c57509f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939384318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1939384318
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3667551785
Short name T1036
Test name
Test status
Simulation time 193903208 ps
CPU time 3.51 seconds
Started Mar 10 01:51:53 PM PDT 24
Finished Mar 10 01:51:57 PM PDT 24
Peak memory 218124 kb
Host smart-a21a258f-da58-470d-9e38-1d4445b5f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667551785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3667551785
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3628217396
Short name T1447
Test name
Test status
Simulation time 22432407 ps
CPU time 0.8 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:48:32 PM PDT 24
Peak memory 205464 kb
Host smart-d403f2c4-b801-47b5-8c61-0255d1d4da3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628217396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3628217396
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.660186697
Short name T525
Test name
Test status
Simulation time 12574841 ps
CPU time 0.78 seconds
Started Mar 10 01:51:56 PM PDT 24
Finished Mar 10 01:51:57 PM PDT 24
Peak memory 205780 kb
Host smart-fff59149-7b2b-419b-967c-8d58c2e4a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660186697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.660186697
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2361307051
Short name T1024
Test name
Test status
Simulation time 18340654457 ps
CPU time 28.79 seconds
Started Mar 10 02:48:44 PM PDT 24
Finished Mar 10 02:49:13 PM PDT 24
Peak memory 247528 kb
Host smart-db8c728f-a3b0-4558-9da8-e30b4b7151d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361307051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2361307051
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3699720852
Short name T912
Test name
Test status
Simulation time 8819516101 ps
CPU time 107.86 seconds
Started Mar 10 01:51:56 PM PDT 24
Finished Mar 10 01:53:44 PM PDT 24
Peak memory 266224 kb
Host smart-a88d3e14-ff8d-4f03-bca6-929ef8dd11bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699720852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3699720852
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2111658117
Short name T1223
Test name
Test status
Simulation time 4585389205 ps
CPU time 58.57 seconds
Started Mar 10 01:51:58 PM PDT 24
Finished Mar 10 01:52:57 PM PDT 24
Peak memory 239960 kb
Host smart-e89b46e7-f370-4d13-8211-301196b02d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111658117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2111658117
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.4019981217
Short name T32
Test name
Test status
Simulation time 14873925728 ps
CPU time 176.45 seconds
Started Mar 10 02:48:36 PM PDT 24
Finished Mar 10 02:51:32 PM PDT 24
Peak memory 264824 kb
Host smart-e225a48e-d857-40c0-b397-f35ed35b35bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019981217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4019981217
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1409373713
Short name T1810
Test name
Test status
Simulation time 3453353273 ps
CPU time 65.37 seconds
Started Mar 10 02:48:36 PM PDT 24
Finished Mar 10 02:49:42 PM PDT 24
Peak memory 255580 kb
Host smart-7bab10a2-3576-4590-a614-84d25290c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409373713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1409373713
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1671191086
Short name T1271
Test name
Test status
Simulation time 37593679430 ps
CPU time 128.18 seconds
Started Mar 10 01:51:53 PM PDT 24
Finished Mar 10 01:54:02 PM PDT 24
Peak memory 249728 kb
Host smart-9920af08-7f8e-443b-ae5e-246c31067e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671191086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1671191086
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1105553402
Short name T1931
Test name
Test status
Simulation time 454718436 ps
CPU time 12.13 seconds
Started Mar 10 02:48:33 PM PDT 24
Finished Mar 10 02:48:46 PM PDT 24
Peak memory 247516 kb
Host smart-93a0a73c-c987-43c5-a542-84ae644451b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105553402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1105553402
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1180286147
Short name T207
Test name
Test status
Simulation time 247138135 ps
CPU time 6.19 seconds
Started Mar 10 01:51:54 PM PDT 24
Finished Mar 10 01:52:00 PM PDT 24
Peak memory 239236 kb
Host smart-96ba3262-c78d-4a1c-8c81-57adae08c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180286147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1180286147
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1241013959
Short name T1704
Test name
Test status
Simulation time 9475620619 ps
CPU time 10.73 seconds
Started Mar 10 01:51:53 PM PDT 24
Finished Mar 10 01:52:04 PM PDT 24
Peak memory 232668 kb
Host smart-c615614f-70e9-4cb7-afba-8bd0dcc73bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241013959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1241013959
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intercept.568482489
Short name T1221
Test name
Test status
Simulation time 4191775076 ps
CPU time 10.92 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:48:42 PM PDT 24
Peak memory 234112 kb
Host smart-8c548305-b7a4-4d84-aa70-100dc3bbde90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568482489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.568482489
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1349415027
Short name T497
Test name
Test status
Simulation time 39960475386 ps
CPU time 22.37 seconds
Started Mar 10 01:51:55 PM PDT 24
Finished Mar 10 01:52:18 PM PDT 24
Peak memory 226028 kb
Host smart-851cb1c3-7074-45a6-b4e6-794998f539bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349415027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1349415027
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3642632960
Short name T1832
Test name
Test status
Simulation time 2869810243 ps
CPU time 9.56 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:48:40 PM PDT 24
Peak memory 229440 kb
Host smart-99f700a0-be54-44df-8f75-966348b0528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642632960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3642632960
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2212096900
Short name T1607
Test name
Test status
Simulation time 84743437764 ps
CPU time 37.04 seconds
Started Mar 10 02:48:30 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 235716 kb
Host smart-08874c02-ed16-46b3-a892-96a89003258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212096900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2212096900
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2459979766
Short name T1215
Test name
Test status
Simulation time 290680236 ps
CPU time 3.09 seconds
Started Mar 10 01:51:53 PM PDT 24
Finished Mar 10 01:51:56 PM PDT 24
Peak memory 215964 kb
Host smart-fac10a84-1643-4c67-abad-0f7a7120af3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459979766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2459979766
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.215080769
Short name T1059
Test name
Test status
Simulation time 1578397189 ps
CPU time 9.81 seconds
Started Mar 10 01:52:02 PM PDT 24
Finished Mar 10 01:52:12 PM PDT 24
Peak memory 232812 kb
Host smart-5c40f4fa-5fe0-4734-abc0-3c5c41f1bb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215080769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.215080769
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.529582521
Short name T526
Test name
Test status
Simulation time 22102682192 ps
CPU time 17 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:48:48 PM PDT 24
Peak memory 233508 kb
Host smart-8f5f79d0-eb61-4da4-a211-1f6b06cc03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529582521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.529582521
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.473505915
Short name T445
Test name
Test status
Simulation time 3631131022 ps
CPU time 4.8 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:48:36 PM PDT 24
Peak memory 219492 kb
Host smart-df23ea3a-56c6-4c07-9467-481ed9ca49f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=473505915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.473505915
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.652942164
Short name T1662
Test name
Test status
Simulation time 100749671 ps
CPU time 3.29 seconds
Started Mar 10 01:51:52 PM PDT 24
Finished Mar 10 01:51:56 PM PDT 24
Peak memory 222104 kb
Host smart-2cd19b0c-a94f-4dbd-b213-220c04de4bb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=652942164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.652942164
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.490507613
Short name T251
Test name
Test status
Simulation time 37588597602 ps
CPU time 373.67 seconds
Started Mar 10 02:48:37 PM PDT 24
Finished Mar 10 02:54:51 PM PDT 24
Peak memory 272240 kb
Host smart-cfcd7cce-7227-4ea1-b5e7-b9e6d1039b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490507613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.490507613
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4090307926
Short name T277
Test name
Test status
Simulation time 10550874021 ps
CPU time 41.98 seconds
Started Mar 10 02:48:30 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 215808 kb
Host smart-31409dac-c0a5-4f5f-bb80-0a4a1d0c4304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090307926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4090307926
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.806759499
Short name T1023
Test name
Test status
Simulation time 4656750285 ps
CPU time 28.18 seconds
Started Mar 10 01:51:55 PM PDT 24
Finished Mar 10 01:52:23 PM PDT 24
Peak memory 215860 kb
Host smart-d9bac853-02af-43d8-8cdb-598452f4d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806759499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.806759499
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3172016822
Short name T1544
Test name
Test status
Simulation time 3866625033 ps
CPU time 10.22 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:48:41 PM PDT 24
Peak memory 215764 kb
Host smart-3aa3221a-3ad7-4e13-8242-8e8b4012d796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172016822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3172016822
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3603076989
Short name T1732
Test name
Test status
Simulation time 2280062003 ps
CPU time 8.83 seconds
Started Mar 10 01:51:56 PM PDT 24
Finished Mar 10 01:52:05 PM PDT 24
Peak memory 215732 kb
Host smart-3e4aef98-a0c4-4eea-b089-6d6722545218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603076989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3603076989
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4067171466
Short name T1382
Test name
Test status
Simulation time 498138697 ps
CPU time 3.44 seconds
Started Mar 10 01:51:57 PM PDT 24
Finished Mar 10 01:52:00 PM PDT 24
Peak memory 215744 kb
Host smart-eea0a92e-7511-4be8-8010-70a6d16d3a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067171466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4067171466
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.740044018
Short name T572
Test name
Test status
Simulation time 1709973073 ps
CPU time 7.65 seconds
Started Mar 10 02:48:32 PM PDT 24
Finished Mar 10 02:48:40 PM PDT 24
Peak memory 215728 kb
Host smart-de69e2fc-99b7-4bd9-9413-58da7521d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740044018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.740044018
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1559947768
Short name T1729
Test name
Test status
Simulation time 49734902 ps
CPU time 0.76 seconds
Started Mar 10 01:51:53 PM PDT 24
Finished Mar 10 01:51:54 PM PDT 24
Peak memory 204808 kb
Host smart-0a4aeae8-fd6e-4a19-9c4b-ff6d039b1054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559947768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1559947768
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3142837405
Short name T825
Test name
Test status
Simulation time 528052018 ps
CPU time 1.15 seconds
Started Mar 10 02:48:31 PM PDT 24
Finished Mar 10 02:48:33 PM PDT 24
Peak memory 205896 kb
Host smart-9bdb91e0-7c4d-4f09-8bc8-be78c23d9dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142837405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3142837405
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1493441373
Short name T1719
Test name
Test status
Simulation time 8326681293 ps
CPU time 30.14 seconds
Started Mar 10 02:48:29 PM PDT 24
Finished Mar 10 02:48:59 PM PDT 24
Peak memory 237484 kb
Host smart-daedb7a2-e26d-45cd-8267-a1b51148bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493441373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1493441373
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_upload.38862769
Short name T1866
Test name
Test status
Simulation time 1484494439 ps
CPU time 9.63 seconds
Started Mar 10 01:51:54 PM PDT 24
Finished Mar 10 01:52:04 PM PDT 24
Peak memory 232076 kb
Host smart-26bbc222-4e1e-4a81-a0a3-f0aedb417651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38862769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.38862769
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3656482378
Short name T663
Test name
Test status
Simulation time 72428363 ps
CPU time 0.73 seconds
Started Mar 10 02:48:42 PM PDT 24
Finished Mar 10 02:48:43 PM PDT 24
Peak memory 204436 kb
Host smart-edeae04d-a8e2-4428-88b7-eae3f1c2c9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656482378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3656482378
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3862853972
Short name T287
Test name
Test status
Simulation time 15631885 ps
CPU time 0.74 seconds
Started Mar 10 01:52:04 PM PDT 24
Finished Mar 10 01:52:05 PM PDT 24
Peak memory 204424 kb
Host smart-2d9a246d-afda-4346-bbe1-dc92de123cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862853972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3862853972
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.250788393
Short name T422
Test name
Test status
Simulation time 1361387129 ps
CPU time 2.93 seconds
Started Mar 10 02:48:43 PM PDT 24
Finished Mar 10 02:48:46 PM PDT 24
Peak memory 223820 kb
Host smart-22d86264-5f79-4c5b-9baf-6f86da4a5be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250788393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.250788393
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4287006515
Short name T346
Test name
Test status
Simulation time 682596781 ps
CPU time 5.7 seconds
Started Mar 10 01:52:00 PM PDT 24
Finished Mar 10 01:52:06 PM PDT 24
Peak memory 223788 kb
Host smart-5c4069c2-195f-4072-90f5-3b1a3da7c051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287006515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4287006515
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2023630039
Short name T723
Test name
Test status
Simulation time 18659858 ps
CPU time 0.79 seconds
Started Mar 10 02:48:35 PM PDT 24
Finished Mar 10 02:48:36 PM PDT 24
Peak memory 205488 kb
Host smart-bcc1b4b8-16df-480e-bc7a-1a5c39841296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023630039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2023630039
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.585245185
Short name T847
Test name
Test status
Simulation time 44725403 ps
CPU time 0.74 seconds
Started Mar 10 01:52:02 PM PDT 24
Finished Mar 10 01:52:03 PM PDT 24
Peak memory 204416 kb
Host smart-b1fd6cac-ce82-47fb-9f30-100757f96d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585245185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.585245185
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2005715820
Short name T13
Test name
Test status
Simulation time 215724669 ps
CPU time 4.28 seconds
Started Mar 10 01:51:59 PM PDT 24
Finished Mar 10 01:52:04 PM PDT 24
Peak memory 236564 kb
Host smart-f6ce6901-e07a-4b0b-af9f-357f035da17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005715820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2005715820
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3890261464
Short name T1098
Test name
Test status
Simulation time 10439793136 ps
CPU time 70.26 seconds
Started Mar 10 02:48:43 PM PDT 24
Finished Mar 10 02:49:53 PM PDT 24
Peak memory 249556 kb
Host smart-170e48ad-0e6b-4605-a38a-93342975beab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890261464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3890261464
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2262826754
Short name T1239
Test name
Test status
Simulation time 6406685961 ps
CPU time 39.91 seconds
Started Mar 10 01:51:59 PM PDT 24
Finished Mar 10 01:52:39 PM PDT 24
Peak memory 232452 kb
Host smart-8a503df4-812a-4a20-a527-5db145b48941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262826754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2262826754
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.166850559
Short name T1320
Test name
Test status
Simulation time 61846858307 ps
CPU time 238.2 seconds
Started Mar 10 01:51:58 PM PDT 24
Finished Mar 10 01:55:57 PM PDT 24
Peak memory 250884 kb
Host smart-d19e08ed-4984-4bf5-9cbd-5e88fc697b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166850559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.166850559
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1997359351
Short name T196
Test name
Test status
Simulation time 8170005964 ps
CPU time 40.3 seconds
Started Mar 10 02:48:40 PM PDT 24
Finished Mar 10 02:49:21 PM PDT 24
Peak memory 252696 kb
Host smart-05329fd6-f7b0-4b61-b214-3f4b79cfd37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997359351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1997359351
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2645403558
Short name T1000
Test name
Test status
Simulation time 5704992481 ps
CPU time 13.26 seconds
Started Mar 10 01:52:00 PM PDT 24
Finished Mar 10 01:52:13 PM PDT 24
Peak memory 233100 kb
Host smart-68732a5e-fdcf-44e2-b37e-5f69d0b21643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645403558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2645403558
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3020020055
Short name T39
Test name
Test status
Simulation time 3759491401 ps
CPU time 23.64 seconds
Started Mar 10 02:48:44 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 239312 kb
Host smart-080359bf-3f5d-4284-b5ce-2214ea324d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020020055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3020020055
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2998999528
Short name T911
Test name
Test status
Simulation time 236314516 ps
CPU time 4.29 seconds
Started Mar 10 01:51:57 PM PDT 24
Finished Mar 10 01:52:02 PM PDT 24
Peak memory 232868 kb
Host smart-a5564671-dcec-40a2-a6f8-9bfeca8668bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998999528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2998999528
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4213537941
Short name T624
Test name
Test status
Simulation time 195936745 ps
CPU time 3.51 seconds
Started Mar 10 02:48:35 PM PDT 24
Finished Mar 10 02:48:39 PM PDT 24
Peak memory 233584 kb
Host smart-7808dac3-7bb3-4483-82a0-a3c18553bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213537941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4213537941
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2260186339
Short name T1696
Test name
Test status
Simulation time 1017119952 ps
CPU time 8.38 seconds
Started Mar 10 02:48:33 PM PDT 24
Finished Mar 10 02:48:42 PM PDT 24
Peak memory 232024 kb
Host smart-bee5cf34-86fb-492f-b01e-252533b715e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260186339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2260186339
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2647969247
Short name T357
Test name
Test status
Simulation time 13673994507 ps
CPU time 21.4 seconds
Started Mar 10 01:52:04 PM PDT 24
Finished Mar 10 01:52:26 PM PDT 24
Peak memory 229488 kb
Host smart-fab61370-d8f6-4825-9723-f3c10b8cf08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647969247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2647969247
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2374179266
Short name T710
Test name
Test status
Simulation time 306569053 ps
CPU time 3.08 seconds
Started Mar 10 02:48:34 PM PDT 24
Finished Mar 10 02:48:37 PM PDT 24
Peak memory 223768 kb
Host smart-6faf1824-a0b8-4ea3-a27d-bb4065c9569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374179266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2374179266
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3412697293
Short name T881
Test name
Test status
Simulation time 264046479 ps
CPU time 4.73 seconds
Started Mar 10 01:51:57 PM PDT 24
Finished Mar 10 01:52:02 PM PDT 24
Peak memory 235288 kb
Host smart-9ee9c7f5-a91e-472f-b500-25fbb9bbdb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412697293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3412697293
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2447294248
Short name T713
Test name
Test status
Simulation time 23752274683 ps
CPU time 17.71 seconds
Started Mar 10 02:48:36 PM PDT 24
Finished Mar 10 02:48:54 PM PDT 24
Peak memory 234240 kb
Host smart-ea10a062-0a6d-4503-82dd-e59f4f807267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447294248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2447294248
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3104952878
Short name T1789
Test name
Test status
Simulation time 383506024 ps
CPU time 4.37 seconds
Started Mar 10 01:52:01 PM PDT 24
Finished Mar 10 01:52:06 PM PDT 24
Peak memory 233064 kb
Host smart-d0d3c6d9-51f2-4dc0-a235-f28612b188b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104952878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3104952878
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3642198582
Short name T1267
Test name
Test status
Simulation time 480224767 ps
CPU time 4.71 seconds
Started Mar 10 01:51:59 PM PDT 24
Finished Mar 10 01:52:05 PM PDT 24
Peak memory 222004 kb
Host smart-e0c1f421-1bcf-456f-8906-521e5c469206
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3642198582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3642198582
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4086536210
Short name T40
Test name
Test status
Simulation time 1101980346 ps
CPU time 5.98 seconds
Started Mar 10 02:48:40 PM PDT 24
Finished Mar 10 02:48:47 PM PDT 24
Peak memory 221412 kb
Host smart-eacdf3a1-d151-4a96-8bcf-17e9a541699b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4086536210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4086536210
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1321067514
Short name T154
Test name
Test status
Simulation time 411109042 ps
CPU time 1.2 seconds
Started Mar 10 01:51:58 PM PDT 24
Finished Mar 10 01:52:00 PM PDT 24
Peak memory 206824 kb
Host smart-92879a4c-f74d-4716-a5ea-ab09ae314bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321067514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1321067514
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.446274574
Short name T156
Test name
Test status
Simulation time 41498873052 ps
CPU time 134.65 seconds
Started Mar 10 02:48:43 PM PDT 24
Finished Mar 10 02:50:58 PM PDT 24
Peak memory 251140 kb
Host smart-f5409fc2-4c1a-4742-aa3b-a37b4cfba056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446274574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.446274574
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1647992736
Short name T1723
Test name
Test status
Simulation time 932029297 ps
CPU time 10.39 seconds
Started Mar 10 01:51:58 PM PDT 24
Finished Mar 10 01:52:08 PM PDT 24
Peak memory 215728 kb
Host smart-06c44849-fb10-4114-8e1e-8772e11b76b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647992736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1647992736
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2432137829
Short name T1029
Test name
Test status
Simulation time 6240024726 ps
CPU time 37.88 seconds
Started Mar 10 02:48:36 PM PDT 24
Finished Mar 10 02:49:14 PM PDT 24
Peak memory 215784 kb
Host smart-257418f2-8d21-4c15-b3a4-d0297849c7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432137829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2432137829
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3460678237
Short name T285
Test name
Test status
Simulation time 13384259846 ps
CPU time 33.93 seconds
Started Mar 10 01:51:58 PM PDT 24
Finished Mar 10 01:52:32 PM PDT 24
Peak memory 215852 kb
Host smart-fc392b1c-4166-49e7-be34-2ff071b5c5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460678237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3460678237
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.663840191
Short name T1687
Test name
Test status
Simulation time 8365864770 ps
CPU time 14.65 seconds
Started Mar 10 02:48:33 PM PDT 24
Finished Mar 10 02:48:48 PM PDT 24
Peak memory 215880 kb
Host smart-fdc256e7-e742-4e55-bb41-7cb96098793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663840191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.663840191
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2776127399
Short name T1246
Test name
Test status
Simulation time 142154253 ps
CPU time 1.61 seconds
Started Mar 10 01:51:58 PM PDT 24
Finished Mar 10 01:52:00 PM PDT 24
Peak memory 215768 kb
Host smart-3abfa81c-e174-484e-8c0c-c4805627b7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776127399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2776127399
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2940567243
Short name T968
Test name
Test status
Simulation time 1261924433 ps
CPU time 3.73 seconds
Started Mar 10 02:48:37 PM PDT 24
Finished Mar 10 02:48:41 PM PDT 24
Peak memory 215752 kb
Host smart-44f5ed53-c057-4574-9b48-599d5939ee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940567243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2940567243
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1624287654
Short name T1058
Test name
Test status
Simulation time 236609950 ps
CPU time 1.04 seconds
Started Mar 10 02:48:35 PM PDT 24
Finished Mar 10 02:48:36 PM PDT 24
Peak memory 205892 kb
Host smart-00998525-3fab-423a-b63b-ceb7bbc9e621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624287654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1624287654
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3413483225
Short name T986
Test name
Test status
Simulation time 150668188 ps
CPU time 0.78 seconds
Started Mar 10 01:51:57 PM PDT 24
Finished Mar 10 01:51:58 PM PDT 24
Peak memory 204904 kb
Host smart-b95a06ba-b3ea-4d68-a742-8b607ee4ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413483225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3413483225
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2593861712
Short name T1458
Test name
Test status
Simulation time 4828334407 ps
CPU time 8.89 seconds
Started Mar 10 01:52:01 PM PDT 24
Finished Mar 10 01:52:10 PM PDT 24
Peak memory 235952 kb
Host smart-d614b27b-6163-44e1-bdbd-cb4d5ec465e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593861712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2593861712
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_upload.552772203
Short name T1295
Test name
Test status
Simulation time 545032224 ps
CPU time 4.54 seconds
Started Mar 10 02:48:44 PM PDT 24
Finished Mar 10 02:48:48 PM PDT 24
Peak memory 218168 kb
Host smart-0a7ea56e-b178-45a3-aa8a-ac7a47f3f358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552772203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.552772203
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1535849387
Short name T485
Test name
Test status
Simulation time 11842144 ps
CPU time 0.69 seconds
Started Mar 10 01:49:10 PM PDT 24
Finished Mar 10 01:49:10 PM PDT 24
Peak memory 204624 kb
Host smart-c719d504-6e84-4fd1-b1aa-6d7a4839834f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535849387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
535849387
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4041156199
Short name T835
Test name
Test status
Simulation time 117067791 ps
CPU time 0.74 seconds
Started Mar 10 02:46:23 PM PDT 24
Finished Mar 10 02:46:24 PM PDT 24
Peak memory 204760 kb
Host smart-ffd2a88c-1591-4508-8e60-a4548d46f992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041156199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
041156199
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1915591229
Short name T461
Test name
Test status
Simulation time 1239822856 ps
CPU time 4.86 seconds
Started Mar 10 01:49:02 PM PDT 24
Finished Mar 10 01:49:07 PM PDT 24
Peak memory 218396 kb
Host smart-b3c64ef9-eed1-4f76-83c1-59cdcdf1ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915591229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1915591229
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.536014960
Short name T1520
Test name
Test status
Simulation time 16154893443 ps
CPU time 11.88 seconds
Started Mar 10 02:46:21 PM PDT 24
Finished Mar 10 02:46:33 PM PDT 24
Peak memory 219968 kb
Host smart-6fc02eee-1b92-4274-91da-b157e52ae8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536014960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.536014960
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1609143799
Short name T1593
Test name
Test status
Simulation time 72699869 ps
CPU time 0.82 seconds
Started Mar 10 01:49:05 PM PDT 24
Finished Mar 10 01:49:06 PM PDT 24
Peak memory 205544 kb
Host smart-a33369e7-4973-43a2-a450-8f58a2d5aefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609143799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1609143799
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2820245493
Short name T1780
Test name
Test status
Simulation time 18604212 ps
CPU time 0.78 seconds
Started Mar 10 02:46:18 PM PDT 24
Finished Mar 10 02:46:18 PM PDT 24
Peak memory 204520 kb
Host smart-7a50cbb9-d962-4653-8a66-b9bffcd09f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820245493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2820245493
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1581028681
Short name T1388
Test name
Test status
Simulation time 35699153994 ps
CPU time 173.87 seconds
Started Mar 10 02:46:23 PM PDT 24
Finished Mar 10 02:49:17 PM PDT 24
Peak memory 236748 kb
Host smart-8a9889c0-ebc5-4c1e-83e0-ddf823162374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581028681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1581028681
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.877964051
Short name T603
Test name
Test status
Simulation time 394897617 ps
CPU time 4.15 seconds
Started Mar 10 01:49:09 PM PDT 24
Finished Mar 10 01:49:14 PM PDT 24
Peak memory 233868 kb
Host smart-4e02ea3a-e8b9-431b-a759-b1ceb1f55c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877964051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.877964051
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4185663235
Short name T862
Test name
Test status
Simulation time 6151547661 ps
CPU time 54.02 seconds
Started Mar 10 01:49:08 PM PDT 24
Finished Mar 10 01:50:02 PM PDT 24
Peak memory 252608 kb
Host smart-6388c2da-2cf8-43d0-a6d7-39b7215dd0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185663235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4185663235
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4206463890
Short name T1356
Test name
Test status
Simulation time 21112735888 ps
CPU time 73.9 seconds
Started Mar 10 02:46:26 PM PDT 24
Finished Mar 10 02:47:40 PM PDT 24
Peak memory 248644 kb
Host smart-c60b610c-ebd8-467c-ba9c-cca48133ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206463890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4206463890
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2239556458
Short name T363
Test name
Test status
Simulation time 8663816855 ps
CPU time 51.51 seconds
Started Mar 10 01:49:08 PM PDT 24
Finished Mar 10 01:49:59 PM PDT 24
Peak memory 235760 kb
Host smart-ca28f0b6-9a87-4141-beba-a288d1aed9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239556458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2239556458
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2866805219
Short name T171
Test name
Test status
Simulation time 21765303553 ps
CPU time 150.43 seconds
Started Mar 10 02:46:25 PM PDT 24
Finished Mar 10 02:48:55 PM PDT 24
Peak memory 249636 kb
Host smart-31a962da-48e5-45f4-a9bd-614fd1f16924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866805219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2866805219
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.21709665
Short name T1641
Test name
Test status
Simulation time 33365871410 ps
CPU time 103.79 seconds
Started Mar 10 01:49:05 PM PDT 24
Finished Mar 10 01:50:49 PM PDT 24
Peak memory 248540 kb
Host smart-68f5d06b-3708-4b2b-83b9-5a2430a8a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21709665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.21709665
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2666161188
Short name T586
Test name
Test status
Simulation time 5275944215 ps
CPU time 23.92 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:46:43 PM PDT 24
Peak memory 235972 kb
Host smart-93802fa8-6da5-43a3-b1f7-3e4cf0334740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666161188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2666161188
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2113313471
Short name T246
Test name
Test status
Simulation time 132362442 ps
CPU time 2.3 seconds
Started Mar 10 02:46:18 PM PDT 24
Finished Mar 10 02:46:21 PM PDT 24
Peak memory 232112 kb
Host smart-5ae0ee22-7177-4c71-afe1-6cb9c9ff79c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113313471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2113313471
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2336064101
Short name T1103
Test name
Test status
Simulation time 408909755 ps
CPU time 5.08 seconds
Started Mar 10 01:49:05 PM PDT 24
Finished Mar 10 01:49:10 PM PDT 24
Peak memory 233096 kb
Host smart-e6078207-fb8c-43fd-9c95-20d2f34c802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336064101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2336064101
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3804289783
Short name T807
Test name
Test status
Simulation time 18744598329 ps
CPU time 12.12 seconds
Started Mar 10 02:46:21 PM PDT 24
Finished Mar 10 02:46:33 PM PDT 24
Peak memory 225576 kb
Host smart-f0e7a2c3-5f51-4643-b371-3dd99b5ca243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804289783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3804289783
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4088922856
Short name T1411
Test name
Test status
Simulation time 16151708884 ps
CPU time 19.42 seconds
Started Mar 10 01:49:02 PM PDT 24
Finished Mar 10 01:49:22 PM PDT 24
Peak memory 245652 kb
Host smart-adcb68c2-5c12-4d91-8515-d3777626de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088922856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4088922856
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1016889300
Short name T419
Test name
Test status
Simulation time 31550601 ps
CPU time 1.07 seconds
Started Mar 10 02:46:17 PM PDT 24
Finished Mar 10 02:46:18 PM PDT 24
Peak memory 215984 kb
Host smart-c0f0756f-0c6f-4485-b841-45e8794571eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016889300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1016889300
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1211852326
Short name T1373
Test name
Test status
Simulation time 53947864 ps
CPU time 1.12 seconds
Started Mar 10 01:49:03 PM PDT 24
Finished Mar 10 01:49:04 PM PDT 24
Peak memory 216076 kb
Host smart-29240b56-4ca3-4ee7-93d3-382335b551d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211852326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1211852326
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1817646396
Short name T564
Test name
Test status
Simulation time 7745904581 ps
CPU time 25.52 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:46:45 PM PDT 24
Peak memory 232044 kb
Host smart-9a956dc3-afad-4155-9451-a2d84f779a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817646396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1817646396
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3896636843
Short name T242
Test name
Test status
Simulation time 716082601 ps
CPU time 5.06 seconds
Started Mar 10 01:49:04 PM PDT 24
Finished Mar 10 01:49:10 PM PDT 24
Peak memory 216988 kb
Host smart-34782e55-1626-4163-8148-d56c1b10fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896636843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3896636843
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1237845066
Short name T1415
Test name
Test status
Simulation time 3707724816 ps
CPU time 7.55 seconds
Started Mar 10 02:46:17 PM PDT 24
Finished Mar 10 02:46:25 PM PDT 24
Peak memory 233648 kb
Host smart-6d193451-cf43-47a0-a692-5bad32c4f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237845066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1237845066
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2475536697
Short name T1405
Test name
Test status
Simulation time 2164931942 ps
CPU time 9.01 seconds
Started Mar 10 01:49:06 PM PDT 24
Finished Mar 10 01:49:15 PM PDT 24
Peak memory 227904 kb
Host smart-daa2bf13-0b1a-4431-8c77-b1d4c08efe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475536697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2475536697
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1520214043
Short name T1047
Test name
Test status
Simulation time 21447467 ps
CPU time 0.76 seconds
Started Mar 10 01:49:03 PM PDT 24
Finished Mar 10 01:49:03 PM PDT 24
Peak memory 215656 kb
Host smart-39007b47-d753-4355-86df-14d412ca80ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520214043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1520214043
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3009217999
Short name T60
Test name
Test status
Simulation time 56392672 ps
CPU time 0.73 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:46:20 PM PDT 24
Peak memory 215648 kb
Host smart-628dcb0c-0205-42bc-a0a3-701d25eb41e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009217999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3009217999
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1313848395
Short name T1057
Test name
Test status
Simulation time 93267655 ps
CPU time 3.51 seconds
Started Mar 10 01:49:09 PM PDT 24
Finished Mar 10 01:49:12 PM PDT 24
Peak memory 218380 kb
Host smart-cdd1dcd3-8acd-41d5-bc75-578a10527c96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1313848395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1313848395
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3754649507
Short name T567
Test name
Test status
Simulation time 2244937898 ps
CPU time 5.57 seconds
Started Mar 10 02:46:24 PM PDT 24
Finished Mar 10 02:46:29 PM PDT 24
Peak memory 219564 kb
Host smart-4151ade4-49a3-477f-886b-5deeadf73c25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3754649507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3754649507
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3948184016
Short name T70
Test name
Test status
Simulation time 100042857 ps
CPU time 1.19 seconds
Started Mar 10 01:49:09 PM PDT 24
Finished Mar 10 01:49:10 PM PDT 24
Peak memory 235080 kb
Host smart-54a0af9b-4723-4ff8-8c92-5de7611d8eda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948184016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3948184016
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.819138991
Short name T67
Test name
Test status
Simulation time 959693696 ps
CPU time 1 seconds
Started Mar 10 02:46:25 PM PDT 24
Finished Mar 10 02:46:26 PM PDT 24
Peak memory 235072 kb
Host smart-27366605-0f16-4a34-b507-cde3c9464ea8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819138991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.819138991
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2768215117
Short name T1270
Test name
Test status
Simulation time 50498630 ps
CPU time 0.99 seconds
Started Mar 10 02:46:25 PM PDT 24
Finished Mar 10 02:46:26 PM PDT 24
Peak memory 205792 kb
Host smart-b25c1089-cea2-4af2-8699-eeab38106d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768215117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2768215117
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3817437979
Short name T1432
Test name
Test status
Simulation time 5629708121 ps
CPU time 103.21 seconds
Started Mar 10 01:49:09 PM PDT 24
Finished Mar 10 01:50:52 PM PDT 24
Peak memory 270976 kb
Host smart-bb7a4b37-25cc-400b-882a-cc08036c1a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817437979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3817437979
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1901320391
Short name T1860
Test name
Test status
Simulation time 1817919013 ps
CPU time 12.7 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:46:32 PM PDT 24
Peak memory 215748 kb
Host smart-42fcb571-8433-415b-b070-a16218f21bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901320391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1901320391
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2210659892
Short name T589
Test name
Test status
Simulation time 2093196193 ps
CPU time 4.51 seconds
Started Mar 10 01:49:05 PM PDT 24
Finished Mar 10 01:49:09 PM PDT 24
Peak memory 215604 kb
Host smart-2fb781d9-6e89-4785-bd5d-b8a24d07a2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210659892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2210659892
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2783453801
Short name T1251
Test name
Test status
Simulation time 916913721 ps
CPU time 2.24 seconds
Started Mar 10 02:46:21 PM PDT 24
Finished Mar 10 02:46:23 PM PDT 24
Peak memory 207612 kb
Host smart-94d833bb-9e84-449d-8376-7bd6f0163212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783453801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2783453801
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4159389838
Short name T811
Test name
Test status
Simulation time 27640547 ps
CPU time 0.88 seconds
Started Mar 10 01:49:06 PM PDT 24
Finished Mar 10 01:49:06 PM PDT 24
Peak memory 205108 kb
Host smart-f3424bcf-aa21-4ec4-bd16-9163241b7375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159389838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4159389838
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.662665756
Short name T429
Test name
Test status
Simulation time 60734026 ps
CPU time 1.45 seconds
Started Mar 10 02:46:20 PM PDT 24
Finished Mar 10 02:46:21 PM PDT 24
Peak memory 215640 kb
Host smart-930156a1-cd39-4c32-9f44-7e4f7746bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662665756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.662665756
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1126535099
Short name T1371
Test name
Test status
Simulation time 30129821 ps
CPU time 0.8 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:46:20 PM PDT 24
Peak memory 204868 kb
Host smart-8322c6bd-efa2-48f9-a656-436ed25d78c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126535099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1126535099
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3591194792
Short name T822
Test name
Test status
Simulation time 237469711 ps
CPU time 1.01 seconds
Started Mar 10 01:49:03 PM PDT 24
Finished Mar 10 01:49:04 PM PDT 24
Peak memory 205916 kb
Host smart-13575833-d589-4571-af52-3bcbf08d38d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591194792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3591194792
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1750531299
Short name T705
Test name
Test status
Simulation time 41746481670 ps
CPU time 18.19 seconds
Started Mar 10 02:46:19 PM PDT 24
Finished Mar 10 02:46:37 PM PDT 24
Peak memory 218252 kb
Host smart-68e12103-6b0b-416d-8dd2-bce3e068d1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750531299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1750531299
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_upload.3878386486
Short name T896
Test name
Test status
Simulation time 183853030 ps
CPU time 3.39 seconds
Started Mar 10 01:49:04 PM PDT 24
Finished Mar 10 01:49:07 PM PDT 24
Peak memory 233780 kb
Host smart-ac0747e1-d5fb-4d96-858d-9ead3db01b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878386486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3878386486
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1674515557
Short name T1391
Test name
Test status
Simulation time 43399217 ps
CPU time 0.72 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:48:46 PM PDT 24
Peak memory 203804 kb
Host smart-c7671696-e669-47bf-8b52-e38cd5df4868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674515557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1674515557
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.556668973
Short name T1222
Test name
Test status
Simulation time 14467456 ps
CPU time 0.78 seconds
Started Mar 10 01:52:03 PM PDT 24
Finished Mar 10 01:52:04 PM PDT 24
Peak memory 203832 kb
Host smart-a86b281e-7f01-46dc-b3ae-931ba16661d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556668973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.556668973
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3717519625
Short name T1620
Test name
Test status
Simulation time 794924415 ps
CPU time 3.01 seconds
Started Mar 10 02:48:37 PM PDT 24
Finished Mar 10 02:48:41 PM PDT 24
Peak memory 223900 kb
Host smart-eb37857a-8408-4772-be54-0ec3609824e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717519625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3717519625
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.602835181
Short name T1171
Test name
Test status
Simulation time 534528987 ps
CPU time 3.94 seconds
Started Mar 10 01:52:05 PM PDT 24
Finished Mar 10 01:52:09 PM PDT 24
Peak memory 233040 kb
Host smart-4f1b535a-005b-4441-8cff-db956f2113eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602835181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.602835181
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1335174762
Short name T861
Test name
Test status
Simulation time 99509580 ps
CPU time 0.8 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:10 PM PDT 24
Peak memory 205384 kb
Host smart-9327908b-75bd-49eb-a0ed-56242e50cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335174762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1335174762
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3854625915
Short name T1088
Test name
Test status
Simulation time 52101794 ps
CPU time 0.78 seconds
Started Mar 10 02:48:40 PM PDT 24
Finished Mar 10 02:48:41 PM PDT 24
Peak memory 204504 kb
Host smart-1042b508-922a-46f5-acf5-87fc3d5ba17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854625915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3854625915
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.340968441
Short name T254
Test name
Test status
Simulation time 17695009756 ps
CPU time 91.06 seconds
Started Mar 10 01:52:05 PM PDT 24
Finished Mar 10 01:53:37 PM PDT 24
Peak memory 264872 kb
Host smart-7d627b84-64c0-421a-8b12-66b4a4922aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340968441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.340968441
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.864148799
Short name T1793
Test name
Test status
Simulation time 8468163165 ps
CPU time 64.47 seconds
Started Mar 10 02:48:42 PM PDT 24
Finished Mar 10 02:49:47 PM PDT 24
Peak memory 248540 kb
Host smart-d564240f-0286-4aca-bab5-80dd8685adea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864148799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.864148799
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3972980742
Short name T602
Test name
Test status
Simulation time 9273171230 ps
CPU time 31.15 seconds
Started Mar 10 01:52:02 PM PDT 24
Finished Mar 10 01:52:34 PM PDT 24
Peak memory 220760 kb
Host smart-a870c14c-6a20-4d9b-90f7-2646e24c6e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972980742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3972980742
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.566859880
Short name T1225
Test name
Test status
Simulation time 210539351263 ps
CPU time 347.07 seconds
Started Mar 10 02:48:48 PM PDT 24
Finished Mar 10 02:54:37 PM PDT 24
Peak memory 236724 kb
Host smart-a750642c-04d8-4729-9aec-50f36bd483c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566859880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.566859880
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1475797005
Short name T1579
Test name
Test status
Simulation time 6997972314 ps
CPU time 40.52 seconds
Started Mar 10 02:48:43 PM PDT 24
Finished Mar 10 02:49:23 PM PDT 24
Peak memory 220776 kb
Host smart-bb73116a-442f-4bc2-9136-575e4b25e00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475797005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1475797005
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3833104053
Short name T1514
Test name
Test status
Simulation time 93230776599 ps
CPU time 472.22 seconds
Started Mar 10 01:52:03 PM PDT 24
Finished Mar 10 01:59:56 PM PDT 24
Peak memory 265164 kb
Host smart-ebed1c41-7fa5-4dc1-b5ec-2897635c9d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833104053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3833104053
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3928759278
Short name T1794
Test name
Test status
Simulation time 4600462536 ps
CPU time 26.52 seconds
Started Mar 10 02:48:46 PM PDT 24
Finished Mar 10 02:49:13 PM PDT 24
Peak memory 231988 kb
Host smart-afc16515-9404-4f80-b4a5-513b0ec0837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928759278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3928759278
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.91816794
Short name T904
Test name
Test status
Simulation time 17493041993 ps
CPU time 27.5 seconds
Started Mar 10 01:52:03 PM PDT 24
Finished Mar 10 01:52:30 PM PDT 24
Peak memory 255572 kb
Host smart-db624a64-2b5e-42db-a0b2-a2357e8632c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91816794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.91816794
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3407449194
Short name T1448
Test name
Test status
Simulation time 755284173 ps
CPU time 5.55 seconds
Started Mar 10 01:52:04 PM PDT 24
Finished Mar 10 01:52:10 PM PDT 24
Peak memory 232312 kb
Host smart-2088fb0e-9c71-496d-ad9c-b9310254c2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407449194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3407449194
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3775332555
Short name T685
Test name
Test status
Simulation time 466331514 ps
CPU time 4.8 seconds
Started Mar 10 02:48:42 PM PDT 24
Finished Mar 10 02:48:47 PM PDT 24
Peak memory 232232 kb
Host smart-ce37b172-3389-49a5-992e-fd2bb6f3dbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775332555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3775332555
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.222623020
Short name T646
Test name
Test status
Simulation time 18260020502 ps
CPU time 18.47 seconds
Started Mar 10 02:48:40 PM PDT 24
Finished Mar 10 02:48:59 PM PDT 24
Peak memory 232016 kb
Host smart-5a5417ec-034d-4ab2-b412-406dc627a4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222623020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.222623020
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.452256863
Short name T1800
Test name
Test status
Simulation time 3705073032 ps
CPU time 13.78 seconds
Started Mar 10 01:52:05 PM PDT 24
Finished Mar 10 01:52:19 PM PDT 24
Peak memory 239832 kb
Host smart-6c102b6d-8e8d-4c9b-b544-11f02157e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452256863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.452256863
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.134054775
Short name T371
Test name
Test status
Simulation time 5888130427 ps
CPU time 13.86 seconds
Started Mar 10 01:52:03 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 235036 kb
Host smart-ed6e44ba-2252-4f16-a20b-d57e4250765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134054775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.134054775
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4187763877
Short name T983
Test name
Test status
Simulation time 54984995106 ps
CPU time 42.52 seconds
Started Mar 10 02:48:39 PM PDT 24
Finished Mar 10 02:49:23 PM PDT 24
Peak memory 228556 kb
Host smart-78e03536-a647-4895-bd70-aff781274626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187763877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4187763877
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2595921420
Short name T550
Test name
Test status
Simulation time 6437931652 ps
CPU time 18.9 seconds
Started Mar 10 02:48:41 PM PDT 24
Finished Mar 10 02:49:00 PM PDT 24
Peak memory 223908 kb
Host smart-eb331438-aa8f-4b22-bf28-788f8ebc8de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595921420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2595921420
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3166727050
Short name T696
Test name
Test status
Simulation time 1103049858 ps
CPU time 3.82 seconds
Started Mar 10 01:52:04 PM PDT 24
Finished Mar 10 01:52:08 PM PDT 24
Peak memory 223816 kb
Host smart-8f878840-5885-42d8-bc50-5eea9561f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166727050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3166727050
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4232629579
Short name T1311
Test name
Test status
Simulation time 1403023446 ps
CPU time 5.61 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:48:51 PM PDT 24
Peak memory 215840 kb
Host smart-14e6b897-48b6-4b9f-b345-7bce3463da26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4232629579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4232629579
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.707843908
Short name T1327
Test name
Test status
Simulation time 1277716487 ps
CPU time 4 seconds
Started Mar 10 01:52:06 PM PDT 24
Finished Mar 10 01:52:10 PM PDT 24
Peak memory 219372 kb
Host smart-07721f9f-f61c-41f5-b6c8-cb17a6e16b89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=707843908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.707843908
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2085058716
Short name T1496
Test name
Test status
Simulation time 146165308594 ps
CPU time 504.56 seconds
Started Mar 10 01:52:04 PM PDT 24
Finished Mar 10 02:00:29 PM PDT 24
Peak memory 271972 kb
Host smart-e78666e0-0bbb-45dc-974b-85bb90c1090f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085058716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2085058716
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.651457644
Short name T151
Test name
Test status
Simulation time 295404754 ps
CPU time 1.12 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:48:47 PM PDT 24
Peak memory 205936 kb
Host smart-f484b5a9-5030-4a8b-a8f8-66b7586bf467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651457644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.651457644
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2399158801
Short name T404
Test name
Test status
Simulation time 2012833802 ps
CPU time 8.92 seconds
Started Mar 10 02:48:40 PM PDT 24
Finished Mar 10 02:48:49 PM PDT 24
Peak memory 215716 kb
Host smart-a47a86f0-3e26-4756-bb42-6ccd80a28dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399158801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2399158801
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.328603204
Short name T831
Test name
Test status
Simulation time 1083341661 ps
CPU time 12.86 seconds
Started Mar 10 01:52:04 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 215632 kb
Host smart-60d82c39-cabd-48ab-8157-2f3b9ba3cc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328603204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.328603204
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4042492211
Short name T1208
Test name
Test status
Simulation time 8888716697 ps
CPU time 14.36 seconds
Started Mar 10 01:52:03 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 215720 kb
Host smart-59d1ae4c-d2f0-4f94-b662-6db5733c2893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042492211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4042492211
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.780199621
Short name T1288
Test name
Test status
Simulation time 20514063511 ps
CPU time 12.29 seconds
Started Mar 10 02:48:43 PM PDT 24
Finished Mar 10 02:48:55 PM PDT 24
Peak memory 215860 kb
Host smart-e8942f03-469d-4676-9ad0-2e83bbf8d03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780199621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.780199621
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2161139010
Short name T1375
Test name
Test status
Simulation time 34628244 ps
CPU time 1.42 seconds
Started Mar 10 02:48:41 PM PDT 24
Finished Mar 10 02:48:42 PM PDT 24
Peak memory 215780 kb
Host smart-7aacfd23-7fd0-4e9d-b514-4c5278c91992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161139010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2161139010
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.909159919
Short name T405
Test name
Test status
Simulation time 26272722 ps
CPU time 1.4 seconds
Started Mar 10 01:52:06 PM PDT 24
Finished Mar 10 01:52:07 PM PDT 24
Peak memory 215988 kb
Host smart-bef3d715-8eef-4584-8e92-c8bb290eca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909159919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.909159919
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1233653448
Short name T1849
Test name
Test status
Simulation time 219881412 ps
CPU time 1.02 seconds
Started Mar 10 01:52:03 PM PDT 24
Finished Mar 10 01:52:04 PM PDT 24
Peak memory 204788 kb
Host smart-226bca29-8e2c-43c5-8af9-1a123e217eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233653448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1233653448
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2982524463
Short name T1869
Test name
Test status
Simulation time 61706359 ps
CPU time 0.71 seconds
Started Mar 10 02:48:39 PM PDT 24
Finished Mar 10 02:48:40 PM PDT 24
Peak memory 204900 kb
Host smart-9ddb4b70-4b5d-41fe-b3ed-3fdd076dea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982524463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2982524463
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1636838428
Short name T1922
Test name
Test status
Simulation time 4071935350 ps
CPU time 10.56 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:20 PM PDT 24
Peak memory 234732 kb
Host smart-cd72509d-0f38-4d98-a016-1e492440892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636838428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1636838428
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_upload.2078979595
Short name T235
Test name
Test status
Simulation time 269927959 ps
CPU time 4.78 seconds
Started Mar 10 02:48:48 PM PDT 24
Finished Mar 10 02:48:55 PM PDT 24
Peak memory 232068 kb
Host smart-76c30fa7-0689-4da7-b74a-a368e3143a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078979595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2078979595
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3855774035
Short name T162
Test name
Test status
Simulation time 30608628 ps
CPU time 0.75 seconds
Started Mar 10 01:52:13 PM PDT 24
Finished Mar 10 01:52:14 PM PDT 24
Peak memory 204804 kb
Host smart-35d854f1-5f9a-40c0-af20-a03a61c897b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855774035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3855774035
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4064188323
Short name T930
Test name
Test status
Simulation time 13619281 ps
CPU time 0.71 seconds
Started Mar 10 02:48:47 PM PDT 24
Finished Mar 10 02:48:51 PM PDT 24
Peak memory 204408 kb
Host smart-ec8bb6ce-aa1b-4f2a-8dc6-ceb806ceb8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064188323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4064188323
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.117667991
Short name T353
Test name
Test status
Simulation time 1775551969 ps
CPU time 4.07 seconds
Started Mar 10 02:48:46 PM PDT 24
Finished Mar 10 02:48:51 PM PDT 24
Peak memory 234556 kb
Host smart-a236b8ad-0b7a-42ba-a7fc-279c0bcbb18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117667991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.117667991
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2909132373
Short name T1928
Test name
Test status
Simulation time 689721923 ps
CPU time 3.58 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:13 PM PDT 24
Peak memory 233328 kb
Host smart-19c870d9-c57d-4ad0-ba0d-d9c451f7d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909132373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2909132373
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.481125808
Short name T1747
Test name
Test status
Simulation time 35446797 ps
CPU time 0.79 seconds
Started Mar 10 02:48:44 PM PDT 24
Finished Mar 10 02:48:45 PM PDT 24
Peak memory 204820 kb
Host smart-82287c84-bf8f-4dcf-b55f-bdfd19f831bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481125808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.481125808
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.763918174
Short name T1715
Test name
Test status
Simulation time 62148694 ps
CPU time 0.77 seconds
Started Mar 10 01:52:08 PM PDT 24
Finished Mar 10 01:52:10 PM PDT 24
Peak memory 204496 kb
Host smart-82a3c088-9897-4760-900f-d5d4513ea028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763918174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.763918174
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1220840514
Short name T803
Test name
Test status
Simulation time 19980372450 ps
CPU time 121.12 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:50:47 PM PDT 24
Peak memory 249992 kb
Host smart-d78ea053-7c97-4c55-bb30-85f40a19f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220840514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1220840514
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.36467457
Short name T907
Test name
Test status
Simulation time 16380057261 ps
CPU time 42.77 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:52 PM PDT 24
Peak memory 232152 kb
Host smart-1a888456-5581-4a26-918d-9058074cc11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36467457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.36467457
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.355861251
Short name T784
Test name
Test status
Simulation time 60950438524 ps
CPU time 115.86 seconds
Started Mar 10 02:48:46 PM PDT 24
Finished Mar 10 02:50:43 PM PDT 24
Peak memory 251888 kb
Host smart-188d9732-f337-4c1d-a994-7e7d73e4ad90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355861251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.355861251
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3658423574
Short name T1190
Test name
Test status
Simulation time 43569522162 ps
CPU time 340.79 seconds
Started Mar 10 01:52:07 PM PDT 24
Finished Mar 10 01:57:48 PM PDT 24
Peak memory 256728 kb
Host smart-d0d01a26-9a8e-4d9c-a02b-4722bcc0967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658423574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3658423574
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3033010710
Short name T675
Test name
Test status
Simulation time 10400293944 ps
CPU time 47.68 seconds
Started Mar 10 01:52:11 PM PDT 24
Finished Mar 10 01:52:59 PM PDT 24
Peak memory 247872 kb
Host smart-7e4e037f-5122-4ec3-95fd-eaffb0b4b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033010710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3033010710
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3977153332
Short name T365
Test name
Test status
Simulation time 1911721925 ps
CPU time 20.97 seconds
Started Mar 10 02:48:47 PM PDT 24
Finished Mar 10 02:49:11 PM PDT 24
Peak memory 234344 kb
Host smart-b373f708-03fd-4039-a7d6-815f79be111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977153332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3977153332
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3856360605
Short name T334
Test name
Test status
Simulation time 5860607949 ps
CPU time 33.32 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:43 PM PDT 24
Peak memory 247788 kb
Host smart-efb8c03e-29ae-4949-9172-4f46342fc421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856360605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3856360605
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3933904563
Short name T1688
Test name
Test status
Simulation time 935633303 ps
CPU time 9.71 seconds
Started Mar 10 02:48:44 PM PDT 24
Finished Mar 10 02:48:54 PM PDT 24
Peak memory 233124 kb
Host smart-8c456921-5040-46da-a303-ed1c045eca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933904563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3933904563
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1444079109
Short name T523
Test name
Test status
Simulation time 2323351017 ps
CPU time 9.95 seconds
Started Mar 10 01:52:10 PM PDT 24
Finished Mar 10 01:52:20 PM PDT 24
Peak memory 223916 kb
Host smart-5de66ba5-3563-4e1b-b148-1d339e03f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444079109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1444079109
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1754690289
Short name T1712
Test name
Test status
Simulation time 244872244 ps
CPU time 3.31 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:48:49 PM PDT 24
Peak memory 216996 kb
Host smart-50e2b024-b40d-4580-ac27-c22397dc6146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754690289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1754690289
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.389752053
Short name T935
Test name
Test status
Simulation time 19840524160 ps
CPU time 9.27 seconds
Started Mar 10 02:48:48 PM PDT 24
Finished Mar 10 02:49:00 PM PDT 24
Peak memory 235204 kb
Host smart-5c7c2cd4-cb28-49a7-9e02-23cc64bcf414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389752053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.389752053
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.597109526
Short name T1053
Test name
Test status
Simulation time 6497287859 ps
CPU time 18.04 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:27 PM PDT 24
Peak memory 235128 kb
Host smart-b89a3fab-f0c0-414b-a726-ce9f09696634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597109526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.597109526
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1141136979
Short name T1547
Test name
Test status
Simulation time 1565590208 ps
CPU time 3.64 seconds
Started Mar 10 02:48:46 PM PDT 24
Finished Mar 10 02:48:50 PM PDT 24
Peak memory 232816 kb
Host smart-4a6e25c8-6058-4c75-a46c-c66d61aafde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141136979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1141136979
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.839735037
Short name T1454
Test name
Test status
Simulation time 28616119190 ps
CPU time 23.55 seconds
Started Mar 10 01:52:11 PM PDT 24
Finished Mar 10 01:52:35 PM PDT 24
Peak memory 230732 kb
Host smart-c3b3e3fd-d14b-4f6c-ab7f-adbf9910abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839735037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.839735037
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3747119938
Short name T1397
Test name
Test status
Simulation time 14125507705 ps
CPU time 40.44 seconds
Started Mar 10 02:48:43 PM PDT 24
Finished Mar 10 02:49:23 PM PDT 24
Peak memory 247992 kb
Host smart-a6e80dc2-07b5-4549-a86e-9dba4e9e425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747119938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3747119938
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4088210623
Short name T1781
Test name
Test status
Simulation time 9976364293 ps
CPU time 9 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:18 PM PDT 24
Peak memory 223872 kb
Host smart-4b21d966-fc1b-4e19-9f4e-c5b01d5c24d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088210623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4088210623
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1936278953
Short name T1550
Test name
Test status
Simulation time 5117185533 ps
CPU time 6.23 seconds
Started Mar 10 02:48:47 PM PDT 24
Finished Mar 10 02:48:56 PM PDT 24
Peak memory 221692 kb
Host smart-8c4e0a99-e704-4af3-9649-e5102ac1a41a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1936278953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1936278953
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.25448666
Short name T1407
Test name
Test status
Simulation time 11771864410 ps
CPU time 5.07 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:15 PM PDT 24
Peak memory 216728 kb
Host smart-f5181ce7-404b-4e0f-ab57-d5a0b20a3e1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=25448666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc
t.25448666
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.279079738
Short name T1149
Test name
Test status
Simulation time 523389683 ps
CPU time 1.2 seconds
Started Mar 10 02:48:42 PM PDT 24
Finished Mar 10 02:48:44 PM PDT 24
Peak memory 205932 kb
Host smart-0428a16e-9b8d-4eae-b76f-7a811f3f6e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279079738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.279079738
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.920994797
Short name T203
Test name
Test status
Simulation time 189637693533 ps
CPU time 746.51 seconds
Started Mar 10 01:52:14 PM PDT 24
Finished Mar 10 02:04:41 PM PDT 24
Peak memory 289584 kb
Host smart-f76e57cc-0697-4f18-aa59-4dbe0b2a1a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920994797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.920994797
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2394462017
Short name T1730
Test name
Test status
Simulation time 2305382166 ps
CPU time 12.98 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:23 PM PDT 24
Peak memory 215760 kb
Host smart-5d7eb253-9680-4c40-815c-9fb1cd680d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394462017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2394462017
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2856691048
Short name T1750
Test name
Test status
Simulation time 865189013 ps
CPU time 9.27 seconds
Started Mar 10 02:48:47 PM PDT 24
Finished Mar 10 02:48:57 PM PDT 24
Peak memory 215812 kb
Host smart-202a58b9-55b3-44fd-946d-791987bb9c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856691048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2856691048
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1521810632
Short name T618
Test name
Test status
Simulation time 49424255874 ps
CPU time 19.75 seconds
Started Mar 10 02:48:44 PM PDT 24
Finished Mar 10 02:49:04 PM PDT 24
Peak memory 215812 kb
Host smart-07f2c776-02d7-4fd8-906f-40e466ce4f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521810632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1521810632
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4117195796
Short name T961
Test name
Test status
Simulation time 6039146136 ps
CPU time 18.68 seconds
Started Mar 10 01:52:07 PM PDT 24
Finished Mar 10 01:52:26 PM PDT 24
Peak memory 215816 kb
Host smart-1fdcdf43-1ddc-4ad0-9fc5-6331c7b405b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117195796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4117195796
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1622975648
Short name T360
Test name
Test status
Simulation time 57428943 ps
CPU time 1.45 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:11 PM PDT 24
Peak memory 206928 kb
Host smart-d78e96ce-7221-49a7-9e83-1fa0787ca06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622975648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1622975648
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.877757397
Short name T1904
Test name
Test status
Simulation time 1113991770 ps
CPU time 4.01 seconds
Started Mar 10 02:48:44 PM PDT 24
Finished Mar 10 02:48:48 PM PDT 24
Peak memory 216888 kb
Host smart-41c38dc4-b5e4-44f1-a7ed-fc6bbc6620bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877757397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.877757397
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2254283708
Short name T300
Test name
Test status
Simulation time 181477748 ps
CPU time 0.99 seconds
Started Mar 10 02:48:44 PM PDT 24
Finished Mar 10 02:48:45 PM PDT 24
Peak memory 204872 kb
Host smart-b7a44b2c-57b9-495c-820c-2ea09057d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254283708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2254283708
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.628747625
Short name T89
Test name
Test status
Simulation time 253984054 ps
CPU time 0.85 seconds
Started Mar 10 01:52:07 PM PDT 24
Finished Mar 10 01:52:08 PM PDT 24
Peak memory 204828 kb
Host smart-cba849ce-65ed-4e08-bf2f-59c3f7dadc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628747625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.628747625
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.383004106
Short name T534
Test name
Test status
Simulation time 83052571602 ps
CPU time 51.21 seconds
Started Mar 10 02:48:46 PM PDT 24
Finished Mar 10 02:49:38 PM PDT 24
Peak memory 240384 kb
Host smart-99300ef2-59b9-45d6-b4a0-78a36936f014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383004106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.383004106
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_upload.565666399
Short name T1546
Test name
Test status
Simulation time 8571858292 ps
CPU time 19.09 seconds
Started Mar 10 01:52:09 PM PDT 24
Finished Mar 10 01:52:28 PM PDT 24
Peak memory 246980 kb
Host smart-017807b0-e517-4227-a339-4482c70ea5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565666399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.565666399
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1386497878
Short name T501
Test name
Test status
Simulation time 13150527 ps
CPU time 0.71 seconds
Started Mar 10 02:48:51 PM PDT 24
Finished Mar 10 02:48:53 PM PDT 24
Peak memory 203880 kb
Host smart-b9544b2e-12cb-469f-bb34-0db1c40a969f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386497878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1386497878
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3251693560
Short name T1495
Test name
Test status
Simulation time 11814253 ps
CPU time 0.74 seconds
Started Mar 10 01:52:18 PM PDT 24
Finished Mar 10 01:52:19 PM PDT 24
Peak memory 204128 kb
Host smart-c0c562b3-6f45-4a22-90d3-0721260bdb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251693560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3251693560
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3168012372
Short name T1390
Test name
Test status
Simulation time 148781644 ps
CPU time 2.65 seconds
Started Mar 10 02:48:49 PM PDT 24
Finished Mar 10 02:48:54 PM PDT 24
Peak memory 232616 kb
Host smart-c2da27ec-6f95-4600-9c6c-34f7ba104470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168012372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3168012372
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3698182121
Short name T615
Test name
Test status
Simulation time 73734524 ps
CPU time 2.41 seconds
Started Mar 10 01:52:15 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 217780 kb
Host smart-8535f088-cdd8-4ce4-a8ab-0e013a2f64c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698182121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3698182121
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3003617261
Short name T1369
Test name
Test status
Simulation time 20618939 ps
CPU time 0.82 seconds
Started Mar 10 01:52:17 PM PDT 24
Finished Mar 10 01:52:18 PM PDT 24
Peak memory 205476 kb
Host smart-5d86e07d-0c8e-4997-a30e-e3b128eaa51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003617261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3003617261
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4252867412
Short name T1300
Test name
Test status
Simulation time 36974983 ps
CPU time 0.8 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:48:47 PM PDT 24
Peak memory 205548 kb
Host smart-171ce511-47d6-4214-8235-732747d78cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252867412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4252867412
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1623505811
Short name T1467
Test name
Test status
Simulation time 12003889241 ps
CPU time 52.37 seconds
Started Mar 10 02:48:52 PM PDT 24
Finished Mar 10 02:49:47 PM PDT 24
Peak memory 235972 kb
Host smart-4cdca38d-0028-44d2-bcff-8c45cfaec4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623505811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1623505811
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4268024182
Short name T184
Test name
Test status
Simulation time 14775249161 ps
CPU time 66.44 seconds
Started Mar 10 01:52:14 PM PDT 24
Finished Mar 10 01:53:20 PM PDT 24
Peak memory 253488 kb
Host smart-d569201d-13f0-4362-a38c-9eececc4b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268024182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4268024182
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1393576044
Short name T1590
Test name
Test status
Simulation time 64947692500 ps
CPU time 121.58 seconds
Started Mar 10 02:48:51 PM PDT 24
Finished Mar 10 02:50:56 PM PDT 24
Peak memory 256884 kb
Host smart-7c9b3ea6-57c9-46e0-9935-c2fdaaded083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393576044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1393576044
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2421232550
Short name T1485
Test name
Test status
Simulation time 7927805409 ps
CPU time 115.3 seconds
Started Mar 10 01:52:13 PM PDT 24
Finished Mar 10 01:54:09 PM PDT 24
Peak memory 261348 kb
Host smart-ab61ae97-18c7-45e8-8576-b288d66de3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421232550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2421232550
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1746537628
Short name T1689
Test name
Test status
Simulation time 4878792606 ps
CPU time 86.2 seconds
Started Mar 10 02:48:52 PM PDT 24
Finished Mar 10 02:50:20 PM PDT 24
Peak memory 256256 kb
Host smart-f108f348-bc27-4aec-8b71-97eb0e0f6a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746537628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1746537628
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.975445846
Short name T1132
Test name
Test status
Simulation time 4071285671 ps
CPU time 39.95 seconds
Started Mar 10 01:52:11 PM PDT 24
Finished Mar 10 01:52:51 PM PDT 24
Peak memory 238636 kb
Host smart-da5057d5-b961-4837-a499-c7c28f1811ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975445846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.975445846
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3416516902
Short name T1882
Test name
Test status
Simulation time 751002597 ps
CPU time 19.32 seconds
Started Mar 10 02:48:51 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 249060 kb
Host smart-b94beaa7-c507-4949-8982-5f3817c8305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416516902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3416516902
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.470895538
Short name T1323
Test name
Test status
Simulation time 26718978141 ps
CPU time 27.91 seconds
Started Mar 10 01:52:16 PM PDT 24
Finished Mar 10 01:52:44 PM PDT 24
Peak memory 240300 kb
Host smart-ec4b17c9-2129-4e91-accd-aefd9aed4e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470895538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.470895538
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3607754678
Short name T1112
Test name
Test status
Simulation time 10468882022 ps
CPU time 9.02 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:48:54 PM PDT 24
Peak memory 234004 kb
Host smart-1e4d4743-c17d-4b8e-ae71-9bf555e27533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607754678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3607754678
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intercept.58401047
Short name T840
Test name
Test status
Simulation time 13466620460 ps
CPU time 11.41 seconds
Started Mar 10 01:52:18 PM PDT 24
Finished Mar 10 01:52:30 PM PDT 24
Peak memory 217200 kb
Host smart-838e94f6-85cb-4097-8316-bdba9b0fec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58401047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.58401047
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1867748182
Short name T1698
Test name
Test status
Simulation time 1061593950 ps
CPU time 7.58 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:48:54 PM PDT 24
Peak memory 232100 kb
Host smart-0555faf7-7050-4393-b5bd-a3308703dfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867748182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1867748182
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2710469239
Short name T776
Test name
Test status
Simulation time 2566540651 ps
CPU time 6.26 seconds
Started Mar 10 01:52:14 PM PDT 24
Finished Mar 10 01:52:21 PM PDT 24
Peak memory 237476 kb
Host smart-54b53cba-ddc7-4260-a90c-2acc1531fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710469239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2710469239
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2347309116
Short name T1811
Test name
Test status
Simulation time 14268807827 ps
CPU time 13.12 seconds
Started Mar 10 01:52:14 PM PDT 24
Finished Mar 10 01:52:28 PM PDT 24
Peak memory 248804 kb
Host smart-5cc47eac-cee0-4b8d-bdaa-b056c6866c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347309116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2347309116
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.719675345
Short name T571
Test name
Test status
Simulation time 1557593935 ps
CPU time 5.76 seconds
Started Mar 10 02:48:46 PM PDT 24
Finished Mar 10 02:48:52 PM PDT 24
Peak memory 232912 kb
Host smart-32b07e79-8d5e-4fd8-8ca5-7eca8110cf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719675345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.719675345
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2487326220
Short name T976
Test name
Test status
Simulation time 14588227296 ps
CPU time 37.81 seconds
Started Mar 10 01:52:14 PM PDT 24
Finished Mar 10 01:52:52 PM PDT 24
Peak memory 234232 kb
Host smart-e974f6ca-b536-4a9e-b342-2f3821202656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487326220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2487326220
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.737708830
Short name T374
Test name
Test status
Simulation time 1697716653 ps
CPU time 8.06 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:48:54 PM PDT 24
Peak memory 216192 kb
Host smart-4413d57a-a8a2-4fbf-a648-19650cce2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737708830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.737708830
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2611691334
Short name T1837
Test name
Test status
Simulation time 604639651 ps
CPU time 5.24 seconds
Started Mar 10 01:52:13 PM PDT 24
Finished Mar 10 01:52:19 PM PDT 24
Peak memory 222028 kb
Host smart-99d54ac3-3e62-403b-9341-90804ef6d0db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2611691334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2611691334
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3839228435
Short name T382
Test name
Test status
Simulation time 1881068147 ps
CPU time 7.48 seconds
Started Mar 10 02:48:49 PM PDT 24
Finished Mar 10 02:48:59 PM PDT 24
Peak memory 221456 kb
Host smart-577e1893-22af-4495-91c6-70aa8258e563
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3839228435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3839228435
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3589678699
Short name T745
Test name
Test status
Simulation time 32537648508 ps
CPU time 260.3 seconds
Started Mar 10 02:48:54 PM PDT 24
Finished Mar 10 02:53:16 PM PDT 24
Peak memory 261676 kb
Host smart-896260b0-072d-4af4-9fb0-ab6c7368bf03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589678699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3589678699
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1685645627
Short name T316
Test name
Test status
Simulation time 12041551608 ps
CPU time 65.48 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:49:51 PM PDT 24
Peak memory 215804 kb
Host smart-aead7054-a040-4079-8e68-a8401bfc5f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685645627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1685645627
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.371809
Short name T1121
Test name
Test status
Simulation time 7169246382 ps
CPU time 20.92 seconds
Started Mar 10 01:52:15 PM PDT 24
Finished Mar 10 01:52:36 PM PDT 24
Peak memory 215868 kb
Host smart-75d2b658-e4b3-491f-80d8-fa0e90d9ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.371809
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1717593382
Short name T390
Test name
Test status
Simulation time 8116423535 ps
CPU time 23.86 seconds
Started Mar 10 01:52:16 PM PDT 24
Finished Mar 10 01:52:40 PM PDT 24
Peak memory 215768 kb
Host smart-c6e73aa0-cd13-4d04-9e23-c32d5505cc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717593382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1717593382
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2094340905
Short name T387
Test name
Test status
Simulation time 571591173 ps
CPU time 1.46 seconds
Started Mar 10 02:48:47 PM PDT 24
Finished Mar 10 02:48:51 PM PDT 24
Peak memory 206148 kb
Host smart-7f18c390-0dfe-4dce-a00b-1de474cb703b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094340905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2094340905
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1215574682
Short name T582
Test name
Test status
Simulation time 557593055 ps
CPU time 15.23 seconds
Started Mar 10 02:48:45 PM PDT 24
Finished Mar 10 02:49:01 PM PDT 24
Peak memory 215884 kb
Host smart-11cfc84f-51d1-494b-89ed-4ee98fb4ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215574682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1215574682
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1715079984
Short name T1487
Test name
Test status
Simulation time 207589908 ps
CPU time 3.2 seconds
Started Mar 10 01:52:14 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 215756 kb
Host smart-65be7c8b-2ba4-41e6-a68f-f6fab4fe773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715079984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1715079984
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.183918
Short name T468
Test name
Test status
Simulation time 234587412 ps
CPU time 1.12 seconds
Started Mar 10 01:52:12 PM PDT 24
Finished Mar 10 01:52:14 PM PDT 24
Peak memory 205904 kb
Host smart-ca41e8ab-4948-4e22-ba8a-7854c1200ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.183918
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3643522475
Short name T1617
Test name
Test status
Simulation time 75176801 ps
CPU time 0.84 seconds
Started Mar 10 02:48:46 PM PDT 24
Finished Mar 10 02:48:47 PM PDT 24
Peak memory 204876 kb
Host smart-a6ae2321-afa5-4df5-aba8-4f0908362a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643522475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3643522475
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2927092563
Short name T1706
Test name
Test status
Simulation time 5760722811 ps
CPU time 17.61 seconds
Started Mar 10 01:52:17 PM PDT 24
Finished Mar 10 01:52:34 PM PDT 24
Peak memory 235084 kb
Host smart-55ee772e-9719-4105-ac54-ed103933b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927092563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2927092563
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_upload.764955557
Short name T908
Test name
Test status
Simulation time 10059876292 ps
CPU time 24.87 seconds
Started Mar 10 02:48:47 PM PDT 24
Finished Mar 10 02:49:15 PM PDT 24
Peak memory 248480 kb
Host smart-8e71ddfd-f870-43f2-933a-b2fc1037dcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764955557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.764955557
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3501985907
Short name T298
Test name
Test status
Simulation time 15934907 ps
CPU time 0.72 seconds
Started Mar 10 02:48:54 PM PDT 24
Finished Mar 10 02:48:56 PM PDT 24
Peak memory 204752 kb
Host smart-30bbb107-284e-4911-b9f8-a9cc037398ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501985907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3501985907
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4213853708
Short name T1308
Test name
Test status
Simulation time 17047416 ps
CPU time 0.72 seconds
Started Mar 10 01:52:24 PM PDT 24
Finished Mar 10 01:52:25 PM PDT 24
Peak memory 204420 kb
Host smart-29a946aa-efaa-4a43-b51c-c2169b219574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213853708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4213853708
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3840478052
Short name T1923
Test name
Test status
Simulation time 342768667 ps
CPU time 2.46 seconds
Started Mar 10 02:48:49 PM PDT 24
Finished Mar 10 02:48:54 PM PDT 24
Peak memory 223756 kb
Host smart-db7149bd-716f-4bf2-883e-97992b4c8722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840478052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3840478052
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4118232710
Short name T872
Test name
Test status
Simulation time 55085991 ps
CPU time 2.68 seconds
Started Mar 10 01:52:17 PM PDT 24
Finished Mar 10 01:52:20 PM PDT 24
Peak memory 216192 kb
Host smart-fb634301-e022-4b55-a456-3e4c131fff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118232710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4118232710
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2606610349
Short name T850
Test name
Test status
Simulation time 16629547 ps
CPU time 0.76 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:48:53 PM PDT 24
Peak memory 204756 kb
Host smart-6a604508-72e0-4d02-9bd8-b994f93a617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606610349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2606610349
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.521674298
Short name T1377
Test name
Test status
Simulation time 34832402 ps
CPU time 0.78 seconds
Started Mar 10 01:52:14 PM PDT 24
Finished Mar 10 01:52:15 PM PDT 24
Peak memory 205844 kb
Host smart-2c7d51fc-dd3d-478f-8551-accbf8175c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521674298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.521674298
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3170042790
Short name T400
Test name
Test status
Simulation time 33990724507 ps
CPU time 120.22 seconds
Started Mar 10 02:48:54 PM PDT 24
Finished Mar 10 02:50:56 PM PDT 24
Peak memory 251244 kb
Host smart-b9d8ca5b-416b-426f-a42a-8c79585b6e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170042790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3170042790
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3614830072
Short name T1691
Test name
Test status
Simulation time 26013520944 ps
CPU time 108.02 seconds
Started Mar 10 01:52:16 PM PDT 24
Finished Mar 10 01:54:04 PM PDT 24
Peak memory 268728 kb
Host smart-52e4bb44-1050-4d3f-a91e-1c59091a6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614830072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3614830072
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1290354442
Short name T1530
Test name
Test status
Simulation time 94881052441 ps
CPU time 193.08 seconds
Started Mar 10 01:52:20 PM PDT 24
Finished Mar 10 01:55:33 PM PDT 24
Peak memory 266496 kb
Host smart-6ff9d8b8-ae84-486a-88e0-ca6a7f1530ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290354442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1290354442
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2359040863
Short name T1606
Test name
Test status
Simulation time 576842393928 ps
CPU time 445.66 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:56:24 PM PDT 24
Peak memory 250036 kb
Host smart-3e05b0bb-3d19-42d2-89a4-212024c22c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359040863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2359040863
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3056830529
Short name T1545
Test name
Test status
Simulation time 70712127927 ps
CPU time 134.24 seconds
Started Mar 10 01:52:22 PM PDT 24
Finished Mar 10 01:54:36 PM PDT 24
Peak memory 248692 kb
Host smart-b0921a63-0668-4f9d-9b74-b83fab3b932f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056830529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3056830529
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3619215074
Short name T1867
Test name
Test status
Simulation time 34360409179 ps
CPU time 239.22 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:52:51 PM PDT 24
Peak memory 250160 kb
Host smart-4839fe0d-ed49-47a7-a6e5-901f8da090cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619215074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3619215074
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1055091686
Short name T1926
Test name
Test status
Simulation time 479144569 ps
CPU time 12.87 seconds
Started Mar 10 01:52:16 PM PDT 24
Finished Mar 10 01:52:29 PM PDT 24
Peak memory 228480 kb
Host smart-deaa2a89-9648-41a5-aea3-69d183858664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055091686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1055091686
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.820974903
Short name T1540
Test name
Test status
Simulation time 3972088678 ps
CPU time 15.26 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 233180 kb
Host smart-03240c70-3997-4e9f-8f78-2260adba4f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820974903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.820974903
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2209863227
Short name T640
Test name
Test status
Simulation time 226275660 ps
CPU time 3.62 seconds
Started Mar 10 02:48:52 PM PDT 24
Finished Mar 10 02:48:56 PM PDT 24
Peak memory 223904 kb
Host smart-3737dd1b-86ed-4a99-a2e9-e88043800b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209863227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2209863227
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intercept.609631969
Short name T1749
Test name
Test status
Simulation time 6635733685 ps
CPU time 3.98 seconds
Started Mar 10 01:52:17 PM PDT 24
Finished Mar 10 01:52:21 PM PDT 24
Peak memory 233384 kb
Host smart-f374274f-d70c-4dfd-bc2e-e330a24ca620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609631969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.609631969
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1363362280
Short name T709
Test name
Test status
Simulation time 39525811663 ps
CPU time 48.83 seconds
Started Mar 10 01:52:17 PM PDT 24
Finished Mar 10 01:53:06 PM PDT 24
Peak memory 240196 kb
Host smart-1e129c51-b656-4452-bb13-cec7bfecb16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363362280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1363362280
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4070016827
Short name T1346
Test name
Test status
Simulation time 11108027356 ps
CPU time 20.81 seconds
Started Mar 10 02:48:49 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 231296 kb
Host smart-2852d607-d5fc-491c-82eb-bd95be05f811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070016827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4070016827
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1092637872
Short name T236
Test name
Test status
Simulation time 27142759551 ps
CPU time 23.25 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:49:15 PM PDT 24
Peak memory 235472 kb
Host smart-aa716553-4d80-4cdb-8f5f-37931be90231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092637872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1092637872
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1714631396
Short name T1046
Test name
Test status
Simulation time 1192368689 ps
CPU time 5.81 seconds
Started Mar 10 01:52:18 PM PDT 24
Finished Mar 10 01:52:24 PM PDT 24
Peak memory 235988 kb
Host smart-ba4bd3a4-cb0f-4ea3-9dea-c4436fe7ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714631396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1714631396
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2613459907
Short name T537
Test name
Test status
Simulation time 6517045579 ps
CPU time 8.08 seconds
Started Mar 10 01:52:17 PM PDT 24
Finished Mar 10 01:52:25 PM PDT 24
Peak memory 240192 kb
Host smart-e745230e-9f73-4b73-b9d4-ef757514a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613459907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2613459907
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3152084678
Short name T1012
Test name
Test status
Simulation time 3839186743 ps
CPU time 10.83 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:49:02 PM PDT 24
Peak memory 247176 kb
Host smart-c1d6f1c3-adca-47d4-8bea-e7b1e3e055ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152084678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3152084678
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1111226249
Short name T771
Test name
Test status
Simulation time 374660459 ps
CPU time 3.78 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:48:57 PM PDT 24
Peak memory 218832 kb
Host smart-dcc4ea7d-652f-45ff-a09d-363642e189d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1111226249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1111226249
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3654469155
Short name T1599
Test name
Test status
Simulation time 1788569182 ps
CPU time 5.68 seconds
Started Mar 10 01:52:18 PM PDT 24
Finished Mar 10 01:52:24 PM PDT 24
Peak memory 222004 kb
Host smart-64abc5c4-ec66-4e20-a0e8-a046886811f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654469155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3654469155
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1924985473
Short name T1135
Test name
Test status
Simulation time 48568811 ps
CPU time 1.05 seconds
Started Mar 10 02:48:51 PM PDT 24
Finished Mar 10 02:48:54 PM PDT 24
Peak memory 205844 kb
Host smart-8ef209ae-cb56-491e-b8a8-de95369bddc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924985473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1924985473
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3266824757
Short name T1255
Test name
Test status
Simulation time 27558168760 ps
CPU time 194.49 seconds
Started Mar 10 01:52:24 PM PDT 24
Finished Mar 10 01:55:39 PM PDT 24
Peak memory 268616 kb
Host smart-6a9feb6e-adf3-404a-a6e7-d23223d9ad53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266824757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3266824757
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1264760065
Short name T25
Test name
Test status
Simulation time 1640052049 ps
CPU time 16.17 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:49:08 PM PDT 24
Peak memory 215712 kb
Host smart-572cce8a-ca42-43b0-93ae-1a915536bc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264760065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1264760065
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3019560759
Short name T910
Test name
Test status
Simulation time 9557704172 ps
CPU time 51.64 seconds
Started Mar 10 01:52:18 PM PDT 24
Finished Mar 10 01:53:10 PM PDT 24
Peak memory 215864 kb
Host smart-91152e37-f3bf-4b44-a849-55c72755fe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019560759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3019560759
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.165482704
Short name T1557
Test name
Test status
Simulation time 12809599012 ps
CPU time 14.37 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:49:13 PM PDT 24
Peak memory 215588 kb
Host smart-98a3b68d-4cdd-48cb-948a-c89ec7413837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165482704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.165482704
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3383697490
Short name T1260
Test name
Test status
Simulation time 84822898946 ps
CPU time 18.44 seconds
Started Mar 10 01:52:15 PM PDT 24
Finished Mar 10 01:52:34 PM PDT 24
Peak memory 215812 kb
Host smart-40577637-2666-4901-81bf-d12b5450b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383697490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3383697490
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2370750794
Short name T588
Test name
Test status
Simulation time 184185189 ps
CPU time 1.79 seconds
Started Mar 10 02:48:54 PM PDT 24
Finished Mar 10 02:48:57 PM PDT 24
Peak memory 215760 kb
Host smart-64cbc1c8-2429-423e-b664-0e4f6eed55aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370750794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2370750794
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3986677831
Short name T411
Test name
Test status
Simulation time 569276314 ps
CPU time 1.38 seconds
Started Mar 10 01:52:19 PM PDT 24
Finished Mar 10 01:52:20 PM PDT 24
Peak memory 207536 kb
Host smart-193da98f-cca3-45b8-ace9-1c0c30f522b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986677831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3986677831
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3803558324
Short name T1433
Test name
Test status
Simulation time 29792736 ps
CPU time 0.71 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:48:59 PM PDT 24
Peak memory 204828 kb
Host smart-3e0810eb-1e71-4385-bf6a-c0af1db80348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803558324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3803558324
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4094664727
Short name T1276
Test name
Test status
Simulation time 214848512 ps
CPU time 0.86 seconds
Started Mar 10 01:52:16 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 205904 kb
Host smart-034d8ace-ba00-447e-8997-d28da83c584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094664727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4094664727
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1737594066
Short name T964
Test name
Test status
Simulation time 1963901248 ps
CPU time 3.81 seconds
Started Mar 10 01:52:16 PM PDT 24
Finished Mar 10 01:52:19 PM PDT 24
Peak memory 223844 kb
Host smart-833e2b97-dc36-488e-a7d3-50f7011ceea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737594066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1737594066
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_upload.1798571042
Short name T1198
Test name
Test status
Simulation time 122297976 ps
CPU time 3.17 seconds
Started Mar 10 02:48:52 PM PDT 24
Finished Mar 10 02:48:57 PM PDT 24
Peak memory 233476 kb
Host smart-c4baa202-34af-48d3-8718-144240d7f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798571042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1798571042
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.270186403
Short name T1861
Test name
Test status
Simulation time 12844361 ps
CPU time 0.72 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:10 PM PDT 24
Peak memory 204476 kb
Host smart-2c712116-3554-4112-ab1c-9be1d8559622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270186403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.270186403
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2812267243
Short name T288
Test name
Test status
Simulation time 43951941 ps
CPU time 0.74 seconds
Started Mar 10 01:52:25 PM PDT 24
Finished Mar 10 01:52:26 PM PDT 24
Peak memory 203856 kb
Host smart-a7b7c3b6-bdfa-42ff-91d3-9c6807fbe037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812267243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2812267243
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1508846859
Short name T1071
Test name
Test status
Simulation time 117185267 ps
CPU time 2.3 seconds
Started Mar 10 01:52:20 PM PDT 24
Finished Mar 10 01:52:23 PM PDT 24
Peak memory 232744 kb
Host smart-c38d3711-91ec-440b-afb0-178ff49bca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508846859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1508846859
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.822669525
Short name T1200
Test name
Test status
Simulation time 1078450369 ps
CPU time 3.37 seconds
Started Mar 10 02:48:55 PM PDT 24
Finished Mar 10 02:49:00 PM PDT 24
Peak memory 216772 kb
Host smart-82e608bb-93f5-45df-8c57-910874396256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822669525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.822669525
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2438975308
Short name T1659
Test name
Test status
Simulation time 72523677 ps
CPU time 0.81 seconds
Started Mar 10 01:52:23 PM PDT 24
Finished Mar 10 01:52:24 PM PDT 24
Peak memory 205844 kb
Host smart-c98bcc0c-7369-4c26-87e2-4edefea7e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438975308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2438975308
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2976669119
Short name T299
Test name
Test status
Simulation time 102920663 ps
CPU time 0.78 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:48:52 PM PDT 24
Peak memory 204464 kb
Host smart-24bfde34-3b22-4697-bdbb-f93830289f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976669119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2976669119
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1021007891
Short name T1372
Test name
Test status
Simulation time 55543296644 ps
CPU time 275.21 seconds
Started Mar 10 01:52:22 PM PDT 24
Finished Mar 10 01:56:57 PM PDT 24
Peak memory 248496 kb
Host smart-e02db881-c482-48b7-bd8d-c03a89408b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021007891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1021007891
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.407175335
Short name T560
Test name
Test status
Simulation time 10067799939 ps
CPU time 44.45 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:49:43 PM PDT 24
Peak memory 234092 kb
Host smart-f3a39961-f384-4b65-b52f-52ddf6eb38da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407175335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.407175335
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1639998525
Short name T479
Test name
Test status
Simulation time 79762302312 ps
CPU time 164.45 seconds
Started Mar 10 01:52:24 PM PDT 24
Finished Mar 10 01:55:09 PM PDT 24
Peak memory 254344 kb
Host smart-71777d32-9793-4e52-8b14-4fda9b8d095d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639998525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1639998525
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2082173444
Short name T1109
Test name
Test status
Simulation time 30484922848 ps
CPU time 156.87 seconds
Started Mar 10 02:48:56 PM PDT 24
Finished Mar 10 02:51:34 PM PDT 24
Peak memory 256856 kb
Host smart-30c9b6b1-7441-408d-a35e-8f4c352ddcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082173444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2082173444
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1792821138
Short name T971
Test name
Test status
Simulation time 27007722522 ps
CPU time 175.01 seconds
Started Mar 10 01:52:22 PM PDT 24
Finished Mar 10 01:55:17 PM PDT 24
Peak memory 254852 kb
Host smart-dcd09c79-5c71-4e24-9f23-fec82acf7c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792821138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1792821138
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2591592919
Short name T1417
Test name
Test status
Simulation time 22642579988 ps
CPU time 43.62 seconds
Started Mar 10 02:48:55 PM PDT 24
Finished Mar 10 02:49:40 PM PDT 24
Peak memory 238720 kb
Host smart-fe10b929-13de-4de8-97a7-8210aa13f5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591592919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2591592919
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3356116458
Short name T749
Test name
Test status
Simulation time 4999751923 ps
CPU time 27.92 seconds
Started Mar 10 02:48:57 PM PDT 24
Finished Mar 10 02:49:25 PM PDT 24
Peak memory 233620 kb
Host smart-929d2c4a-8b6e-48d7-a49b-c5239c0064c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356116458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3356116458
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4288027482
Short name T1571
Test name
Test status
Simulation time 11745940890 ps
CPU time 19.28 seconds
Started Mar 10 01:52:23 PM PDT 24
Finished Mar 10 01:52:43 PM PDT 24
Peak memory 233056 kb
Host smart-e036d938-9f3d-43b9-b077-c1d31cfcf3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288027482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4288027482
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3311536159
Short name T205
Test name
Test status
Simulation time 2497244544 ps
CPU time 12.02 seconds
Started Mar 10 02:48:59 PM PDT 24
Finished Mar 10 02:49:11 PM PDT 24
Peak memory 232528 kb
Host smart-c1820ae3-c867-4d5b-b2d2-c2e019c955ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311536159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3311536159
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intercept.617585399
Short name T1713
Test name
Test status
Simulation time 550944365 ps
CPU time 4.51 seconds
Started Mar 10 01:52:24 PM PDT 24
Finished Mar 10 01:52:29 PM PDT 24
Peak memory 232248 kb
Host smart-066bded2-a87c-451c-92ec-c9cde6884274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617585399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.617585399
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3317251851
Short name T1076
Test name
Test status
Simulation time 119385738199 ps
CPU time 37.06 seconds
Started Mar 10 02:48:53 PM PDT 24
Finished Mar 10 02:49:31 PM PDT 24
Peak memory 234772 kb
Host smart-5cfe28ff-28ad-4a36-b9a3-993dc6b9968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317251851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3317251851
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4158282168
Short name T1742
Test name
Test status
Simulation time 4657638869 ps
CPU time 22.86 seconds
Started Mar 10 01:52:21 PM PDT 24
Finished Mar 10 01:52:44 PM PDT 24
Peak memory 232128 kb
Host smart-8656718a-e0ab-43dd-8e78-5e0a931291e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158282168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4158282168
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1217570826
Short name T652
Test name
Test status
Simulation time 1881998279 ps
CPU time 10.31 seconds
Started Mar 10 01:52:24 PM PDT 24
Finished Mar 10 01:52:34 PM PDT 24
Peak memory 243244 kb
Host smart-d39751f5-8176-4715-8294-e9d553a27750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217570826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1217570826
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1680582392
Short name T970
Test name
Test status
Simulation time 302821930 ps
CPU time 5.3 seconds
Started Mar 10 02:48:56 PM PDT 24
Finished Mar 10 02:49:02 PM PDT 24
Peak memory 223836 kb
Host smart-ca382dd0-07fc-4d4f-b466-b64f9dee2b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680582392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1680582392
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3605532145
Short name T1924
Test name
Test status
Simulation time 3120315931 ps
CPU time 9.69 seconds
Started Mar 10 02:48:55 PM PDT 24
Finished Mar 10 02:49:06 PM PDT 24
Peak memory 217100 kb
Host smart-f12b4d3d-df7b-46bb-9de2-1c90eaabaadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605532145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3605532145
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3667874858
Short name T922
Test name
Test status
Simulation time 650476552 ps
CPU time 8.76 seconds
Started Mar 10 01:52:20 PM PDT 24
Finished Mar 10 01:52:29 PM PDT 24
Peak memory 234088 kb
Host smart-a8149596-4caa-4339-b781-33e950b809e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667874858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3667874858
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1274420863
Short name T493
Test name
Test status
Simulation time 2776637020 ps
CPU time 4.49 seconds
Started Mar 10 01:52:21 PM PDT 24
Finished Mar 10 01:52:25 PM PDT 24
Peak memory 222088 kb
Host smart-e1b02711-a013-4900-878c-948827a3c5c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274420863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1274420863
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.201416815
Short name T1636
Test name
Test status
Simulation time 598669734 ps
CPU time 3.66 seconds
Started Mar 10 02:48:53 PM PDT 24
Finished Mar 10 02:48:58 PM PDT 24
Peak memory 218000 kb
Host smart-448e7168-dedb-4060-8dc3-5d05b83522b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=201416815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.201416815
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.522474502
Short name T1932
Test name
Test status
Simulation time 67593990781 ps
CPU time 471.64 seconds
Started Mar 10 01:52:21 PM PDT 24
Finished Mar 10 02:00:13 PM PDT 24
Peak memory 273020 kb
Host smart-30de21bc-6d34-4520-b366-8faa810f7367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522474502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.522474502
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.110922978
Short name T480
Test name
Test status
Simulation time 4244575765 ps
CPU time 31.6 seconds
Started Mar 10 02:48:50 PM PDT 24
Finished Mar 10 02:49:24 PM PDT 24
Peak memory 215872 kb
Host smart-d6e83a44-0bcd-4adf-9afe-e6ec9dc47bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110922978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.110922978
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3326112945
Short name T794
Test name
Test status
Simulation time 2021041890 ps
CPU time 24.83 seconds
Started Mar 10 01:52:24 PM PDT 24
Finished Mar 10 01:52:49 PM PDT 24
Peak memory 215740 kb
Host smart-ef9b16a2-db9e-4f0f-a199-95c8b50dbde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326112945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3326112945
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1970893528
Short name T657
Test name
Test status
Simulation time 15028265893 ps
CPU time 13.61 seconds
Started Mar 10 02:48:49 PM PDT 24
Finished Mar 10 02:49:05 PM PDT 24
Peak memory 215836 kb
Host smart-8d055249-c3f8-4e3f-85a9-5eba44ba3243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970893528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1970893528
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2006969366
Short name T446
Test name
Test status
Simulation time 1547792780 ps
CPU time 6.89 seconds
Started Mar 10 01:52:21 PM PDT 24
Finished Mar 10 01:52:29 PM PDT 24
Peak memory 215964 kb
Host smart-84d5069d-16cd-4276-8caf-02c8b11cfc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006969366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2006969366
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1153031597
Short name T1762
Test name
Test status
Simulation time 349228668 ps
CPU time 5.26 seconds
Started Mar 10 01:52:24 PM PDT 24
Finished Mar 10 01:52:30 PM PDT 24
Peak memory 215720 kb
Host smart-8604c0f4-c722-48aa-92b0-bd4615edfbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153031597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1153031597
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3834907279
Short name T1325
Test name
Test status
Simulation time 329220097 ps
CPU time 1.74 seconds
Started Mar 10 02:48:53 PM PDT 24
Finished Mar 10 02:48:57 PM PDT 24
Peak memory 207108 kb
Host smart-05bc56d3-fc0f-4267-8ce9-7262fa5f484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834907279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3834907279
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3179290922
Short name T711
Test name
Test status
Simulation time 58837591 ps
CPU time 0.75 seconds
Started Mar 10 02:48:53 PM PDT 24
Finished Mar 10 02:48:56 PM PDT 24
Peak memory 204852 kb
Host smart-7d3e629a-dd9f-4b30-b203-fb62b09e5e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179290922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3179290922
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.487342409
Short name T366
Test name
Test status
Simulation time 37713985 ps
CPU time 0.85 seconds
Started Mar 10 01:52:22 PM PDT 24
Finished Mar 10 01:52:22 PM PDT 24
Peak memory 204856 kb
Host smart-fbad3df9-a82c-404e-b908-ccee02b95d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487342409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.487342409
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.326197147
Short name T552
Test name
Test status
Simulation time 9696481636 ps
CPU time 17.46 seconds
Started Mar 10 02:48:55 PM PDT 24
Finished Mar 10 02:49:14 PM PDT 24
Peak memory 223920 kb
Host smart-70af450f-4418-4575-a6ae-36bd68ae4215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326197147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.326197147
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_upload.4020194044
Short name T459
Test name
Test status
Simulation time 136291423 ps
CPU time 3.87 seconds
Started Mar 10 01:52:23 PM PDT 24
Finished Mar 10 01:52:27 PM PDT 24
Peak memory 223776 kb
Host smart-dbda81f4-16bf-4c7d-ad44-5c0cc43907c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020194044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4020194044
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2549783728
Short name T1422
Test name
Test status
Simulation time 15429280 ps
CPU time 0.75 seconds
Started Mar 10 02:49:01 PM PDT 24
Finished Mar 10 02:49:02 PM PDT 24
Peak memory 204752 kb
Host smart-6abe6751-39d4-404e-87a3-13f2ca0cfc01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549783728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2549783728
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3142344475
Short name T399
Test name
Test status
Simulation time 10701036 ps
CPU time 0.7 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 01:52:28 PM PDT 24
Peak memory 204808 kb
Host smart-2668047e-d2b3-4222-a82e-537aa70f66b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142344475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3142344475
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.285635256
Short name T1501
Test name
Test status
Simulation time 171034265 ps
CPU time 3.12 seconds
Started Mar 10 01:52:30 PM PDT 24
Finished Mar 10 01:52:34 PM PDT 24
Peak memory 232936 kb
Host smart-d7ec14e5-b949-4d7a-a33a-fd42201b9e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285635256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.285635256
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3276195168
Short name T1063
Test name
Test status
Simulation time 590462728 ps
CPU time 3.29 seconds
Started Mar 10 02:49:01 PM PDT 24
Finished Mar 10 02:49:05 PM PDT 24
Peak memory 232892 kb
Host smart-44b6a5be-c263-488c-912c-08791104c112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276195168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3276195168
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1357131370
Short name T297
Test name
Test status
Simulation time 42378806 ps
CPU time 0.78 seconds
Started Mar 10 02:48:55 PM PDT 24
Finished Mar 10 02:48:58 PM PDT 24
Peak memory 205492 kb
Host smart-6f7587f0-05c4-44dd-924b-6d1b945851f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357131370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1357131370
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4058410368
Short name T1430
Test name
Test status
Simulation time 62096517 ps
CPU time 0.74 seconds
Started Mar 10 01:52:23 PM PDT 24
Finished Mar 10 01:52:24 PM PDT 24
Peak memory 204828 kb
Host smart-42e5944f-8894-4bf2-9e05-ce784618eb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058410368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4058410368
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1470011719
Short name T1403
Test name
Test status
Simulation time 15730179831 ps
CPU time 75.85 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 01:53:43 PM PDT 24
Peak memory 256200 kb
Host smart-01837037-1d66-4fc8-904c-24b3d5dfbed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470011719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1470011719
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1915802756
Short name T132
Test name
Test status
Simulation time 5969673802 ps
CPU time 27.55 seconds
Started Mar 10 01:52:25 PM PDT 24
Finished Mar 10 01:52:53 PM PDT 24
Peak memory 220548 kb
Host smart-02c48c82-6387-489a-bd75-7e22a197579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915802756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1915802756
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2968809382
Short name T1892
Test name
Test status
Simulation time 9892165837 ps
CPU time 100.87 seconds
Started Mar 10 02:49:01 PM PDT 24
Finished Mar 10 02:50:42 PM PDT 24
Peak memory 264588 kb
Host smart-2d0822e5-9067-4823-ac22-0576aa594f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968809382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2968809382
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2367806055
Short name T38
Test name
Test status
Simulation time 52263036384 ps
CPU time 192.81 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:52:12 PM PDT 24
Peak memory 249108 kb
Host smart-0020b18a-e4c1-40fe-bcbc-8f623fad197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367806055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2367806055
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.623678691
Short name T547
Test name
Test status
Simulation time 335765028235 ps
CPU time 251.13 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 01:56:39 PM PDT 24
Peak memory 256492 kb
Host smart-2ca9d4a6-3fe2-49e6-9a0b-87935e6579dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623678691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.623678691
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1230539013
Short name T544
Test name
Test status
Simulation time 5356626230 ps
CPU time 20.86 seconds
Started Mar 10 01:52:28 PM PDT 24
Finished Mar 10 01:52:49 PM PDT 24
Peak memory 237572 kb
Host smart-9eab3039-45e0-47fa-8503-f3061e539e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230539013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1230539013
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1285470237
Short name T1561
Test name
Test status
Simulation time 1895310718 ps
CPU time 23.94 seconds
Started Mar 10 02:48:59 PM PDT 24
Finished Mar 10 02:49:24 PM PDT 24
Peak memory 235720 kb
Host smart-fb9cbfc8-11d1-4f70-a15b-acc8f3793e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285470237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1285470237
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1643968248
Short name T782
Test name
Test status
Simulation time 514764441 ps
CPU time 3.77 seconds
Started Mar 10 01:52:28 PM PDT 24
Finished Mar 10 01:52:32 PM PDT 24
Peak memory 215776 kb
Host smart-32368052-8381-4c0e-8a6e-4eb73bb17f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643968248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1643968248
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2288489717
Short name T1690
Test name
Test status
Simulation time 13294254214 ps
CPU time 14.29 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:49:13 PM PDT 24
Peak memory 234244 kb
Host smart-3b8e9cb7-397c-4d3c-81c8-5f4919f506d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288489717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2288489717
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2364292703
Short name T1708
Test name
Test status
Simulation time 3847791308 ps
CPU time 13.87 seconds
Started Mar 10 02:49:02 PM PDT 24
Finished Mar 10 02:49:16 PM PDT 24
Peak memory 247372 kb
Host smart-95ee183d-bb1c-488f-be44-ae357989263a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364292703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2364292703
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2584497945
Short name T888
Test name
Test status
Simulation time 566925544 ps
CPU time 6.79 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 01:52:34 PM PDT 24
Peak memory 237356 kb
Host smart-44d78f21-486b-4d11-a655-8d7c3b4e7559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584497945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2584497945
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3155133555
Short name T463
Test name
Test status
Simulation time 20298823881 ps
CPU time 30.25 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 01:52:58 PM PDT 24
Peak memory 232852 kb
Host smart-13dedd1e-abcd-43d8-8456-16e25d02e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155133555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3155133555
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4120638519
Short name T101
Test name
Test status
Simulation time 5195536907 ps
CPU time 3.7 seconds
Started Mar 10 02:49:01 PM PDT 24
Finished Mar 10 02:49:05 PM PDT 24
Peak memory 217092 kb
Host smart-89881ead-23ee-405d-a204-867f69d26e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120638519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4120638519
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.27961031
Short name T1718
Test name
Test status
Simulation time 1927625136 ps
CPU time 4.67 seconds
Started Mar 10 01:52:30 PM PDT 24
Finished Mar 10 01:52:35 PM PDT 24
Peak memory 216056 kb
Host smart-a1092b08-66a7-48cd-92c6-359931057fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27961031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.27961031
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4022381914
Short name T482
Test name
Test status
Simulation time 895507454 ps
CPU time 5.89 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:49:05 PM PDT 24
Peak memory 234380 kb
Host smart-42878bac-afc7-49e8-8f7a-2a579311ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022381914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4022381914
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3440026673
Short name T720
Test name
Test status
Simulation time 128044052 ps
CPU time 3.46 seconds
Started Mar 10 01:52:29 PM PDT 24
Finished Mar 10 01:52:33 PM PDT 24
Peak memory 222108 kb
Host smart-ca480209-0ad6-46b7-b293-0e736784bba4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3440026673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3440026673
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.849655879
Short name T759
Test name
Test status
Simulation time 7099672468 ps
CPU time 7.92 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 221640 kb
Host smart-2ce9e5d0-2604-4e04-9133-ae4f643ff555
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=849655879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.849655879
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1553116308
Short name T956
Test name
Test status
Simulation time 417448578965 ps
CPU time 608.18 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 02:02:35 PM PDT 24
Peak memory 272160 kb
Host smart-07331c1a-8610-460e-a706-7d2e7e43afb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553116308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1553116308
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2034548453
Short name T1818
Test name
Test status
Simulation time 75812981888 ps
CPU time 181.45 seconds
Started Mar 10 02:49:00 PM PDT 24
Finished Mar 10 02:52:02 PM PDT 24
Peak memory 267192 kb
Host smart-91840e45-f8e0-46f2-b17e-ab5eeda4f449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034548453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2034548453
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1870600036
Short name T1918
Test name
Test status
Simulation time 3231202130 ps
CPU time 15.35 seconds
Started Mar 10 02:48:55 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 215840 kb
Host smart-d8dfeb76-0abe-44c4-a0d8-1448619d8836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870600036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1870600036
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2713969997
Short name T867
Test name
Test status
Simulation time 6349128051 ps
CPU time 33.92 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 01:53:01 PM PDT 24
Peak memory 215776 kb
Host smart-bd06f00e-200e-4116-a9cf-743012340f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713969997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2713969997
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2684598090
Short name T376
Test name
Test status
Simulation time 787038594 ps
CPU time 3.6 seconds
Started Mar 10 01:52:22 PM PDT 24
Finished Mar 10 01:52:26 PM PDT 24
Peak memory 207444 kb
Host smart-57f46442-aa39-467a-bae8-d0165b98aac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684598090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2684598090
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2958911779
Short name T1910
Test name
Test status
Simulation time 1880505460 ps
CPU time 3.26 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:49:02 PM PDT 24
Peak memory 207540 kb
Host smart-9218f7a5-5573-41c5-9eb1-064c50c12e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958911779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2958911779
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3978494135
Short name T1015
Test name
Test status
Simulation time 1916490270 ps
CPU time 5.64 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 01:52:33 PM PDT 24
Peak memory 215776 kb
Host smart-10e0782d-4adc-416b-828d-94ee83a765c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978494135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3978494135
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.552793024
Short name T1552
Test name
Test status
Simulation time 74347241 ps
CPU time 1.22 seconds
Started Mar 10 02:48:56 PM PDT 24
Finished Mar 10 02:48:58 PM PDT 24
Peak memory 207332 kb
Host smart-71726f43-ffa1-4e1e-8d43-13317f26ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552793024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.552793024
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1459652102
Short name T1768
Test name
Test status
Simulation time 243864681 ps
CPU time 1.12 seconds
Started Mar 10 01:52:26 PM PDT 24
Finished Mar 10 01:52:27 PM PDT 24
Peak memory 205900 kb
Host smart-8d2a2201-18ee-4188-b689-cb6733eb0f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459652102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1459652102
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.912128459
Short name T1844
Test name
Test status
Simulation time 104566009 ps
CPU time 1 seconds
Started Mar 10 02:48:55 PM PDT 24
Finished Mar 10 02:48:58 PM PDT 24
Peak memory 205836 kb
Host smart-75c53916-d2a0-4aa5-b56a-d9c35589d855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912128459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.912128459
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2803446773
Short name T439
Test name
Test status
Simulation time 703754068 ps
CPU time 7.5 seconds
Started Mar 10 02:48:59 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 233248 kb
Host smart-0dc2de88-48a8-45d9-a265-30d1aefbd44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803446773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2803446773
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_upload.2943823346
Short name T309
Test name
Test status
Simulation time 937545787 ps
CPU time 6.54 seconds
Started Mar 10 01:52:27 PM PDT 24
Finished Mar 10 01:52:34 PM PDT 24
Peak memory 218188 kb
Host smart-e2160182-80d4-446a-b7be-1b87ef11da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943823346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2943823346
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1046139487
Short name T849
Test name
Test status
Simulation time 12565852 ps
CPU time 0.73 seconds
Started Mar 10 02:49:05 PM PDT 24
Finished Mar 10 02:49:05 PM PDT 24
Peak memory 204460 kb
Host smart-edb14004-d7e7-4166-b5ff-c1bc8bc825ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046139487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1046139487
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3920870419
Short name T762
Test name
Test status
Simulation time 20669606 ps
CPU time 0.71 seconds
Started Mar 10 01:52:32 PM PDT 24
Finished Mar 10 01:52:33 PM PDT 24
Peak memory 204452 kb
Host smart-d8618fcc-9b92-46fd-97b9-decec79931a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920870419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3920870419
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.256236975
Short name T945
Test name
Test status
Simulation time 823398735 ps
CPU time 2.5 seconds
Started Mar 10 02:49:04 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 233064 kb
Host smart-37b288bb-e08b-494f-ae23-a4e4734935d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256236975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.256236975
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3507661183
Short name T133
Test name
Test status
Simulation time 1005327315 ps
CPU time 3.9 seconds
Started Mar 10 01:52:29 PM PDT 24
Finished Mar 10 01:52:33 PM PDT 24
Peak memory 223836 kb
Host smart-b6d525df-e28b-4338-9918-a8010df16da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507661183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3507661183
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1795023180
Short name T623
Test name
Test status
Simulation time 17143793 ps
CPU time 0.83 seconds
Started Mar 10 01:52:32 PM PDT 24
Finished Mar 10 01:52:33 PM PDT 24
Peak memory 204384 kb
Host smart-dbad2377-b6c4-4ec4-bdcf-79a4d026b813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795023180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1795023180
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.822997062
Short name T294
Test name
Test status
Simulation time 42204645 ps
CPU time 0.81 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:49:00 PM PDT 24
Peak memory 205468 kb
Host smart-f1466908-1ec6-4396-b64f-e30b7ae6901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822997062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.822997062
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2250876878
Short name T1526
Test name
Test status
Simulation time 53702543645 ps
CPU time 292.88 seconds
Started Mar 10 01:52:32 PM PDT 24
Finished Mar 10 01:57:25 PM PDT 24
Peak memory 253764 kb
Host smart-9b035b8b-fc18-4a2c-809a-ac8979cfe9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250876878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2250876878
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2941488379
Short name T1003
Test name
Test status
Simulation time 110937045007 ps
CPU time 150.06 seconds
Started Mar 10 02:49:06 PM PDT 24
Finished Mar 10 02:51:36 PM PDT 24
Peak memory 249856 kb
Host smart-febfde7f-3bf7-4175-8fca-a41ed9d2e7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941488379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2941488379
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1863664046
Short name T266
Test name
Test status
Simulation time 58429235581 ps
CPU time 417.34 seconds
Started Mar 10 02:49:07 PM PDT 24
Finished Mar 10 02:56:05 PM PDT 24
Peak memory 250708 kb
Host smart-db968332-247a-4122-8b6c-471aa0849b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863664046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1863664046
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2285960224
Short name T1784
Test name
Test status
Simulation time 19534847974 ps
CPU time 136.68 seconds
Started Mar 10 01:52:34 PM PDT 24
Finished Mar 10 01:54:51 PM PDT 24
Peak memory 248676 kb
Host smart-b37961a8-5587-428a-b0cd-23a7e0ed43ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285960224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2285960224
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2414896098
Short name T1548
Test name
Test status
Simulation time 25546664884 ps
CPU time 96.71 seconds
Started Mar 10 01:52:33 PM PDT 24
Finished Mar 10 01:54:10 PM PDT 24
Peak memory 251056 kb
Host smart-6345de7c-5cb9-4b0f-8ab5-b01922e9f2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414896098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2414896098
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.96279649
Short name T191
Test name
Test status
Simulation time 35030334952 ps
CPU time 132.94 seconds
Started Mar 10 02:49:07 PM PDT 24
Finished Mar 10 02:51:20 PM PDT 24
Peak memory 237800 kb
Host smart-4674ee53-ab8d-4910-b60f-3522ac1a7cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96279649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.96279649
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2519608668
Short name T715
Test name
Test status
Simulation time 4285011085 ps
CPU time 29.33 seconds
Started Mar 10 01:52:33 PM PDT 24
Finished Mar 10 01:53:03 PM PDT 24
Peak memory 237412 kb
Host smart-0590ce7e-d024-4d3b-816e-e174b601a2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519608668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2519608668
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.352727602
Short name T594
Test name
Test status
Simulation time 12664272275 ps
CPU time 63.06 seconds
Started Mar 10 02:49:06 PM PDT 24
Finished Mar 10 02:50:10 PM PDT 24
Peak memory 240052 kb
Host smart-daae9bb7-c753-4df9-9cda-463c97704991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352727602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.352727602
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1114992569
Short name T929
Test name
Test status
Simulation time 316588932 ps
CPU time 2.55 seconds
Started Mar 10 01:52:33 PM PDT 24
Finished Mar 10 01:52:36 PM PDT 24
Peak memory 216124 kb
Host smart-b9213564-4ecb-450d-b656-ddbcd66c8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114992569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1114992569
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3608268848
Short name T742
Test name
Test status
Simulation time 1415395451 ps
CPU time 8.04 seconds
Started Mar 10 02:49:07 PM PDT 24
Finished Mar 10 02:49:15 PM PDT 24
Peak memory 232948 kb
Host smart-c2ce7b15-3d75-4d93-9064-fbb698f3baa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608268848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3608268848
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1866106660
Short name T1111
Test name
Test status
Simulation time 7825920890 ps
CPU time 15.87 seconds
Started Mar 10 01:52:34 PM PDT 24
Finished Mar 10 01:52:50 PM PDT 24
Peak memory 229596 kb
Host smart-d3f89b5f-d92a-45bb-80ac-c7155a684675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866106660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1866106660
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2915705887
Short name T1117
Test name
Test status
Simulation time 34583532 ps
CPU time 2.29 seconds
Started Mar 10 02:49:06 PM PDT 24
Finished Mar 10 02:49:08 PM PDT 24
Peak memory 232136 kb
Host smart-9bd96a46-edc4-4fe7-8ac4-881eade937c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915705887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2915705887
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3676256103
Short name T29
Test name
Test status
Simulation time 7261266321 ps
CPU time 23.59 seconds
Started Mar 10 01:52:31 PM PDT 24
Finished Mar 10 01:52:55 PM PDT 24
Peak memory 240220 kb
Host smart-c941b712-79e1-4b79-b8a5-7ec52b0a6da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676256103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3676256103
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3714587154
Short name T592
Test name
Test status
Simulation time 4794498236 ps
CPU time 8.12 seconds
Started Mar 10 02:48:59 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 232068 kb
Host smart-546db831-c85d-4d78-ba8d-6ccb63f362a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714587154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3714587154
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.109693348
Short name T788
Test name
Test status
Simulation time 30390296313 ps
CPU time 27.07 seconds
Started Mar 10 01:52:34 PM PDT 24
Finished Mar 10 01:53:01 PM PDT 24
Peak memory 248872 kb
Host smart-f4e36f5a-6409-44c5-b0fa-7a74bc23af5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109693348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.109693348
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2812927713
Short name T1380
Test name
Test status
Simulation time 67333998326 ps
CPU time 24.55 seconds
Started Mar 10 02:49:02 PM PDT 24
Finished Mar 10 02:49:26 PM PDT 24
Peak memory 249324 kb
Host smart-ecfbce7d-5595-40ae-868c-c060d1ca84fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812927713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2812927713
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.121786277
Short name T1279
Test name
Test status
Simulation time 808525148 ps
CPU time 5.86 seconds
Started Mar 10 02:49:06 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 221952 kb
Host smart-7e76f80f-a4cb-4448-a021-78217282fa7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=121786277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.121786277
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2396396664
Short name T1576
Test name
Test status
Simulation time 229621380 ps
CPU time 3.98 seconds
Started Mar 10 01:52:35 PM PDT 24
Finished Mar 10 01:52:39 PM PDT 24
Peak memory 222220 kb
Host smart-3fb5e46b-8373-4957-add9-ee8132303db6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2396396664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2396396664
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2941753784
Short name T1336
Test name
Test status
Simulation time 120156867 ps
CPU time 1.12 seconds
Started Mar 10 02:49:09 PM PDT 24
Finished Mar 10 02:49:11 PM PDT 24
Peak memory 205884 kb
Host smart-f356f654-c7cf-4e53-a2a5-31f81c223a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941753784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2941753784
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.631685905
Short name T690
Test name
Test status
Simulation time 65342841 ps
CPU time 1.13 seconds
Started Mar 10 01:52:31 PM PDT 24
Finished Mar 10 01:52:32 PM PDT 24
Peak memory 205636 kb
Host smart-fef9ec03-1f1c-4593-a7b6-3789d55de2b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631685905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.631685905
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.558209767
Short name T925
Test name
Test status
Simulation time 9907501954 ps
CPU time 26.63 seconds
Started Mar 10 01:52:34 PM PDT 24
Finished Mar 10 01:53:01 PM PDT 24
Peak memory 215844 kb
Host smart-a48a7a08-e18a-4b56-a2d6-3a1ccdae8f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558209767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.558209767
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.925953620
Short name T1123
Test name
Test status
Simulation time 2178476447 ps
CPU time 30.42 seconds
Started Mar 10 02:48:57 PM PDT 24
Finished Mar 10 02:49:28 PM PDT 24
Peak memory 215784 kb
Host smart-6aef988f-af37-4fde-afc0-0b631e4341db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925953620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.925953620
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2382385447
Short name T851
Test name
Test status
Simulation time 30849776870 ps
CPU time 22.09 seconds
Started Mar 10 02:49:00 PM PDT 24
Finished Mar 10 02:49:23 PM PDT 24
Peak memory 215800 kb
Host smart-63b3300e-dfd0-4894-9470-0b0aee96154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382385447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2382385447
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.896632440
Short name T1846
Test name
Test status
Simulation time 11024006439 ps
CPU time 16.51 seconds
Started Mar 10 01:52:31 PM PDT 24
Finished Mar 10 01:52:48 PM PDT 24
Peak memory 215788 kb
Host smart-32aa349f-1069-4f64-a205-19effb703ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896632440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.896632440
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2713672732
Short name T858
Test name
Test status
Simulation time 293002602 ps
CPU time 2.27 seconds
Started Mar 10 01:52:34 PM PDT 24
Finished Mar 10 01:52:37 PM PDT 24
Peak memory 208316 kb
Host smart-418540a7-f4ae-4330-b33e-88fc4a406464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713672732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2713672732
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3317478064
Short name T514
Test name
Test status
Simulation time 1422793062 ps
CPU time 4.07 seconds
Started Mar 10 02:48:59 PM PDT 24
Finished Mar 10 02:49:03 PM PDT 24
Peak memory 215920 kb
Host smart-708f8cf2-b336-4f01-b6d0-ea9eaf8c9575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317478064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3317478064
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2776499055
Short name T1685
Test name
Test status
Simulation time 117311912 ps
CPU time 0.89 seconds
Started Mar 10 01:52:31 PM PDT 24
Finished Mar 10 01:52:32 PM PDT 24
Peak memory 204876 kb
Host smart-705bd604-3d82-42db-a442-fe16b6fce404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776499055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2776499055
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4062531530
Short name T1738
Test name
Test status
Simulation time 245325245 ps
CPU time 0.89 seconds
Started Mar 10 02:48:58 PM PDT 24
Finished Mar 10 02:49:00 PM PDT 24
Peak memory 205232 kb
Host smart-1eac17c2-d00b-4056-a294-a732060e310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062531530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4062531530
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3676775261
Short name T1538
Test name
Test status
Simulation time 472305738 ps
CPU time 3.41 seconds
Started Mar 10 01:52:33 PM PDT 24
Finished Mar 10 01:52:37 PM PDT 24
Peak memory 218192 kb
Host smart-b5f3078d-2d84-41d6-aad0-c73ada0d2137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676775261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3676775261
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_upload.70723452
Short name T1611
Test name
Test status
Simulation time 657533391 ps
CPU time 3.86 seconds
Started Mar 10 02:49:06 PM PDT 24
Finished Mar 10 02:49:10 PM PDT 24
Peak memory 216720 kb
Host smart-752764b3-4501-4478-936c-c0d2dc746252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70723452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.70723452
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1757637957
Short name T656
Test name
Test status
Simulation time 31368728 ps
CPU time 0.68 seconds
Started Mar 10 01:52:36 PM PDT 24
Finished Mar 10 01:52:37 PM PDT 24
Peak memory 204444 kb
Host smart-2a30037a-79ee-44bc-a220-3b71182e9083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757637957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1757637957
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.573840376
Short name T876
Test name
Test status
Simulation time 157756145 ps
CPU time 0.7 seconds
Started Mar 10 02:49:08 PM PDT 24
Finished Mar 10 02:49:09 PM PDT 24
Peak memory 203872 kb
Host smart-8546a422-a763-4ea8-8f8f-12585e9d9a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573840376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.573840376
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1891793752
Short name T1146
Test name
Test status
Simulation time 905966192 ps
CPU time 2.68 seconds
Started Mar 10 02:49:05 PM PDT 24
Finished Mar 10 02:49:08 PM PDT 24
Peak memory 217392 kb
Host smart-b324d4a9-d5b2-47ba-8d37-6dfd8d5f4894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891793752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1891793752
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2627297513
Short name T1441
Test name
Test status
Simulation time 5028624194 ps
CPU time 8.47 seconds
Started Mar 10 01:52:36 PM PDT 24
Finished Mar 10 01:52:45 PM PDT 24
Peak memory 219904 kb
Host smart-1ee9a999-16c6-4188-a542-cd35159bcfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627297513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2627297513
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1351945264
Short name T324
Test name
Test status
Simulation time 64068811 ps
CPU time 0.78 seconds
Started Mar 10 01:52:32 PM PDT 24
Finished Mar 10 01:52:33 PM PDT 24
Peak memory 205496 kb
Host smart-4e683373-4edf-4f76-ae0f-b78565809aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351945264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1351945264
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2621207673
Short name T1263
Test name
Test status
Simulation time 20161539 ps
CPU time 0.78 seconds
Started Mar 10 02:49:06 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 205476 kb
Host smart-4a91d181-8b89-4b6d-bf53-a6c605de03b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621207673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2621207673
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4259613980
Short name T186
Test name
Test status
Simulation time 173759744945 ps
CPU time 223.83 seconds
Started Mar 10 01:52:37 PM PDT 24
Finished Mar 10 01:56:21 PM PDT 24
Peak memory 256688 kb
Host smart-c5b198cd-c0a1-43f4-aaee-f561c0be3bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259613980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4259613980
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1900404176
Short name T1376
Test name
Test status
Simulation time 24175661429 ps
CPU time 52.72 seconds
Started Mar 10 02:49:07 PM PDT 24
Finished Mar 10 02:50:00 PM PDT 24
Peak memory 248472 kb
Host smart-1f88efe0-6bc3-498b-95d3-852dcd34e27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900404176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1900404176
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3216302971
Short name T1252
Test name
Test status
Simulation time 550534547222 ps
CPU time 735.29 seconds
Started Mar 10 01:52:43 PM PDT 24
Finished Mar 10 02:04:58 PM PDT 24
Peak memory 281464 kb
Host smart-baf03bc4-0df0-4f7e-94fb-ef1c85987e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216302971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3216302971
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2631246323
Short name T939
Test name
Test status
Simulation time 18910833560 ps
CPU time 52.08 seconds
Started Mar 10 02:49:14 PM PDT 24
Finished Mar 10 02:50:07 PM PDT 24
Peak memory 249332 kb
Host smart-2bc9576c-dfc5-4b29-a495-42b9f7458e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631246323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2631246323
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4275175741
Short name T54
Test name
Test status
Simulation time 48979847545 ps
CPU time 56.21 seconds
Started Mar 10 01:52:42 PM PDT 24
Finished Mar 10 01:53:39 PM PDT 24
Peak memory 240304 kb
Host smart-04b7903e-d32c-487a-9a79-a0e913695aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275175741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4275175741
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3191928520
Short name T1587
Test name
Test status
Simulation time 1997877420 ps
CPU time 20.37 seconds
Started Mar 10 01:52:36 PM PDT 24
Finished Mar 10 01:52:57 PM PDT 24
Peak memory 248312 kb
Host smart-9870b028-571f-4956-abce-0eb8d8cb75a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191928520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3191928520
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1651436885
Short name T1532
Test name
Test status
Simulation time 8461138934 ps
CPU time 7.84 seconds
Started Mar 10 01:52:37 PM PDT 24
Finished Mar 10 01:52:45 PM PDT 24
Peak memory 232868 kb
Host smart-6df3ec07-bd55-4bfb-a6ed-d57be1db1ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651436885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1651436885
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3130539722
Short name T645
Test name
Test status
Simulation time 6663928979 ps
CPU time 5.78 seconds
Started Mar 10 02:49:05 PM PDT 24
Finished Mar 10 02:49:10 PM PDT 24
Peak memory 217980 kb
Host smart-f8607d0d-6cb2-450f-a508-c86a5d9f50e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130539722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3130539722
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2824349282
Short name T1398
Test name
Test status
Simulation time 76842366508 ps
CPU time 51.06 seconds
Started Mar 10 01:52:36 PM PDT 24
Finished Mar 10 01:53:28 PM PDT 24
Peak memory 248480 kb
Host smart-6d170160-dafe-4439-8d9b-e047d10cc4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824349282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2824349282
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.656275332
Short name T1351
Test name
Test status
Simulation time 12448740147 ps
CPU time 8.21 seconds
Started Mar 10 02:49:06 PM PDT 24
Finished Mar 10 02:49:14 PM PDT 24
Peak memory 232128 kb
Host smart-a84de6fb-b9e7-49b0-8cca-23313ff56aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656275332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.656275332
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2182635827
Short name T237
Test name
Test status
Simulation time 6589276080 ps
CPU time 11.55 seconds
Started Mar 10 02:49:06 PM PDT 24
Finished Mar 10 02:49:17 PM PDT 24
Peak memory 232864 kb
Host smart-a6987c0b-6df7-4ad5-ad40-b0b84a043dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182635827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2182635827
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.415496282
Short name T1104
Test name
Test status
Simulation time 23698086291 ps
CPU time 35.9 seconds
Started Mar 10 01:52:34 PM PDT 24
Finished Mar 10 01:53:10 PM PDT 24
Peak memory 233936 kb
Host smart-451b0f70-c1e2-464a-b2af-052df0767db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415496282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.415496282
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1658272018
Short name T1187
Test name
Test status
Simulation time 6640751803 ps
CPU time 12.59 seconds
Started Mar 10 01:52:35 PM PDT 24
Finished Mar 10 01:52:48 PM PDT 24
Peak memory 223900 kb
Host smart-1dd5240e-cb2a-4f53-ab1d-f141806fd854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658272018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1658272018
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2020270986
Short name T1852
Test name
Test status
Simulation time 668051020 ps
CPU time 5.07 seconds
Started Mar 10 02:49:05 PM PDT 24
Finished Mar 10 02:49:10 PM PDT 24
Peak memory 217168 kb
Host smart-619e7890-3a70-4257-a0a0-42a879e23063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020270986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2020270986
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3018890213
Short name T1113
Test name
Test status
Simulation time 3172165338 ps
CPU time 7.57 seconds
Started Mar 10 01:52:35 PM PDT 24
Finished Mar 10 01:52:43 PM PDT 24
Peak memory 222080 kb
Host smart-221c3fb1-10b0-4cec-b365-30f77a99c5ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3018890213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3018890213
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3127099739
Short name T599
Test name
Test status
Simulation time 1497639519 ps
CPU time 5.17 seconds
Started Mar 10 02:49:08 PM PDT 24
Finished Mar 10 02:49:13 PM PDT 24
Peak memory 222028 kb
Host smart-c4027d91-1d78-4068-a689-43d5e4e94b55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3127099739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3127099739
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2954753401
Short name T1505
Test name
Test status
Simulation time 114550783 ps
CPU time 1.04 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:11 PM PDT 24
Peak memory 206200 kb
Host smart-a320dd25-88ae-4158-99bf-cc35db12d409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954753401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2954753401
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.953968340
Short name T1503
Test name
Test status
Simulation time 175069201 ps
CPU time 0.97 seconds
Started Mar 10 01:52:37 PM PDT 24
Finished Mar 10 01:52:38 PM PDT 24
Peak memory 205520 kb
Host smart-8d7684d7-1fa8-44b3-9c2c-467189ea5bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953968340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.953968340
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1168290056
Short name T1763
Test name
Test status
Simulation time 11501321855 ps
CPU time 65.39 seconds
Started Mar 10 02:49:05 PM PDT 24
Finished Mar 10 02:50:10 PM PDT 24
Peak memory 215760 kb
Host smart-a510f6cb-d80f-4719-b196-b70df91ad21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168290056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1168290056
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.999138880
Short name T474
Test name
Test status
Simulation time 2263562850 ps
CPU time 37.79 seconds
Started Mar 10 01:52:39 PM PDT 24
Finished Mar 10 01:53:18 PM PDT 24
Peak memory 215844 kb
Host smart-2d5485c3-b6f8-4793-8cbc-c4ef8f966497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999138880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.999138880
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1611180150
Short name T1823
Test name
Test status
Simulation time 2122786941 ps
CPU time 6.18 seconds
Started Mar 10 02:49:05 PM PDT 24
Finished Mar 10 02:49:11 PM PDT 24
Peak memory 215940 kb
Host smart-ae0998ec-4c33-4e85-946f-46c7fc84fd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611180150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1611180150
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2721237415
Short name T381
Test name
Test status
Simulation time 17581837462 ps
CPU time 29.67 seconds
Started Mar 10 01:52:38 PM PDT 24
Finished Mar 10 01:53:08 PM PDT 24
Peak memory 215708 kb
Host smart-181c033f-4ed7-4c8d-8909-689c45e7cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721237415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2721237415
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2491433506
Short name T1238
Test name
Test status
Simulation time 98472153 ps
CPU time 4.16 seconds
Started Mar 10 01:52:42 PM PDT 24
Finished Mar 10 01:52:47 PM PDT 24
Peak memory 215996 kb
Host smart-1286c11f-cf51-4002-94d2-9785f78ca15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491433506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2491433506
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3281653892
Short name T406
Test name
Test status
Simulation time 16641325 ps
CPU time 0.89 seconds
Started Mar 10 02:49:05 PM PDT 24
Finished Mar 10 02:49:06 PM PDT 24
Peak memory 205904 kb
Host smart-02ead48a-d40b-437a-86d0-1afd4d6db1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281653892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3281653892
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2712771163
Short name T336
Test name
Test status
Simulation time 573201075 ps
CPU time 1.2 seconds
Started Mar 10 01:52:37 PM PDT 24
Finished Mar 10 01:52:39 PM PDT 24
Peak memory 205804 kb
Host smart-d200c623-1927-42e9-b69d-e43859b862d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712771163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2712771163
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3609262989
Short name T1096
Test name
Test status
Simulation time 292760715 ps
CPU time 1.23 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 205936 kb
Host smart-3624e3bf-5fca-4c87-8253-548da5c6750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609262989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3609262989
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2233479392
Short name T247
Test name
Test status
Simulation time 142443329 ps
CPU time 2.35 seconds
Started Mar 10 02:49:05 PM PDT 24
Finished Mar 10 02:49:08 PM PDT 24
Peak memory 216808 kb
Host smart-36892ec2-93a0-4d04-a9c7-8a3ea4d7b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233479392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2233479392
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_upload.2313890942
Short name T1128
Test name
Test status
Simulation time 119998315 ps
CPU time 2.78 seconds
Started Mar 10 01:52:38 PM PDT 24
Finished Mar 10 01:52:42 PM PDT 24
Peak memory 223852 kb
Host smart-2e1ddcab-6016-4737-b323-e6779253488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313890942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2313890942
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1917778211
Short name T981
Test name
Test status
Simulation time 11765917 ps
CPU time 0.69 seconds
Started Mar 10 01:52:41 PM PDT 24
Finished Mar 10 01:52:43 PM PDT 24
Peak memory 204356 kb
Host smart-f81f4958-b2a4-45d1-96f9-01065d6b1d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917778211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1917778211
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2967721142
Short name T740
Test name
Test status
Simulation time 13111368 ps
CPU time 0.73 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:11 PM PDT 24
Peak memory 204452 kb
Host smart-41943ba4-f357-4296-aadd-ba561fc41ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967721142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2967721142
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1853752511
Short name T1286
Test name
Test status
Simulation time 916104830 ps
CPU time 3.16 seconds
Started Mar 10 01:52:42 PM PDT 24
Finished Mar 10 01:52:46 PM PDT 24
Peak memory 217540 kb
Host smart-d5df69ce-04c1-4ca6-9354-67b15a8bb348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853752511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1853752511
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3159070524
Short name T1313
Test name
Test status
Simulation time 263457236 ps
CPU time 2.91 seconds
Started Mar 10 02:49:14 PM PDT 24
Finished Mar 10 02:49:17 PM PDT 24
Peak memory 217212 kb
Host smart-ce408623-2b89-41d8-b8b1-98b702fae210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159070524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3159070524
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1178644816
Short name T1425
Test name
Test status
Simulation time 12635519 ps
CPU time 0.76 seconds
Started Mar 10 02:49:12 PM PDT 24
Finished Mar 10 02:49:13 PM PDT 24
Peak memory 204492 kb
Host smart-3cfe843d-ba24-4435-a60b-935577871fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178644816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1178644816
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3887170115
Short name T359
Test name
Test status
Simulation time 204910850 ps
CPU time 0.79 seconds
Started Mar 10 01:52:43 PM PDT 24
Finished Mar 10 01:52:44 PM PDT 24
Peak memory 205572 kb
Host smart-01ca541d-58bd-452f-b518-7ae79e13aec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887170115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3887170115
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2504076951
Short name T1315
Test name
Test status
Simulation time 17983610820 ps
CPU time 28.76 seconds
Started Mar 10 02:49:12 PM PDT 24
Finished Mar 10 02:49:41 PM PDT 24
Peak memory 233980 kb
Host smart-e83024af-4a0b-420b-b2fa-98a2e85fd9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504076951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2504076951
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2829880198
Short name T1472
Test name
Test status
Simulation time 104825558819 ps
CPU time 193.28 seconds
Started Mar 10 01:52:41 PM PDT 24
Finished Mar 10 01:55:55 PM PDT 24
Peak memory 250872 kb
Host smart-b89f78c6-e7fc-499d-89fd-c9208c066d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829880198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2829880198
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3925540169
Short name T611
Test name
Test status
Simulation time 26751392487 ps
CPU time 210.46 seconds
Started Mar 10 01:52:42 PM PDT 24
Finished Mar 10 01:56:13 PM PDT 24
Peak memory 248644 kb
Host smart-dfe4aae0-5dff-4a4d-9ef7-aefdd7fc2a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925540169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3925540169
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4113490267
Short name T1887
Test name
Test status
Simulation time 8006338095 ps
CPU time 50.29 seconds
Started Mar 10 02:49:12 PM PDT 24
Finished Mar 10 02:50:02 PM PDT 24
Peak memory 232300 kb
Host smart-7021c061-8f61-4065-ba3d-b4ffcfd6dd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113490267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4113490267
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1483723024
Short name T14
Test name
Test status
Simulation time 327976500742 ps
CPU time 368.99 seconds
Started Mar 10 02:49:16 PM PDT 24
Finished Mar 10 02:55:25 PM PDT 24
Peak memory 255440 kb
Host smart-a8dd69ab-3e57-4370-8bac-1f03837e9ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483723024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1483723024
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1841556733
Short name T1180
Test name
Test status
Simulation time 1054055654246 ps
CPU time 354.43 seconds
Started Mar 10 01:52:48 PM PDT 24
Finished Mar 10 01:58:43 PM PDT 24
Peak memory 248676 kb
Host smart-ba649dad-07fd-456a-8d6f-c1629d263783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841556733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1841556733
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1246499248
Short name T472
Test name
Test status
Simulation time 26253677730 ps
CPU time 34.34 seconds
Started Mar 10 01:52:40 PM PDT 24
Finished Mar 10 01:53:14 PM PDT 24
Peak memory 234424 kb
Host smart-d509bbc1-d61c-4cbc-9930-bba0f34df71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246499248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1246499248
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3989742884
Short name T1257
Test name
Test status
Simulation time 684689546 ps
CPU time 11.15 seconds
Started Mar 10 02:49:12 PM PDT 24
Finished Mar 10 02:49:24 PM PDT 24
Peak memory 240224 kb
Host smart-42592fc9-d752-4ee2-a558-684070f06336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989742884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3989742884
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4218993752
Short name T221
Test name
Test status
Simulation time 334793750 ps
CPU time 3.11 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:14 PM PDT 24
Peak memory 233444 kb
Host smart-63886368-29a8-411c-a9db-87fb458521a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218993752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4218993752
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intercept.700513221
Short name T1845
Test name
Test status
Simulation time 298635777 ps
CPU time 2.92 seconds
Started Mar 10 01:52:48 PM PDT 24
Finished Mar 10 01:52:51 PM PDT 24
Peak memory 233544 kb
Host smart-d38099db-a15e-4f2f-ad4a-67b4b145fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700513221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.700513221
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2493653159
Short name T1683
Test name
Test status
Simulation time 9792806167 ps
CPU time 27.44 seconds
Started Mar 10 01:52:41 PM PDT 24
Finished Mar 10 01:53:09 PM PDT 24
Peak memory 231784 kb
Host smart-1299a1e0-1741-47e1-981d-566cadca0e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493653159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2493653159
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3580628551
Short name T506
Test name
Test status
Simulation time 1126644322 ps
CPU time 8.77 seconds
Started Mar 10 02:49:12 PM PDT 24
Finished Mar 10 02:49:21 PM PDT 24
Peak memory 234008 kb
Host smart-c643f06e-e01c-4888-80eb-562a33914ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580628551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3580628551
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2263989517
Short name T892
Test name
Test status
Simulation time 1492585191 ps
CPU time 6.78 seconds
Started Mar 10 01:52:43 PM PDT 24
Finished Mar 10 01:52:51 PM PDT 24
Peak memory 232988 kb
Host smart-56710e5c-42c2-4767-9b30-c63cb5ab6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263989517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2263989517
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2994617341
Short name T464
Test name
Test status
Simulation time 14208006483 ps
CPU time 5.72 seconds
Started Mar 10 02:49:11 PM PDT 24
Finished Mar 10 02:49:17 PM PDT 24
Peak memory 232936 kb
Host smart-e838629c-8f03-4bb5-bd2f-b5db343ac129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994617341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2994617341
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3172481868
Short name T1803
Test name
Test status
Simulation time 39959801380 ps
CPU time 31.62 seconds
Started Mar 10 01:52:40 PM PDT 24
Finished Mar 10 01:53:13 PM PDT 24
Peak memory 237204 kb
Host smart-e75414a8-c074-4e27-bbd6-1063d978599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172481868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3172481868
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3601988460
Short name T1601
Test name
Test status
Simulation time 29628412281 ps
CPU time 22.07 seconds
Started Mar 10 02:49:12 PM PDT 24
Finished Mar 10 02:49:34 PM PDT 24
Peak memory 226608 kb
Host smart-1a5a6c7b-577d-457a-9d14-c5626f6bb3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601988460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3601988460
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1302705168
Short name T949
Test name
Test status
Simulation time 871929344 ps
CPU time 5.92 seconds
Started Mar 10 01:52:40 PM PDT 24
Finished Mar 10 01:52:47 PM PDT 24
Peak memory 221696 kb
Host smart-a3e03aa5-d470-480e-8214-2ffb9ff07662
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1302705168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1302705168
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1856379553
Short name T1517
Test name
Test status
Simulation time 4602951250 ps
CPU time 6.58 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:17 PM PDT 24
Peak memory 221564 kb
Host smart-fb6e66df-1d92-4767-ad5a-201df326ca40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1856379553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1856379553
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1333915059
Short name T730
Test name
Test status
Simulation time 18170988405 ps
CPU time 26.39 seconds
Started Mar 10 01:52:36 PM PDT 24
Finished Mar 10 01:53:03 PM PDT 24
Peak memory 215668 kb
Host smart-8751029c-de0f-4601-97d9-2ef738781196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333915059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1333915059
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3354241910
Short name T1541
Test name
Test status
Simulation time 5517036619 ps
CPU time 14.55 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:25 PM PDT 24
Peak memory 215832 kb
Host smart-acb13362-c39e-4ea1-a45b-7603e321d737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354241910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3354241910
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2682025643
Short name T331
Test name
Test status
Simulation time 1329045702 ps
CPU time 6.12 seconds
Started Mar 10 02:49:12 PM PDT 24
Finished Mar 10 02:49:19 PM PDT 24
Peak memory 215792 kb
Host smart-f0d5f485-75f7-45c5-97e5-3a68d4b20242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682025643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2682025643
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3531213015
Short name T1839
Test name
Test status
Simulation time 4229175612 ps
CPU time 6.59 seconds
Started Mar 10 01:52:36 PM PDT 24
Finished Mar 10 01:52:43 PM PDT 24
Peak memory 215748 kb
Host smart-717baeeb-66b7-46be-84a0-a3a3b9293c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531213015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3531213015
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2586184122
Short name T838
Test name
Test status
Simulation time 20334261 ps
CPU time 0.84 seconds
Started Mar 10 01:52:48 PM PDT 24
Finished Mar 10 01:52:49 PM PDT 24
Peak memory 204804 kb
Host smart-85b12f39-634a-4254-a50a-ce72238ef68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586184122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2586184122
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3377237752
Short name T1265
Test name
Test status
Simulation time 257708637 ps
CPU time 4.38 seconds
Started Mar 10 02:49:13 PM PDT 24
Finished Mar 10 02:49:18 PM PDT 24
Peak memory 215696 kb
Host smart-46940e4e-5c50-4e8a-929e-98ae5697ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377237752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3377237752
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2644268588
Short name T1340
Test name
Test status
Simulation time 40902638 ps
CPU time 0.78 seconds
Started Mar 10 02:49:11 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 204892 kb
Host smart-953d6e9c-4095-4105-9b86-196174f728ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644268588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2644268588
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2682581407
Short name T1855
Test name
Test status
Simulation time 126288471 ps
CPU time 1.03 seconds
Started Mar 10 01:52:41 PM PDT 24
Finished Mar 10 01:52:42 PM PDT 24
Peak memory 204880 kb
Host smart-fd98ac95-8e7c-4ba3-962e-f9a8f7bf8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682581407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2682581407
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1632715705
Short name T637
Test name
Test status
Simulation time 3509842270 ps
CPU time 9.94 seconds
Started Mar 10 01:52:43 PM PDT 24
Finished Mar 10 01:52:54 PM PDT 24
Peak memory 233484 kb
Host smart-75bd1859-4a1b-439a-9c64-f952b4872d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632715705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1632715705
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_upload.927380207
Short name T1506
Test name
Test status
Simulation time 5303456817 ps
CPU time 14.86 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:25 PM PDT 24
Peak memory 233392 kb
Host smart-1fabc679-4b3c-4f73-9214-f91909b3a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927380207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.927380207
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2183443088
Short name T75
Test name
Test status
Simulation time 178553415 ps
CPU time 0.73 seconds
Started Mar 10 01:52:52 PM PDT 24
Finished Mar 10 01:52:53 PM PDT 24
Peak memory 203872 kb
Host smart-0633becf-b31d-48de-a5f3-bb82b80be123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183443088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2183443088
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2826212028
Short name T553
Test name
Test status
Simulation time 51869121 ps
CPU time 0.76 seconds
Started Mar 10 02:49:16 PM PDT 24
Finished Mar 10 02:49:16 PM PDT 24
Peak memory 204476 kb
Host smart-5bbd5e1f-d89a-4cb4-acb5-2e43e3ac755d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826212028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2826212028
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3119095604
Short name T290
Test name
Test status
Simulation time 3314327722 ps
CPU time 9.44 seconds
Started Mar 10 02:49:19 PM PDT 24
Finished Mar 10 02:49:29 PM PDT 24
Peak memory 232908 kb
Host smart-3d702a44-ce16-4193-8930-2365f13c1d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119095604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3119095604
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.718118717
Short name T518
Test name
Test status
Simulation time 351258575 ps
CPU time 4.18 seconds
Started Mar 10 01:52:45 PM PDT 24
Finished Mar 10 01:52:50 PM PDT 24
Peak memory 233048 kb
Host smart-871f6ebf-f15a-4feb-af76-210d421f6c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718118717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.718118717
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.110280320
Short name T1726
Test name
Test status
Simulation time 17966525 ps
CPU time 0.75 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 204756 kb
Host smart-99c75b32-3c25-44e1-99cb-bcdaf1ad134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110280320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.110280320
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1417206119
Short name T1185
Test name
Test status
Simulation time 101251006 ps
CPU time 0.78 seconds
Started Mar 10 01:52:44 PM PDT 24
Finished Mar 10 01:52:46 PM PDT 24
Peak memory 204328 kb
Host smart-73677cbc-bcfa-4725-837f-bdadd427385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417206119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1417206119
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1542145804
Short name T1642
Test name
Test status
Simulation time 54174259301 ps
CPU time 206.41 seconds
Started Mar 10 01:52:45 PM PDT 24
Finished Mar 10 01:56:12 PM PDT 24
Peak memory 256736 kb
Host smart-06883aa5-dec2-4ba1-98b0-5275efa60c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542145804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1542145804
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2628944958
Short name T1299
Test name
Test status
Simulation time 17640521829 ps
CPU time 87.9 seconds
Started Mar 10 02:49:16 PM PDT 24
Finished Mar 10 02:50:44 PM PDT 24
Peak memory 240324 kb
Host smart-4f89eb0e-c5e3-48a2-93c2-ebab11c5bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628944958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2628944958
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2713394384
Short name T1395
Test name
Test status
Simulation time 237049226570 ps
CPU time 499.86 seconds
Started Mar 10 02:49:20 PM PDT 24
Finished Mar 10 02:57:41 PM PDT 24
Peak memory 266624 kb
Host smart-93b08317-285e-4f24-a98f-f4086875538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713394384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2713394384
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.564975820
Short name T209
Test name
Test status
Simulation time 20656266983 ps
CPU time 132.01 seconds
Started Mar 10 01:52:45 PM PDT 24
Finished Mar 10 01:54:58 PM PDT 24
Peak memory 262988 kb
Host smart-21eedee8-e620-428b-9491-ee43b835998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564975820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.564975820
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1801336888
Short name T1056
Test name
Test status
Simulation time 35203913313 ps
CPU time 94.65 seconds
Started Mar 10 02:49:16 PM PDT 24
Finished Mar 10 02:50:50 PM PDT 24
Peak memory 251256 kb
Host smart-5be49b45-c39e-4230-bb5d-37391e874ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801336888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1801336888
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2584298131
Short name T647
Test name
Test status
Simulation time 30200424750 ps
CPU time 157.66 seconds
Started Mar 10 01:52:56 PM PDT 24
Finished Mar 10 01:55:34 PM PDT 24
Peak memory 252860 kb
Host smart-12f4c8db-cda8-4081-b922-62957a40f829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584298131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2584298131
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2144807146
Short name T274
Test name
Test status
Simulation time 6440573092 ps
CPU time 30.64 seconds
Started Mar 10 01:52:45 PM PDT 24
Finished Mar 10 01:53:16 PM PDT 24
Peak memory 239204 kb
Host smart-eb4e0eb8-66b5-4c33-a6bf-122f1e6243d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144807146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2144807146
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2503267272
Short name T275
Test name
Test status
Simulation time 2421856220 ps
CPU time 18.74 seconds
Started Mar 10 02:49:16 PM PDT 24
Finished Mar 10 02:49:34 PM PDT 24
Peak memory 232132 kb
Host smart-18a1709f-1f06-450b-92f7-16be4e660d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503267272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2503267272
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3073046327
Short name T1739
Test name
Test status
Simulation time 4695389001 ps
CPU time 6.48 seconds
Started Mar 10 02:49:16 PM PDT 24
Finished Mar 10 02:49:23 PM PDT 24
Peak memory 232872 kb
Host smart-00579b86-046f-45de-9d1b-046641169b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073046327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3073046327
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3260951183
Short name T457
Test name
Test status
Simulation time 831462441 ps
CPU time 7.85 seconds
Started Mar 10 01:52:46 PM PDT 24
Finished Mar 10 01:52:54 PM PDT 24
Peak memory 232996 kb
Host smart-8bd3f47f-c42c-491a-a02d-032dbdafb8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260951183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3260951183
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3087561873
Short name T1077
Test name
Test status
Simulation time 1148065892 ps
CPU time 2.99 seconds
Started Mar 10 01:52:48 PM PDT 24
Finished Mar 10 01:52:52 PM PDT 24
Peak memory 217476 kb
Host smart-2d783c40-b399-42cb-959f-d7b298d5c4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087561873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3087561873
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.443379320
Short name T926
Test name
Test status
Simulation time 1880891421 ps
CPU time 9.26 seconds
Started Mar 10 02:49:18 PM PDT 24
Finished Mar 10 02:49:28 PM PDT 24
Peak memory 218240 kb
Host smart-df09a104-eec3-4858-a458-d01e4b16b21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443379320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.443379320
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2385646703
Short name T26
Test name
Test status
Simulation time 4775099272 ps
CPU time 7.59 seconds
Started Mar 10 02:49:16 PM PDT 24
Finished Mar 10 02:49:24 PM PDT 24
Peak memory 218060 kb
Host smart-29f796de-c9fe-4e97-bd9e-7200b05e15f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385646703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2385646703
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.647564174
Short name T769
Test name
Test status
Simulation time 201698427 ps
CPU time 4.94 seconds
Started Mar 10 01:52:44 PM PDT 24
Finished Mar 10 01:52:49 PM PDT 24
Peak memory 232984 kb
Host smart-f652bbc2-9618-48c2-b1b1-5af1df0e1382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647564174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.647564174
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3182903630
Short name T555
Test name
Test status
Simulation time 13388066300 ps
CPU time 6.04 seconds
Started Mar 10 02:49:18 PM PDT 24
Finished Mar 10 02:49:25 PM PDT 24
Peak memory 233088 kb
Host smart-7cc48107-1d58-4a84-96f3-104537d7958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182903630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3182903630
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.860750836
Short name T1052
Test name
Test status
Simulation time 5742041009 ps
CPU time 11.05 seconds
Started Mar 10 01:52:45 PM PDT 24
Finished Mar 10 01:52:56 PM PDT 24
Peak memory 233176 kb
Host smart-0160d7a0-36f8-4956-8718-ff2117111949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860750836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.860750836
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1476921428
Short name T948
Test name
Test status
Simulation time 5280609989 ps
CPU time 4.55 seconds
Started Mar 10 01:52:47 PM PDT 24
Finished Mar 10 01:52:51 PM PDT 24
Peak memory 215860 kb
Host smart-72da3771-1b0f-4baf-89db-e3dec0313de3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1476921428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1476921428
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4024544007
Short name T1634
Test name
Test status
Simulation time 1222570368 ps
CPU time 6.12 seconds
Started Mar 10 02:49:17 PM PDT 24
Finished Mar 10 02:49:24 PM PDT 24
Peak memory 221668 kb
Host smart-6171a4eb-d856-47d3-b005-2fca0b56a2b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4024544007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4024544007
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1951550524
Short name T833
Test name
Test status
Simulation time 150458595564 ps
CPU time 365.63 seconds
Started Mar 10 01:52:56 PM PDT 24
Finished Mar 10 01:59:02 PM PDT 24
Peak memory 286576 kb
Host smart-cd68fc75-20c3-46b3-8303-226437f0b57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951550524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1951550524
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3117029814
Short name T921
Test name
Test status
Simulation time 41095743156 ps
CPU time 76.6 seconds
Started Mar 10 02:49:17 PM PDT 24
Finished Mar 10 02:50:34 PM PDT 24
Peak memory 248116 kb
Host smart-02f8e841-ae43-4ad4-8923-e39a0d28472f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117029814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3117029814
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1065590153
Short name T1522
Test name
Test status
Simulation time 6422758866 ps
CPU time 35.34 seconds
Started Mar 10 02:49:12 PM PDT 24
Finished Mar 10 02:49:48 PM PDT 24
Peak memory 215764 kb
Host smart-421465ff-ce3e-46f6-bb52-d3f3b2e8f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065590153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1065590153
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2872548027
Short name T1879
Test name
Test status
Simulation time 661055538 ps
CPU time 5.61 seconds
Started Mar 10 01:52:47 PM PDT 24
Finished Mar 10 01:52:52 PM PDT 24
Peak memory 215776 kb
Host smart-b5f6ad98-6a4e-4c63-927c-dc04cb8d1d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872548027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2872548027
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1708286737
Short name T341
Test name
Test status
Simulation time 191182792624 ps
CPU time 26.78 seconds
Started Mar 10 02:49:13 PM PDT 24
Finished Mar 10 02:49:41 PM PDT 24
Peak memory 215816 kb
Host smart-261c3717-ccbb-4fcc-8e7a-3c50c6b5f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708286737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1708286737
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2637315329
Short name T1386
Test name
Test status
Simulation time 3660403105 ps
CPU time 8.54 seconds
Started Mar 10 01:52:44 PM PDT 24
Finished Mar 10 01:52:53 PM PDT 24
Peak memory 215788 kb
Host smart-6e3e01c5-d733-4319-aa40-92d2344592c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637315329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2637315329
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1075780247
Short name T330
Test name
Test status
Simulation time 551961672 ps
CPU time 2.11 seconds
Started Mar 10 02:49:15 PM PDT 24
Finished Mar 10 02:49:18 PM PDT 24
Peak memory 207836 kb
Host smart-b1169fe8-70f7-4e53-851a-00841dd20e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075780247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1075780247
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.356167569
Short name T1592
Test name
Test status
Simulation time 514090097 ps
CPU time 6.65 seconds
Started Mar 10 01:52:48 PM PDT 24
Finished Mar 10 01:52:55 PM PDT 24
Peak memory 215712 kb
Host smart-ca7ecf84-c5fa-4d02-a8dc-87596b1fd518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356167569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.356167569
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2787202921
Short name T1474
Test name
Test status
Simulation time 74223974 ps
CPU time 0.77 seconds
Started Mar 10 01:52:44 PM PDT 24
Finished Mar 10 01:52:45 PM PDT 24
Peak memory 204804 kb
Host smart-b2869465-bc95-46d4-8497-73df0cf78a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787202921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2787202921
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4227537271
Short name T1085
Test name
Test status
Simulation time 165281734 ps
CPU time 1.13 seconds
Started Mar 10 02:49:10 PM PDT 24
Finished Mar 10 02:49:12 PM PDT 24
Peak memory 205888 kb
Host smart-8e412dc8-228a-4a70-8c88-e7fad217f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227537271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4227537271
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2447911481
Short name T1303
Test name
Test status
Simulation time 768468245 ps
CPU time 6.39 seconds
Started Mar 10 01:52:46 PM PDT 24
Finished Mar 10 01:52:52 PM PDT 24
Peak memory 217500 kb
Host smart-a174961b-70a3-465e-a69c-eb55437d738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447911481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2447911481
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_upload.3521691557
Short name T891
Test name
Test status
Simulation time 114685117642 ps
CPU time 29.82 seconds
Started Mar 10 02:49:17 PM PDT 24
Finished Mar 10 02:49:47 PM PDT 24
Peak memory 238296 kb
Host smart-274bd125-61a1-4741-aa66-f8c65a36131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521691557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3521691557
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2769587317
Short name T55
Test name
Test status
Simulation time 41549713 ps
CPU time 0.71 seconds
Started Mar 10 01:49:13 PM PDT 24
Finished Mar 10 01:49:14 PM PDT 24
Peak memory 204436 kb
Host smart-abd4742c-cab5-4a85-9d76-2a15de4454a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769587317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
769587317
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3555708100
Short name T700
Test name
Test status
Simulation time 15265560 ps
CPU time 0.71 seconds
Started Mar 10 02:46:30 PM PDT 24
Finished Mar 10 02:46:30 PM PDT 24
Peak memory 204404 kb
Host smart-825f24ff-c5d0-41b3-bc1b-f04c57ac90b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555708100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
555708100
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2027485731
Short name T704
Test name
Test status
Simulation time 602078410 ps
CPU time 3.66 seconds
Started Mar 10 02:46:23 PM PDT 24
Finished Mar 10 02:46:27 PM PDT 24
Peak memory 223876 kb
Host smart-547931b0-d691-4df1-9ead-bb53afc69883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027485731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2027485731
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2870507895
Short name T1174
Test name
Test status
Simulation time 124320886 ps
CPU time 2.47 seconds
Started Mar 10 01:49:12 PM PDT 24
Finished Mar 10 01:49:15 PM PDT 24
Peak memory 216220 kb
Host smart-7876c33b-2157-4056-af4f-e4adde70a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870507895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2870507895
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3544875320
Short name T306
Test name
Test status
Simulation time 126061793 ps
CPU time 0.7 seconds
Started Mar 10 01:49:08 PM PDT 24
Finished Mar 10 01:49:09 PM PDT 24
Peak memory 204412 kb
Host smart-06c15b75-b7b9-43c2-8f91-4f8fca8dbc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544875320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3544875320
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.455798208
Short name T809
Test name
Test status
Simulation time 40797827 ps
CPU time 0.74 seconds
Started Mar 10 02:46:21 PM PDT 24
Finished Mar 10 02:46:22 PM PDT 24
Peak memory 205528 kb
Host smart-41ea7371-c6c5-4f7f-97eb-8dde92ed40b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455798208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.455798208
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2116732261
Short name T255
Test name
Test status
Simulation time 44789091363 ps
CPU time 248.06 seconds
Started Mar 10 01:49:13 PM PDT 24
Finished Mar 10 01:53:22 PM PDT 24
Peak memory 245820 kb
Host smart-cff51e40-357e-403d-8842-f79df3426c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116732261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2116732261
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3829833811
Short name T860
Test name
Test status
Simulation time 8351510978 ps
CPU time 78.9 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:47:46 PM PDT 24
Peak memory 248484 kb
Host smart-cf11a670-c774-448d-8cfd-46f4f66e4abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829833811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3829833811
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1865709139
Short name T1007
Test name
Test status
Simulation time 12485278216 ps
CPU time 89.03 seconds
Started Mar 10 02:46:26 PM PDT 24
Finished Mar 10 02:47:55 PM PDT 24
Peak memory 248888 kb
Host smart-dfa7dd41-e16d-4d55-81dc-f434498bc6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865709139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1865709139
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3459984741
Short name T212
Test name
Test status
Simulation time 102381465844 ps
CPU time 308.56 seconds
Started Mar 10 01:49:11 PM PDT 24
Finished Mar 10 01:54:20 PM PDT 24
Peak memory 253416 kb
Host smart-b5745387-a2eb-4ddd-8e62-6795af1e3f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459984741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3459984741
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2862302636
Short name T1170
Test name
Test status
Simulation time 44367977262 ps
CPU time 160.43 seconds
Started Mar 10 02:46:25 PM PDT 24
Finished Mar 10 02:49:06 PM PDT 24
Peak memory 248716 kb
Host smart-8325491b-517b-44ef-9785-2fbb95f044e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862302636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2862302636
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3109127465
Short name T337
Test name
Test status
Simulation time 2896001243 ps
CPU time 56.72 seconds
Started Mar 10 01:49:12 PM PDT 24
Finished Mar 10 01:50:09 PM PDT 24
Peak memory 248656 kb
Host smart-fbe854f8-1f92-440d-a871-246a94727e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109127465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3109127465
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1737519068
Short name T1799
Test name
Test status
Simulation time 325287709 ps
CPU time 8.72 seconds
Started Mar 10 02:46:23 PM PDT 24
Finished Mar 10 02:46:31 PM PDT 24
Peak memory 240260 kb
Host smart-150f740f-e79f-4924-82fb-133fb4f89eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737519068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1737519068
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4035185520
Short name T1560
Test name
Test status
Simulation time 48040960092 ps
CPU time 53.99 seconds
Started Mar 10 01:49:15 PM PDT 24
Finished Mar 10 01:50:10 PM PDT 24
Peak memory 248088 kb
Host smart-551ec243-37eb-40f0-ad54-1cb854dde5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035185520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4035185520
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1242633495
Short name T393
Test name
Test status
Simulation time 737601300 ps
CPU time 4.2 seconds
Started Mar 10 01:49:07 PM PDT 24
Finished Mar 10 01:49:12 PM PDT 24
Peak memory 215816 kb
Host smart-00e3091b-0565-4943-8fc2-661589de276e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242633495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1242633495
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intercept.885339791
Short name T1126
Test name
Test status
Simulation time 1245320277 ps
CPU time 5.67 seconds
Started Mar 10 02:46:23 PM PDT 24
Finished Mar 10 02:46:29 PM PDT 24
Peak memory 217328 kb
Host smart-3310b7cd-9a0b-4ae3-8620-99c066b8fb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885339791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.885339791
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1518229509
Short name T1032
Test name
Test status
Simulation time 45193238438 ps
CPU time 30.47 seconds
Started Mar 10 01:49:14 PM PDT 24
Finished Mar 10 01:49:45 PM PDT 24
Peak memory 236812 kb
Host smart-e22aa49a-9769-4e34-ad76-6bf85fbaa059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518229509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1518229509
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4040014206
Short name T1326
Test name
Test status
Simulation time 1952462991 ps
CPU time 10.58 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:46:37 PM PDT 24
Peak memory 230448 kb
Host smart-305d5942-9dc6-4851-9e62-ba1cfd033d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040014206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4040014206
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2502324680
Short name T1119
Test name
Test status
Simulation time 34983715 ps
CPU time 1.1 seconds
Started Mar 10 01:49:08 PM PDT 24
Finished Mar 10 01:49:09 PM PDT 24
Peak memory 216076 kb
Host smart-e8964369-8ec6-4a94-8164-20999d00f17a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502324680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2502324680
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3269803384
Short name T543
Test name
Test status
Simulation time 14131976 ps
CPU time 1.03 seconds
Started Mar 10 02:46:23 PM PDT 24
Finished Mar 10 02:46:24 PM PDT 24
Peak memory 216040 kb
Host smart-21bc1d34-32df-4db6-9ae9-feca606509bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269803384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3269803384
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1071004192
Short name T1277
Test name
Test status
Simulation time 7135986683 ps
CPU time 22.82 seconds
Started Mar 10 02:46:24 PM PDT 24
Finished Mar 10 02:46:47 PM PDT 24
Peak memory 218452 kb
Host smart-1bd758c2-e1c1-40c4-bd7a-4beaf94fb28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071004192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1071004192
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2929337843
Short name T605
Test name
Test status
Simulation time 2312184963 ps
CPU time 9.05 seconds
Started Mar 10 01:49:10 PM PDT 24
Finished Mar 10 01:49:19 PM PDT 24
Peak memory 232880 kb
Host smart-499e6ebd-9413-4d5a-b0d7-c4d6fcb72015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929337843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2929337843
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1922484680
Short name T562
Test name
Test status
Simulation time 645732060 ps
CPU time 10.27 seconds
Started Mar 10 02:46:24 PM PDT 24
Finished Mar 10 02:46:34 PM PDT 24
Peak memory 244208 kb
Host smart-70fb73bf-60a1-4617-a0b5-887fd6673a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922484680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1922484680
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2324649599
Short name T610
Test name
Test status
Simulation time 394402032 ps
CPU time 5.31 seconds
Started Mar 10 01:49:08 PM PDT 24
Finished Mar 10 01:49:13 PM PDT 24
Peak memory 219704 kb
Host smart-cc5f23e6-5a29-48d9-83ca-4b2259c8734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324649599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2324649599
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1147710650
Short name T1115
Test name
Test status
Simulation time 39230597 ps
CPU time 0.73 seconds
Started Mar 10 01:49:08 PM PDT 24
Finished Mar 10 01:49:09 PM PDT 24
Peak memory 215640 kb
Host smart-d57c9e02-b66c-46ec-9dcf-014a7e368d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147710650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1147710650
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3159959158
Short name T1237
Test name
Test status
Simulation time 43428093 ps
CPU time 0.79 seconds
Started Mar 10 02:46:21 PM PDT 24
Finished Mar 10 02:46:22 PM PDT 24
Peak memory 215588 kb
Host smart-efe8de36-d014-4c2f-a0a5-0a73b551ce17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159959158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3159959158
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2242905268
Short name T1083
Test name
Test status
Simulation time 1429550966 ps
CPU time 6.45 seconds
Started Mar 10 01:49:12 PM PDT 24
Finished Mar 10 01:49:19 PM PDT 24
Peak memory 217920 kb
Host smart-e9b2e68a-f251-4b1c-8c45-b179733a8d4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2242905268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2242905268
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.679574551
Short name T1131
Test name
Test status
Simulation time 1010799278 ps
CPU time 3.89 seconds
Started Mar 10 02:46:22 PM PDT 24
Finished Mar 10 02:46:26 PM PDT 24
Peak memory 221540 kb
Host smart-94be5cb2-5dc6-4f50-bdcc-19be7b4675cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=679574551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.679574551
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1028008013
Short name T1087
Test name
Test status
Simulation time 54598651511 ps
CPU time 385.2 seconds
Started Mar 10 02:46:23 PM PDT 24
Finished Mar 10 02:52:49 PM PDT 24
Peak memory 268488 kb
Host smart-fbe607f7-f23d-4bbb-b068-155c84145aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028008013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1028008013
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1516259832
Short name T1635
Test name
Test status
Simulation time 10037803672 ps
CPU time 70.31 seconds
Started Mar 10 01:49:13 PM PDT 24
Finished Mar 10 01:50:24 PM PDT 24
Peak memory 237616 kb
Host smart-9e76f81f-f194-438b-b61d-5d49cf7c0d64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516259832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1516259832
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3007031527
Short name T1061
Test name
Test status
Simulation time 3077515303 ps
CPU time 25.81 seconds
Started Mar 10 01:49:09 PM PDT 24
Finished Mar 10 01:49:35 PM PDT 24
Peak memory 215760 kb
Host smart-6310511c-8034-46ad-9edb-5a4c01060af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007031527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3007031527
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3716333868
Short name T1785
Test name
Test status
Simulation time 19157264945 ps
CPU time 26.02 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:46:53 PM PDT 24
Peak memory 215936 kb
Host smart-782dd813-458e-487d-b878-4941d4d6f8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716333868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3716333868
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1604004815
Short name T557
Test name
Test status
Simulation time 10466225982 ps
CPU time 4.92 seconds
Started Mar 10 01:49:08 PM PDT 24
Finished Mar 10 01:49:13 PM PDT 24
Peak memory 215800 kb
Host smart-5ab9797d-1d92-4a58-ac8d-6f9f2192e12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604004815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1604004815
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.7192563
Short name T706
Test name
Test status
Simulation time 14554187858 ps
CPU time 12.61 seconds
Started Mar 10 02:46:26 PM PDT 24
Finished Mar 10 02:46:39 PM PDT 24
Peak memory 215788 kb
Host smart-b9637ec0-aec7-4cf1-8bae-ce79fbaf0014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7192563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.7192563
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.269591548
Short name T1347
Test name
Test status
Simulation time 250969395 ps
CPU time 1.76 seconds
Started Mar 10 01:49:09 PM PDT 24
Finished Mar 10 01:49:11 PM PDT 24
Peak memory 215708 kb
Host smart-465f277b-04a5-47cd-8134-33e7c89506c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269591548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.269591548
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.904609871
Short name T1656
Test name
Test status
Simulation time 1391931494 ps
CPU time 2.89 seconds
Started Mar 10 02:46:23 PM PDT 24
Finished Mar 10 02:46:26 PM PDT 24
Peak memory 215808 kb
Host smart-57dd5185-49d2-422b-bd88-088bb361f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904609871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.904609871
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2817869900
Short name T1192
Test name
Test status
Simulation time 16772071 ps
CPU time 0.77 seconds
Started Mar 10 02:46:26 PM PDT 24
Finished Mar 10 02:46:27 PM PDT 24
Peak memory 204892 kb
Host smart-bde31367-df6b-4487-b7e7-b73299afd7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817869900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2817869900
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.36687712
Short name T1357
Test name
Test status
Simulation time 183983095 ps
CPU time 1.05 seconds
Started Mar 10 01:49:09 PM PDT 24
Finished Mar 10 01:49:10 PM PDT 24
Peak memory 205916 kb
Host smart-c3f4cd16-bc8a-4ebd-9d57-fdb722b2479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36687712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.36687712
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2308699539
Short name T873
Test name
Test status
Simulation time 65778103998 ps
CPU time 12.15 seconds
Started Mar 10 01:49:13 PM PDT 24
Finished Mar 10 01:49:25 PM PDT 24
Peak memory 233672 kb
Host smart-837fd7b9-140b-4d58-a476-7049e6931b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308699539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2308699539
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_upload.3514107856
Short name T633
Test name
Test status
Simulation time 2586343945 ps
CPU time 8.37 seconds
Started Mar 10 02:46:22 PM PDT 24
Finished Mar 10 02:46:30 PM PDT 24
Peak memory 244888 kb
Host smart-e3d1179a-ae3f-44e7-8b8f-3ae66803514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514107856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3514107856
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1398896274
Short name T619
Test name
Test status
Simulation time 44258514 ps
CPU time 0.73 seconds
Started Mar 10 02:46:29 PM PDT 24
Finished Mar 10 02:46:30 PM PDT 24
Peak memory 203896 kb
Host smart-9687321d-3223-40ac-aab0-0d0e849f9798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398896274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
398896274
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2998030291
Short name T667
Test name
Test status
Simulation time 56905969 ps
CPU time 0.7 seconds
Started Mar 10 01:49:16 PM PDT 24
Finished Mar 10 01:49:17 PM PDT 24
Peak memory 204472 kb
Host smart-fff339ac-9380-4afe-976d-118007c919c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998030291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
998030291
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2190492433
Short name T223
Test name
Test status
Simulation time 383399736 ps
CPU time 3.33 seconds
Started Mar 10 01:49:15 PM PDT 24
Finished Mar 10 01:49:19 PM PDT 24
Peak memory 232900 kb
Host smart-62c322cc-d4e8-4c8e-9948-81996391db26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190492433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2190492433
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3670545456
Short name T325
Test name
Test status
Simulation time 11246180820 ps
CPU time 13.06 seconds
Started Mar 10 02:46:28 PM PDT 24
Finished Mar 10 02:46:41 PM PDT 24
Peak memory 233096 kb
Host smart-852155cb-05aa-47ea-bd4b-98fa14bc9120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670545456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3670545456
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2128320855
Short name T367
Test name
Test status
Simulation time 14578478 ps
CPU time 0.79 seconds
Started Mar 10 01:49:15 PM PDT 24
Finished Mar 10 01:49:16 PM PDT 24
Peak memory 205516 kb
Host smart-5e879be9-b6f1-4227-8489-7291fa98eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128320855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2128320855
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.884555428
Short name T129
Test name
Test status
Simulation time 41218621 ps
CPU time 0.83 seconds
Started Mar 10 02:46:30 PM PDT 24
Finished Mar 10 02:46:31 PM PDT 24
Peak memory 205856 kb
Host smart-718381a1-86bf-4cd9-9861-0f53308ac549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884555428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.884555428
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2348142254
Short name T1278
Test name
Test status
Simulation time 12116890390 ps
CPU time 26.36 seconds
Started Mar 10 01:49:19 PM PDT 24
Finished Mar 10 01:49:45 PM PDT 24
Peak memory 240180 kb
Host smart-74f63c7d-fba0-4527-afc2-a2f112fe44e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348142254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2348142254
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3885800277
Short name T1360
Test name
Test status
Simulation time 1677723098 ps
CPU time 33.79 seconds
Started Mar 10 02:46:31 PM PDT 24
Finished Mar 10 02:47:05 PM PDT 24
Peak memory 240252 kb
Host smart-81e2660b-3295-40d0-a15d-df4104b59110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885800277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3885800277
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1590932426
Short name T781
Test name
Test status
Simulation time 45872931089 ps
CPU time 326.29 seconds
Started Mar 10 01:49:16 PM PDT 24
Finished Mar 10 01:54:42 PM PDT 24
Peak memory 255536 kb
Host smart-86749293-ebcd-4b02-9c65-59a95a38625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590932426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1590932426
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.769015852
Short name T1906
Test name
Test status
Simulation time 8286021597 ps
CPU time 83.17 seconds
Started Mar 10 02:46:29 PM PDT 24
Finished Mar 10 02:47:53 PM PDT 24
Peak memory 237436 kb
Host smart-937a93e7-a5ba-4da4-8612-178defd58f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769015852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.769015852
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3006432359
Short name T1907
Test name
Test status
Simulation time 50765566808 ps
CPU time 369.43 seconds
Started Mar 10 02:46:28 PM PDT 24
Finished Mar 10 02:52:38 PM PDT 24
Peak memory 256792 kb
Host smart-3a50acf8-2ba7-4f84-b93c-f1d5b05e1284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006432359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3006432359
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4170805662
Short name T195
Test name
Test status
Simulation time 25669109969 ps
CPU time 220.33 seconds
Started Mar 10 01:49:18 PM PDT 24
Finished Mar 10 01:52:58 PM PDT 24
Peak memory 253892 kb
Host smart-2b4d4a38-256e-4807-b899-9b3cbb179920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170805662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4170805662
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2009981030
Short name T1863
Test name
Test status
Simulation time 12040958899 ps
CPU time 31.91 seconds
Started Mar 10 01:49:19 PM PDT 24
Finished Mar 10 01:49:51 PM PDT 24
Peak memory 237716 kb
Host smart-f7a60063-f058-4683-b92a-1d5a28a4b1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009981030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2009981030
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.42744512
Short name T683
Test name
Test status
Simulation time 6108404256 ps
CPU time 18.9 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:46:46 PM PDT 24
Peak memory 256736 kb
Host smart-61818c90-e4db-4e7b-82d0-8437cfe73df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42744512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.42744512
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2433863474
Short name T688
Test name
Test status
Simulation time 6161479366 ps
CPU time 6.59 seconds
Started Mar 10 01:49:19 PM PDT 24
Finished Mar 10 01:49:26 PM PDT 24
Peak memory 232560 kb
Host smart-57ee4af7-b713-4e58-8f58-40b0c732ed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433863474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2433863474
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3803373249
Short name T1626
Test name
Test status
Simulation time 616289666 ps
CPU time 4.27 seconds
Started Mar 10 02:46:30 PM PDT 24
Finished Mar 10 02:46:34 PM PDT 24
Peak memory 232956 kb
Host smart-d1684c9c-9c6c-48d6-9788-6abd5e822c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803373249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3803373249
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2121600312
Short name T617
Test name
Test status
Simulation time 2334247243 ps
CPU time 12.24 seconds
Started Mar 10 02:46:34 PM PDT 24
Finished Mar 10 02:46:46 PM PDT 24
Peak memory 235996 kb
Host smart-f7dc92ea-48fc-48b1-90ac-906b480a6525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121600312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2121600312
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.314433321
Short name T343
Test name
Test status
Simulation time 1408312161 ps
CPU time 7.18 seconds
Started Mar 10 01:49:21 PM PDT 24
Finished Mar 10 01:49:28 PM PDT 24
Peak memory 232688 kb
Host smart-2cefe1b8-2ed0-42b8-8798-0e3de1ac5b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314433321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.314433321
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2194968779
Short name T1819
Test name
Test status
Simulation time 17563464 ps
CPU time 1.03 seconds
Started Mar 10 01:49:12 PM PDT 24
Finished Mar 10 01:49:13 PM PDT 24
Peak memory 217252 kb
Host smart-3a2f9544-3592-4d69-9a4d-7c2b4ca1b590
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194968779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2194968779
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2758047645
Short name T23
Test name
Test status
Simulation time 15116509 ps
CPU time 1.04 seconds
Started Mar 10 02:46:29 PM PDT 24
Finished Mar 10 02:46:30 PM PDT 24
Peak memory 217300 kb
Host smart-76936851-4abf-40db-9e05-c55ef4d9b590
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758047645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2758047645
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2415126687
Short name T12
Test name
Test status
Simulation time 3144107169 ps
CPU time 3.74 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:46:31 PM PDT 24
Peak memory 216084 kb
Host smart-f94a7d86-8344-4d99-a2a9-cb6ba4f96de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415126687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2415126687
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2758372912
Short name T1772
Test name
Test status
Simulation time 1165945609 ps
CPU time 5.85 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:28 PM PDT 24
Peak memory 232956 kb
Host smart-5f63a25e-79f5-41d8-8cd8-4350bb4d72a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758372912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2758372912
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1353974574
Short name T1568
Test name
Test status
Simulation time 929307943 ps
CPU time 5.98 seconds
Started Mar 10 01:49:21 PM PDT 24
Finished Mar 10 01:49:28 PM PDT 24
Peak memory 232756 kb
Host smart-d344dee6-76bf-4e88-9922-1e9389ab6296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353974574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1353974574
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.913583068
Short name T625
Test name
Test status
Simulation time 92881279835 ps
CPU time 39.29 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:47:07 PM PDT 24
Peak memory 239116 kb
Host smart-b4423fa8-dc54-464a-b9c3-09eef4f21196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913583068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.913583068
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2310915955
Short name T545
Test name
Test status
Simulation time 88728092 ps
CPU time 0.75 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:46:28 PM PDT 24
Peak memory 215604 kb
Host smart-bd08c5ed-8962-4e69-83a3-d9f2c4a2d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310915955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2310915955
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2557762002
Short name T1179
Test name
Test status
Simulation time 18252004 ps
CPU time 0.73 seconds
Started Mar 10 01:49:13 PM PDT 24
Finished Mar 10 01:49:15 PM PDT 24
Peak memory 215620 kb
Host smart-6896e266-c081-4b33-a1e2-925c47d543b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557762002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2557762002
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1423553383
Short name T815
Test name
Test status
Simulation time 834450230 ps
CPU time 4.2 seconds
Started Mar 10 01:49:18 PM PDT 24
Finished Mar 10 01:49:22 PM PDT 24
Peak memory 221996 kb
Host smart-39baa5ee-4245-4d85-a5dd-26d0511a38a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423553383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1423553383
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3235055613
Short name T1070
Test name
Test status
Simulation time 612293839 ps
CPU time 4.66 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:46:32 PM PDT 24
Peak memory 216016 kb
Host smart-7510e97c-1de4-4704-b659-50a72b2e38d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3235055613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3235055613
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.304353679
Short name T189
Test name
Test status
Simulation time 82494495438 ps
CPU time 572.58 seconds
Started Mar 10 02:46:32 PM PDT 24
Finished Mar 10 02:56:05 PM PDT 24
Peak memory 273000 kb
Host smart-ad5a7353-69e9-4295-9f61-e83e51d31259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304353679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.304353679
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3219910922
Short name T1450
Test name
Test status
Simulation time 92208453139 ps
CPU time 312.04 seconds
Started Mar 10 01:49:24 PM PDT 24
Finished Mar 10 01:54:37 PM PDT 24
Peak memory 289404 kb
Host smart-e8a6e824-2f2e-465a-bbb9-bdd9266ddd5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219910922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3219910922
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2429857975
Short name T955
Test name
Test status
Simulation time 697026753 ps
CPU time 7.88 seconds
Started Mar 10 02:46:39 PM PDT 24
Finished Mar 10 02:46:47 PM PDT 24
Peak memory 215784 kb
Host smart-e4f9e713-0e54-41d6-848c-568f32ce7507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429857975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2429857975
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3465791307
Short name T761
Test name
Test status
Simulation time 14107456011 ps
CPU time 19.94 seconds
Started Mar 10 01:49:24 PM PDT 24
Finished Mar 10 01:49:45 PM PDT 24
Peak memory 215776 kb
Host smart-d7ac9005-6216-495e-be21-2d5a0d2ab430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465791307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3465791307
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2970819941
Short name T1801
Test name
Test status
Simulation time 2407993797 ps
CPU time 7.98 seconds
Started Mar 10 01:49:13 PM PDT 24
Finished Mar 10 01:49:21 PM PDT 24
Peak memory 215836 kb
Host smart-056d4121-888e-403f-ab43-40d3c5e32f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970819941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2970819941
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4100170405
Short name T282
Test name
Test status
Simulation time 20484960579 ps
CPU time 10.05 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:46:37 PM PDT 24
Peak memory 215860 kb
Host smart-07f8f01c-5648-489e-b3ab-25976010db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100170405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4100170405
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.104880324
Short name T510
Test name
Test status
Simulation time 22121022 ps
CPU time 1.01 seconds
Started Mar 10 01:49:18 PM PDT 24
Finished Mar 10 01:49:19 PM PDT 24
Peak memory 206324 kb
Host smart-456a1de6-c308-4424-bfba-98922b3e2f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104880324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.104880324
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3608553472
Short name T1427
Test name
Test status
Simulation time 50718993 ps
CPU time 0.78 seconds
Started Mar 10 02:46:27 PM PDT 24
Finished Mar 10 02:46:28 PM PDT 24
Peak memory 204936 kb
Host smart-d05e9b12-4afd-4b28-a483-3828d420cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608553472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3608553472
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3927845984
Short name T1307
Test name
Test status
Simulation time 361776656 ps
CPU time 0.92 seconds
Started Mar 10 01:49:15 PM PDT 24
Finished Mar 10 01:49:16 PM PDT 24
Peak memory 204876 kb
Host smart-2e7555f2-b0e7-49f9-8d90-b4c2274db96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927845984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3927845984
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.453729854
Short name T1608
Test name
Test status
Simulation time 89634724 ps
CPU time 1.02 seconds
Started Mar 10 02:46:31 PM PDT 24
Finished Mar 10 02:46:32 PM PDT 24
Peak memory 205876 kb
Host smart-352b1110-3293-42fa-9caf-57d4f648653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453729854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.453729854
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1037546763
Short name T1479
Test name
Test status
Simulation time 12589139028 ps
CPU time 42.97 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 231592 kb
Host smart-d11486af-2516-4c8d-97ff-dc3c8bbd20ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037546763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1037546763
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_upload.3331897155
Short name T1305
Test name
Test status
Simulation time 26162963561 ps
CPU time 7.72 seconds
Started Mar 10 02:46:28 PM PDT 24
Finished Mar 10 02:46:36 PM PDT 24
Peak memory 233328 kb
Host smart-51b0fc94-37c8-46a3-bb34-dfd77472e8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331897155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3331897155
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1065894081
Short name T841
Test name
Test status
Simulation time 22812368 ps
CPU time 0.73 seconds
Started Mar 10 01:49:27 PM PDT 24
Finished Mar 10 01:49:28 PM PDT 24
Peak memory 204432 kb
Host smart-2eec9c55-a43a-439f-867e-e472b6cf2498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065894081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
065894081
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3547996762
Short name T512
Test name
Test status
Simulation time 62453826 ps
CPU time 0.71 seconds
Started Mar 10 02:46:35 PM PDT 24
Finished Mar 10 02:46:35 PM PDT 24
Peak memory 203728 kb
Host smart-9330965e-988d-4f72-9489-96aef2f14127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547996762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
547996762
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1284861547
Short name T734
Test name
Test status
Simulation time 1229185104 ps
CPU time 4.2 seconds
Started Mar 10 01:49:24 PM PDT 24
Finished Mar 10 01:49:29 PM PDT 24
Peak memory 233156 kb
Host smart-5ce10c36-53d8-4779-8012-ee98417146fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284861547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1284861547
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4138328032
Short name T1876
Test name
Test status
Simulation time 458545320 ps
CPU time 3.36 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:46:36 PM PDT 24
Peak memory 223796 kb
Host smart-d57c2f03-2ea6-47ad-aeeb-b02e10403b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138328032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4138328032
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.271145804
Short name T100
Test name
Test status
Simulation time 20610203 ps
CPU time 0.81 seconds
Started Mar 10 02:46:30 PM PDT 24
Finished Mar 10 02:46:31 PM PDT 24
Peak memory 205816 kb
Host smart-bff6c0ac-650d-4cda-8e7b-60f81f2d4248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271145804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.271145804
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.627594282
Short name T386
Test name
Test status
Simulation time 16783849 ps
CPU time 0.78 seconds
Started Mar 10 01:49:17 PM PDT 24
Finished Mar 10 01:49:18 PM PDT 24
Peak memory 204816 kb
Host smart-f972892b-8c94-4a1f-a375-93112bdc409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627594282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.627594282
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3024279488
Short name T1368
Test name
Test status
Simulation time 96739697564 ps
CPU time 136.87 seconds
Started Mar 10 01:49:23 PM PDT 24
Finished Mar 10 01:51:40 PM PDT 24
Peak memory 254044 kb
Host smart-93fddbcc-2d38-43e2-bccc-e839762b69dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024279488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3024279488
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3815927385
Short name T42
Test name
Test status
Simulation time 23754828666 ps
CPU time 123.52 seconds
Started Mar 10 02:46:32 PM PDT 24
Finished Mar 10 02:48:36 PM PDT 24
Peak memory 246996 kb
Host smart-a61d571a-3805-4e4c-aa41-a155f7ef20a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815927385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3815927385
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1508420628
Short name T1114
Test name
Test status
Simulation time 24160170664 ps
CPU time 180.01 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:49:33 PM PDT 24
Peak memory 261004 kb
Host smart-4775bfb8-2c58-4686-9166-065389e2055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508420628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1508420628
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2634246019
Short name T1584
Test name
Test status
Simulation time 42204370916 ps
CPU time 164.06 seconds
Started Mar 10 01:49:21 PM PDT 24
Finished Mar 10 01:52:05 PM PDT 24
Peak memory 250032 kb
Host smart-820e1b24-4703-43d7-b6cf-fa91565a7529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634246019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2634246019
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2907915714
Short name T1473
Test name
Test status
Simulation time 6423668267 ps
CPU time 136.97 seconds
Started Mar 10 02:46:32 PM PDT 24
Finished Mar 10 02:48:49 PM PDT 24
Peak memory 264464 kb
Host smart-6ba3d8f6-270b-41f6-ab73-fdb55a367494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907915714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2907915714
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.674385228
Short name T1909
Test name
Test status
Simulation time 6162545014 ps
CPU time 29.52 seconds
Started Mar 10 01:49:21 PM PDT 24
Finished Mar 10 01:49:50 PM PDT 24
Peak memory 232260 kb
Host smart-ed1814ff-00ae-46ef-980b-d801c113cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674385228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
674385228
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.403654207
Short name T995
Test name
Test status
Simulation time 16604402925 ps
CPU time 38.91 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:47:12 PM PDT 24
Peak memory 240296 kb
Host smart-0c13d82e-4174-40e7-94a7-4d59086bd4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403654207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.403654207
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.832530876
Short name T1902
Test name
Test status
Simulation time 23825206716 ps
CPU time 32.4 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:55 PM PDT 24
Peak memory 240312 kb
Host smart-4f6099e2-b96f-4e56-b718-0f01460c66a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832530876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.832530876
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3703703342
Short name T1261
Test name
Test status
Simulation time 3784451524 ps
CPU time 9.14 seconds
Started Mar 10 02:46:41 PM PDT 24
Finished Mar 10 02:46:50 PM PDT 24
Peak memory 232812 kb
Host smart-22b9745f-1ff3-44ec-95b9-9496964b62e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703703342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3703703342
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4186260000
Short name T712
Test name
Test status
Simulation time 519312853 ps
CPU time 4.88 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:27 PM PDT 24
Peak memory 233008 kb
Host smart-0e3522b9-1be9-476b-aa74-45d97831ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186260000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4186260000
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.172379187
Short name T1627
Test name
Test status
Simulation time 2432819193 ps
CPU time 16.07 seconds
Started Mar 10 01:49:21 PM PDT 24
Finished Mar 10 01:49:37 PM PDT 24
Peak memory 240276 kb
Host smart-9937b642-2325-4df2-88f7-0d0e9e4bb81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172379187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.172379187
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2369684204
Short name T1426
Test name
Test status
Simulation time 12806019536 ps
CPU time 33.21 seconds
Started Mar 10 02:46:42 PM PDT 24
Finished Mar 10 02:47:16 PM PDT 24
Peak memory 233168 kb
Host smart-48cf9bc3-79a6-407e-8b1f-646378891f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369684204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2369684204
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2534922263
Short name T952
Test name
Test status
Simulation time 35621808 ps
CPU time 1.1 seconds
Started Mar 10 02:46:28 PM PDT 24
Finished Mar 10 02:46:29 PM PDT 24
Peak memory 216036 kb
Host smart-e3536441-8470-4ff5-84fa-6df6edf04a03
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534922263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2534922263
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.307822953
Short name T606
Test name
Test status
Simulation time 44041281 ps
CPU time 1.05 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:24 PM PDT 24
Peak memory 216028 kb
Host smart-02f77cce-9c5c-40c8-ba6e-8826db385241
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307822953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.307822953
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4283503937
Short name T969
Test name
Test status
Simulation time 6582791709 ps
CPU time 13.02 seconds
Started Mar 10 02:46:35 PM PDT 24
Finished Mar 10 02:46:48 PM PDT 24
Peak memory 233100 kb
Host smart-882b852f-287f-4336-a4de-26d88a199d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283503937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4283503937
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.552565020
Short name T1836
Test name
Test status
Simulation time 10523380279 ps
CPU time 28.65 seconds
Started Mar 10 01:49:27 PM PDT 24
Finished Mar 10 01:49:56 PM PDT 24
Peak memory 233028 kb
Host smart-38ea9b7f-5375-431e-a15c-d29350e36267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552565020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
552565020
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4034244991
Short name T551
Test name
Test status
Simulation time 75916858 ps
CPU time 2.83 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:26 PM PDT 24
Peak memory 231952 kb
Host smart-63b041d5-e179-4e14-abda-f6d92d61f28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034244991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4034244991
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.446349402
Short name T1782
Test name
Test status
Simulation time 288296073 ps
CPU time 4.08 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:46:37 PM PDT 24
Peak memory 217088 kb
Host smart-b541f3a9-bb1d-4c5e-8351-9844619997f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446349402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.446349402
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3920768572
Short name T1773
Test name
Test status
Simulation time 16642400 ps
CPU time 0.75 seconds
Started Mar 10 01:49:19 PM PDT 24
Finished Mar 10 01:49:21 PM PDT 24
Peak memory 215640 kb
Host smart-4ee8c083-8dcd-46e2-b5b5-94f48b10dfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920768572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3920768572
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.4243752354
Short name T443
Test name
Test status
Simulation time 32686384 ps
CPU time 0.71 seconds
Started Mar 10 02:46:29 PM PDT 24
Finished Mar 10 02:46:29 PM PDT 24
Peak memory 215612 kb
Host smart-5ed43f9c-d8a5-4a5d-8301-74ffb2c385c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243752354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.4243752354
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2070723265
Short name T942
Test name
Test status
Simulation time 1087594075 ps
CPU time 5.57 seconds
Started Mar 10 01:49:24 PM PDT 24
Finished Mar 10 01:49:30 PM PDT 24
Peak memory 215788 kb
Host smart-308146d1-76f9-47cd-8131-7abe53a1b2a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2070723265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2070723265
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2583289541
Short name T1378
Test name
Test status
Simulation time 3454875447 ps
CPU time 4.52 seconds
Started Mar 10 02:46:34 PM PDT 24
Finished Mar 10 02:46:39 PM PDT 24
Peak memory 221676 kb
Host smart-cc80a996-f815-48c3-95a5-8342a57afb55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2583289541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2583289541
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1328034176
Short name T1809
Test name
Test status
Simulation time 201154931 ps
CPU time 0.97 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:46:35 PM PDT 24
Peak memory 204548 kb
Host smart-d46c2722-400b-4705-b993-e7fa0d7dafcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328034176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1328034176
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1999160746
Short name T1154
Test name
Test status
Simulation time 12301276140 ps
CPU time 49.42 seconds
Started Mar 10 01:49:21 PM PDT 24
Finished Mar 10 01:50:11 PM PDT 24
Peak memory 256164 kb
Host smart-2614c2b7-682d-4592-a851-15ea77436e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999160746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1999160746
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1223143002
Short name T820
Test name
Test status
Simulation time 796912730 ps
CPU time 5.09 seconds
Started Mar 10 02:46:34 PM PDT 24
Finished Mar 10 02:46:39 PM PDT 24
Peak memory 217088 kb
Host smart-a6e9efb2-9775-4825-bfcc-8d55ecf4be3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223143002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1223143002
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.823482220
Short name T328
Test name
Test status
Simulation time 19791954251 ps
CPU time 29.21 seconds
Started Mar 10 01:49:18 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 215828 kb
Host smart-863feea4-2c20-4a03-902c-5ed649863dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823482220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.823482220
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4018312887
Short name T1512
Test name
Test status
Simulation time 170411431 ps
CPU time 1.55 seconds
Started Mar 10 02:46:29 PM PDT 24
Finished Mar 10 02:46:30 PM PDT 24
Peak memory 207296 kb
Host smart-02d132ae-344a-419f-8465-bb23ae2d9bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018312887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4018312887
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4114407070
Short name T159
Test name
Test status
Simulation time 36101399926 ps
CPU time 21.39 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 215712 kb
Host smart-166f8f8d-f963-4656-8cc9-2ee491f63099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114407070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4114407070
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.106445118
Short name T1583
Test name
Test status
Simulation time 21334471 ps
CPU time 0.79 seconds
Started Mar 10 01:49:24 PM PDT 24
Finished Mar 10 01:49:26 PM PDT 24
Peak memory 204892 kb
Host smart-b9f7ce31-97e8-49c3-bace-c14422156767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106445118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.106445118
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2839849898
Short name T670
Test name
Test status
Simulation time 776783585 ps
CPU time 13.3 seconds
Started Mar 10 02:46:32 PM PDT 24
Finished Mar 10 02:46:45 PM PDT 24
Peak memory 215952 kb
Host smart-f63070c5-05be-485b-831c-e2fd21eb6ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839849898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2839849898
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3476579278
Short name T1175
Test name
Test status
Simulation time 80639418 ps
CPU time 0.74 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:23 PM PDT 24
Peak memory 204896 kb
Host smart-bf7bf157-a3b8-40ae-baad-1d7866c2adbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476579278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3476579278
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.971236647
Short name T874
Test name
Test status
Simulation time 227092874 ps
CPU time 0.93 seconds
Started Mar 10 02:46:30 PM PDT 24
Finished Mar 10 02:46:31 PM PDT 24
Peak memory 205280 kb
Host smart-60927ff1-038f-4b73-82db-011c4ee499e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971236647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.971236647
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1683286799
Short name T515
Test name
Test status
Simulation time 6189619813 ps
CPU time 13.73 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:36 PM PDT 24
Peak memory 237976 kb
Host smart-5a62c63e-4ef5-4f2e-b223-b2c34d80370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683286799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1683286799
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_upload.4158410472
Short name T201
Test name
Test status
Simulation time 6584701001 ps
CPU time 21.09 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:46:54 PM PDT 24
Peak memory 232176 kb
Host smart-7b735196-5695-4182-8344-302648e5cdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158410472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4158410472
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2838680129
Short name T755
Test name
Test status
Simulation time 49038359 ps
CPU time 0.79 seconds
Started Mar 10 01:49:29 PM PDT 24
Finished Mar 10 01:49:30 PM PDT 24
Peak memory 203872 kb
Host smart-ae888161-ef10-4e5b-9396-f9c882dedb1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838680129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
838680129
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.472521499
Short name T126
Test name
Test status
Simulation time 37814951 ps
CPU time 0.7 seconds
Started Mar 10 02:46:40 PM PDT 24
Finished Mar 10 02:46:41 PM PDT 24
Peak memory 203812 kb
Host smart-021e642c-917a-4046-826c-acf048f03019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472521499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.472521499
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1141225782
Short name T226
Test name
Test status
Simulation time 1075947339 ps
CPU time 5.01 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:47:00 PM PDT 24
Peak memory 216940 kb
Host smart-fff27809-89c0-4b06-9120-3a34978ed999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141225782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1141225782
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3421442665
Short name T1521
Test name
Test status
Simulation time 221127580 ps
CPU time 2.85 seconds
Started Mar 10 01:49:26 PM PDT 24
Finished Mar 10 01:49:29 PM PDT 24
Peak memory 233044 kb
Host smart-d532f4d5-9025-4528-af80-a1eeac1b65d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421442665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3421442665
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2267238591
Short name T283
Test name
Test status
Simulation time 51101887 ps
CPU time 0.76 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:23 PM PDT 24
Peak memory 205480 kb
Host smart-e06eaca8-d830-4f07-8e00-45d9afdd0dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267238591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2267238591
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3832483748
Short name T412
Test name
Test status
Simulation time 45046114 ps
CPU time 0.8 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:46:34 PM PDT 24
Peak memory 205516 kb
Host smart-dd4330d5-194f-4b6e-9d83-9b08654d4baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832483748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3832483748
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1974019307
Short name T261
Test name
Test status
Simulation time 70861503203 ps
CPU time 132.26 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:49:07 PM PDT 24
Peak memory 261268 kb
Host smart-c18d614d-e6a3-4173-b3f5-b51fe645b7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974019307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1974019307
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3635037750
Short name T590
Test name
Test status
Simulation time 10697845917 ps
CPU time 58.51 seconds
Started Mar 10 01:49:28 PM PDT 24
Finished Mar 10 01:50:27 PM PDT 24
Peak memory 254680 kb
Host smart-05557efa-9df7-46d1-aa2c-fed785b4e4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635037750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3635037750
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2575556103
Short name T1556
Test name
Test status
Simulation time 3167295077 ps
CPU time 24.56 seconds
Started Mar 10 02:46:37 PM PDT 24
Finished Mar 10 02:47:02 PM PDT 24
Peak memory 233804 kb
Host smart-38470ed4-98af-48db-ac21-b9527ea7eeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575556103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2575556103
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4140150671
Short name T992
Test name
Test status
Simulation time 22304572742 ps
CPU time 105.08 seconds
Started Mar 10 01:49:34 PM PDT 24
Finished Mar 10 01:51:19 PM PDT 24
Peak memory 248544 kb
Host smart-ad00850b-1688-4ecf-a2ce-a884ce278a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140150671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4140150671
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1229639682
Short name T134
Test name
Test status
Simulation time 4510045514 ps
CPU time 94.96 seconds
Started Mar 10 02:46:38 PM PDT 24
Finished Mar 10 02:48:13 PM PDT 24
Peak memory 249668 kb
Host smart-9d371564-dcc0-41f9-8034-2d13c3e1b217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229639682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1229639682
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3741831386
Short name T1868
Test name
Test status
Simulation time 26930246765 ps
CPU time 61.28 seconds
Started Mar 10 01:49:26 PM PDT 24
Finished Mar 10 01:50:27 PM PDT 24
Peak memory 249584 kb
Host smart-e421824c-d680-466c-adc7-18bcd61f054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741831386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3741831386
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3996296017
Short name T1285
Test name
Test status
Simulation time 3369203749 ps
CPU time 18.46 seconds
Started Mar 10 01:49:28 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 248568 kb
Host smart-20a2eb82-ebd9-41d5-99a9-20a7dff4b556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996296017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3996296017
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1113861867
Short name T629
Test name
Test status
Simulation time 6320979480 ps
CPU time 5.71 seconds
Started Mar 10 01:49:27 PM PDT 24
Finished Mar 10 01:49:33 PM PDT 24
Peak memory 223936 kb
Host smart-785c7dea-db04-4e52-80ff-b9ee698afa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113861867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1113861867
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2587327517
Short name T1152
Test name
Test status
Simulation time 20295970015 ps
CPU time 8.07 seconds
Started Mar 10 02:46:40 PM PDT 24
Finished Mar 10 02:46:48 PM PDT 24
Peak memory 217036 kb
Host smart-e2413817-dae0-40c2-a1a2-1b75e3f9f973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587327517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2587327517
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1631496450
Short name T1761
Test name
Test status
Simulation time 1296875954 ps
CPU time 10.69 seconds
Started Mar 10 02:46:38 PM PDT 24
Finished Mar 10 02:46:49 PM PDT 24
Peak memory 241200 kb
Host smart-80039cd2-2af3-4c84-a609-0abacdbb7ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631496450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1631496450
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2960842548
Short name T210
Test name
Test status
Simulation time 6290545285 ps
CPU time 24.19 seconds
Started Mar 10 01:49:25 PM PDT 24
Finished Mar 10 01:49:50 PM PDT 24
Peak memory 226364 kb
Host smart-7d92ba28-68d0-4ae9-af65-008a7a274519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960842548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2960842548
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3156275345
Short name T1026
Test name
Test status
Simulation time 63192058 ps
CPU time 1.14 seconds
Started Mar 10 02:46:41 PM PDT 24
Finished Mar 10 02:46:42 PM PDT 24
Peak memory 217284 kb
Host smart-364c0fde-dda4-4c71-ad42-3aa9e83c22a5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156275345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3156275345
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.497513422
Short name T1880
Test name
Test status
Simulation time 16841541 ps
CPU time 1.05 seconds
Started Mar 10 01:49:27 PM PDT 24
Finished Mar 10 01:49:29 PM PDT 24
Peak memory 216044 kb
Host smart-e1cf0e6a-3693-4929-ab65-1152bf16b9f8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497513422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.497513422
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2329904373
Short name T649
Test name
Test status
Simulation time 6743797995 ps
CPU time 17.78 seconds
Started Mar 10 01:49:24 PM PDT 24
Finished Mar 10 01:49:42 PM PDT 24
Peak memory 223924 kb
Host smart-3aacdc11-a405-4ba0-8d13-4695821c7f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329904373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2329904373
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2924916114
Short name T797
Test name
Test status
Simulation time 12904674269 ps
CPU time 33.88 seconds
Started Mar 10 02:46:37 PM PDT 24
Finished Mar 10 02:47:11 PM PDT 24
Peak memory 232064 kb
Host smart-9bacda25-7fc2-4dfc-b29b-1bc15f3542d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924916114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2924916114
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1449351630
Short name T1856
Test name
Test status
Simulation time 7131794361 ps
CPU time 3.92 seconds
Started Mar 10 01:49:26 PM PDT 24
Finished Mar 10 01:49:30 PM PDT 24
Peak memory 223960 kb
Host smart-8173d6ae-a0ac-48cf-ac91-d1dbf51280e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449351630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1449351630
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4178451942
Short name T1523
Test name
Test status
Simulation time 498271365 ps
CPU time 3.35 seconds
Started Mar 10 02:46:40 PM PDT 24
Finished Mar 10 02:46:44 PM PDT 24
Peak memory 216060 kb
Host smart-2f173fa7-92aa-454f-b1e1-36737c0908e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178451942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4178451942
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.1048857290
Short name T1211
Test name
Test status
Simulation time 36779013 ps
CPU time 0.75 seconds
Started Mar 10 02:46:35 PM PDT 24
Finished Mar 10 02:46:36 PM PDT 24
Peak memory 215660 kb
Host smart-98225f6f-a19e-413a-9d10-cd1cec482353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048857290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.1048857290
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2918220782
Short name T1572
Test name
Test status
Simulation time 17555981 ps
CPU time 0.74 seconds
Started Mar 10 01:49:22 PM PDT 24
Finished Mar 10 01:49:23 PM PDT 24
Peak memory 215640 kb
Host smart-9d7ef815-509a-4891-aa01-8a7edc282f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918220782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2918220782
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1437141476
Short name T1066
Test name
Test status
Simulation time 786884662 ps
CPU time 5.33 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:47:00 PM PDT 24
Peak memory 221704 kb
Host smart-f2409e69-a127-4d7d-818b-92270d40f1af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1437141476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1437141476
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3543898493
Short name T1484
Test name
Test status
Simulation time 5161727731 ps
CPU time 6.27 seconds
Started Mar 10 01:49:28 PM PDT 24
Finished Mar 10 01:49:34 PM PDT 24
Peak memory 221736 kb
Host smart-2424c464-3540-45e7-9417-500b4627791a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3543898493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3543898493
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1202191583
Short name T440
Test name
Test status
Simulation time 37114734738 ps
CPU time 280.41 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:51:35 PM PDT 24
Peak memory 263740 kb
Host smart-58988104-8d0e-4b6a-ac93-1865c8d1749a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202191583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1202191583
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1670397599
Short name T451
Test name
Test status
Simulation time 4263014984 ps
CPU time 34.5 seconds
Started Mar 10 01:49:29 PM PDT 24
Finished Mar 10 01:50:04 PM PDT 24
Peak memory 237308 kb
Host smart-2979f249-05b1-4286-817a-c8ec5bc1d7b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670397599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1670397599
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2792678069
Short name T677
Test name
Test status
Simulation time 2203381927 ps
CPU time 9.61 seconds
Started Mar 10 02:46:31 PM PDT 24
Finished Mar 10 02:46:41 PM PDT 24
Peak memory 215816 kb
Host smart-9e1e8a1c-1c2d-46a1-80c6-8a4b27078d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792678069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2792678069
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.755435850
Short name T668
Test name
Test status
Simulation time 1732325018 ps
CPU time 13.17 seconds
Started Mar 10 01:49:27 PM PDT 24
Finished Mar 10 01:49:41 PM PDT 24
Peak memory 215712 kb
Host smart-93361510-1aa5-48c6-8fc7-aecfadc29756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755435850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.755435850
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1238493454
Short name T1319
Test name
Test status
Simulation time 4604346904 ps
CPU time 14.31 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:46:47 PM PDT 24
Peak memory 215808 kb
Host smart-be54e089-a67c-4f75-bab1-a629c9316b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238493454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1238493454
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2188634850
Short name T1586
Test name
Test status
Simulation time 1269579390 ps
CPU time 3.44 seconds
Started Mar 10 01:49:28 PM PDT 24
Finished Mar 10 01:49:32 PM PDT 24
Peak memory 215536 kb
Host smart-835a3d01-43e5-49e4-821a-a9e707cd61f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188634850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2188634850
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2351759316
Short name T1871
Test name
Test status
Simulation time 691193562 ps
CPU time 3.12 seconds
Started Mar 10 02:46:42 PM PDT 24
Finished Mar 10 02:46:45 PM PDT 24
Peak memory 215936 kb
Host smart-81a3fbaa-ad2f-4747-b4d7-55d16cb337be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351759316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2351759316
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3089989389
Short name T622
Test name
Test status
Simulation time 262678167 ps
CPU time 2.75 seconds
Started Mar 10 01:49:29 PM PDT 24
Finished Mar 10 01:49:32 PM PDT 24
Peak memory 215736 kb
Host smart-cc84a4b8-deb7-48e6-82ef-4dcbc8b4e1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089989389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3089989389
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1910025961
Short name T1178
Test name
Test status
Simulation time 39244046 ps
CPU time 0.85 seconds
Started Mar 10 01:49:29 PM PDT 24
Finished Mar 10 01:49:30 PM PDT 24
Peak memory 204880 kb
Host smart-71688dc1-8e89-4224-9d48-7269618fc9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910025961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1910025961
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.445755938
Short name T1106
Test name
Test status
Simulation time 16803474 ps
CPU time 0.75 seconds
Started Mar 10 02:46:33 PM PDT 24
Finished Mar 10 02:46:34 PM PDT 24
Peak memory 204904 kb
Host smart-bfa1f22b-d444-42af-a614-40918d81327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445755938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.445755938
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1988115721
Short name T1783
Test name
Test status
Simulation time 1702401212 ps
CPU time 7.6 seconds
Started Mar 10 02:46:38 PM PDT 24
Finished Mar 10 02:46:45 PM PDT 24
Peak memory 236904 kb
Host smart-25f92be6-aed3-42f8-b419-a66a8a2aacec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988115721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1988115721
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_upload.402941792
Short name T963
Test name
Test status
Simulation time 4763458859 ps
CPU time 16.18 seconds
Started Mar 10 01:49:31 PM PDT 24
Finished Mar 10 01:49:47 PM PDT 24
Peak memory 219344 kb
Host smart-04c611de-13c7-466a-b550-8674c35b5a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402941792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.402941792
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2106505586
Short name T473
Test name
Test status
Simulation time 13985466 ps
CPU time 0.75 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:46:49 PM PDT 24
Peak memory 204336 kb
Host smart-c03642e6-6520-4b2d-bbb9-8bbee991fe38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106505586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
106505586
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.544659895
Short name T503
Test name
Test status
Simulation time 17854959 ps
CPU time 0.67 seconds
Started Mar 10 01:49:34 PM PDT 24
Finished Mar 10 01:49:35 PM PDT 24
Peak memory 204276 kb
Host smart-c0a62afd-b7d8-4fb3-8715-d94dd835dfd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544659895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.544659895
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1550574516
Short name T1850
Test name
Test status
Simulation time 95772707 ps
CPU time 2.56 seconds
Started Mar 10 01:49:31 PM PDT 24
Finished Mar 10 01:49:35 PM PDT 24
Peak memory 216124 kb
Host smart-e6998418-9449-4c04-ad29-18da40c1ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550574516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1550574516
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2800116610
Short name T714
Test name
Test status
Simulation time 2013506160 ps
CPU time 4.27 seconds
Started Mar 10 02:46:42 PM PDT 24
Finished Mar 10 02:46:47 PM PDT 24
Peak memory 218896 kb
Host smart-acae2475-663c-45f4-8ce7-07e76646e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800116610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2800116610
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.147269161
Short name T702
Test name
Test status
Simulation time 84607962 ps
CPU time 0.82 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:46:56 PM PDT 24
Peak memory 205460 kb
Host smart-6b8bfb98-a519-4596-b5bb-8d2b20986984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147269161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.147269161
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4044619329
Short name T1165
Test name
Test status
Simulation time 25530634 ps
CPU time 0.78 seconds
Started Mar 10 01:49:26 PM PDT 24
Finished Mar 10 01:49:27 PM PDT 24
Peak memory 204524 kb
Host smart-3bdaefb0-0aac-49a0-aa73-923d39725be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044619329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4044619329
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1299489033
Short name T632
Test name
Test status
Simulation time 92853481816 ps
CPU time 167.93 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:49:31 PM PDT 24
Peak memory 235364 kb
Host smart-f5b7d5a5-d16c-4089-af99-af513b26408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299489033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1299489033
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2075636314
Short name T1821
Test name
Test status
Simulation time 30557961321 ps
CPU time 129.59 seconds
Started Mar 10 01:49:30 PM PDT 24
Finished Mar 10 01:51:40 PM PDT 24
Peak memory 251580 kb
Host smart-4adbe041-3e2b-486a-ac9a-1818dfe64289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075636314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2075636314
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1187529201
Short name T250
Test name
Test status
Simulation time 58193223787 ps
CPU time 373.33 seconds
Started Mar 10 01:49:35 PM PDT 24
Finished Mar 10 01:55:49 PM PDT 24
Peak memory 268876 kb
Host smart-c95929fb-c9ce-4b04-bfae-6bef7ab1c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187529201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1187529201
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2199805118
Short name T244
Test name
Test status
Simulation time 10757512433 ps
CPU time 67.86 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:47:51 PM PDT 24
Peak memory 248020 kb
Host smart-b51a0806-573c-480b-af9c-b0d3c51f87ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199805118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2199805118
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2184498473
Short name T1068
Test name
Test status
Simulation time 54074337142 ps
CPU time 162.61 seconds
Started Mar 10 01:49:35 PM PDT 24
Finished Mar 10 01:52:18 PM PDT 24
Peak memory 283864 kb
Host smart-f21287a4-811a-4ad5-af0e-74843b11cad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184498473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2184498473
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2215559387
Short name T259
Test name
Test status
Simulation time 37244965354 ps
CPU time 74.22 seconds
Started Mar 10 02:46:46 PM PDT 24
Finished Mar 10 02:48:01 PM PDT 24
Peak memory 233256 kb
Host smart-09b1d790-01eb-451b-a195-2596564e6c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215559387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2215559387
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2579005601
Short name T1204
Test name
Test status
Simulation time 1953656120 ps
CPU time 10.2 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:46:57 PM PDT 24
Peak memory 236024 kb
Host smart-1a7968c5-2a42-439e-8eaa-b0ecb81700dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579005601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2579005601
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3135677644
Short name T865
Test name
Test status
Simulation time 12771193468 ps
CPU time 30.83 seconds
Started Mar 10 01:49:35 PM PDT 24
Finished Mar 10 01:50:07 PM PDT 24
Peak memory 233156 kb
Host smart-d0e50223-eefe-4348-a091-074b8c316fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135677644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3135677644
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2382437652
Short name T846
Test name
Test status
Simulation time 12640636223 ps
CPU time 11.85 seconds
Started Mar 10 01:49:31 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 233860 kb
Host smart-4e5ec1e5-0d32-43a9-8ab2-35d752436602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382437652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2382437652
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intercept.841938320
Short name T1423
Test name
Test status
Simulation time 211427045 ps
CPU time 2.57 seconds
Started Mar 10 02:46:45 PM PDT 24
Finished Mar 10 02:46:48 PM PDT 24
Peak memory 215780 kb
Host smart-6bde8bfd-4605-403a-bb3c-9d93209764bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841938320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.841938320
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1307305045
Short name T1294
Test name
Test status
Simulation time 19009595700 ps
CPU time 8.51 seconds
Started Mar 10 01:49:31 PM PDT 24
Finished Mar 10 01:49:39 PM PDT 24
Peak memory 223964 kb
Host smart-90515612-e781-4846-8c43-602b260c81ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307305045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1307305045
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3787605949
Short name T1353
Test name
Test status
Simulation time 16802673062 ps
CPU time 30.78 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:47:14 PM PDT 24
Peak memory 235084 kb
Host smart-6ccd4055-58be-41a4-97ea-5287114dc48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787605949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3787605949
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2012752858
Short name T1434
Test name
Test status
Simulation time 33138613 ps
CPU time 1.11 seconds
Started Mar 10 01:49:28 PM PDT 24
Finished Mar 10 01:49:29 PM PDT 24
Peak memory 216056 kb
Host smart-c27dd04a-998c-4e9d-8739-327f481e5fce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012752858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2012752858
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2162612820
Short name T1554
Test name
Test status
Simulation time 26647542 ps
CPU time 1.1 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:46:56 PM PDT 24
Peak memory 216032 kb
Host smart-9c974713-91fd-4b17-935d-bf0c6df3e812
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162612820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2162612820
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4122582284
Short name T1486
Test name
Test status
Simulation time 2518164108 ps
CPU time 10.27 seconds
Started Mar 10 01:49:35 PM PDT 24
Finished Mar 10 01:49:46 PM PDT 24
Peak memory 234804 kb
Host smart-47350367-e43d-40ac-b265-01decf431024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122582284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4122582284
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.448582591
Short name T651
Test name
Test status
Simulation time 13870588661 ps
CPU time 11.36 seconds
Started Mar 10 02:46:44 PM PDT 24
Finished Mar 10 02:46:55 PM PDT 24
Peak memory 237424 kb
Host smart-77b737aa-89b8-41e8-a874-5c57b49a9e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448582591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
448582591
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2015966712
Short name T1765
Test name
Test status
Simulation time 732426066 ps
CPU time 3.01 seconds
Started Mar 10 01:49:34 PM PDT 24
Finished Mar 10 01:49:37 PM PDT 24
Peak memory 232560 kb
Host smart-5d418127-0460-49d9-8d61-4dadce9da4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015966712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2015966712
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.792510364
Short name T924
Test name
Test status
Simulation time 48523331865 ps
CPU time 16.96 seconds
Started Mar 10 02:46:47 PM PDT 24
Finished Mar 10 02:47:04 PM PDT 24
Peak memory 217796 kb
Host smart-f254f6c2-20e0-446e-b58d-8151574af0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792510364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.792510364
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1815899930
Short name T1189
Test name
Test status
Simulation time 71796049 ps
CPU time 0.79 seconds
Started Mar 10 02:46:55 PM PDT 24
Finished Mar 10 02:46:56 PM PDT 24
Peak memory 215604 kb
Host smart-29ba4a85-e39a-4536-9da3-9a8ad8257995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815899930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1815899930
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2220481894
Short name T915
Test name
Test status
Simulation time 23918335 ps
CPU time 0.75 seconds
Started Mar 10 01:49:31 PM PDT 24
Finished Mar 10 01:49:33 PM PDT 24
Peak memory 215648 kb
Host smart-008ba0ec-d8f5-47b1-bd4c-8955fa22df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220481894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2220481894
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2909109055
Short name T996
Test name
Test status
Simulation time 2166048659 ps
CPU time 3.62 seconds
Started Mar 10 02:46:44 PM PDT 24
Finished Mar 10 02:46:48 PM PDT 24
Peak memory 218388 kb
Host smart-d1a8401e-5fa4-4d71-8ec0-b6553ebdeacf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2909109055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2909109055
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3564054726
Short name T638
Test name
Test status
Simulation time 149064167 ps
CPU time 3.67 seconds
Started Mar 10 01:49:31 PM PDT 24
Finished Mar 10 01:49:35 PM PDT 24
Peak memory 221960 kb
Host smart-41ba3fb5-7abe-4206-9ae3-8f22e15ed9b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3564054726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3564054726
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3449426598
Short name T1201
Test name
Test status
Simulation time 30518118613 ps
CPU time 48.95 seconds
Started Mar 10 01:49:30 PM PDT 24
Finished Mar 10 01:50:19 PM PDT 24
Peak memory 248640 kb
Host smart-4c20b197-a513-45db-851e-d987b76689aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449426598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3449426598
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.564068840
Short name T936
Test name
Test status
Simulation time 975230102265 ps
CPU time 1013.52 seconds
Started Mar 10 02:46:48 PM PDT 24
Finished Mar 10 03:03:42 PM PDT 24
Peak memory 280716 kb
Host smart-39f414d1-d44a-41eb-80f5-cbcdd63daef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564068840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.564068840
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2674376639
Short name T87
Test name
Test status
Simulation time 5073903268 ps
CPU time 41.71 seconds
Started Mar 10 01:49:34 PM PDT 24
Finished Mar 10 01:50:17 PM PDT 24
Peak memory 215804 kb
Host smart-5f6f26b4-1e91-4bf2-93b2-29b4cf75f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674376639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2674376639
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4052964728
Short name T1603
Test name
Test status
Simulation time 10200927813 ps
CPU time 54.73 seconds
Started Mar 10 02:46:54 PM PDT 24
Finished Mar 10 02:47:49 PM PDT 24
Peak memory 215760 kb
Host smart-2ed744e7-24b6-4fe0-b0ca-b94d9ba93337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052964728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4052964728
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.154533145
Short name T568
Test name
Test status
Simulation time 7500188700 ps
CPU time 11.33 seconds
Started Mar 10 02:46:39 PM PDT 24
Finished Mar 10 02:46:50 PM PDT 24
Peak memory 216920 kb
Host smart-3b7a97a2-da7f-4928-8072-7a8eadfa5651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154533145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.154533145
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.858637397
Short name T292
Test name
Test status
Simulation time 17579337843 ps
CPU time 32.3 seconds
Started Mar 10 01:49:34 PM PDT 24
Finished Mar 10 01:50:06 PM PDT 24
Peak memory 215796 kb
Host smart-3a8750fb-4e0c-424a-8c73-cc2773651f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858637397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.858637397
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2038711333
Short name T1027
Test name
Test status
Simulation time 353914057 ps
CPU time 6.21 seconds
Started Mar 10 02:46:39 PM PDT 24
Finished Mar 10 02:46:45 PM PDT 24
Peak memory 215740 kb
Host smart-5fa75e62-35a0-4662-a892-eebe20184cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038711333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2038711333
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.449659809
Short name T407
Test name
Test status
Simulation time 12099589 ps
CPU time 0.74 seconds
Started Mar 10 01:49:31 PM PDT 24
Finished Mar 10 01:49:33 PM PDT 24
Peak memory 204856 kb
Host smart-22984249-91f5-4164-b32d-2e9918ea6d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449659809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.449659809
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1020810768
Short name T549
Test name
Test status
Simulation time 260324901 ps
CPU time 1.14 seconds
Started Mar 10 01:49:29 PM PDT 24
Finished Mar 10 01:49:31 PM PDT 24
Peak memory 205936 kb
Host smart-fb9616ad-f3d0-4660-8991-68c812b45abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020810768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1020810768
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4236662648
Short name T722
Test name
Test status
Simulation time 628900626 ps
CPU time 0.8 seconds
Started Mar 10 02:46:37 PM PDT 24
Finished Mar 10 02:46:38 PM PDT 24
Peak memory 204912 kb
Host smart-3389f3ac-9d37-4f12-ab78-dd707ebe347e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236662648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4236662648
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1839326960
Short name T158
Test name
Test status
Simulation time 893230114 ps
CPU time 6.78 seconds
Started Mar 10 02:46:43 PM PDT 24
Finished Mar 10 02:46:50 PM PDT 24
Peak memory 223544 kb
Host smart-7c60ab60-08bd-4880-955f-15ac4928fc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839326960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1839326960
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_upload.3441782697
Short name T1195
Test name
Test status
Simulation time 56309200624 ps
CPU time 41.03 seconds
Started Mar 10 01:49:36 PM PDT 24
Finished Mar 10 01:50:18 PM PDT 24
Peak memory 246392 kb
Host smart-0e836631-1c69-4f53-9cdd-ee25a89d6e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441782697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3441782697
Directory /workspace/9.spi_device_upload/latest
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