Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15989822	1			T2	1898		T3	1		T4	1
all_values[1]	15989822	1			T2	1898		T3	1		T4	1
all_values[2]	15989822	1			T2	1898		T3	1		T4	1
all_values[3]	15989822	1			T2	1898		T3	1		T4	1
all_values[4]	15989822	1			T2	1898		T3	1		T4	1
all_values[5]	15989822	1			T2	1898		T3	1		T4	1
all_values[6]	15989822	1			T2	1898		T3	1		T4	1
all_values[7]	15989822	1			T2	1898		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125342025

1

T2

15184

T3

8

T4

8

auto[1]

2576551

1

T28

47

T49

44

T53

239792

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127770008

1

T2

15184

T3

8

T4

8

auto[1]

148568

1

T5

531

T7

815

T9

188

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	15626733	1			T2	1898		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	81757	1			T5	314		T7	585		T9	117
all_values[0]	auto[1]	auto[0]	277649	1			T28	2		T49	3		T53	29752
all_values[0]	auto[1]	auto[1]	3683	1			T28	4		T49	2		T53	221
all_values[1]	auto[0]	auto[0]	15672345	1			T2	1898		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	40620	1			T5	144		T7	184		T9	71
all_values[1]	auto[1]	auto[0]	274632	1			T28	5		T49	1		T53	29894
all_values[1]	auto[1]	auto[1]	2225	1			T28	3		T49	1		T53	81
all_values[2]	auto[0]	auto[0]	15694856	1			T2	1898		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	15509	1			T5	73		T7	46		T11	152
all_values[2]	auto[1]	auto[0]	278813	1			T28	3		T49	1		T53	29967
all_values[2]	auto[1]	auto[1]	644	1			T28	2		T49	1		T53	10
all_values[3]	auto[0]	auto[0]	15760845	1			T2	1898		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	410	1			T28	3		T49	4		T53	6
all_values[3]	auto[1]	auto[0]	228199	1			T28	1		T49	4		T53	29973
all_values[3]	auto[1]	auto[1]	368	1			T28	1		T49	3		T53	2
all_values[4]	auto[0]	auto[0]	15567546	1			T2	1898		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	391	1			T28	3		T49	2		T53	6
all_values[4]	auto[1]	auto[0]	421485	1			T28	5		T49	7		T53	29963
all_values[4]	auto[1]	auto[1]	400	1			T28	3		T49	2		T53	6
all_values[5]	auto[0]	auto[0]	15501613	1			T2	1898		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	725	1			T24	5		T28	1		T49	3
all_values[5]	auto[1]	auto[0]	487142	1			T28	10		T49	4		T53	29969
all_values[5]	auto[1]	auto[1]	342	1			T28	1		T49	3		T53	2
all_values[6]	auto[0]	auto[0]	15678737	1			T2	1898		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	365	1			T28	2		T49	3		T53	1
all_values[6]	auto[1]	auto[0]	310351	1			T28	3		T49	5		T53	29966
all_values[6]	auto[1]	auto[1]	369	1			T28	3		T49	2		T53	8
all_values[7]	auto[0]	auto[0]	15699195	1			T2	1898		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	378	1			T28	1		T49	4		T53	6
all_values[7]	auto[1]	auto[0]	289867	1			T28	1		T49	2		T53	29973
all_values[7]	auto[1]	auto[1]	382	1			T49	3		T53	5		T136	3