ASSERT | PROPERTIES | SEQUENCES | |
Total | 673 | 0 | 10 |
Category 0 | 673 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 673 | 0 | 10 |
Severity 0 | 673 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 673 | 100.00 |
Uncovered | 29 | 4.31 |
Success | 644 | 95.69 |
Failure | 0 | 0.00 |
Incomplete | 1 | 0.15 |
Without Attempts | 6 | 0.89 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A | 0 | 0 | 1203785710 | 11 | 0 | 1852 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1 | 0 | 0 | 0 | 0 | 0 | 0 | |
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1 | 0 | 0 | 0 | 0 | 0 | 0 | |
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1 | 0 | 0 | 0 | 0 | 0 | 0 | |
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 | 0 | 0 | 0 | 0 | 0 | 0 | |
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 | 0 | 0 | 0 | 0 | 0 | 0 | |
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 | 0 | 0 | 0 | 0 | 0 | 0 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1208499989 | 228938 | 228938 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1208499989 | 5034 | 5034 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1208499989 | 5162 | 5162 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1208499989 | 3379 | 3379 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1208499989 | 425 | 425 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1208499989 | 2648 | 2648 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1208499989 | 2342 | 2342 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1208499989 | 25510 | 25510 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1208499989 | 2514562 | 2514562 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1208499989 | 12200899 | 12200899 | 2162 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1208499989 | 228938 | 228938 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1208499989 | 5034 | 5034 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1208499989 | 5162 | 5162 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1208499989 | 3379 | 3379 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1208499989 | 425 | 425 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1208499989 | 2648 | 2648 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1208499989 | 2342 | 2342 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1208499989 | 25510 | 25510 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1208499989 | 2514562 | 2514562 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1208499989 | 12200899 | 12200899 | 2162 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |