Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total673010
Category 0673010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total673010
Severity 0673010


Summary for Assertions
NUMBERPERCENT
Total Number673100.00
Uncovered294.31
Success64495.69
Failure00.00
Incomplete10.15
Without Attempts60.89


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.InterceptLevel_M 00381990775000
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.SyncReqAckAckNeedsReq 00381988954000
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.SyncReqAckHoldReq 001203785710000
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A 00381988954000
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A 00381988954000
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M 00381988954000
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A 00381988954000
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataHoldSrc2Dst 001203785710000
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A 001203785710000
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A 001203785710000
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M 001203785710000
tb.dut.u_tlul2sram_egress.rvalidHighReqFifoEmpty 001203785710000
tb.dut.u_tlul2sram_egress.rvalidHighWhenRspFifoFull 001203785710000
tb.dut.u_tlul2sram_egress.u_rspfifo.DataKnown_A 001203785710000
tb.dut.u_tlul2sram_egress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 001203785710000
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DataKnown_A 001203785710000
tb.dut.u_tlul2sram_egress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 001203785710000
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A 00381988954000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A 00381988954000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M 00381988954000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A 00381988954000
tb.dut.u_upload.u_arbiter.u_req_fifo.DataKnown_A 00381988954000
tb.dut.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00381988954000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertKnownO_A 001203785710120361784400
tb.dut.CioSdoEnOKnown 001203785710120361784400
tb.dut.CioSdoEnOffWhenInactive 001203785710120361784400
tb.dut.FpvSecCmRegWeOnehotCheck_A 00120378571019000
tb.dut.IntrReadbufFlipOKnown 001203785710120361784400
tb.dut.IntrReadbufWatermarkOKnown 001203785710120361784400
tb.dut.IntrTpmHeaderNotEmptyOKnown 001203785710120361784400
tb.dut.IntrTpmRdfifoCmdEndOKnown 001203785710120361784400
tb.dut.IntrTpmRdfifoDropOKnown 001203785710120361784400
tb.dut.IntrUploadCmdfifoNotEmptyOKnown 001203785710120361784400
tb.dut.IntrUploadPayloadNotEmptyOKnown 001203785710120361784400
tb.dut.IntrUploadPayloadOverflowOKnown 001203785710120361784400
tb.dut.PayloadStartIdxWidthMatch_A 001852185200
tb.dut.SpiModeKnown_A 001203785710120361784400
tb.dut.TpmEnableWhenTpmCsbIdle_M 00120378571069200
tb.dut.g_sram_connect[0].ReqAlwaysAccepted_A 001203785710438222400
tb.dut.g_sram_connect[1].ReqAlwaysAccepted_A 00120378571042329900
tb.dut.g_sram_connect[2].ReqAlwaysAccepted_A 001203785710472400
tb.dut.g_sram_connect[3].ReqAlwaysAccepted_A 001203785710350800
tb.dut.g_sram_connect[4].ReqAlwaysAccepted_A 00120378571055554800
tb.dut.scanmodeKnown 001203785710120378571000
tb.dut.spi_device_csr_assert.TlulOOBAddrErr_A 001208498655708500
tb.dut.spi_device_csr_assert.addr_swap_data_rd_A 001208498655443300
tb.dut.spi_device_csr_assert.addr_swap_mask_rd_A 001208498655445200
tb.dut.spi_device_csr_assert.cfg_rd_A 001208498655571700
tb.dut.spi_device_csr_assert.cmd_filter_0_rd_A 0012084986552459700
tb.dut.spi_device_csr_assert.cmd_filter_1_rd_A 0012084986552784700
tb.dut.spi_device_csr_assert.cmd_filter_2_rd_A 0012084986552670900
tb.dut.spi_device_csr_assert.cmd_filter_3_rd_A 0012084986552738200
tb.dut.spi_device_csr_assert.cmd_filter_4_rd_A 0012084986552662900
tb.dut.spi_device_csr_assert.cmd_filter_5_rd_A 0012084986552895600
tb.dut.spi_device_csr_assert.cmd_filter_6_rd_A 0012084986552600600
tb.dut.spi_device_csr_assert.cmd_filter_7_rd_A 0012084986552630300
tb.dut.spi_device_csr_assert.cmd_info_0_rd_A 0012084986551311800
tb.dut.spi_device_csr_assert.cmd_info_10_rd_A 0012084986551304900
tb.dut.spi_device_csr_assert.cmd_info_11_rd_A 0012084986551441200
tb.dut.spi_device_csr_assert.cmd_info_12_rd_A 0012084986551357500
tb.dut.spi_device_csr_assert.cmd_info_13_rd_A 0012084986551283400
tb.dut.spi_device_csr_assert.cmd_info_14_rd_A 0012084986551311200
tb.dut.spi_device_csr_assert.cmd_info_15_rd_A 0012084986551264500
tb.dut.spi_device_csr_assert.cmd_info_16_rd_A 0012084986551295700
tb.dut.spi_device_csr_assert.cmd_info_17_rd_A 0012084986551330300
tb.dut.spi_device_csr_assert.cmd_info_18_rd_A 0012084986551250300
tb.dut.spi_device_csr_assert.cmd_info_19_rd_A 0012084986551205000
tb.dut.spi_device_csr_assert.cmd_info_1_rd_A 0012084986551321500
tb.dut.spi_device_csr_assert.cmd_info_20_rd_A 0012084986551259600
tb.dut.spi_device_csr_assert.cmd_info_21_rd_A 0012084986551280100
tb.dut.spi_device_csr_assert.cmd_info_22_rd_A 0012084986551318200
tb.dut.spi_device_csr_assert.cmd_info_23_rd_A 0012084986551264800
tb.dut.spi_device_csr_assert.cmd_info_2_rd_A 0012084986551365800
tb.dut.spi_device_csr_assert.cmd_info_3_rd_A 0012084986551273200
tb.dut.spi_device_csr_assert.cmd_info_4_rd_A 0012084986551258100
tb.dut.spi_device_csr_assert.cmd_info_5_rd_A 0012084986551389900
tb.dut.spi_device_csr_assert.cmd_info_6_rd_A 0012084986551403400
tb.dut.spi_device_csr_assert.cmd_info_7_rd_A 0012084986551260100
tb.dut.spi_device_csr_assert.cmd_info_8_rd_A 0012084986551314600
tb.dut.spi_device_csr_assert.cmd_info_9_rd_A 0012084986551338300
tb.dut.spi_device_csr_assert.cmd_info_en4b_rd_A 001208498655516100
tb.dut.spi_device_csr_assert.cmd_info_ex4b_rd_A 001208498655493300
tb.dut.spi_device_csr_assert.cmd_info_wrdi_rd_A 001208498655495600
tb.dut.spi_device_csr_assert.cmd_info_wren_rd_A 001208498655503300
tb.dut.spi_device_csr_assert.intercept_en_rd_A 001208498655619600
tb.dut.spi_device_csr_assert.intr_enable_rd_A 0012084986551043100
tb.dut.spi_device_csr_assert.jedec_cc_rd_A 001208498655517900
tb.dut.spi_device_csr_assert.jedec_id_rd_A 001208498655505100
tb.dut.spi_device_csr_assert.mailbox_addr_rd_A 001208498655437000
tb.dut.spi_device_csr_assert.payload_swap_data_rd_A 001208498655431000
tb.dut.spi_device_csr_assert.payload_swap_mask_rd_A 001208498655467200
tb.dut.spi_device_csr_assert.read_threshold_rd_A 001208498655449200
tb.dut.spi_device_csr_assert.tpm_access_0_rd_A 001208498655659000
tb.dut.spi_device_csr_assert.tpm_access_1_rd_A 001208498655423800
tb.dut.spi_device_csr_assert.tpm_cfg_rd_A 001208498655767400
tb.dut.spi_device_csr_assert.tpm_did_vid_rd_A 001208498655494500
tb.dut.spi_device_csr_assert.tpm_int_enable_rd_A 001208498655430800
tb.dut.spi_device_csr_assert.tpm_int_status_rd_A 001208498655417000
tb.dut.spi_device_csr_assert.tpm_int_vector_rd_A 001208498655448000
tb.dut.spi_device_csr_assert.tpm_intf_capability_rd_A 001208498655432300
tb.dut.spi_device_csr_assert.tpm_rid_rd_A 001208498655433300
tb.dut.spi_device_csr_assert.tpm_sts_rd_A 001208498655440400
tb.dut.tlul_assert_device.aKnown_A 0012084986553110688300
tb.dut.tlul_assert_device.aKnown_AKnownEnable 001208498655120823656200
tb.dut.tlul_assert_device.aReadyKnown_A 001208498655120823656200
tb.dut.tlul_assert_device.dKnown_A 0012084986556007419300
tb.dut.tlul_assert_device.dKnown_AKnownEnable 001208498655120823656200
tb.dut.tlul_assert_device.dReadyKnown_A 001208498655120823656200
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 002202220200
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tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 002202220200
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tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 002202220200
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 0012084999891252547400
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 0012084986551532600
tb.dut.tlul_assert_device.gen_device.contigMask_M 0012084999892406869800
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 0012084999894015033300
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 0012084986551261400
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012084999893110688300
tb.dut.tlul_assert_device.gen_device.legalDParam_A 0012084999896007419300
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012084999893110688300
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 0012084999896007419300
tb.dut.tlul_assert_device.gen_device.respOpcode_A 0012084999896007419300
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 0012084999896007419300
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 0012084986551153100
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 0012084986551145400
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 002202220200
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown0 0014772914587700
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown0 0038199077538198892300
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown1 0038198895438198740000
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown0 0038198895438198740000
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown0 0038199077538198892300
tb.dut.u_cmdparse.CmdOnlySelDpKnown_A 0038198895429357861100
tb.dut.u_cmdparse.OnlyOneDatapath_A 0038198895414405000
tb.dut.u_cmdparse.SelDpKnown_A 0038198895429357861100
tb.dut.u_cmdparse.StKnown_A 0038198895429357861100
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0 0014587714459500
tb.dut.u_flash_readbuf_flip_pulse_sync.DstPulseCheck_A 001203785710116200
tb.dut.u_flash_readbuf_flip_pulse_sync.SrcPulseCheck_M 00381988954116200
tb.dut.u_flash_readbuf_watermark_pulse_sync.DstPulseCheck_A 00120378571080200
tb.dut.u_flash_readbuf_watermark_pulse_sync.SrcPulseCheck_M 0038198895480200
tb.dut.u_intr_cmdfifo_not_empty.IntrTKind_A 001852185200
tb.dut.u_intr_payload_not_empty.IntrTKind_A 001852185200
tb.dut.u_intr_payload_overflow.IntrTKind_A 001852185200
tb.dut.u_intr_readbuf_flip.IntrTKind_A 001852185200
tb.dut.u_intr_readbuf_watermark.IntrTKind_A 001852185200
tb.dut.u_intr_tpm_cmdaddr_notempty.IntrTKind_A 001852185200
tb.dut.u_intr_tpm_rdfifo_cmd_end.IntrTKind_A 001852185200
tb.dut.u_intr_tpm_rdfifo_drop.IntrTKind_A 001852185200
tb.dut.u_jedec.JedecStKnown_A 0038198895429357861100
tb.dut.u_p2s.IoModeChangeValid_A 003819907751810600
tb.dut.u_p2s.IoModeDefault_A 003819907755888200
tb.dut.u_passthrough.PassThroughStKnown_A 0038198895429357861100
tb.dut.u_passthrough.PayloadSwapConstraint_M 00381988954392900000
tb.dut.u_readcmd.AddrIncNotAssertInAddressState_A 003819889541186071000
tb.dut.u_readcmd.MailboxSizeMatch_M 0038198895429357861100
tb.dut.u_readcmd.ValidCmdConfig_A 0038198895452820800
tb.dut.u_readcmd.u_readbuffer.StartWithAddressUpdate_A 003819889541993600
tb.dut.u_readcmd.u_readsram.AddrLatchedPulse_M 0038198895416392600
tb.dut.u_readcmd.u_readsram.FifoNotEmpty_A 003819889541186071000
tb.dut.u_readcmd.u_readsram.NotOverflow_A 00381988954299005100
tb.dut.u_readcmd.u_readsram.ReqStrbRelation_M 003819889541993600
tb.dut.u_readcmd.u_readsram.SramDataReturnRequirement_M 00381988954298876500
tb.dut.u_readcmd.u_readsram.SramReadOnly_A 00381988954299005100
tb.dut.u_readcmd.u_readsram.u_fifo.DataKnown_A 003819889545954082200
tb.dut.u_readcmd.u_readsram.u_fifo.DepthKnown_A 0038198895429357861100
tb.dut.u_readcmd.u_readsram.u_fifo.RvalidKnown_A 0038198895429357861100
tb.dut.u_readcmd.u_readsram.u_fifo.WreadyKnown_A 0038198895429357861100
tb.dut.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003819889545954082200
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A 003819889545661057900
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DepthKnown_A 0038198895429357861100
tb.dut.u_readcmd.u_readsram.u_sram_fifo.RvalidKnown_A 0038198895429357861100
tb.dut.u_readcmd.u_readsram.u_sram_fifo.WreadyKnown_A 0038198895429357861100
tb.dut.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003819889545661057900
tb.dut.u_reg.en2addrHit 0012084986552179634800
tb.dut.u_reg.reAfterRv 0012084986552179634800
tb.dut.u_reg.rePulse 0012084986551700875900
tb.dut.u_reg.u_chk.PayLoadWidthCheck 002202220200
tb.dut.u_reg.u_reg_if.AllowedLatency_A 002202220200
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 002202220200
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 002202220200
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 002202220200
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 002202220200
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 002202220200
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 002202220200
tb.dut.u_reg.u_socket.NotOverflowed_A 001208498655120823656200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A 0012084986553110688300
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 002202220200
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A 0012084986556007419300
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 002202220200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 001208498655663396300
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 002202220200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 001208498655732809200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 002202220200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 00120849865543697200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 002202220200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 001208498655105202800
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 002202220200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A 0012084986552334653200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 002202220200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A 0012084986555169407300
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A 001208498655120823656200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 002202220200
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A 002202220200
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck 002202220200
tb.dut.u_reg.u_socket.maxN 002202220200
tb.dut.u_reg.wePulse 001208498655478758900
tb.dut.u_s2p.IoModeDefault_A 003819889545888200
tb.dut.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 001852185200
tb.dut.u_scanmode_sync.OutputsKnown_A 001203785710120361784400
tb.dut.u_scanmode_sync.gen_no_flops.OutputDelay_A 001203785710120361784400
tb.dut.u_spi_tpm.CmdAddrAvailable_A 0038198895414323000
tb.dut.u_spi_tpm.CmdAddrBitCntInAddrSt_A 00381988954154688000
tb.dut.u_spi_tpm.CmdAddrInfo_A 0038198895415503500
tb.dut.u_spi_tpm.CmdPowerof2_A 001852185200
tb.dut.u_spi_tpm.DataFifoLessThan64_A 001852185200
tb.dut.u_spi_tpm.DataSelKnown_A 003819907758479708700
tb.dut.u_spi_tpm.HwRegCondition2_a 003819889543123700
tb.dut.u_spi_tpm.HwRegCondition_A 0038198895419336000
tb.dut.u_spi_tpm.HwRegIdxKnown_A 003819907758479708700
tb.dut.u_spi_tpm.LocalityLatchCondition_A 0038198895419336000
tb.dut.u_spi_tpm.RdFifoDepthPoT_A 001852185200
tb.dut.u_spi_tpm.RdFifoNumBytesPoT_A 001852185200
tb.dut.u_spi_tpm.RdPowerof2_A 001852185200
tb.dut.u_spi_tpm.SckFifoAddrLatchCondition_A 0038198895419336000
tb.dut.u_spi_tpm.TpmRegSizeMatch_A 001852185200
tb.dut.u_spi_tpm.WrDepthSpec_A 001852185200
tb.dut.u_spi_tpm.WrFifoAvailable_A 00381988954122517500
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A 003819889548479708700
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A 001852185200
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A 00381988954183362100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A 00381988954183362100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A 00381988954183362100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A 00381988954183362100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A 00381988954183362100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A 00381988954183362100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A 00381988954183362100
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.DataKnown_A 0038198895455554800
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.DepthKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.RvalidKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.WreadyKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0038198895455554800
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayRptr_A 001203785710120361561100
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayWptr_A 0038198895438198737100
tb.dut.u_spi_tpm.u_cmdaddr_buffer.ParamCheckDepth_A 001852185200
tb.dut.u_spi_tpm.u_hw_reg_slice.ValidWidth_A 001852185200
tb.dut.u_spi_tpm.u_sram_fifo.DataKnown_A 003819889541728706600
tb.dut.u_spi_tpm.u_sram_fifo.DepthKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_sram_fifo.RvalidKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_sram_fifo.WreadyKnown_A 003819889548479708700
tb.dut.u_spi_tpm.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003819889541728706600
tb.dut.u_spi_tpm.u_tpm_wr_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A 001852185200
tb.dut.u_spi_tpm.u_tpm_wr_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A 001852185200
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.SyncReqAckAckNeedsReq 0038198895424453800
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.SyncReqAckHoldReq 00120378571023499800
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataReg 001852185200
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckAckNeedsReq 00381988954118300
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckHoldReq 001203785710118300
tb.dut.u_spid_status.BusyBitZero_A 001852185200
tb.dut.u_spid_status.u_sw_status_update_sync.GrayRptr_A 0038198895438198737100
tb.dut.u_spid_status.u_sw_status_update_sync.GrayWptr_A 001203785710120361561100
tb.dut.u_spid_status.u_sw_status_update_sync.ParamCheckDepth_A 001852185200
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A 001203785710120361784400
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A 001852185200
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A 001203785710536930300
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A 001203785710536930300
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A 001203785710120361784400
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A 001203785710120361784400
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A 001203785710536930300
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A 001203785710536930300
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A 001203785710536930300
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A 001203785710536930300
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A 0012037857101101852
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A 001203785710120361784400
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A 001203785710536930300
tb.dut.u_sys_sram_arbiter.u_req_fifo.DataKnown_A 00120378571043153100
tb.dut.u_sys_sram_arbiter.u_req_fifo.DepthKnown_A 001203785710120361784400
tb.dut.u_sys_sram_arbiter.u_req_fifo.RvalidKnown_A 001203785710120361784400
tb.dut.u_sys_sram_arbiter.u_req_fifo.WreadyKnown_A 001203785710120361784400
tb.dut.u_sys_sram_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00120378571043153100
tb.dut.u_tlul2sram_egress.AddrOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.DataIntgOptions_A 001852185200
tb.dut.u_tlul2sram_egress.ReqOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.SramDwHasByteGranularity_A 001852185200
tb.dut.u_tlul2sram_egress.SramDwIsMultipleOfTlulWidth_A 001852185200
tb.dut.u_tlul2sram_egress.TlOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.TlOutPayloadKnown_A 001203785710726634800
tb.dut.u_tlul2sram_egress.TlOutPayloadKnown_AKnownEnable 001203785710120361784400
tb.dut.u_tlul2sram_egress.WdataOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.WeOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.WmaskOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.adapterNoReadOrWrite 001852185200
tb.dut.u_tlul2sram_egress.u_err.dataWidthOnly32_A 001852185200
tb.dut.u_tlul2sram_egress.u_reqfifo.DataKnown_A 001203785710726634800
tb.dut.u_tlul2sram_egress.u_reqfifo.DepthKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.u_reqfifo.RvalidKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.u_reqfifo.WreadyKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 001203785710726634800
tb.dut.u_tlul2sram_egress.u_rsp_gen.DataWidthCheck_A 001852185200
tb.dut.u_tlul2sram_egress.u_rsp_gen.PayLoadWidthCheck 001852185200
tb.dut.u_tlul2sram_egress.u_rspfifo.DepthKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.u_rspfifo.RvalidKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.u_rspfifo.WreadyKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DepthKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.u_sramreqfifo.RvalidKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_egress.u_sramreqfifo.WreadyKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.AddrOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.DataIntgOptions_A 001852185200
tb.dut.u_tlul2sram_ingress.ReqOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.SramDwHasByteGranularity_A 001852185200
tb.dut.u_tlul2sram_ingress.SramDwIsMultipleOfTlulWidth_A 001852185200
tb.dut.u_tlul2sram_ingress.TlOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.TlOutPayloadKnown_A 001203785710103224200
tb.dut.u_tlul2sram_ingress.TlOutPayloadKnown_AKnownEnable 001203785710120361784400
tb.dut.u_tlul2sram_ingress.WdataOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.WeOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.WmaskOutKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.adapterNoReadOrWrite 001852185200
tb.dut.u_tlul2sram_ingress.rvalidHighReqFifoEmpty 00120378571042329900
tb.dut.u_tlul2sram_ingress.rvalidHighWhenRspFifoFull 00120378571042329900
tb.dut.u_tlul2sram_ingress.u_err.dataWidthOnly32_A 001852185200
tb.dut.u_tlul2sram_ingress.u_reqfifo.DataKnown_A 001203785710103224200
tb.dut.u_tlul2sram_ingress.u_reqfifo.DepthKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_reqfifo.RvalidKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_reqfifo.WreadyKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 001203785710103224200
tb.dut.u_tlul2sram_ingress.u_rsp_gen.DataWidthCheck_A 001852185200
tb.dut.u_tlul2sram_ingress.u_rsp_gen.PayLoadWidthCheck 001852185200
tb.dut.u_tlul2sram_ingress.u_rspfifo.DataKnown_A 001203785710103224200
tb.dut.u_tlul2sram_ingress.u_rspfifo.DepthKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_rspfifo.RvalidKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_rspfifo.WreadyKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 001203785710103224200
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DataKnown_A 00120378571042329900
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DepthKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.RvalidKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.WreadyKnown_A 001203785710120361784400
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00120378571042329900
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0 0019516619437600
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 0019516519437500
tb.dut.u_upload.AddrFifoNeverFull_M 00381988954350800
tb.dut.u_upload.CmdFifoNeverFull_M 00381988954472400
tb.dut.u_upload.CmdFifoPush_A 00381988954472400
tb.dut.u_upload.FifosOnlyOneValid_A 0038198895429357861100
tb.dut.u_upload.PayloadNeverFull_M 00381988954138405100
tb.dut.u_upload.u_addrfifo.MinDepth_A 001852185200
tb.dut.u_upload.u_addrfifo.NoRAckInEmpty_A 001203785710350800
tb.dut.u_upload.u_addrfifo.NoWAckInFull_A 00381988954350800
tb.dut.u_upload.u_addrfifo.ParamCheckDepth_A 001852185200
tb.dut.u_upload.u_addrfifo.RSramRvalidOneCycle_M 001203785710350800
tb.dut.u_upload.u_addrfifo.RptrGrayOneBitAtATime_A 001203785710350800
tb.dut.u_upload.u_addrfifo.RptrIncDataValid_A 001203785710350800
tb.dut.u_upload.u_addrfifo.RptrIncrease_A 001203785710350800
tb.dut.u_upload.u_addrfifo.SramRvalid_A 001203785710350800
tb.dut.u_upload.u_addrfifo.WSramRvalid_A 0038198895438198895400
tb.dut.u_upload.u_addrfifo.WidthMatch_A 001852185200
tb.dut.u_upload.u_addrfifo.WptrGrayOneBitAtATime_A 00381988954350800
tb.dut.u_upload.u_addrfifo.WptrIncrease_A 00381988954350800
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A 0038198895429357861100
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A 001852185200
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A 00381988954139228300
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A 00381988954139228300
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A 0038198895429357861100
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A 0038198895429357861100
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A 00381988954139228300
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A 00381988954139228300
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A 00381988954139228300
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A 00381988954139228300
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A 0038198895429357861100
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A 00381988954139228300
tb.dut.u_upload.u_arbiter.u_req_fifo.DepthKnown_A 0038198895429357861100
tb.dut.u_upload.u_arbiter.u_req_fifo.RvalidKnown_A 0038198895429357861100
tb.dut.u_upload.u_arbiter.u_req_fifo.WreadyKnown_A 0038198895429357861100
tb.dut.u_upload.u_cmdfifo.MinDepth_A 001852185200
tb.dut.u_upload.u_cmdfifo.NoRAckInEmpty_A 001203785710472400
tb.dut.u_upload.u_cmdfifo.NoWAckInFull_A 00381988954472400
tb.dut.u_upload.u_cmdfifo.ParamCheckDepth_A 001852185200
tb.dut.u_upload.u_cmdfifo.RSramRvalidOneCycle_M 001203785710472400
tb.dut.u_upload.u_cmdfifo.RptrGrayOneBitAtATime_A 001203785710472400
tb.dut.u_upload.u_cmdfifo.RptrIncDataValid_A 001203785710472400
tb.dut.u_upload.u_cmdfifo.RptrIncrease_A 001203785710472400
tb.dut.u_upload.u_cmdfifo.SramRvalid_A 001203785710472400
tb.dut.u_upload.u_cmdfifo.WSramRvalid_A 0038198895438198895400
tb.dut.u_upload.u_cmdfifo.WidthMatch_A 001852185200
tb.dut.u_upload.u_cmdfifo.WptrGrayOneBitAtATime_A 00381988954472400
tb.dut.u_upload.u_cmdfifo.WptrIncrease_A 00381988954472400
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A 001852185200
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A 001852185200
tb.dut.u_upload.u_payloadptr_clr_psync.DstPulseCheck_A 001203785710472400
tb.dut.u_upload.u_payloadptr_clr_psync.SrcPulseCheck_M 00381988954472400

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A 0012037857101101852

Assertions Without Attempts:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 000000


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0012084999892289382289380
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 001208499989503450340
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 001208499989516251620
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 001208499989337933790
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0012084999894254250
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 001208499989264826480
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 001208499989234223420
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00120849998925510255100
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001208499989251456225145620
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 00120849998912200899122008992162

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0012084999892289382289380
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 001208499989503450340
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 001208499989516251620
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 001208499989337933790
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0012084999894254250
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 001208499989264826480
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 001208499989234223420
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00120849998925510255100
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001208499989251456225145620
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 00120849998912200899122008992162

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