| | | | | | | |
prim_rst_sync |
50.00 |
50.00 |
|
|
|
|
|
tlul_err_resp |
57.80 |
76.92 |
40.91 |
|
|
55.56 |
|
prim_sync_reqack_data |
75.00 |
100.00 |
|
|
|
|
50.00 |
spi_p2s |
84.73 |
100.00 |
71.43 |
|
|
67.50 |
100.00 |
prim_generic_clock_mux2 |
85.19 |
100.00 |
55.56 |
|
|
|
100.00 |
spi_s2p |
86.75 |
100.00 |
78.57 |
|
|
68.42 |
100.00 |
tlul_adapter_sram |
88.56 |
94.03 |
68.53 |
|
|
91.67 |
100.00 |
tlul_adapter_sram |
95.83 |
|
|
|
|
91.67 |
100.00 |
tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 ) |
78.05 |
94.03 |
62.07 |
|
|
|
|
tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 ) |
84.51 |
94.03 |
75.00 |
|
|
|
|
spi_passthrough |
89.32 |
92.31 |
88.66 |
|
75.00 |
90.62 |
100.00 |
spid_readbuffer |
89.97 |
87.76 |
97.14 |
|
|
75.00 |
100.00 |
prim_arbiter_ppc |
91.61 |
100.00 |
85.19 |
|
|
100.00 |
81.25 |
prim_arbiter_ppc |
90.62 |
|
|
|
|
100.00 |
81.25 |
prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 ) |
88.89 |
100.00 |
77.78 |
|
|
|
|
prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 ) |
88.89 |
|
88.89 |
|
|
|
|
prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 ) |
88.89 |
|
88.89 |
|
|
|
|
prim_sram_arbiter |
91.67 |
100.00 |
83.33 |
|
|
|
|
prim_sram_arbiter |
83.33 |
|
83.33 |
|
|
|
|
prim_sram_arbiter ( parameter N=2,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_sram_arbiter ( parameter N=3,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_sram_arbiter ( parameter N=5,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 ) |
100.00 |
100.00 |
|
|
|
|
|
spid_dpram |
91.67 |
100.00 |
75.00 |
|
|
100.00 |
|
prim_sync_reqack |
91.67 |
100.00 |
66.67 |
|
|
100.00 |
100.00 |
spi_device |
91.69 |
94.25 |
84.31 |
96.94 |
|
87.50 |
95.45 |
prim_fifo_sync |
91.73 |
100.00 |
69.69 |
|
|
97.22 |
100.00 |
prim_fifo_sync |
100.00 |
|
|
|
|
|
100.00 |
prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
73.08 |
|
73.08 |
|
|
|
|
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 ) |
65.38 |
|
65.38 |
|
|
|
|
prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 ) |
42.31 |
|
42.31 |
|
|
|
|
prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 ) |
100.00 |
|
|
|
|
100.00 |
|
prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
89.06 |
100.00 |
78.12 |
|
|
|
|
prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
100.00 |
|
|
|
|
100.00 |
|
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
89.38 |
100.00 |
76.47 |
|
|
91.67 |
|
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
69.23 |
|
69.23 |
|
|
|
|
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 ) |
65.38 |
|
65.38 |
|
|
|
|
prim_fifo_sync ( parameter Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
93.75 |
100.00 |
87.50 |
|
|
|
|
spi_readcmd |
92.19 |
96.32 |
100.00 |
|
80.00 |
84.62 |
100.00 |
prim_fifo_async |
92.53 |
100.00 |
78.46 |
|
|
91.67 |
100.00 |
prim_fifo_async |
97.22 |
100.00 |
|
|
|
91.67 |
100.00 |
prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 ) |
80.00 |
|
80.00 |
|
|
|
|
prim_fifo_async ( parameter Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 ) |
76.92 |
|
76.92 |
|
|
|
|
prim_fifo_async_sram_adapter |
93.75 |
100.00 |
75.00 |
|
|
100.00 |
100.00 |
prim_fifo_async_sram_adapter |
100.00 |
|
|
|
|
100.00 |
100.00 |
prim_fifo_async_sram_adapter ( parameter Width=16,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=960,DepthW=5,PtrVW=4,PtrW=5 ) |
87.50 |
100.00 |
75.00 |
|
|
|
|
prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=976,DepthW=5,PtrVW=4,PtrW=5 ) |
87.50 |
100.00 |
75.00 |
|
|
|
|
prim_subreg_arb |
94.50 |
87.50 |
96.00 |
|
|
100.00 |
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=5,SwAccess=1,Mubi=0 + DW=9,SwAccess=1,Mubi=0 + DW=8,SwAccess=1,Mubi=0 + DW=3,SwAccess=1,Mubi=0 ) |
50.00 |
50.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 ) |
80.00 |
100.00 |
60.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
spid_fifo2sram_adapter |
94.87 |
100.00 |
79.49 |
|
|
100.00 |
100.00 |
spid_fifo2sram_adapter |
100.00 |
|
|
|
|
|
100.00 |
spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 ) |
89.74 |
100.00 |
69.23 |
|
|
100.00 |
|
spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 ) |
94.87 |
100.00 |
84.62 |
|
|
100.00 |
|
spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 ) |
94.87 |
100.00 |
84.62 |
|
|
100.00 |
|
spi_tpm |
95.66 |
99.29 |
91.20 |
|
91.67 |
96.13 |
100.00 |
tlul_rsp_intg_gen |
95.83 |
91.67 |
|
|
|
|
100.00 |
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
83.33 |
83.33 |
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
spid_upload |
96.37 |
100.00 |
86.11 |
|
100.00 |
95.74 |
100.00 |
prim_subreg |
96.67 |
100.00 |
90.00 |
|
|
100.00 |
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL=7,Mubi=0 + DW=3,SwAccess=1,RESVAL=6,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=5,SwAccess=1,RESVAL=0,Mubi=0 ) |
50.00 |
|
50.00 |
|
|
|
|
prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=1,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=9,SwAccess=1,RESVAL=0,Mubi=0 ) |
50.00 |
|
50.00 |
|
|
|
|
spi_cmdparse |
96.74 |
100.00 |
87.80 |
|
100.00 |
95.92 |
100.00 |
tlul_socket_1n |
97.25 |
100.00 |
93.33 |
|
|
95.65 |
100.00 |
spid_readsram |
97.77 |
98.25 |
100.00 |
|
100.00 |
90.62 |
100.00 |
tlul_adapter_reg |
98.91 |
100.00 |
95.65 |
|
|
100.00 |
100.00 |
spid_status |
99.31 |
100.00 |
100.00 |
|
|
97.22 |
100.00 |
spid_jedec |
99.38 |
100.00 |
100.00 |
|
100.00 |
96.88 |
100.00 |
spi_device_reg_top |
99.74 |
100.00 |
98.94 |
|
|
100.00 |
100.00 |
spid_csb_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_fifo_sync_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_fifo_sync_cnt |
100.00 |
|
|
|
|
100.00 |
|
prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 + Depth=2,Width=2,Secure=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_fifo_sync_cnt ( parameter Depth=4,Width=3,Secure=0 ) |
100.00 |
100.00 |
|
|
|
|
|
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
prim_generic_ram_1r1w |
100.00 |
100.00 |
|
|
|
100.00 |
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
tlul_fifo_sync |
100.00 |
|
100.00 |
|
|
100.00 |
|
prim_generic_clock_gating |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_edge_detector |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_edge_detector |
100.00 |
|
100.00 |
|
|
100.00 |
|
prim_edge_detector ( parameter Width=1,ResetValue=0,EnSync=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_edge_detector ( parameter Width=2,ResetValue=0,EnSync=0 + Width=1,ResetValue=0,EnSync=0 ) |
100.00 |
100.00 |
|
|
|
|
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
prim_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_intr_hw |
100.00 |
|
|
|
|
|
100.00 |
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" ) |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" ) |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_pulse_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_slicer |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
prim_generic_flop_en |
100.00 |
100.00 |
|
|
|
100.00 |
|
spi_device_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
prim_ram_1r1w_async_adv |
100.00 |
100.00 |
|
|
|
100.00 |
|
tlul_sram_byte |
100.00 |
100.00 |
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
spid_addr_4b |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_mubi4_sync |
100.00 |
|
|
|
|
|
100.00 |
prim_generic_clock_buf |
100.00 |
100.00 |
|
|
|
|
|
prim_clock_gating |
|
|
|
|
|
|
|
prim_clock_buf |
|
|
|
|
|
|
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tlul_data_integ_enc |
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prim_reg_we_check |
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prim_flop_en |
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prim_clock_mux2 |
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prim_buf |
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prim_ram_1r1w |
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prim_generic_clock_inv |
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prim_clock_inv |
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prim_flop |
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prim_flop_2sync |
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tb |
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