Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts


Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 12 0 0.00
Crosses 16 16 0 0.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_bit_order 2 2 0 0.00 100 1 1 2
cp_cpha 2 2 0 0.00 100 1 1 2
cp_cpol 2 2 0 0.00 100 1 1 2
cp_rx_order 2 2 0 0.00 100 1 1 2
rx_order 2 2 0 0.00 100 1 1 2
tx_order 2 2 0 0.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 16 0 0.00 100 1 1 0


Summary for Variable cp_bit_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_bit_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_cpha

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_cpha

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_cpol

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_cpol

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_rx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_rx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable rx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for rx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable tx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for tx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 16 0 0.00 16


Automatically Generated Cross Bins for cr_all

Uncovered bins
tx_orderrx_ordercp_cpolcp_cphaCOUNTAT LEASTNUMBERSTATUS
* * * * -- -- 16

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%