Summary for Variable cp_bit_order
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_bit_order
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_cpha
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_cpha
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_cpol
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_cpol
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_rx_order
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_rx_order
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable rx_order
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for rx_order
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable tx_order
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for tx_order
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Cross cr_all
Samples crossed: tx_order rx_order cp_cpol cp_cpha
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
16 |
0 |
0.00 |
16 |
Automatically Generated Cross Bins for cr_all
Uncovered bins
tx_order | rx_order | cp_cpol | cp_cpha | COUNT | AT LEAST | NUMBER | STATUS |
* |
* |
* |
* |
-- |
-- |
16 |
|