Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	79154	1			T5	328		T7	443		T8	10
auto[SpiFlashAddrCfg]	18192	1			T2	4		T5	66		T7	63
auto[SpiFlashAddr3b]	21842	1			T5	60		T7	87		T8	4
auto[SpiFlashAddr4b]	18414	1			T5	43		T7	59		T8	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79482

1

T2

4

T5

242

T7

305

auto[1]

58120

1

T5

255

T7

347

T9

77

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72845

1

T2

4

T5

322

T7

326

auto[1]

64757

1

T5

175

T7

326

T8

16

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	89720	1			T5	359		T7	499		T8	10
values[1]	2598	1			T5	5		T7	11		T9	5
values[2]	3555	1			T5	4		T7	15		T9	6
values[3]	3433	1			T5	7		T7	14		T8	4
values[4]	3452	1			T5	10		T7	15		T8	2
values[5]	3646	1			T5	11		T7	6		T9	2
values[6]	3585	1			T5	5		T7	7		T9	1
values[7]	3584	1			T5	6		T7	9		T9	8
values[8]	24029	1			T2	4		T5	90		T7	76

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75323

1

T5

497

T8

24

T11

720

auto[1]

62279

1

T2

4

T7

652

T9

156

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

132708

1

T2

4

T5

477

T7

624

write

4894

1

T5

20

T7

28

T8

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

47038

1

T2

4

T5

133

T7

166

valids[0x1]

90564

1

T5

364

T7

486

T8

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	3719	1			T5	6		T7	8		T9	8
internal_process_ops[0x5a]	3668	1			T5	8		T7	12		T9	4
internal_process_ops[0x05]	46649	1			T5	245		T7	331		T9	20
internal_process_ops[0x35]	3702	1			T5	6		T7	10		T9	9
internal_process_ops[0x15]	3770	1			T5	15		T7	12		T8	2
internal_process_ops[0x03]	2792	1			T5	13		T7	3		T9	2
internal_process_ops[0x0b]	2832	1			T5	5		T7	6		T9	2
internal_process_ops[0x3b]	2639	1			T5	10		T7	3		T11	10
internal_process_ops[0x6b]	2717	1			T2	4		T5	5		T7	9
internal_process_ops[0xbb]	2817	1			T5	8		T7	7		T11	11
internal_process_ops[0xeb]	2845	1			T5	13		T7	7		T8	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135189

1

T2

4

T5

491

T7

633

auto[1]

2413

1

T5

6

T7

19

T9

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132878

1

T2

4

T5

475

T7

624

auto[1]

4724

1

T5

22

T7

28

T9

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

25307

1

T5

164

T8

10

T11

271

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

14957

1

T5

161

T11

190

T13

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

5406

1

T5

36

T8

8

T11

51

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

4706

1

T5

27

T11

35

T13

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

6478

1

T5

20

T8

4

T11

38

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

5520

1

T5

36

T11

52

T13

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

5696

1

T5

14

T11

30

T12

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

4606

1

T5

19

T11

29

T14

19

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

205

1

T11

2

T14

2

T29

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

143

1

T14

1

T23

1

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

151

1

T5

2

T27

3

T29

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

186

1

T5

1

T11

5

T28

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

195

1

T11

2

T23

1

T28

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

145

1

T5

1

T23

2

T28

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

151

1

T11

2

T29

3

T155

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

179

1

T5

2

T11

5

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

231

1

T5

1

T11

1

T46

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

138

1

T11

1

T14

2

T29

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

165

1

T5

1

T14

2

T29

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

146

1

T5

2

T11

2

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

155

1

T5

6

T8

2

T11

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

161

1

T14

3

T23

1

T27

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

136

1

T5

4

T23

1

T27

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

160

1

T11

3

T27

1

T28

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

22218

1

T7

201

T9

49

T15

335

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

15414

1

T7

236

T9

42

T15

445

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

3707

1

T2

4

T7

30

T9

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

3182

1

T7

25

T9

10

T15

35

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

4420

1

T7

35

T9

15

T15

37

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

4136

1

T7

38

T9

8

T15

49

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

3710

1

T7

23

T9

8

T15

24

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

3245

1

T7

36

T9

12

T15

17

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

168

1

T7

2

T15

1

T16

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

152

1

T7

2

T16

1

T151

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

124

1

T7

1

T15

2

T151

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

129

1

T7

1

T15

1

T16

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

149

1

T7

3

T15

3

T16

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

128

1

T7

2

T15

1

T16

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

126

1

T7

1

T15

3

T16

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

118

1

T7

2

T9

1

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

147

1

T7

2

T136

2

T17

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

159

1

T7

5

T151

2

T53

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

138

1

T9

2

T15

2

T16

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

164

1

T7

7

T15

1

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

103

1

T15

3

T151

4

T48

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

161

1

T9

2

T151

1

T48

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

137

1

T9

1

T16

1

T48

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

144

1

T9

1

T15

1

T16

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	10215	1			T5	47		T8	4		T11	55
auto[0]	values[0]	valids[0x1]	36748	1			T5	312		T8	6		T11	460
auto[0]	values[1]	valids[0x1]	1422	1			T5	5		T11	10		T13	2
auto[0]	values[2]	valids[0x0]	1375	1			T5	4		T11	13		T13	2
auto[0]	values[2]	valids[0x1]	742	1			T11	8		T13	2		T14	3
auto[0]	values[3]	valids[0x0]	1283	1			T5	6		T11	10		T14	9
auto[0]	values[3]	valids[0x1]	756	1			T5	1		T8	4		T11	3
auto[0]	values[4]	valids[0x0]	1294	1			T5	5		T8	2		T11	13
auto[0]	values[4]	valids[0x1]	815	1			T5	5		T11	8		T14	7
auto[0]	values[5]	valids[0x0]	1343	1			T5	7		T11	12		T14	5
auto[0]	values[5]	valids[0x1]	779	1			T5	4		T11	7		T14	2
auto[0]	values[6]	valids[0x0]	1330	1			T5	4		T11	8		T14	5
auto[0]	values[6]	valids[0x1]	754	1			T5	1		T11	7		T12	2
auto[0]	values[7]	valids[0x0]	1446	1			T5	4		T11	9		T14	9
auto[0]	values[7]	valids[0x1]	745	1			T5	2		T11	2		T28	1
auto[0]	values[8]	valids[0x0]	8868	1			T5	56		T8	8		T11	54
auto[0]	values[8]	valids[0x1]	5408	1			T5	34		T11	41		T14	20
auto[1]	values[0]	valids[0x0]	8894	1			T7	77		T9	37		T15	104
auto[1]	values[0]	valids[0x1]	33863	1			T7	422		T9	62		T15	727
auto[1]	values[1]	valids[0x1]	1176	1			T7	11		T9	5		T15	10
auto[1]	values[2]	valids[0x0]	853	1			T7	7		T9	4		T15	7
auto[1]	values[2]	valids[0x1]	585	1			T7	8		T9	2		T15	1
auto[1]	values[3]	valids[0x0]	872	1			T7	6		T9	3		T15	11
auto[1]	values[3]	valids[0x1]	522	1			T7	8		T9	1		T15	2
auto[1]	values[4]	valids[0x0]	812	1			T7	12		T9	4		T15	8
auto[1]	values[4]	valids[0x1]	531	1			T7	3		T15	4		T16	6
auto[1]	values[5]	valids[0x0]	924	1			T7	3		T15	13		T16	6
auto[1]	values[5]	valids[0x1]	600	1			T7	3		T9	2		T15	4
auto[1]	values[6]	valids[0x0]	903	1			T7	3		T15	6		T16	5
auto[1]	values[6]	valids[0x1]	598	1			T7	4		T9	1		T15	6
auto[1]	values[7]	valids[0x0]	910	1			T7	4		T9	3		T15	17
auto[1]	values[7]	valids[0x1]	483	1			T7	5		T9	5		T15	1
auto[1]	values[8]	valids[0x0]	5716	1			T2	4		T7	54		T9	16
auto[1]	values[8]	valids[0x1]	4037	1			T7	22		T9	11		T15	25