Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38395

1

T2

12

T5

114

T7

142

auto[1]

47300

1

T5

253

T7

335

T9

23

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32230

1

T2

12

T5

101

T7

124

auto[1]

53465

1

T5

266

T7

353

T9

35

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	13927	1			T2	5		T5	57		T7	103
auto[524288:1048575]	11160	1			T5	57		T7	9		T9	8
auto[1048576:1572863]	10484	1			T5	134		T7	50		T9	18
auto[1572864:2097151]	10078	1			T2	1		T5	6		T7	57
auto[2097152:2621439]	9837	1			T2	6		T5	15		T7	35
auto[2621440:3145727]	10656	1			T5	16		T7	85		T9	8
auto[3145728:3670015]	9649	1			T5	45		T7	21		T9	23
auto[3670016:4194303]	9904	1			T5	37		T7	117		T9	13

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83887

1

T2

12

T5

348

T7

462

auto[1]

1808

1

T5

19

T7

15

T11

12

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68799

1

T2

12

T5

306

T7

369

auto[1]

16896

1

T5

61

T7

108

T9

25

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	3891	1			T2	5		T5	9		T7	7
auto[0]	auto[0]	auto[0:524287]	auto[1]	1565	1			T5	2		T7	5		T11	3
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	2748	1			T5	8		T7	3		T9	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	1054	1			T5	3		T7	2		T9	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	2586	1			T5	17		T7	9		T9	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	1029	1			T5	13		T7	4		T9	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	2638	1			T2	1		T5	4		T7	14
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	933	1			T5	2		T7	6		T9	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	2596	1			T2	6		T5	7		T7	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	1000	1			T5	1		T7	5		T9	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	2755	1			T5	5		T7	14		T9	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	1043	1			T5	6		T7	8		T9	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	2536	1			T5	6		T7	8		T9	9
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	982	1			T5	2		T7	6		T9	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	2628	1			T5	9		T7	21		T9	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	1002	1			T5	2		T7	7		T9	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	749	1			T5	9		T7	5		T11	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	342	1			T5	2		T7	1		T16	4
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	618	1			T7	1		T9	2		T11	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	264	1			T11	1		T15	4		T151	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	579	1			T7	2		T9	6		T15	15
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	278	1			T7	1		T9	1		T15	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	603	1			T7	2		T11	2		T14	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	274	1			T14	1		T15	1		T23	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	643	1			T5	1		T7	1		T11	9
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	292	1			T7	1		T11	2		T15	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	704	1			T5	2		T7	5		T11	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	291	1			T11	1		T15	3		T16	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	612	1			T5	1		T9	1		T11	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	260	1			T5	1		T9	4		T11	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	614	1			T5	1		T7	1		T9	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	286	1			T5	1		T9	2		T23	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	587	1			T7	1		T11	1		T14	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	5324	1			T7	42		T11	10		T14	4
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	493	1			T5	3		T7	1		T11	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4843	1			T5	43		T7	2		T11	36
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	472	1			T5	7		T7	4		T9	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	4482	1			T5	97		T7	17		T9	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	452	1			T7	5		T9	2		T11	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4065	1			T7	30		T9	3		T11	30
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	453	1			T5	1		T7	1		T11	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3804	1			T5	5		T7	24		T11	54
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	457	1			T5	1		T7	3		T9	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4076	1			T5	2		T7	25		T9	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	426	1			T5	3		T7	1		T9	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3691	1			T5	32		T7	6		T9	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	423	1			T5	3		T7	7		T11	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3765	1			T5	13		T7	78		T11	61
auto[1]	auto[1]	auto[0:524287]	auto[0]	163	1			T5	3		T7	2		T11	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1306	1			T5	32		T7	40		T11	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	105	1			T11	1		T15	3		T29	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1035	1			T11	38		T15	50		T29	35
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	97	1			T7	1		T9	1		T15	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	961	1			T7	12		T9	1		T15	135
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	122	1			T11	1		T14	1		T29	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	991	1			T11	7		T14	5		T29	28
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	124	1			T11	4		T151	2		T48	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	925	1			T11	12		T151	34		T48	15
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	123	1			T7	1		T15	1		T23	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1207	1			T7	29		T15	9		T23	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	121	1			T11	1		T16	1		T25	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1021	1			T11	40		T16	3		T25	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	112	1			T5	1		T7	1		T14	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1074	1			T5	7		T7	2		T14	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	30258	1			T2	12		T5	92		T7	117
auto[0]	auto[0]	auto[1]	728	1			T5	4		T7	5		T11	9
auto[0]	auto[1]	auto[0]	7231	1			T5	17		T7	19		T9	23
auto[0]	auto[1]	auto[1]	178	1			T5	1		T7	1		T11	1
auto[1]	auto[0]	auto[0]	37084	1			T5	199		T7	240		T9	21
auto[1]	auto[0]	auto[1]	729	1			T5	11		T7	7		T11	2
auto[1]	auto[1]	auto[0]	9314	1			T5	40		T7	86		T9	2
auto[1]	auto[1]	auto[1]	173	1			T5	3		T7	2		T15	2