Group : spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 8 0 8 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_write 2 0 2 100.00 100 1 1 0
cp_payload_size 7 0 7 100.00 100 1 1 0


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 8 0 8 100.00 100 1 1 0


Summary for Variable cp_is_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_is_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read 2318 1 T5 8 T7 14 T9 3
write 2406 1 T5 14 T7 14 T9 4



Summary for Variable cp_payload_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for cp_payload_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
excess_fifo 873 1 T5 7 T7 2 T11 6
frequent_use_values[0] 2392 1 T5 8 T7 14 T9 3
frequent_use_values[1] 91 1 T5 1 T7 1 T15 1
frequent_use_values[2] 73 1 T5 1 T9 1 T15 1
frequent_use_values[3] 96 1 T5 1 T203 2 T119 3
frequent_use_values[4] 105 1 T7 2 T9 1 T11 3
frequent_use_values[256] 555 1 T5 3 T7 7 T11 5



Summary for Cross cr_all

Samples crossed: cp_is_write cp_payload_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_all

Bins
cp_is_writecp_payload_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read frequent_use_values[0] 2318 1 T5 8 T7 14 T9 3
write excess_fifo 873 1 T5 7 T7 2 T11 6
write frequent_use_values[0] 74 1 T11 1 T27 1 T151 2
write frequent_use_values[1] 91 1 T5 1 T7 1 T15 1
write frequent_use_values[2] 73 1 T5 1 T9 1 T15 1
write frequent_use_values[3] 96 1 T5 1 T203 2 T119 3
write frequent_use_values[4] 105 1 T7 2 T9 1 T11 3
write frequent_use_values[256] 555 1 T5 3 T7 7 T11 5


User Defined Cross Bins for cr_all

Excluded/Illegal bins
NAMECOUNTSTATUS
read_w_nonzero_payload 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%