Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44260

1

T5

242

T8

24

T11

397

auto[1]

31063

1

T5

255

T11

323

T13

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	9652	1			T5	54		T11	40		T14	29
values[1]	10378	1			T5	42		T8	24		T11	71
values[2]	8717	1			T11	138		T12	18		T14	53
values[3]	9149	1			T5	98		T11	114		T14	20
values[4]	9730	1			T5	99		T11	155		T13	22
values[5]	9438	1			T5	103		T11	113		T14	20
values[6]	8991	1			T11	38		T26	4		T28	20
values[7]	9268	1			T5	101		T11	51		T14	62

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	9337	1			T5	94		T11	123		T14	69
values[1]	9983	1			T5	41		T12	18		T45	12
values[2]	9051	1			T8	24		T11	41		T13	22
values[3]	9024	1			T11	66		T14	27		T23	50
values[4]	10304	1			T5	62		T11	189		T26	4
values[5]	9724	1			T5	153		T11	60		T23	28
values[6]	8090	1			T5	42		T11	241		T14	20
values[7]	9810	1			T5	105		T14	33		T23	28

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	687	1			T5	20		T14	21		T29	12
auto[0]	values[0]	values[1]	829	1			T27	84		T194	24		T179	41
auto[0]	values[0]	values[2]	755	1			T29	17		T119	22		T153	11
auto[0]	values[0]	values[3]	711	1			T153	27		T205	20		T168	21
auto[0]	values[0]	values[4]	993	1			T11	24		T28	9		T155	14
auto[0]	values[0]	values[5]	580	1			T214	20		T215	7		T182	8
auto[0]	values[0]	values[6]	467	1			T28	14		T32	24		T206	14
auto[0]	values[0]	values[7]	798	1			T5	20		T46	34		T120	18
auto[0]	values[1]	values[0]	645	1			T14	18		T28	9		T29	16
auto[0]	values[1]	values[1]	647	1			T28	24		T48	12		T120	9
auto[0]	values[1]	values[2]	1052	1			T8	24		T11	7		T32	12
auto[0]	values[1]	values[3]	804	1			T11	11		T23	41		T48	10
auto[0]	values[1]	values[4]	876	1			T23	56		T28	12		T178	18
auto[0]	values[1]	values[5]	739	1			T152	12		T191	93		T168	12
auto[0]	values[1]	values[6]	792	1			T5	18		T23	12		T48	14
auto[0]	values[1]	values[7]	925	1			T30	11		T216	42		T120	15
auto[0]	values[2]	values[0]	531	1			T217	24		T213	4		T152	16
auto[0]	values[2]	values[1]	649	1			T12	18		T45	12		T28	24
auto[0]	values[2]	values[2]	464	1			T218	4		T153	20		T219	10
auto[0]	values[2]	values[3]	656	1			T155	8		T175	23		T172	24
auto[0]	values[2]	values[4]	727	1			T11	90		T220	26		T172	10
auto[0]	values[2]	values[5]	931	1			T11	8		T44	4		T30	17
auto[0]	values[2]	values[6]	369	1			T11	11		T14	12		T30	13
auto[0]	values[2]	values[7]	525	1			T14	11		T29	25		T155	13
auto[0]	values[3]	values[0]	682	1			T5	11		T11	29		T120	16
auto[0]	values[3]	values[1]	784	1			T155	10		T172	20		T221	14
auto[0]	values[3]	values[2]	610	1			T28	11		T168	13		T189	33
auto[0]	values[3]	values[3]	631	1			T11	13		T145	6		T222	10
auto[0]	values[3]	values[4]	532	1			T14	11		T30	12		T123	12
auto[0]	values[3]	values[5]	711	1			T11	33		T23	9		T30	9
auto[0]	values[3]	values[6]	638	1			T32	20		T18	11		T191	11
auto[0]	values[3]	values[7]	760	1			T5	62		T48	11		T29	21
auto[0]	values[4]	values[0]	839	1			T5	22		T11	37		T172	8
auto[0]	values[4]	values[1]	779	1			T148	6		T223	18		T120	9
auto[0]	values[4]	values[2]	762	1			T14	18		T32	19		T175	12
auto[0]	values[4]	values[3]	608	1			T29	5		T119	13		T177	16
auto[0]	values[4]	values[4]	952	1			T119	16		T120	13		T175	8
auto[0]	values[4]	values[5]	543	1			T5	42		T29	18		T18	15
auto[0]	values[4]	values[6]	625	1			T11	21		T29	11		T155	91
auto[0]	values[4]	values[7]	683	1			T23	23		T28	14		T155	11
auto[0]	values[5]	values[0]	640	1			T11	20		T147	6		T30	10
auto[0]	values[5]	values[1]	915	1			T5	28		T27	10		T224	34
auto[0]	values[5]	values[2]	686	1			T32	6		T189	11		T225	12
auto[0]	values[5]	values[3]	568	1			T27	11		T226	2		T123	26
auto[0]	values[5]	values[4]	727	1			T5	7		T14	16		T27	102
auto[0]	values[5]	values[5]	776	1			T28	9		T29	12		T179	8
auto[0]	values[5]	values[6]	518	1			T11	76		T227	6		T120	7
auto[0]	values[5]	values[7]	624	1			T29	9		T155	12		T119	22
auto[0]	values[6]	values[0]	579	1			T29	11		T195	10		T32	7
auto[0]	values[6]	values[1]	874	1			T28	14		T30	11		T179	12
auto[0]	values[6]	values[2]	545	1			T179	11		T153	19		T189	13
auto[0]	values[6]	values[3]	540	1			T228	12		T35	38		T174	12
auto[0]	values[6]	values[4]	639	1			T29	16		T32	11		T175	15
auto[0]	values[6]	values[5]	649	1			T29	25		T32	12		T119	32
auto[0]	values[6]	values[6]	757	1			T11	8		T229	16		T119	13
auto[0]	values[6]	values[7]	608	1			T35	7		T189	9		T215	15
auto[0]	values[7]	values[0]	877	1			T32	14		T168	11		T206	11
auto[0]	values[7]	values[1]	633	1			T155	9		T120	16		T230	14
auto[0]	values[7]	values[2]	510	1			T14	30		T29	13		T119	11
auto[0]	values[7]	values[3]	734	1			T14	10		T48	18		T183	22
auto[0]	values[7]	values[4]	652	1			T11	9		T119	23		T123	38
auto[0]	values[7]	values[5]	690	1			T5	12		T27	14		T30	12
auto[0]	values[7]	values[6]	591	1			T47	14		T29	19		T119	14
auto[0]	values[7]	values[7]	637	1			T29	13		T30	13		T153	5
auto[1]	values[0]	values[0]	407	1			T5	7		T14	8		T29	8
auto[1]	values[0]	values[1]	504	1			T27	6		T179	8		T168	17
auto[1]	values[0]	values[2]	356	1			T29	7		T119	7		T153	10
auto[1]	values[0]	values[3]	723	1			T153	13		T168	5		T189	18
auto[1]	values[0]	values[4]	594	1			T11	16		T28	12		T155	6
auto[1]	values[0]	values[5]	336	1			T215	13		T182	12		T231	10
auto[1]	values[0]	values[6]	343	1			T28	6		T32	18		T206	6
auto[1]	values[0]	values[7]	569	1			T5	7		T120	25		T177	9
auto[1]	values[1]	values[0]	454	1			T14	22		T28	17		T29	4
auto[1]	values[1]	values[1]	357	1			T28	6		T48	10		T120	12
auto[1]	values[1]	values[2]	507	1			T11	34		T32	17		T119	8
auto[1]	values[1]	values[3]	487	1			T11	19		T23	9		T48	10
auto[1]	values[1]	values[4]	480	1			T23	6		T28	11		T177	9
auto[1]	values[1]	values[5]	483	1			T152	8		T191	3		T168	8
auto[1]	values[1]	values[6]	411	1			T5	24		T23	13		T48	6
auto[1]	values[1]	values[7]	719	1			T30	9		T120	9		T177	42
auto[1]	values[2]	values[0]	508	1			T31	22		T152	21		T189	14
auto[1]	values[2]	values[1]	379	1			T28	7		T152	12		T191	7
auto[1]	values[2]	values[2]	488	1			T153	10		T189	32		T169	10
auto[1]	values[2]	values[3]	452	1			T155	22		T175	12		T172	27
auto[1]	values[2]	values[4]	540	1			T11	8		T172	13		T179	34
auto[1]	values[2]	values[5]	596	1			T11	12		T30	4		T120	9
auto[1]	values[2]	values[6]	346	1			T11	9		T14	8		T30	7
auto[1]	values[2]	values[7]	556	1			T14	22		T29	20		T155	70
auto[1]	values[3]	values[0]	473	1			T5	9		T11	9		T120	4
auto[1]	values[3]	values[1]	370	1			T155	59		T172	4		T232	6
auto[1]	values[3]	values[2]	558	1			T28	9		T168	8		T189	8
auto[1]	values[3]	values[3]	288	1			T11	23		T179	6		T35	19
auto[1]	values[3]	values[4]	464	1			T14	9		T30	8		T123	8
auto[1]	values[3]	values[5]	698	1			T11	7		T23	19		T30	11
auto[1]	values[3]	values[6]	640	1			T32	5		T18	9		T233	10
auto[1]	values[3]	values[7]	310	1			T5	16		T48	25		T29	9
auto[1]	values[4]	values[0]	687	1			T5	25		T11	16		T187	8
auto[1]	values[4]	values[1]	549	1			T120	11		T18	11		T35	11
auto[1]	values[4]	values[2]	461	1			T13	22		T14	6		T32	6
auto[1]	values[4]	values[3]	419	1			T29	28		T119	7		T177	12
auto[1]	values[4]	values[4]	580	1			T119	4		T120	11		T175	25
auto[1]	values[4]	values[5]	394	1			T5	10		T29	23		T18	5
auto[1]	values[4]	values[6]	418	1			T11	81		T29	9		T155	8
auto[1]	values[4]	values[7]	431	1			T23	5		T28	6		T155	9
auto[1]	values[5]	values[0]	413	1			T11	12		T30	10		T35	21
auto[1]	values[5]	values[1]	848	1			T5	13		T27	41		T155	6
auto[1]	values[5]	values[2]	411	1			T32	14		T189	9		T225	8
auto[1]	values[5]	values[3]	424	1			T27	9		T123	3		T35	10
auto[1]	values[5]	values[4]	527	1			T5	55		T14	4		T27	7
auto[1]	values[5]	values[5]	500	1			T28	16		T29	20		T179	22
auto[1]	values[5]	values[6]	333	1			T11	5		T120	16		T18	12
auto[1]	values[5]	values[7]	528	1			T29	11		T155	8		T119	32
auto[1]	values[6]	values[0]	472	1			T29	11		T32	18		T119	6
auto[1]	values[6]	values[1]	471	1			T28	6		T30	11		T179	8
auto[1]	values[6]	values[2]	449	1			T179	9		T153	14		T189	10
auto[1]	values[6]	values[3]	458	1			T35	58		T174	21		T234	7
auto[1]	values[6]	values[4]	579	1			T26	4		T29	69		T32	9
auto[1]	values[6]	values[5]	371	1			T29	4		T32	8		T119	14
auto[1]	values[6]	values[6]	409	1			T11	30		T119	7		T35	22
auto[1]	values[6]	values[7]	591	1			T176	16		T35	15		T189	11
auto[1]	values[7]	values[0]	443	1			T32	6		T168	9		T206	13
auto[1]	values[7]	values[1]	395	1			T155	55		T120	4		T179	5
auto[1]	values[7]	values[2]	437	1			T14	5		T29	35		T119	17
auto[1]	values[7]	values[3]	521	1			T14	17		T48	4		T120	14
auto[1]	values[7]	values[4]	442	1			T11	42		T119	12		T123	27
auto[1]	values[7]	values[5]	727	1			T5	89		T27	94		T30	10
auto[1]	values[7]	values[6]	433	1			T29	6		T119	97		T215	29
auto[1]	values[7]	values[7]	546	1			T29	7		T30	7		T153	41