Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	989	1			T5	8		T11	2		T14	4
auto[ReadAddrCrossIntoMailbox]	802	1			T5	7		T11	4		T14	2
auto[ReadAddrCrossOutOfMailbox]	840	1			T5	7		T11	4		T14	4
auto[ReadAddrCrossAllMailbox]	602	1			T5	3		T11	2		T14	1
auto[ReadAddrOutsideMailbox]	9140	1			T5	29		T8	2		T11	71

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6210

1

T5

35

T8

1

T11

29

auto[1]

6163

1

T5

19

T8

1

T11

54

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	2077	1			T5	13		T11	19		T12	2
read_ops[0x0b]	2119	1			T5	5		T11	14		T12	2
read_ops[0x3b]	1954	1			T5	10		T11	10		T26	2
read_ops[0x6b]	1993	1			T5	5		T11	16		T14	8
read_ops[0xbb]	2089	1			T5	8		T11	11		T12	4
read_ops[0xeb]	2141	1			T5	13		T8	2		T11	13

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	87	1			T11	1		T28	1		T30	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	89	1			T5	1		T11	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	67	1			T11	2		T23	2		T224	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	54	1			T28	1		T48	1		T29	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	55	1			T11	1		T28	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	58	1			T5	2		T14	2		T27	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	64	1			T5	1		T11	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	44	1			T48	1		T224	3		T123	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	779	1			T5	7		T11	7		T12	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	780	1			T5	2		T11	6		T12	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	88	1			T120	1		T175	1		T172	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	78	1			T30	1		T179	1		T193	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	75	1			T5	1		T48	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	79	1			T5	1		T120	3		T172	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	72	1			T32	1		T179	1		T153	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	64	1			T11	2		T155	1		T172	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	45	1			T5	1		T30	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	60	1			T14	1		T48	1		T175	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	744	1			T5	1		T11	2		T12	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	814	1			T5	1		T11	10		T12	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	89	1			T5	2		T29	2		T30	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	76	1			T5	2		T28	2		T29	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	78	1			T5	1		T27	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	55	1			T11	1		T30	1		T224	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	64	1			T5	2		T195	1		T120	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	61	1			T195	1		T32	1		T119	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	48	1			T29	3		T224	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	47	1			T27	1		T224	1		T189	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	726	1			T5	3		T11	5		T26	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	710	1			T11	4		T26	1		T14	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	77	1			T29	1		T193	1		T205	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	66	1			T5	1		T27	1		T32	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	57	1			T23	1		T29	1		T30	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	60	1			T5	1		T30	1		T119	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	84	1			T29	1		T119	1		T120	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	59	1			T14	1		T28	1		T30	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	57	1			T155	1		T119	1		T175	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	43	1			T120	1		T153	2		T235	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	753	1			T5	1		T11	4		T14	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	737	1			T5	2		T11	12		T14	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	85	1			T5	2		T14	1		T48	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	97	1			T14	1		T23	2		T27	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	71	1			T14	1		T28	1		T30	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	80	1			T5	1		T119	1		T123	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	81	1			T23	1		T27	1		T172	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	68	1			T5	1		T11	1		T23	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	52	1			T30	2		T224	2		T123	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	45	1			T11	1		T224	2		T120	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	761	1			T5	2		T11	5		T12	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	749	1			T5	2		T11	4		T12	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	73	1			T14	2		T32	1		T119	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	84	1			T48	1		T29	1		T120	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	54	1			T5	1		T23	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	72	1			T5	1		T11	1		T14	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	84	1			T5	1		T30	1		T224	3
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	90	1			T5	1		T14	1		T28	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	49	1			T5	1		T120	2		T172	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	48	1			T28	2		T194	2		T18	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	791	1			T5	8		T8	1		T11	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	796	1			T8	1		T11	11		T14	3